stm32f10x_adc.c
Go to the documentation of this file.
1 
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x_adc.h"
24 #include "stm32f10x_rcc.h"
25 
47 /* ADC DISCNUM mask */
48 #define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
49 
50 /* ADC DISCEN mask */
51 #define CR1_DISCEN_Set ((uint32_t)0x00000800)
52 #define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
53 
54 /* ADC JAUTO mask */
55 #define CR1_JAUTO_Set ((uint32_t)0x00000400)
56 #define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
57 
58 /* ADC JDISCEN mask */
59 #define CR1_JDISCEN_Set ((uint32_t)0x00001000)
60 #define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
61 
62 /* ADC AWDCH mask */
63 #define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
64 
65 /* ADC Analog watchdog enable mode mask */
66 #define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
67 
68 /* CR1 register Mask */
69 #define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
70 
71 /* ADC ADON mask */
72 #define CR2_ADON_Set ((uint32_t)0x00000001)
73 #define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
74 
75 /* ADC DMA mask */
76 #define CR2_DMA_Set ((uint32_t)0x00000100)
77 #define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
78 
79 /* ADC RSTCAL mask */
80 #define CR2_RSTCAL_Set ((uint32_t)0x00000008)
81 
82 /* ADC CAL mask */
83 #define CR2_CAL_Set ((uint32_t)0x00000004)
84 
85 /* ADC SWSTART mask */
86 #define CR2_SWSTART_Set ((uint32_t)0x00400000)
87 
88 /* ADC EXTTRIG mask */
89 #define CR2_EXTTRIG_Set ((uint32_t)0x00100000)
90 #define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
91 
92 /* ADC Software start mask */
93 #define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
94 #define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
95 
96 /* ADC JEXTSEL mask */
97 #define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
98 
99 /* ADC JEXTTRIG mask */
100 #define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
101 #define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
102 
103 /* ADC JSWSTART mask */
104 #define CR2_JSWSTART_Set ((uint32_t)0x00200000)
105 
106 /* ADC injected software start mask */
107 #define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
108 #define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
109 
110 /* ADC TSPD mask */
111 #define CR2_TSVREFE_Set ((uint32_t)0x00800000)
112 #define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
113 
114 /* CR2 register Mask */
115 #define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
116 
117 /* ADC SQx mask */
118 #define SQR3_SQ_Set ((uint32_t)0x0000001F)
119 #define SQR2_SQ_Set ((uint32_t)0x0000001F)
120 #define SQR1_SQ_Set ((uint32_t)0x0000001F)
121 
122 /* SQR1 register Mask */
123 #define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
124 
125 /* ADC JSQx mask */
126 #define JSQR_JSQ_Set ((uint32_t)0x0000001F)
127 
128 /* ADC JL mask */
129 #define JSQR_JL_Set ((uint32_t)0x00300000)
130 #define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
131 
132 /* ADC SMPx mask */
133 #define SMPR1_SMP_Set ((uint32_t)0x00000007)
134 #define SMPR2_SMP_Set ((uint32_t)0x00000007)
135 
136 /* ADC JDRx registers offset */
137 #define JDR_Offset ((uint8_t)0x28)
138 
139 /* ADC1 DR register base address */
140 #define DR_ADDRESS ((uint32_t)0x4001244C)
141 
180 {
181  /* Check the parameters */
183 
184  if (ADCx == ADC1)
185  {
186  /* Enable ADC1 reset state */
188  /* Release ADC1 from reset state */
190  }
191  else if (ADCx == ADC2)
192  {
193  /* Enable ADC2 reset state */
195  /* Release ADC2 from reset state */
197  }
198  else
199  {
200  if (ADCx == ADC3)
201  {
202  /* Enable ADC3 reset state */
204  /* Release ADC3 from reset state */
206  }
207  }
208 }
209 
218 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
219 {
220  uint32_t tmpreg1 = 0;
221  uint8_t tmpreg2 = 0;
222  /* Check the parameters */
224  assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
228  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
230 
231  /*---------------------------- ADCx CR1 Configuration -----------------*/
232  /* Get the ADCx CR1 value */
233  tmpreg1 = ADCx->CR1;
234  /* Clear DUALMOD and SCAN bits */
235  tmpreg1 &= CR1_CLEAR_Mask;
236  /* Configure ADCx: Dual mode and scan conversion mode */
237  /* Set DUALMOD bits according to ADC_Mode value */
238  /* Set SCAN bit according to ADC_ScanConvMode value */
239  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
240  /* Write to ADCx CR1 */
241  ADCx->CR1 = tmpreg1;
242 
243  /*---------------------------- ADCx CR2 Configuration -----------------*/
244  /* Get the ADCx CR2 value */
245  tmpreg1 = ADCx->CR2;
246  /* Clear CONT, ALIGN and EXTSEL bits */
247  tmpreg1 &= CR2_CLEAR_Mask;
248  /* Configure ADCx: external trigger event and continuous conversion mode */
249  /* Set ALIGN bit according to ADC_DataAlign value */
250  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
251  /* Set CONT bit according to ADC_ContinuousConvMode value */
252  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
253  ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
254  /* Write to ADCx CR2 */
255  ADCx->CR2 = tmpreg1;
256 
257  /*---------------------------- ADCx SQR1 Configuration -----------------*/
258  /* Get the ADCx SQR1 value */
259  tmpreg1 = ADCx->SQR1;
260  /* Clear L bits */
261  tmpreg1 &= SQR1_CLEAR_Mask;
262  /* Configure ADCx: regular channel sequence length */
263  /* Set L bits according to ADC_NbrOfChannel value */
264  tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
265  tmpreg1 |= (uint32_t)tmpreg2 << 20;
266  /* Write to ADCx SQR1 */
267  ADCx->SQR1 = tmpreg1;
268 }
269 
275 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
276 {
277  /* Reset ADC init structure parameters values */
278  /* Initialize the ADC_Mode member */
279  ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
280  /* initialize the ADC_ScanConvMode member */
281  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
282  /* Initialize the ADC_ContinuousConvMode member */
283  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
284  /* Initialize the ADC_ExternalTrigConv member */
286  /* Initialize the ADC_DataAlign member */
287  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
288  /* Initialize the ADC_NbrOfChannel member */
289  ADC_InitStruct->ADC_NbrOfChannel = 1;
290 }
291 
299 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
300 {
301  /* Check the parameters */
304  if (NewState != DISABLE)
305  {
306  /* Set the ADON bit to wake up the ADC from power down mode */
307  ADCx->CR2 |= CR2_ADON_Set;
308  }
309  else
310  {
311  /* Disable the selected ADC peripheral */
312  ADCx->CR2 &= CR2_ADON_Reset;
313  }
314 }
315 
325 {
326  /* Check the parameters */
329  if (NewState != DISABLE)
330  {
331  /* Enable the selected ADC DMA request */
332  ADCx->CR2 |= CR2_DMA_Set;
333  }
334  else
335  {
336  /* Disable the selected ADC DMA request */
337  ADCx->CR2 &= CR2_DMA_Reset;
338  }
339 }
340 
353 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
354 {
355  uint8_t itmask = 0;
356  /* Check the parameters */
359  assert_param(IS_ADC_IT(ADC_IT));
360  /* Get the ADC IT index */
361  itmask = (uint8_t)ADC_IT;
362  if (NewState != DISABLE)
363  {
364  /* Enable the selected ADC interrupts */
365  ADCx->CR1 |= itmask;
366  }
367  else
368  {
369  /* Disable the selected ADC interrupts */
370  ADCx->CR1 &= (~(uint32_t)itmask);
371  }
372 }
373 
380 {
381  /* Check the parameters */
383  /* Resets the selected ADC calibration registers */
384  ADCx->CR2 |= CR2_RSTCAL_Set;
385 }
386 
393 {
394  FlagStatus bitstatus = RESET;
395  /* Check the parameters */
397  /* Check the status of RSTCAL bit */
398  if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
399  {
400  /* RSTCAL bit is set */
401  bitstatus = SET;
402  }
403  else
404  {
405  /* RSTCAL bit is reset */
406  bitstatus = RESET;
407  }
408  /* Return the RSTCAL bit status */
409  return bitstatus;
410 }
411 
418 {
419  /* Check the parameters */
421  /* Enable the selected ADC calibration process */
422  ADCx->CR2 |= CR2_CAL_Set;
423 }
424 
431 {
432  FlagStatus bitstatus = RESET;
433  /* Check the parameters */
435  /* Check the status of CAL bit */
436  if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
437  {
438  /* CAL bit is set: calibration on going */
439  bitstatus = SET;
440  }
441  else
442  {
443  /* CAL bit is reset: end of calibration */
444  bitstatus = RESET;
445  }
446  /* Return the CAL bit status */
447  return bitstatus;
448 }
449 
458 {
459  /* Check the parameters */
462  if (NewState != DISABLE)
463  {
464  /* Enable the selected ADC conversion on external event and start the selected
465  ADC conversion */
466  ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
467  }
468  else
469  {
470  /* Disable the selected ADC conversion on external event and stop the selected
471  ADC conversion */
473  }
474 }
475 
482 {
483  FlagStatus bitstatus = RESET;
484  /* Check the parameters */
486  /* Check the status of SWSTART bit */
487  if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
488  {
489  /* SWSTART bit is set */
490  bitstatus = SET;
491  }
492  else
493  {
494  /* SWSTART bit is reset */
495  bitstatus = RESET;
496  }
497  /* Return the SWSTART bit status */
498  return bitstatus;
499 }
500 
509 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
510 {
511  uint32_t tmpreg1 = 0;
512  uint32_t tmpreg2 = 0;
513  /* Check the parameters */
516  /* Get the old register value */
517  tmpreg1 = ADCx->CR1;
518  /* Clear the old discontinuous mode channel count */
519  tmpreg1 &= CR1_DISCNUM_Reset;
520  /* Set the discontinuous mode channel count */
521  tmpreg2 = Number - 1;
522  tmpreg1 |= tmpreg2 << 13;
523  /* Store the new register value */
524  ADCx->CR1 = tmpreg1;
525 }
526 
537 {
538  /* Check the parameters */
541  if (NewState != DISABLE)
542  {
543  /* Enable the selected ADC regular discontinuous mode */
544  ADCx->CR1 |= CR1_DISCEN_Set;
545  }
546  else
547  {
548  /* Disable the selected ADC regular discontinuous mode */
549  ADCx->CR1 &= CR1_DISCEN_Reset;
550  }
551 }
552 
590 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
591 {
592  uint32_t tmpreg1 = 0, tmpreg2 = 0;
593  /* Check the parameters */
595  assert_param(IS_ADC_CHANNEL(ADC_Channel));
597  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
598  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
599  if (ADC_Channel > ADC_Channel_9)
600  {
601  /* Get the old register value */
602  tmpreg1 = ADCx->SMPR1;
603  /* Calculate the mask to clear */
604  tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
605  /* Clear the old channel sample time */
606  tmpreg1 &= ~tmpreg2;
607  /* Calculate the mask to set */
608  tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
609  /* Set the new channel sample time */
610  tmpreg1 |= tmpreg2;
611  /* Store the new register value */
612  ADCx->SMPR1 = tmpreg1;
613  }
614  else /* ADC_Channel include in ADC_Channel_[0..9] */
615  {
616  /* Get the old register value */
617  tmpreg1 = ADCx->SMPR2;
618  /* Calculate the mask to clear */
619  tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
620  /* Clear the old channel sample time */
621  tmpreg1 &= ~tmpreg2;
622  /* Calculate the mask to set */
623  tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
624  /* Set the new channel sample time */
625  tmpreg1 |= tmpreg2;
626  /* Store the new register value */
627  ADCx->SMPR2 = tmpreg1;
628  }
629  /* For Rank 1 to 6 */
630  if (Rank < 7)
631  {
632  /* Get the old register value */
633  tmpreg1 = ADCx->SQR3;
634  /* Calculate the mask to clear */
635  tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
636  /* Clear the old SQx bits for the selected rank */
637  tmpreg1 &= ~tmpreg2;
638  /* Calculate the mask to set */
639  tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
640  /* Set the SQx bits for the selected rank */
641  tmpreg1 |= tmpreg2;
642  /* Store the new register value */
643  ADCx->SQR3 = tmpreg1;
644  }
645  /* For Rank 7 to 12 */
646  else if (Rank < 13)
647  {
648  /* Get the old register value */
649  tmpreg1 = ADCx->SQR2;
650  /* Calculate the mask to clear */
651  tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
652  /* Clear the old SQx bits for the selected rank */
653  tmpreg1 &= ~tmpreg2;
654  /* Calculate the mask to set */
655  tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
656  /* Set the SQx bits for the selected rank */
657  tmpreg1 |= tmpreg2;
658  /* Store the new register value */
659  ADCx->SQR2 = tmpreg1;
660  }
661  /* For Rank 13 to 16 */
662  else
663  {
664  /* Get the old register value */
665  tmpreg1 = ADCx->SQR1;
666  /* Calculate the mask to clear */
667  tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
668  /* Clear the old SQx bits for the selected rank */
669  tmpreg1 &= ~tmpreg2;
670  /* Calculate the mask to set */
671  tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
672  /* Set the SQx bits for the selected rank */
673  tmpreg1 |= tmpreg2;
674  /* Store the new register value */
675  ADCx->SQR1 = tmpreg1;
676  }
677 }
678 
687 {
688  /* Check the parameters */
691  if (NewState != DISABLE)
692  {
693  /* Enable the selected ADC conversion on external event */
694  ADCx->CR2 |= CR2_EXTTRIG_Set;
695  }
696  else
697  {
698  /* Disable the selected ADC conversion on external event */
699  ADCx->CR2 &= CR2_EXTTRIG_Reset;
700  }
701 }
702 
709 {
710  /* Check the parameters */
712  /* Return the selected ADC conversion value */
713  return (uint16_t) ADCx->DR;
714 }
715 
721 {
722  /* Return the dual mode conversion value */
723  return (*(__IO uint32_t *) DR_ADDRESS);
724 }
725 
735 {
736  /* Check the parameters */
739  if (NewState != DISABLE)
740  {
741  /* Enable the selected ADC automatic injected group conversion */
742  ADCx->CR1 |= CR1_JAUTO_Set;
743  }
744  else
745  {
746  /* Disable the selected ADC automatic injected group conversion */
747  ADCx->CR1 &= CR1_JAUTO_Reset;
748  }
749 }
750 
761 {
762  /* Check the parameters */
765  if (NewState != DISABLE)
766  {
767  /* Enable the selected ADC injected discontinuous mode */
768  ADCx->CR1 |= CR1_JDISCEN_Set;
769  }
770  else
771  {
772  /* Disable the selected ADC injected discontinuous mode */
773  ADCx->CR1 &= CR1_JDISCEN_Reset;
774  }
775 }
776 
799 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
800 {
801  uint32_t tmpreg = 0;
802  /* Check the parameters */
804  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
805  /* Get the old register value */
806  tmpreg = ADCx->CR2;
807  /* Clear the old external event selection for injected group */
808  tmpreg &= CR2_JEXTSEL_Reset;
809  /* Set the external event selection for injected group */
810  tmpreg |= ADC_ExternalTrigInjecConv;
811  /* Store the new register value */
812  ADCx->CR2 = tmpreg;
813 }
814 
825 {
826  /* Check the parameters */
829  if (NewState != DISABLE)
830  {
831  /* Enable the selected ADC external event selection for injected group */
832  ADCx->CR2 |= CR2_JEXTTRIG_Set;
833  }
834  else
835  {
836  /* Disable the selected ADC external event selection for injected group */
837  ADCx->CR2 &= CR2_JEXTTRIG_Reset;
838  }
839 }
840 
850 {
851  /* Check the parameters */
854  if (NewState != DISABLE)
855  {
856  /* Enable the selected ADC conversion for injected group on external event and start the selected
857  ADC injected conversion */
859  }
860  else
861  {
862  /* Disable the selected ADC conversion on external event for injected group and stop the selected
863  ADC injected conversion */
865  }
866 }
867 
874 {
875  FlagStatus bitstatus = RESET;
876  /* Check the parameters */
878  /* Check the status of JSWSTART bit */
879  if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
880  {
881  /* JSWSTART bit is set */
882  bitstatus = SET;
883  }
884  else
885  {
886  /* JSWSTART bit is reset */
887  bitstatus = RESET;
888  }
889  /* Return the JSWSTART bit status */
890  return bitstatus;
891 }
892 
930 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
931 {
932  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
933  /* Check the parameters */
935  assert_param(IS_ADC_CHANNEL(ADC_Channel));
937  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
938  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
939  if (ADC_Channel > ADC_Channel_9)
940  {
941  /* Get the old register value */
942  tmpreg1 = ADCx->SMPR1;
943  /* Calculate the mask to clear */
944  tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
945  /* Clear the old channel sample time */
946  tmpreg1 &= ~tmpreg2;
947  /* Calculate the mask to set */
948  tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
949  /* Set the new channel sample time */
950  tmpreg1 |= tmpreg2;
951  /* Store the new register value */
952  ADCx->SMPR1 = tmpreg1;
953  }
954  else /* ADC_Channel include in ADC_Channel_[0..9] */
955  {
956  /* Get the old register value */
957  tmpreg1 = ADCx->SMPR2;
958  /* Calculate the mask to clear */
959  tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
960  /* Clear the old channel sample time */
961  tmpreg1 &= ~tmpreg2;
962  /* Calculate the mask to set */
963  tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
964  /* Set the new channel sample time */
965  tmpreg1 |= tmpreg2;
966  /* Store the new register value */
967  ADCx->SMPR2 = tmpreg1;
968  }
969  /* Rank configuration */
970  /* Get the old register value */
971  tmpreg1 = ADCx->JSQR;
972  /* Get JL value: Number = JL+1 */
973  tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
974  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
975  tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
976  /* Clear the old JSQx bits for the selected rank */
977  tmpreg1 &= ~tmpreg2;
978  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
979  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
980  /* Set the JSQx bits for the selected rank */
981  tmpreg1 |= tmpreg2;
982  /* Store the new register value */
983  ADCx->JSQR = tmpreg1;
984 }
985 
994 {
995  uint32_t tmpreg1 = 0;
996  uint32_t tmpreg2 = 0;
997  /* Check the parameters */
1000 
1001  /* Get the old register value */
1002  tmpreg1 = ADCx->JSQR;
1003  /* Clear the old injected sequnence lenght JL bits */
1004  tmpreg1 &= JSQR_JL_Reset;
1005  /* Set the injected sequnence lenght JL bits */
1006  tmpreg2 = Length - 1;
1007  tmpreg1 |= tmpreg2 << 20;
1008  /* Store the new register value */
1009  ADCx->JSQR = tmpreg1;
1010 }
1011 
1025 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
1026 {
1027  __IO uint32_t tmp = 0;
1028 
1029  /* Check the parameters */
1031  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
1032  assert_param(IS_ADC_OFFSET(Offset));
1033 
1034  tmp = (uint32_t)ADCx;
1035  tmp += ADC_InjectedChannel;
1036 
1037  /* Set the selected injected channel data offset */
1038  *(__IO uint32_t *) tmp = (uint32_t)Offset;
1039 }
1040 
1052 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
1053 {
1054  __IO uint32_t tmp = 0;
1055 
1056  /* Check the parameters */
1058  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
1059 
1060  tmp = (uint32_t)ADCx;
1061  tmp += ADC_InjectedChannel + JDR_Offset;
1062 
1063  /* Returns the selected injected channel conversion data value */
1064  return (uint16_t) (*(__IO uint32_t*) tmp);
1065 }
1066 
1082 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
1083 {
1084  uint32_t tmpreg = 0;
1085  /* Check the parameters */
1087  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
1088  /* Get the old register value */
1089  tmpreg = ADCx->CR1;
1090  /* Clear AWDEN, AWDENJ and AWDSGL bits */
1091  tmpreg &= CR1_AWDMode_Reset;
1092  /* Set the analog watchdog enable mode */
1093  tmpreg |= ADC_AnalogWatchdog;
1094  /* Store the new register value */
1095  ADCx->CR1 = tmpreg;
1096 }
1097 
1107 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
1108  uint16_t LowThreshold)
1109 {
1110  /* Check the parameters */
1112  assert_param(IS_ADC_THRESHOLD(HighThreshold));
1113  assert_param(IS_ADC_THRESHOLD(LowThreshold));
1114  /* Set the ADCx high threshold */
1115  ADCx->HTR = HighThreshold;
1116  /* Set the ADCx low threshold */
1117  ADCx->LTR = LowThreshold;
1118 }
1119 
1145 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
1146 {
1147  uint32_t tmpreg = 0;
1148  /* Check the parameters */
1150  assert_param(IS_ADC_CHANNEL(ADC_Channel));
1151  /* Get the old register value */
1152  tmpreg = ADCx->CR1;
1153  /* Clear the Analog watchdog channel select bits */
1154  tmpreg &= CR1_AWDCH_Reset;
1155  /* Set the Analog watchdog channel */
1156  tmpreg |= ADC_Channel;
1157  /* Store the new register value */
1158  ADCx->CR1 = tmpreg;
1159 }
1160 
1168 {
1169  /* Check the parameters */
1170  assert_param(IS_FUNCTIONAL_STATE(NewState));
1171  if (NewState != DISABLE)
1172  {
1173  /* Enable the temperature sensor and Vrefint channel*/
1174  ADC1->CR2 |= CR2_TSVREFE_Set;
1175  }
1176  else
1177  {
1178  /* Disable the temperature sensor and Vrefint channel*/
1179  ADC1->CR2 &= CR2_TSVREFE_Reset;
1180  }
1181 }
1182 
1195 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
1196 {
1197  FlagStatus bitstatus = RESET;
1198  /* Check the parameters */
1200  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
1201  /* Check the status of the specified ADC flag */
1202  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
1203  {
1204  /* ADC_FLAG is set */
1205  bitstatus = SET;
1206  }
1207  else
1208  {
1209  /* ADC_FLAG is reset */
1210  bitstatus = RESET;
1211  }
1212  /* Return the ADC_FLAG status */
1213  return bitstatus;
1214 }
1215 
1228 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
1229 {
1230  /* Check the parameters */
1232  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
1233  /* Clear the selected ADC flags */
1234  ADCx->SR = ~(uint32_t)ADC_FLAG;
1235 }
1236 
1247 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
1248 {
1249  ITStatus bitstatus = RESET;
1250  uint32_t itmask = 0, enablestatus = 0;
1251  /* Check the parameters */
1253  assert_param(IS_ADC_GET_IT(ADC_IT));
1254  /* Get the ADC IT index */
1255  itmask = ADC_IT >> 8;
1256  /* Get the ADC_IT enable bit status */
1257  enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
1258  /* Check the status of the specified ADC interrupt */
1259  if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
1260  {
1261  /* ADC_IT is set */
1262  bitstatus = SET;
1263  }
1264  else
1265  {
1266  /* ADC_IT is reset */
1267  bitstatus = RESET;
1268  }
1269  /* Return the ADC_IT status */
1270  return bitstatus;
1271 }
1272 
1283 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
1284 {
1285  uint8_t itmask = 0;
1286  /* Check the parameters */
1288  assert_param(IS_ADC_IT(ADC_IT));
1289  /* Get the ADC IT index */
1290  itmask = (uint8_t)(ADC_IT >> 8);
1291  /* Clear the selected ADC interrupt pending bits */
1292  ADCx->SR = ~(uint32_t)itmask;
1293 }
1294 
1307 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
#define IS_ADC_INJECTED_RANK(RANK)
#define ADC3
Definition: stm32f4xx.h:2085
#define IS_ADC_MODE(MODE)
#define CR2_EXTTRIG_SWSTART_Reset
Definition: stm32f10x_adc.c:94
FlagStatus
Definition: stm32f4xx.h:706
#define IS_ADC_INJECTED_CHANNEL(CHANNEL)
uint32_t ADC_ExternalTrigConv
Definition: stm32f4xx_adc.h:68
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx&#39;s interrupt pending bits.
#define CR2_JEXTTRIG_JSWSTART_Set
#define JSQR_JL_Reset
#define SQR3_SQ_Set
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampl...
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
FunctionalState
Definition: stm32f4xx.h:708
#define CR2_JSWSTART_Set
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Clears the ADCx&#39;s pending flags.
#define CR2_ADON_Reset
Definition: stm32f10x_adc.c:73
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
ADC Init structure definition.
Definition: stm32f4xx_adc.h:53
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
Analog to Digital Converter.
Definition: stm32f4xx.h:725
#define CR2_JEXTSEL_Reset
Definition: stm32f10x_adc.c:97
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
#define ADC_Mode_Independent
__IO uint32_t SMPR2
Definition: stm32f4xx.h:731
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
#define SMPR1_SMP_Set
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
__IO uint32_t SMPR1
Definition: stm32f4xx.h:730
FunctionalState ADC_ContinuousConvMode
Definition: stm32f4xx_adc.h:61
#define DR_ADDRESS
#define CR1_JAUTO_Set
Definition: stm32f10x_adc.c:55
#define CR1_JAUTO_Reset
Definition: stm32f10x_adc.c:56
__IO uint32_t SR
Definition: stm32f4xx.h:727
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
#define IS_ADC_CHANNEL(CHANNEL)
#define JDR_Offset
#define IS_ADC_GET_FLAG(FLAG)
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER)
#define CR2_TSVREFE_Reset
#define IS_ADC_REGULAR_RANK(RANK)
void assert_param(int val)
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
#define CR2_ADON_Set
Definition: stm32f10x_adc.c:72
#define JSQR_JSQ_Set
__IO uint32_t SQR3
Definition: stm32f4xx.h:740
#define CR2_JEXTTRIG_Set
__IO uint32_t SQR2
Definition: stm32f4xx.h:739
#define ADC2
Definition: stm32f4xx.h:2084
#define IS_ADC_THRESHOLD(THRESHOLD)
#define SQR1_CLEAR_Mask
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define CR2_JEXTTRIG_JSWSTART_Reset
#define JSQR_JL_Set
Definition: stm32f4xx.h:706
#define CR2_EXTTRIG_Reset
Definition: stm32f10x_adc.c:90
#define ADC_Channel_9
uint32_t ADC_GetDualModeConversionValue(void)
Returns the last ADC1 and ADC2 conversion result data in dual mode.
__IO uint32_t JSQR
Definition: stm32f4xx.h:741
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC...
enum FlagStatus ITStatus
#define CR2_EXTTRIG_SWSTART_Set
Definition: stm32f10x_adc.c:93
#define CR1_DISCNUM_Reset
Definition: stm32f10x_adc.c:48
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx)
Gets the selected ADC reset calibration registers status.
#define SQR2_SQ_Set
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
#define CR2_RSTCAL_Set
Definition: stm32f10x_adc.c:80
This file contains all the functions prototypes for the ADC firmware library.
uint32_t ADC_DataAlign
Definition: stm32f4xx_adc.h:72
#define __IO
Definition: core_cm0.h:198
void ADC_DeInit(ADC_TypeDef *ADCx)
Deinitializes the ADCx peripheral registers to their default reset values.
#define IS_ADC_DMA_PERIPH(PERIPH)
Definition: stm32f10x_adc.h:87
#define ADC_ExternalTrigConv_T1_CC1
#define CR2_EXTTRIG_Set
Definition: stm32f10x_adc.c:89
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
#define SMPR2_SMP_Set
#define IS_ADC_CLEAR_FLAG(FLAG)
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
#define IS_ADC_SAMPLE_TIME(TIME)
#define CR2_CLEAR_Mask
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC software start conversion .
__IO uint32_t DR
Definition: stm32f4xx.h:746
#define IS_ADC_IT(IT)
This file contains all the functions prototypes for the RCC firmware library.
uint32_t ADC_Mode
Definition: stm32f10x_adc.h:52
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG)
__IO uint32_t SQR1
Definition: stm32f4xx.h:738
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its samp...
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
#define CR1_AWDMode_Reset
Definition: stm32f10x_adc.c:66
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void ADC_StartCalibration(ADC_TypeDef *ADCx)
Starts the selected ADC calibration process.
#define IS_ADC_OFFSET(OFFSET)
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx)
Gets the selected ADC Software start conversion Status.
#define CR2_CAL_Set
Definition: stm32f10x_adc.c:83
void ADC_TempSensorVrefintCmd(FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.
#define IS_ADC_GET_IT(IT)
__IO uint32_t LTR
Definition: stm32f4xx.h:737
#define CR1_DISCEN_Reset
Definition: stm32f10x_adc.c:52
#define IS_ADC_INJECTED_LENGTH(LENGTH)
FunctionalState ADC_ScanConvMode
Definition: stm32f4xx_adc.h:57
uint8_t ADC_NbrOfChannel
Definition: stm32f10x_adc.h:71
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx)
Gets the selected ADC calibration status.
__IO uint32_t CR1
Definition: stm32f4xx.h:728
#define CR1_CLEAR_Mask
Definition: stm32f10x_adc.c:69
#define CR1_AWDCH_Reset
Definition: stm32f10x_adc.c:63
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC...
__IO uint32_t HTR
Definition: stm32f4xx.h:736
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
#define CR2_DMA_Set
Definition: stm32f10x_adc.c:76
#define CR2_JEXTTRIG_Reset
#define IS_ADC_DATA_ALIGN(ALIGN)
#define IS_ADC_ALL_PERIPH(PERIPH)
void ADC_ResetCalibration(ADC_TypeDef *ADCx)
Resets the selected ADC calibration registers.
#define CR1_JDISCEN_Reset
Definition: stm32f10x_adc.c:60
#define CR2_SWSTART_Set
Definition: stm32f10x_adc.c:86
#define ADC_DataAlign_Right
void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx conversion through external trigger.
#define IS_ADC_REGULAR_LENGTH(LENGTH)
#define ADC1
Definition: stm32f4xx.h:2083
#define CR2_TSVREFE_Set
#define CR1_DISCEN_Set
Definition: stm32f10x_adc.c:51
#define IS_ADC_EXT_TRIG(REGTRIG)
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC start of the injected channels conversion.
#define SQR1_SQ_Set
__IO uint32_t CR2
Definition: stm32f4xx.h:729
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx injected channels conversion through external trigger.
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one...
#define CR2_DMA_Reset
Definition: stm32f10x_adc.c:77
#define CR1_JDISCEN_Set
Definition: stm32f10x_adc.c:59
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19