Functions that configure the System. More...
Detailed Description
Functions that configure the System.
Function Documentation
◆ SysTick_Config()
| __STATIC_INLINE uint32_t SysTick_Config | ( | uint32_t | ticks | ) |
System Tick Configuration.
The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts.
- Parameters
-
[in] ticks Number of ticks between two interrupts.
- Returns
- 0 Function succeeded.
- 1 Function failed.
- Note
- When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function.
Definition at line 641 of file core_cm0.h.
Variable Documentation
◆ _reserved0 [1/8]
| uint32_t APSR_Type::_reserved0 |
bit: 0..26 Reserved
Definition at line 185 of file core_cm0.h.
◆ _reserved0 [2/8]
| uint32_t { ... } ::_reserved0 |
bit: 0..26 Reserved
Definition at line 185 of file core_cm0.h.
◆ _reserved0 [3/8]
| uint32_t IPSR_Type::_reserved0 |
bit: 9..31 Reserved
Definition at line 208 of file core_cm0.h.
◆ _reserved0 [4/8]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 208 of file core_cm0.h.
◆ _reserved0 [5/8]
| uint32_t xPSR_Type::_reserved0 |
bit: 9..23 Reserved
Definition at line 222 of file core_cm0.h.
◆ _reserved0 [6/8]
| uint32_t { ... } ::_reserved0 |
bit: 9..23 Reserved
Definition at line 222 of file core_cm0.h.
◆ _reserved0 [7/8]
| uint32_t CONTROL_Type::_reserved0 |
bit: 3..31 Reserved
Definition at line 249 of file core_cm0.h.
◆ _reserved0 [8/8]
| uint32_t { ... } ::_reserved0 |
bit: 3..31 Reserved
Definition at line 249 of file core_cm0.h.
◆ AIRCR
| __IO uint32_t SCB_Type::AIRCR |
Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
Definition at line 295 of file core_cm0.h.
◆ b [1/4]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ b [2/4]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ b [3/4]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ b [4/4]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ C [1/4]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 193 of file core_cm0.h.
◆ C [2/4]
| uint32_t APSR_Type::C |
bit: 29 Carry condition code flag
Definition at line 193 of file core_cm0.h.
◆ C [3/4]
| uint32_t xPSR_Type::C |
bit: 29 Carry condition code flag
Definition at line 232 of file core_cm0.h.
◆ C [4/4]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 232 of file core_cm0.h.
◆ CALIB
| __I uint32_t SysTick_Type::CALIB |
Offset: 0x00C (R/ ) SysTick Calibration Register
Definition at line 400 of file core_cm0.h.
◆ CCR
| __IO uint32_t SCB_Type::CCR |
Offset: 0x014 (R/W) Configuration Control Register
Definition at line 297 of file core_cm0.h.
◆ CPUID
| __I uint32_t SCB_Type::CPUID |
Offset: 0x000 (R/ ) CPUID Base Register
Definition at line 292 of file core_cm0.h.
◆ CTRL
| __IO uint32_t SysTick_Type::CTRL |
Offset: 0x000 (R/W) SysTick Control and Status Register
Definition at line 397 of file core_cm0.h.
◆ FPCA [1/2]
| uint32_t CONTROL_Type::FPCA |
bit: 2 FP extension active flag
Definition at line 248 of file core_cm0.h.
◆ FPCA [2/2]
| uint32_t { ... } ::FPCA |
bit: 2 FP extension active flag
Definition at line 248 of file core_cm0.h.
◆ ICER
| __IO uint32_t NVIC_Type::ICER[1] |
Offset: 0x080 (R/W) Interrupt Clear Enable Register
Definition at line 269 of file core_cm0.h.
◆ ICPR
| __IO uint32_t NVIC_Type::ICPR[1] |
Offset: 0x180 (R/W) Interrupt Clear Pending Register
Definition at line 273 of file core_cm0.h.
◆ ICSR
| __IO uint32_t SCB_Type::ICSR |
Offset: 0x004 (R/W) Interrupt Control and State Register
Definition at line 293 of file core_cm0.h.
◆ IP
| __IO uint32_t NVIC_Type::IP[8] |
Offset: 0x300 (R/W) Interrupt Priority Register
Definition at line 276 of file core_cm0.h.
◆ ISER
| __IO uint32_t NVIC_Type::ISER[1] |
Offset: 0x000 (R/W) Interrupt Set Enable Register
Definition at line 267 of file core_cm0.h.
◆ ISPR
| __IO uint32_t NVIC_Type::ISPR[1] |
Offset: 0x100 (R/W) Interrupt Set Pending Register
Definition at line 271 of file core_cm0.h.
◆ ISR [1/4]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 207 of file core_cm0.h.
◆ ISR [2/4]
| uint32_t IPSR_Type::ISR |
bit: 0.. 8 Exception number
Definition at line 207 of file core_cm0.h.
◆ ISR [3/4]
| uint32_t xPSR_Type::ISR |
bit: 0.. 8 Exception number
Definition at line 220 of file core_cm0.h.
◆ ISR [4/4]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 220 of file core_cm0.h.
◆ IT [1/2]
| uint32_t xPSR_Type::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 229 of file core_cm0.h.
◆ IT [2/2]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 229 of file core_cm0.h.
◆ LOAD
| __IO uint32_t SysTick_Type::LOAD |
Offset: 0x004 (R/W) SysTick Reload Value Register
Definition at line 398 of file core_cm0.h.
◆ N [1/4]
| uint32_t APSR_Type::N |
bit: 31 Negative condition code flag
Definition at line 195 of file core_cm0.h.
◆ N [2/4]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 195 of file core_cm0.h.
◆ N [3/4]
| uint32_t xPSR_Type::N |
bit: 31 Negative condition code flag
Definition at line 234 of file core_cm0.h.
◆ N [4/4]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 234 of file core_cm0.h.
◆ nPRIV [1/2]
| uint32_t CONTROL_Type::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 246 of file core_cm0.h.
◆ nPRIV [2/2]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 246 of file core_cm0.h.
◆ Q [1/4]
| uint32_t APSR_Type::Q |
bit: 27 Saturation condition flag
Definition at line 191 of file core_cm0.h.
◆ Q [2/4]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 191 of file core_cm0.h.
◆ Q [3/4]
| uint32_t xPSR_Type::Q |
bit: 27 Saturation condition flag
Definition at line 230 of file core_cm0.h.
◆ Q [4/4]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 230 of file core_cm0.h.
◆ RESERVED0 [1/2]
| uint32_t SCB_Type::RESERVED0 |
Definition at line 294 of file core_cm0.h.
◆ RESERVED0 [2/2]
| uint32_t NVIC_Type::RESERVED0[31] |
Definition at line 268 of file core_cm0.h.
◆ RESERVED1
| uint32_t SCB_Type::RESERVED1 |
Definition at line 298 of file core_cm0.h.
◆ RESERVED2
| uint32_t NVIC_Type::RESERVED2[31] |
Definition at line 272 of file core_cm0.h.
◆ RESERVED3
| uint32_t NVIC_Type::RESERVED3[31] |
Definition at line 274 of file core_cm0.h.
◆ RESERVED4
| uint32_t NVIC_Type::RESERVED4[64] |
Definition at line 275 of file core_cm0.h.
◆ RSERVED1
| uint32_t NVIC_Type::RSERVED1[31] |
Definition at line 270 of file core_cm0.h.
◆ SCR
| __IO uint32_t SCB_Type::SCR |
Offset: 0x010 (R/W) System Control Register
Definition at line 296 of file core_cm0.h.
◆ SHCSR
| __IO uint32_t SCB_Type::SHCSR |
Offset: 0x024 (R/W) System Handler Control and State Register
Definition at line 300 of file core_cm0.h.
◆ SHP
| __IO uint32_t SCB_Type::SHP[2] |
Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED
Definition at line 299 of file core_cm0.h.
◆ SPSEL [1/2]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
Definition at line 247 of file core_cm0.h.
◆ SPSEL [2/2]
| uint32_t CONTROL_Type::SPSEL |
bit: 1 Stack to be used
Definition at line 247 of file core_cm0.h.
◆ T [1/2]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 228 of file core_cm0.h.
◆ T [2/2]
| uint32_t xPSR_Type::T |
bit: 24 Thumb bit (read 0)
Definition at line 228 of file core_cm0.h.
◆ V [1/4]
| uint32_t APSR_Type::V |
bit: 28 Overflow condition code flag
Definition at line 192 of file core_cm0.h.
◆ V [2/4]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 192 of file core_cm0.h.
◆ V [3/4]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 231 of file core_cm0.h.
◆ V [4/4]
| uint32_t xPSR_Type::V |
bit: 28 Overflow condition code flag
Definition at line 231 of file core_cm0.h.
◆ VAL
| __IO uint32_t SysTick_Type::VAL |
Offset: 0x008 (R/W) SysTick Current Value Register
Definition at line 399 of file core_cm0.h.
◆ w [1/4]
| uint32_t APSR_Type::w |
Type used for word access
Definition at line 197 of file core_cm0.h.
◆ w [2/4]
| uint32_t IPSR_Type::w |
Type used for word access
Definition at line 210 of file core_cm0.h.
◆ w [3/4]
| uint32_t xPSR_Type::w |
Type used for word access
Definition at line 236 of file core_cm0.h.
◆ w [4/4]
| uint32_t CONTROL_Type::w |
Type used for word access
Definition at line 251 of file core_cm0.h.
◆ Z [1/4]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 194 of file core_cm0.h.
◆ Z [2/4]
| uint32_t APSR_Type::Z |
bit: 30 Zero condition code flag
Definition at line 194 of file core_cm0.h.
◆ Z [3/4]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 233 of file core_cm0.h.
◆ Z [4/4]
| uint32_t xPSR_Type::Z |
bit: 30 Zero condition code flag
Definition at line 233 of file core_cm0.h.