Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. More...
Collaboration diagram for Core Debug Registers (CoreDebug):
Modules | |
| Core Definitions | |
| Definitions for base addresses, unions, and structures. | |
Detailed Description
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file.