stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_TIM_EX_H
22 #define STM32H7xx_HAL_TIM_EX_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
48 typedef struct
49 {
50  uint32_t IC1Polarity;
53  uint32_t IC1Prescaler;
56  uint32_t IC1Filter;
59  uint32_t Commutation_Delay;
61 } TIM_HallSensor_InitTypeDef;
62 #if defined(TIM_BREAK_INPUT_SUPPORT)
63 
67 typedef struct
68 {
69  uint32_t Source;
71  uint32_t Enable;
73  uint32_t Polarity;
76 }
77 TIMEx_BreakInputConfigTypeDef;
78 
79 #endif /* TIM_BREAK_INPUT_SUPPORT */
80 
83 /* End of exported types -----------------------------------------------------*/
84 
85 /* Exported constants --------------------------------------------------------*/
93 #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
94 #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
95 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
96 #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
97 #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
98 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
99 #define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
100 #define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
101 #define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
102 
103 #define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
104 #define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
105 #define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
106 #define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
107 #define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
108 #define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
109 #define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
110 #define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
111 #define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
112 
113 #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
114 #define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
115 #define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
116 #define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
117 #define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
118 #define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
119 
120 #define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
121 #define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
122 
123 #define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
124 #define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
125 #define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
126 #define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
127 #define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
128 
129 #define TIM_TIM23_ETR_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
130 #define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
131 #define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
132 
133 #define TIM_TIM24_ETR_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
134 #define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
135 #define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
136 #define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
137 #define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
138 
141 #if defined(TIM_BREAK_INPUT_SUPPORT)
142 
146 #define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
147 #define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
148 
155 #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
156 #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
157 #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
158 #define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
159 
166 #define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
167 #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
168 
175 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
176 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
177 
180 #endif /* TIM_BREAK_INPUT_SUPPORT */
181 
185 #define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */
186 #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1_TI1 is connected to COMP1 OUT */
187 
188 #define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8_TI1 is connected to GPIO */
189 #define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8_TI1 is connected to COMP2 OUT */
190 
191 #define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to GPIO */
192 #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
193 #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2_TI4 is connected to COMP2 OUT */
194 #define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
195 
196 #define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */
197 #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */
198 #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */
199 #define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
200 
201 #define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */
202 #define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */
203 #define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */
204 
205 #define TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */
206 #define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */
207 
208 #define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
209 #define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */
210 #define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */
211 #define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
212 #define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15_TI1 is connected to RCC LSE */
213 #define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */
214 #define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
215 
216 #define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */
217 #define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */
218 #define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */
219 #define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
220 
221 #define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
222 #define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */
223 #define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */
224 #define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
225 
226 #define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
227 #define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */
228 #define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
229 #define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
230 
231 #define TIM_TIM23_TI4_GPIO 0x00000000U /* !< TIM23_TI4 is connected to GPIO */
232 #define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23_TI4 is connected to COMP1 OUT */
233 #define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23_TI4 is connected to COMP2 OUT */
234 #define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
235 
236 #define TIM_TIM24_TI1_GPIO 0x00000000U /* !< TIM24_TI1 is connected to GPIO */
237 #define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24_TI1 is connected to CAN TMP */
238 #define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24_TI1 is connected to CAN RTP */
239 #define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
240 
247 /* End of exported constants -------------------------------------------------*/
248 
249 /* Exported macro ------------------------------------------------------------*/
257 /* End of exported macro -----------------------------------------------------*/
258 
259 /* Private macro -------------------------------------------------------------*/
263 #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
264  ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
265 
266 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
267  ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
268  ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
269  ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
270 
271 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
272  ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
273 
274 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
275  ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
276 
277 #define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\
278  ((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\
279  ((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\
280  ((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\
281  ((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\
282  ((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\
283  ((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\
284  ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\
285  ((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\
286  ((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\
287  ((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\
288  ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\
289  ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\
290  ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\
291  ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\
292  ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\
293  ((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\
294  ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\
295  ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\
296  ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\
297  ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\
298  ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\
299  ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\
300  ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\
301  ((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\
302  ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\
303  ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\
304  ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\
305  ((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\
306  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\
307  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\
308  ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\
309  ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\
310  ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\
311  ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
312  ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\
313  ((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\
314  ((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\
315  ((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\
316  ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
317  ((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\
318  ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\
319  ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\
320  ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
321 
322 #define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\
323  ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
324  ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
325  ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
326  ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
327  ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
328  ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
329  ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\
330  ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\
331  ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\
332  ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
333  ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
334  ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
335  ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
336  ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
337  ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
338  ((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\
339  ((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\
340  ((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\
341  ((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\
342  ((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\
343  ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\
344  ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\
345  ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\
346  ((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\
347  ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\
348  ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\
349  ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\
350  ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\
351  ((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\
352  ((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\
353  ((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\
354  ((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\
355  ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
356  ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
357  ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
358  ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
359 
363 /* End of private macro ------------------------------------------------------*/
364 
365 /* Exported functions --------------------------------------------------------*/
374 /* Timer Hall Sensor functions **********************************************/
375 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
376 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
377 
378 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
379 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
380 
381 /* Blocking mode: Polling */
382 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
383 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
384 /* Non-Blocking mode: Interrupt */
385 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
386 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
387 /* Non-Blocking mode: DMA */
388 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
389 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
398 /* Timer Complementary Output Compare functions *****************************/
399 /* Blocking mode: Polling */
400 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
401 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
402 
403 /* Non-Blocking mode: Interrupt */
404 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
405 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
406 
407 /* Non-Blocking mode: DMA */
408 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
409 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
418 /* Timer Complementary PWM functions ****************************************/
419 /* Blocking mode: Polling */
420 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
421 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
422 
423 /* Non-Blocking mode: Interrupt */
424 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
425 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
426 /* Non-Blocking mode: DMA */
427 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
428 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
437 /* Timer Complementary One Pulse functions **********************************/
438 /* Blocking mode: Polling */
439 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
440 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
441 
442 /* Non-Blocking mode: Interrupt */
443 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
444 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
453 /* Extended Control functions ************************************************/
454 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
455  uint32_t CommutationSource);
456 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
457  uint32_t CommutationSource);
458 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
459  uint32_t CommutationSource);
460 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
461  TIM_MasterConfigTypeDef *sMasterConfig);
462 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
463  TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
464 #if defined(TIM_BREAK_INPUT_SUPPORT)
465 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
466  TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
467 #endif /* TIM_BREAK_INPUT_SUPPORT */
468 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
469 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
470 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
479 /* Extended Callback **********************************************************/
480 void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
481 void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
482 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
483 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
492 /* Extended Peripheral State functions ***************************************/
493 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
494 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
502 /* End of exported functions -------------------------------------------------*/
503 
504 /* Private functions----------------------------------------------------------*/
508 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
509 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
513 /* End of private functions --------------------------------------------------*/
514 
523 #ifdef __cplusplus
524 }
525 #endif
526 
527 
528 #endif /* STM32H7xx_HAL_TIM_EX_H */
529 
530 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_TIMEx_PWMN_Start
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_RemapConfig
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_TIMEx_HallSensor_MspDeInit
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIMEx_PWMN_Start_DMA
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_TIMEx_OCN_Stop_DMA
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_CommutHalfCpltCallback
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
HAL_TIMEx_OnePulseN_Stop_IT
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIMEx_BreakCallback
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
HAL_TIMEx_HallSensor_MspInit
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
HAL_TIMEx_ConfigCommutEvent
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_TIMEx_HallSensor_Start_IT
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
TIMEx_DMACommutationCplt
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
HAL_TIMEx_PWMN_Start_IT
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_OnePulseN_Start
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIMEx_OCN_Stop_IT
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_ConfigCommutEvent_IT
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_TIMEx_Break2Callback
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
HAL_TIMEx_OnePulseN_Stop
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h:48
HAL_TIMEx_PWMN_Stop_IT
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_PWMN_Stop
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_OCN_Stop
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_OCN_Start
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:315
HAL_TIMEx_HallSensor_Stop_DMA
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
HAL_TIMEx_HallSensor_Start_DMA
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
HAL_TIMEx_TISelection
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
HAL_TIMEx_HallSensor_Init
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
HAL_TIM_StateTypeDef
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:288
HAL_TIM_ChannelStateTypeDef
HAL_TIM_ChannelStateTypeDef
TIM Channel States definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:310
HAL_TIMEx_HallSensor_Stop
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
HAL_TIMEx_CommutCallback
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_TIMEx_PWMN_Stop_DMA
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_OnePulseN_Start_IT
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIMEx_OCN_Start_IT
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIMEx_HallSensor_Start
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
TIM_MasterConfigTypeDef
TIM Master configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:229
HAL_TIMEx_MasterConfigSynchronization
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
HAL_TIMEx_GetChannelNState
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
HAL_TIMEx_HallSensor_GetState
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
HAL_TIMEx_ConfigCommutEvent_DMA
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_TIMEx_GroupChannel5
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
TIMEx_DMACommutationHalfCplt
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
HAL_TIMEx_HallSensor_DeInit
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:265
HAL_TIMEx_ConfigBreakDeadTime
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
HAL_TIMEx_OCN_Start_DMA
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_TIMEx_HallSensor_Stop_IT
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)

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autogenerated on Fri Apr 1 2022 02:14:55