- x -
- XBARA1
: MIMXRT1052.h
- XBARA1_BASE
: MIMXRT1052.h
- XBARA_BASE_ADDRS
: MIMXRT1052.h
- XBARA_BASE_PTRS
: MIMXRT1052.h
- XBARA_CLOCKS
: fsl_clock.h
- XBARA_CTRL0_DEN0
: MIMXRT1052.h
- XBARA_CTRL0_DEN0_MASK
: MIMXRT1052.h
- XBARA_CTRL0_DEN0_SHIFT
: MIMXRT1052.h
- XBARA_CTRL0_DEN1
: MIMXRT1052.h
- XBARA_CTRL0_DEN1_MASK
: MIMXRT1052.h
- XBARA_CTRL0_DEN1_SHIFT
: MIMXRT1052.h
- XBARA_CTRL0_EDGE0
: MIMXRT1052.h
- XBARA_CTRL0_EDGE0_MASK
: MIMXRT1052.h
- XBARA_CTRL0_EDGE0_SHIFT
: MIMXRT1052.h
- XBARA_CTRL0_EDGE1
: MIMXRT1052.h
- XBARA_CTRL0_EDGE1_MASK
: MIMXRT1052.h
- XBARA_CTRL0_EDGE1_SHIFT
: MIMXRT1052.h
- XBARA_CTRL0_IEN0
: MIMXRT1052.h
- XBARA_CTRL0_IEN0_MASK
: MIMXRT1052.h
- XBARA_CTRL0_IEN0_SHIFT
: MIMXRT1052.h
- XBARA_CTRL0_IEN1
: MIMXRT1052.h
- XBARA_CTRL0_IEN1_MASK
: MIMXRT1052.h
- XBARA_CTRL0_IEN1_SHIFT
: MIMXRT1052.h
- XBARA_CTRL0_STS0
: MIMXRT1052.h
- XBARA_CTRL0_STS0_MASK
: MIMXRT1052.h
- XBARA_CTRL0_STS0_SHIFT
: MIMXRT1052.h
- XBARA_CTRL0_STS1
: MIMXRT1052.h
- XBARA_CTRL0_STS1_MASK
: MIMXRT1052.h
- XBARA_CTRL0_STS1_SHIFT
: MIMXRT1052.h
- XBARA_CTRL1_DEN2
: MIMXRT1052.h
- XBARA_CTRL1_DEN2_MASK
: MIMXRT1052.h
- XBARA_CTRL1_DEN2_SHIFT
: MIMXRT1052.h
- XBARA_CTRL1_DEN3
: MIMXRT1052.h
- XBARA_CTRL1_DEN3_MASK
: MIMXRT1052.h
- XBARA_CTRL1_DEN3_SHIFT
: MIMXRT1052.h
- XBARA_CTRL1_EDGE2
: MIMXRT1052.h
- XBARA_CTRL1_EDGE2_MASK
: MIMXRT1052.h
- XBARA_CTRL1_EDGE2_SHIFT
: MIMXRT1052.h
- XBARA_CTRL1_EDGE3
: MIMXRT1052.h
- XBARA_CTRL1_EDGE3_MASK
: MIMXRT1052.h
- XBARA_CTRL1_EDGE3_SHIFT
: MIMXRT1052.h
- XBARA_CTRL1_IEN2
: MIMXRT1052.h
- XBARA_CTRL1_IEN2_MASK
: MIMXRT1052.h
- XBARA_CTRL1_IEN2_SHIFT
: MIMXRT1052.h
- XBARA_CTRL1_IEN3
: MIMXRT1052.h
- XBARA_CTRL1_IEN3_MASK
: MIMXRT1052.h
- XBARA_CTRL1_IEN3_SHIFT
: MIMXRT1052.h
- XBARA_CTRL1_STS2
: MIMXRT1052.h
- XBARA_CTRL1_STS2_MASK
: MIMXRT1052.h
- XBARA_CTRL1_STS2_SHIFT
: MIMXRT1052.h
- XBARA_CTRL1_STS3
: MIMXRT1052.h
- XBARA_CTRL1_STS3_MASK
: MIMXRT1052.h
- XBARA_CTRL1_STS3_SHIFT
: MIMXRT1052.h
- XBARA_SEL0_SEL0
: MIMXRT1052.h
- XBARA_SEL0_SEL0_MASK
: MIMXRT1052.h
- XBARA_SEL0_SEL0_SHIFT
: MIMXRT1052.h
- XBARA_SEL0_SEL1
: MIMXRT1052.h
- XBARA_SEL0_SEL1_MASK
: MIMXRT1052.h
- XBARA_SEL0_SEL1_SHIFT
: MIMXRT1052.h
- XBARA_SEL10_SEL20
: MIMXRT1052.h
- XBARA_SEL10_SEL20_MASK
: MIMXRT1052.h
- XBARA_SEL10_SEL20_SHIFT
: MIMXRT1052.h
- XBARA_SEL10_SEL21
: MIMXRT1052.h
- XBARA_SEL10_SEL21_MASK
: MIMXRT1052.h
- XBARA_SEL10_SEL21_SHIFT
: MIMXRT1052.h
- XBARA_SEL11_SEL22
: MIMXRT1052.h
- XBARA_SEL11_SEL22_MASK
: MIMXRT1052.h
- XBARA_SEL11_SEL22_SHIFT
: MIMXRT1052.h
- XBARA_SEL11_SEL23
: MIMXRT1052.h
- XBARA_SEL11_SEL23_MASK
: MIMXRT1052.h
- XBARA_SEL11_SEL23_SHIFT
: MIMXRT1052.h
- XBARA_SEL12_SEL24
: MIMXRT1052.h
- XBARA_SEL12_SEL24_MASK
: MIMXRT1052.h
- XBARA_SEL12_SEL24_SHIFT
: MIMXRT1052.h
- XBARA_SEL12_SEL25
: MIMXRT1052.h
- XBARA_SEL12_SEL25_MASK
: MIMXRT1052.h
- XBARA_SEL12_SEL25_SHIFT
: MIMXRT1052.h
- XBARA_SEL13_SEL26
: MIMXRT1052.h
- XBARA_SEL13_SEL26_MASK
: MIMXRT1052.h
- XBARA_SEL13_SEL26_SHIFT
: MIMXRT1052.h
- XBARA_SEL13_SEL27
: MIMXRT1052.h
- XBARA_SEL13_SEL27_MASK
: MIMXRT1052.h
- XBARA_SEL13_SEL27_SHIFT
: MIMXRT1052.h
- XBARA_SEL14_SEL28
: MIMXRT1052.h
- XBARA_SEL14_SEL28_MASK
: MIMXRT1052.h
- XBARA_SEL14_SEL28_SHIFT
: MIMXRT1052.h
- XBARA_SEL14_SEL29
: MIMXRT1052.h
- XBARA_SEL14_SEL29_MASK
: MIMXRT1052.h
- XBARA_SEL14_SEL29_SHIFT
: MIMXRT1052.h
- XBARA_SEL15_SEL30
: MIMXRT1052.h
- XBARA_SEL15_SEL30_MASK
: MIMXRT1052.h
- XBARA_SEL15_SEL30_SHIFT
: MIMXRT1052.h
- XBARA_SEL15_SEL31
: MIMXRT1052.h
- XBARA_SEL15_SEL31_MASK
: MIMXRT1052.h
- XBARA_SEL15_SEL31_SHIFT
: MIMXRT1052.h
- XBARA_SEL16_SEL32
: MIMXRT1052.h
- XBARA_SEL16_SEL32_MASK
: MIMXRT1052.h
- XBARA_SEL16_SEL32_SHIFT
: MIMXRT1052.h
- XBARA_SEL16_SEL33
: MIMXRT1052.h
- XBARA_SEL16_SEL33_MASK
: MIMXRT1052.h
- XBARA_SEL16_SEL33_SHIFT
: MIMXRT1052.h
- XBARA_SEL17_SEL34
: MIMXRT1052.h
- XBARA_SEL17_SEL34_MASK
: MIMXRT1052.h
- XBARA_SEL17_SEL34_SHIFT
: MIMXRT1052.h
- XBARA_SEL17_SEL35
: MIMXRT1052.h
- XBARA_SEL17_SEL35_MASK
: MIMXRT1052.h
- XBARA_SEL17_SEL35_SHIFT
: MIMXRT1052.h
- XBARA_SEL18_SEL36
: MIMXRT1052.h
- XBARA_SEL18_SEL36_MASK
: MIMXRT1052.h
- XBARA_SEL18_SEL36_SHIFT
: MIMXRT1052.h
- XBARA_SEL18_SEL37
: MIMXRT1052.h
- XBARA_SEL18_SEL37_MASK
: MIMXRT1052.h
- XBARA_SEL18_SEL37_SHIFT
: MIMXRT1052.h
- XBARA_SEL19_SEL38
: MIMXRT1052.h
- XBARA_SEL19_SEL38_MASK
: MIMXRT1052.h
- XBARA_SEL19_SEL38_SHIFT
: MIMXRT1052.h
- XBARA_SEL19_SEL39
: MIMXRT1052.h
- XBARA_SEL19_SEL39_MASK
: MIMXRT1052.h
- XBARA_SEL19_SEL39_SHIFT
: MIMXRT1052.h
- XBARA_SEL1_SEL2
: MIMXRT1052.h
- XBARA_SEL1_SEL2_MASK
: MIMXRT1052.h
- XBARA_SEL1_SEL2_SHIFT
: MIMXRT1052.h
- XBARA_SEL1_SEL3
: MIMXRT1052.h
- XBARA_SEL1_SEL3_MASK
: MIMXRT1052.h
- XBARA_SEL1_SEL3_SHIFT
: MIMXRT1052.h
- XBARA_SEL20_SEL40
: MIMXRT1052.h
- XBARA_SEL20_SEL40_MASK
: MIMXRT1052.h
- XBARA_SEL20_SEL40_SHIFT
: MIMXRT1052.h
- XBARA_SEL20_SEL41
: MIMXRT1052.h
- XBARA_SEL20_SEL41_MASK
: MIMXRT1052.h
- XBARA_SEL20_SEL41_SHIFT
: MIMXRT1052.h
- XBARA_SEL21_SEL42
: MIMXRT1052.h
- XBARA_SEL21_SEL42_MASK
: MIMXRT1052.h
- XBARA_SEL21_SEL42_SHIFT
: MIMXRT1052.h
- XBARA_SEL21_SEL43
: MIMXRT1052.h
- XBARA_SEL21_SEL43_MASK
: MIMXRT1052.h
- XBARA_SEL21_SEL43_SHIFT
: MIMXRT1052.h
- XBARA_SEL22_SEL44
: MIMXRT1052.h
- XBARA_SEL22_SEL44_MASK
: MIMXRT1052.h
- XBARA_SEL22_SEL44_SHIFT
: MIMXRT1052.h
- XBARA_SEL22_SEL45
: MIMXRT1052.h
- XBARA_SEL22_SEL45_MASK
: MIMXRT1052.h
- XBARA_SEL22_SEL45_SHIFT
: MIMXRT1052.h
- XBARA_SEL23_SEL46
: MIMXRT1052.h
- XBARA_SEL23_SEL46_MASK
: MIMXRT1052.h
- XBARA_SEL23_SEL46_SHIFT
: MIMXRT1052.h
- XBARA_SEL23_SEL47
: MIMXRT1052.h
- XBARA_SEL23_SEL47_MASK
: MIMXRT1052.h
- XBARA_SEL23_SEL47_SHIFT
: MIMXRT1052.h
- XBARA_SEL24_SEL48
: MIMXRT1052.h
- XBARA_SEL24_SEL48_MASK
: MIMXRT1052.h
- XBARA_SEL24_SEL48_SHIFT
: MIMXRT1052.h
- XBARA_SEL24_SEL49
: MIMXRT1052.h
- XBARA_SEL24_SEL49_MASK
: MIMXRT1052.h
- XBARA_SEL24_SEL49_SHIFT
: MIMXRT1052.h
- XBARA_SEL25_SEL50
: MIMXRT1052.h
- XBARA_SEL25_SEL50_MASK
: MIMXRT1052.h
- XBARA_SEL25_SEL50_SHIFT
: MIMXRT1052.h
- XBARA_SEL25_SEL51
: MIMXRT1052.h
- XBARA_SEL25_SEL51_MASK
: MIMXRT1052.h
- XBARA_SEL25_SEL51_SHIFT
: MIMXRT1052.h
- XBARA_SEL26_SEL52
: MIMXRT1052.h
- XBARA_SEL26_SEL52_MASK
: MIMXRT1052.h
- XBARA_SEL26_SEL52_SHIFT
: MIMXRT1052.h
- XBARA_SEL26_SEL53
: MIMXRT1052.h
- XBARA_SEL26_SEL53_MASK
: MIMXRT1052.h
- XBARA_SEL26_SEL53_SHIFT
: MIMXRT1052.h
- XBARA_SEL27_SEL54
: MIMXRT1052.h
- XBARA_SEL27_SEL54_MASK
: MIMXRT1052.h
- XBARA_SEL27_SEL54_SHIFT
: MIMXRT1052.h
- XBARA_SEL27_SEL55
: MIMXRT1052.h
- XBARA_SEL27_SEL55_MASK
: MIMXRT1052.h
- XBARA_SEL27_SEL55_SHIFT
: MIMXRT1052.h
- XBARA_SEL28_SEL56
: MIMXRT1052.h
- XBARA_SEL28_SEL56_MASK
: MIMXRT1052.h
- XBARA_SEL28_SEL56_SHIFT
: MIMXRT1052.h
- XBARA_SEL28_SEL57
: MIMXRT1052.h
- XBARA_SEL28_SEL57_MASK
: MIMXRT1052.h
- XBARA_SEL28_SEL57_SHIFT
: MIMXRT1052.h
- XBARA_SEL29_SEL58
: MIMXRT1052.h
- XBARA_SEL29_SEL58_MASK
: MIMXRT1052.h
- XBARA_SEL29_SEL58_SHIFT
: MIMXRT1052.h
- XBARA_SEL29_SEL59
: MIMXRT1052.h
- XBARA_SEL29_SEL59_MASK
: MIMXRT1052.h
- XBARA_SEL29_SEL59_SHIFT
: MIMXRT1052.h
- XBARA_SEL2_SEL4
: MIMXRT1052.h
- XBARA_SEL2_SEL4_MASK
: MIMXRT1052.h
- XBARA_SEL2_SEL4_SHIFT
: MIMXRT1052.h
- XBARA_SEL2_SEL5
: MIMXRT1052.h
- XBARA_SEL2_SEL5_MASK
: MIMXRT1052.h
- XBARA_SEL2_SEL5_SHIFT
: MIMXRT1052.h
- XBARA_SEL30_SEL60
: MIMXRT1052.h
- XBARA_SEL30_SEL60_MASK
: MIMXRT1052.h
- XBARA_SEL30_SEL60_SHIFT
: MIMXRT1052.h
- XBARA_SEL30_SEL61
: MIMXRT1052.h
- XBARA_SEL30_SEL61_MASK
: MIMXRT1052.h
- XBARA_SEL30_SEL61_SHIFT
: MIMXRT1052.h
- XBARA_SEL31_SEL62
: MIMXRT1052.h
- XBARA_SEL31_SEL62_MASK
: MIMXRT1052.h
- XBARA_SEL31_SEL62_SHIFT
: MIMXRT1052.h
- XBARA_SEL31_SEL63
: MIMXRT1052.h
- XBARA_SEL31_SEL63_MASK
: MIMXRT1052.h
- XBARA_SEL31_SEL63_SHIFT
: MIMXRT1052.h
- XBARA_SEL32_SEL64
: MIMXRT1052.h
- XBARA_SEL32_SEL64_MASK
: MIMXRT1052.h
- XBARA_SEL32_SEL64_SHIFT
: MIMXRT1052.h
- XBARA_SEL32_SEL65
: MIMXRT1052.h
- XBARA_SEL32_SEL65_MASK
: MIMXRT1052.h
- XBARA_SEL32_SEL65_SHIFT
: MIMXRT1052.h
- XBARA_SEL33_SEL66
: MIMXRT1052.h
- XBARA_SEL33_SEL66_MASK
: MIMXRT1052.h
- XBARA_SEL33_SEL66_SHIFT
: MIMXRT1052.h
- XBARA_SEL33_SEL67
: MIMXRT1052.h
- XBARA_SEL33_SEL67_MASK
: MIMXRT1052.h
- XBARA_SEL33_SEL67_SHIFT
: MIMXRT1052.h
- XBARA_SEL34_SEL68
: MIMXRT1052.h
- XBARA_SEL34_SEL68_MASK
: MIMXRT1052.h
- XBARA_SEL34_SEL68_SHIFT
: MIMXRT1052.h
- XBARA_SEL34_SEL69
: MIMXRT1052.h
- XBARA_SEL34_SEL69_MASK
: MIMXRT1052.h
- XBARA_SEL34_SEL69_SHIFT
: MIMXRT1052.h
- XBARA_SEL35_SEL70
: MIMXRT1052.h
- XBARA_SEL35_SEL70_MASK
: MIMXRT1052.h
- XBARA_SEL35_SEL70_SHIFT
: MIMXRT1052.h
- XBARA_SEL35_SEL71
: MIMXRT1052.h
- XBARA_SEL35_SEL71_MASK
: MIMXRT1052.h
- XBARA_SEL35_SEL71_SHIFT
: MIMXRT1052.h
- XBARA_SEL36_SEL72
: MIMXRT1052.h
- XBARA_SEL36_SEL72_MASK
: MIMXRT1052.h
- XBARA_SEL36_SEL72_SHIFT
: MIMXRT1052.h
- XBARA_SEL36_SEL73
: MIMXRT1052.h
- XBARA_SEL36_SEL73_MASK
: MIMXRT1052.h
- XBARA_SEL36_SEL73_SHIFT
: MIMXRT1052.h
- XBARA_SEL37_SEL74
: MIMXRT1052.h
- XBARA_SEL37_SEL74_MASK
: MIMXRT1052.h
- XBARA_SEL37_SEL74_SHIFT
: MIMXRT1052.h
- XBARA_SEL37_SEL75
: MIMXRT1052.h
- XBARA_SEL37_SEL75_MASK
: MIMXRT1052.h
- XBARA_SEL37_SEL75_SHIFT
: MIMXRT1052.h
- XBARA_SEL38_SEL76
: MIMXRT1052.h
- XBARA_SEL38_SEL76_MASK
: MIMXRT1052.h
- XBARA_SEL38_SEL76_SHIFT
: MIMXRT1052.h
- XBARA_SEL38_SEL77
: MIMXRT1052.h
- XBARA_SEL38_SEL77_MASK
: MIMXRT1052.h
- XBARA_SEL38_SEL77_SHIFT
: MIMXRT1052.h
- XBARA_SEL39_SEL78
: MIMXRT1052.h
- XBARA_SEL39_SEL78_MASK
: MIMXRT1052.h
- XBARA_SEL39_SEL78_SHIFT
: MIMXRT1052.h
- XBARA_SEL39_SEL79
: MIMXRT1052.h
- XBARA_SEL39_SEL79_MASK
: MIMXRT1052.h
- XBARA_SEL39_SEL79_SHIFT
: MIMXRT1052.h
- XBARA_SEL3_SEL6
: MIMXRT1052.h
- XBARA_SEL3_SEL6_MASK
: MIMXRT1052.h
- XBARA_SEL3_SEL6_SHIFT
: MIMXRT1052.h
- XBARA_SEL3_SEL7
: MIMXRT1052.h
- XBARA_SEL3_SEL7_MASK
: MIMXRT1052.h
- XBARA_SEL3_SEL7_SHIFT
: MIMXRT1052.h
- XBARA_SEL40_SEL80
: MIMXRT1052.h
- XBARA_SEL40_SEL80_MASK
: MIMXRT1052.h
- XBARA_SEL40_SEL80_SHIFT
: MIMXRT1052.h
- XBARA_SEL40_SEL81
: MIMXRT1052.h
- XBARA_SEL40_SEL81_MASK
: MIMXRT1052.h
- XBARA_SEL40_SEL81_SHIFT
: MIMXRT1052.h
- XBARA_SEL41_SEL82
: MIMXRT1052.h
- XBARA_SEL41_SEL82_MASK
: MIMXRT1052.h
- XBARA_SEL41_SEL82_SHIFT
: MIMXRT1052.h
- XBARA_SEL41_SEL83
: MIMXRT1052.h
- XBARA_SEL41_SEL83_MASK
: MIMXRT1052.h
- XBARA_SEL41_SEL83_SHIFT
: MIMXRT1052.h
- XBARA_SEL42_SEL84
: MIMXRT1052.h
- XBARA_SEL42_SEL84_MASK
: MIMXRT1052.h
- XBARA_SEL42_SEL84_SHIFT
: MIMXRT1052.h
- XBARA_SEL42_SEL85
: MIMXRT1052.h
- XBARA_SEL42_SEL85_MASK
: MIMXRT1052.h
- XBARA_SEL42_SEL85_SHIFT
: MIMXRT1052.h
- XBARA_SEL43_SEL86
: MIMXRT1052.h
- XBARA_SEL43_SEL86_MASK
: MIMXRT1052.h
- XBARA_SEL43_SEL86_SHIFT
: MIMXRT1052.h
- XBARA_SEL43_SEL87
: MIMXRT1052.h
- XBARA_SEL43_SEL87_MASK
: MIMXRT1052.h
- XBARA_SEL43_SEL87_SHIFT
: MIMXRT1052.h
- XBARA_SEL44_SEL88
: MIMXRT1052.h
- XBARA_SEL44_SEL88_MASK
: MIMXRT1052.h
- XBARA_SEL44_SEL88_SHIFT
: MIMXRT1052.h
- XBARA_SEL44_SEL89
: MIMXRT1052.h
- XBARA_SEL44_SEL89_MASK
: MIMXRT1052.h
- XBARA_SEL44_SEL89_SHIFT
: MIMXRT1052.h
- XBARA_SEL45_SEL90
: MIMXRT1052.h
- XBARA_SEL45_SEL90_MASK
: MIMXRT1052.h
- XBARA_SEL45_SEL90_SHIFT
: MIMXRT1052.h
- XBARA_SEL45_SEL91
: MIMXRT1052.h
- XBARA_SEL45_SEL91_MASK
: MIMXRT1052.h
- XBARA_SEL45_SEL91_SHIFT
: MIMXRT1052.h
- XBARA_SEL46_SEL92
: MIMXRT1052.h
- XBARA_SEL46_SEL92_MASK
: MIMXRT1052.h
- XBARA_SEL46_SEL92_SHIFT
: MIMXRT1052.h
- XBARA_SEL46_SEL93
: MIMXRT1052.h
- XBARA_SEL46_SEL93_MASK
: MIMXRT1052.h
- XBARA_SEL46_SEL93_SHIFT
: MIMXRT1052.h
- XBARA_SEL47_SEL94
: MIMXRT1052.h
- XBARA_SEL47_SEL94_MASK
: MIMXRT1052.h
- XBARA_SEL47_SEL94_SHIFT
: MIMXRT1052.h
- XBARA_SEL47_SEL95
: MIMXRT1052.h
- XBARA_SEL47_SEL95_MASK
: MIMXRT1052.h
- XBARA_SEL47_SEL95_SHIFT
: MIMXRT1052.h
- XBARA_SEL48_SEL96
: MIMXRT1052.h
- XBARA_SEL48_SEL96_MASK
: MIMXRT1052.h
- XBARA_SEL48_SEL96_SHIFT
: MIMXRT1052.h
- XBARA_SEL48_SEL97
: MIMXRT1052.h
- XBARA_SEL48_SEL97_MASK
: MIMXRT1052.h
- XBARA_SEL48_SEL97_SHIFT
: MIMXRT1052.h
- XBARA_SEL49_SEL98
: MIMXRT1052.h
- XBARA_SEL49_SEL98_MASK
: MIMXRT1052.h
- XBARA_SEL49_SEL98_SHIFT
: MIMXRT1052.h
- XBARA_SEL49_SEL99
: MIMXRT1052.h
- XBARA_SEL49_SEL99_MASK
: MIMXRT1052.h
- XBARA_SEL49_SEL99_SHIFT
: MIMXRT1052.h
- XBARA_SEL4_SEL8
: MIMXRT1052.h
- XBARA_SEL4_SEL8_MASK
: MIMXRT1052.h
- XBARA_SEL4_SEL8_SHIFT
: MIMXRT1052.h
- XBARA_SEL4_SEL9
: MIMXRT1052.h
- XBARA_SEL4_SEL9_MASK
: MIMXRT1052.h
- XBARA_SEL4_SEL9_SHIFT
: MIMXRT1052.h
- XBARA_SEL50_SEL100
: MIMXRT1052.h
- XBARA_SEL50_SEL100_MASK
: MIMXRT1052.h
- XBARA_SEL50_SEL100_SHIFT
: MIMXRT1052.h
- XBARA_SEL50_SEL101
: MIMXRT1052.h
- XBARA_SEL50_SEL101_MASK
: MIMXRT1052.h
- XBARA_SEL50_SEL101_SHIFT
: MIMXRT1052.h
- XBARA_SEL51_SEL102
: MIMXRT1052.h
- XBARA_SEL51_SEL102_MASK
: MIMXRT1052.h
- XBARA_SEL51_SEL102_SHIFT
: MIMXRT1052.h
- XBARA_SEL51_SEL103
: MIMXRT1052.h
- XBARA_SEL51_SEL103_MASK
: MIMXRT1052.h
- XBARA_SEL51_SEL103_SHIFT
: MIMXRT1052.h
- XBARA_SEL52_SEL104
: MIMXRT1052.h
- XBARA_SEL52_SEL104_MASK
: MIMXRT1052.h
- XBARA_SEL52_SEL104_SHIFT
: MIMXRT1052.h
- XBARA_SEL52_SEL105
: MIMXRT1052.h
- XBARA_SEL52_SEL105_MASK
: MIMXRT1052.h
- XBARA_SEL52_SEL105_SHIFT
: MIMXRT1052.h
- XBARA_SEL53_SEL106
: MIMXRT1052.h
- XBARA_SEL53_SEL106_MASK
: MIMXRT1052.h
- XBARA_SEL53_SEL106_SHIFT
: MIMXRT1052.h
- XBARA_SEL53_SEL107
: MIMXRT1052.h
- XBARA_SEL53_SEL107_MASK
: MIMXRT1052.h
- XBARA_SEL53_SEL107_SHIFT
: MIMXRT1052.h
- XBARA_SEL54_SEL108
: MIMXRT1052.h
- XBARA_SEL54_SEL108_MASK
: MIMXRT1052.h
- XBARA_SEL54_SEL108_SHIFT
: MIMXRT1052.h
- XBARA_SEL54_SEL109
: MIMXRT1052.h
- XBARA_SEL54_SEL109_MASK
: MIMXRT1052.h
- XBARA_SEL54_SEL109_SHIFT
: MIMXRT1052.h
- XBARA_SEL55_SEL110
: MIMXRT1052.h
- XBARA_SEL55_SEL110_MASK
: MIMXRT1052.h
- XBARA_SEL55_SEL110_SHIFT
: MIMXRT1052.h
- XBARA_SEL55_SEL111
: MIMXRT1052.h
- XBARA_SEL55_SEL111_MASK
: MIMXRT1052.h
- XBARA_SEL55_SEL111_SHIFT
: MIMXRT1052.h
- XBARA_SEL56_SEL112
: MIMXRT1052.h
- XBARA_SEL56_SEL112_MASK
: MIMXRT1052.h
- XBARA_SEL56_SEL112_SHIFT
: MIMXRT1052.h
- XBARA_SEL56_SEL113
: MIMXRT1052.h
- XBARA_SEL56_SEL113_MASK
: MIMXRT1052.h
- XBARA_SEL56_SEL113_SHIFT
: MIMXRT1052.h
- XBARA_SEL57_SEL114
: MIMXRT1052.h
- XBARA_SEL57_SEL114_MASK
: MIMXRT1052.h
- XBARA_SEL57_SEL114_SHIFT
: MIMXRT1052.h
- XBARA_SEL57_SEL115
: MIMXRT1052.h
- XBARA_SEL57_SEL115_MASK
: MIMXRT1052.h
- XBARA_SEL57_SEL115_SHIFT
: MIMXRT1052.h
- XBARA_SEL58_SEL116
: MIMXRT1052.h
- XBARA_SEL58_SEL116_MASK
: MIMXRT1052.h
- XBARA_SEL58_SEL116_SHIFT
: MIMXRT1052.h
- XBARA_SEL58_SEL117
: MIMXRT1052.h
- XBARA_SEL58_SEL117_MASK
: MIMXRT1052.h
- XBARA_SEL58_SEL117_SHIFT
: MIMXRT1052.h
- XBARA_SEL59_SEL118
: MIMXRT1052.h
- XBARA_SEL59_SEL118_MASK
: MIMXRT1052.h
- XBARA_SEL59_SEL118_SHIFT
: MIMXRT1052.h
- XBARA_SEL59_SEL119
: MIMXRT1052.h
- XBARA_SEL59_SEL119_MASK
: MIMXRT1052.h
- XBARA_SEL59_SEL119_SHIFT
: MIMXRT1052.h
- XBARA_SEL5_SEL10
: MIMXRT1052.h
- XBARA_SEL5_SEL10_MASK
: MIMXRT1052.h
- XBARA_SEL5_SEL10_SHIFT
: MIMXRT1052.h
- XBARA_SEL5_SEL11
: MIMXRT1052.h
- XBARA_SEL5_SEL11_MASK
: MIMXRT1052.h
- XBARA_SEL5_SEL11_SHIFT
: MIMXRT1052.h
- XBARA_SEL60_SEL120
: MIMXRT1052.h
- XBARA_SEL60_SEL120_MASK
: MIMXRT1052.h
- XBARA_SEL60_SEL120_SHIFT
: MIMXRT1052.h
- XBARA_SEL60_SEL121
: MIMXRT1052.h
- XBARA_SEL60_SEL121_MASK
: MIMXRT1052.h
- XBARA_SEL60_SEL121_SHIFT
: MIMXRT1052.h
- XBARA_SEL61_SEL122
: MIMXRT1052.h
- XBARA_SEL61_SEL122_MASK
: MIMXRT1052.h
- XBARA_SEL61_SEL122_SHIFT
: MIMXRT1052.h
- XBARA_SEL61_SEL123
: MIMXRT1052.h
- XBARA_SEL61_SEL123_MASK
: MIMXRT1052.h
- XBARA_SEL61_SEL123_SHIFT
: MIMXRT1052.h
- XBARA_SEL62_SEL124
: MIMXRT1052.h
- XBARA_SEL62_SEL124_MASK
: MIMXRT1052.h
- XBARA_SEL62_SEL124_SHIFT
: MIMXRT1052.h
- XBARA_SEL62_SEL125
: MIMXRT1052.h
- XBARA_SEL62_SEL125_MASK
: MIMXRT1052.h
- XBARA_SEL62_SEL125_SHIFT
: MIMXRT1052.h
- XBARA_SEL63_SEL126
: MIMXRT1052.h
- XBARA_SEL63_SEL126_MASK
: MIMXRT1052.h
- XBARA_SEL63_SEL126_SHIFT
: MIMXRT1052.h
- XBARA_SEL63_SEL127
: MIMXRT1052.h
- XBARA_SEL63_SEL127_MASK
: MIMXRT1052.h
- XBARA_SEL63_SEL127_SHIFT
: MIMXRT1052.h
- XBARA_SEL64_SEL128
: MIMXRT1052.h
- XBARA_SEL64_SEL128_MASK
: MIMXRT1052.h
- XBARA_SEL64_SEL128_SHIFT
: MIMXRT1052.h
- XBARA_SEL64_SEL129
: MIMXRT1052.h
- XBARA_SEL64_SEL129_MASK
: MIMXRT1052.h
- XBARA_SEL64_SEL129_SHIFT
: MIMXRT1052.h
- XBARA_SEL65_SEL130
: MIMXRT1052.h
- XBARA_SEL65_SEL130_MASK
: MIMXRT1052.h
- XBARA_SEL65_SEL130_SHIFT
: MIMXRT1052.h
- XBARA_SEL65_SEL131
: MIMXRT1052.h
- XBARA_SEL65_SEL131_MASK
: MIMXRT1052.h
- XBARA_SEL65_SEL131_SHIFT
: MIMXRT1052.h
- XBARA_SEL6_SEL12
: MIMXRT1052.h
- XBARA_SEL6_SEL12_MASK
: MIMXRT1052.h
- XBARA_SEL6_SEL12_SHIFT
: MIMXRT1052.h
- XBARA_SEL6_SEL13
: MIMXRT1052.h
- XBARA_SEL6_SEL13_MASK
: MIMXRT1052.h
- XBARA_SEL6_SEL13_SHIFT
: MIMXRT1052.h
- XBARA_SEL7_SEL14
: MIMXRT1052.h
- XBARA_SEL7_SEL14_MASK
: MIMXRT1052.h
- XBARA_SEL7_SEL14_SHIFT
: MIMXRT1052.h
- XBARA_SEL7_SEL15
: MIMXRT1052.h
- XBARA_SEL7_SEL15_MASK
: MIMXRT1052.h
- XBARA_SEL7_SEL15_SHIFT
: MIMXRT1052.h
- XBARA_SEL8_SEL16
: MIMXRT1052.h
- XBARA_SEL8_SEL16_MASK
: MIMXRT1052.h
- XBARA_SEL8_SEL16_SHIFT
: MIMXRT1052.h
- XBARA_SEL8_SEL17
: MIMXRT1052.h
- XBARA_SEL8_SEL17_MASK
: MIMXRT1052.h
- XBARA_SEL8_SEL17_SHIFT
: MIMXRT1052.h
- XBARA_SEL9_SEL18
: MIMXRT1052.h
- XBARA_SEL9_SEL18_MASK
: MIMXRT1052.h
- XBARA_SEL9_SEL18_SHIFT
: MIMXRT1052.h
- XBARA_SEL9_SEL19
: MIMXRT1052.h
- XBARA_SEL9_SEL19_MASK
: MIMXRT1052.h
- XBARA_SEL9_SEL19_SHIFT
: MIMXRT1052.h
- XBARB2
: MIMXRT1052.h
- XBARB2_BASE
: MIMXRT1052.h
- XBARB3
: MIMXRT1052.h
- XBARB3_BASE
: MIMXRT1052.h
- XBARB_BASE_ADDRS
: MIMXRT1052.h
- XBARB_BASE_PTRS
: MIMXRT1052.h
- XBARB_CLOCKS
: fsl_clock.h
- XBARB_SEL0_SEL0
: MIMXRT1052.h
- XBARB_SEL0_SEL0_MASK
: MIMXRT1052.h
- XBARB_SEL0_SEL0_SHIFT
: MIMXRT1052.h
- XBARB_SEL0_SEL1
: MIMXRT1052.h
- XBARB_SEL0_SEL1_MASK
: MIMXRT1052.h
- XBARB_SEL0_SEL1_SHIFT
: MIMXRT1052.h
- XBARB_SEL1_SEL2
: MIMXRT1052.h
- XBARB_SEL1_SEL2_MASK
: MIMXRT1052.h
- XBARB_SEL1_SEL2_SHIFT
: MIMXRT1052.h
- XBARB_SEL1_SEL3
: MIMXRT1052.h
- XBARB_SEL1_SEL3_MASK
: MIMXRT1052.h
- XBARB_SEL1_SEL3_SHIFT
: MIMXRT1052.h
- XBARB_SEL2_SEL4
: MIMXRT1052.h
- XBARB_SEL2_SEL4_MASK
: MIMXRT1052.h
- XBARB_SEL2_SEL4_SHIFT
: MIMXRT1052.h
- XBARB_SEL2_SEL5
: MIMXRT1052.h
- XBARB_SEL2_SEL5_MASK
: MIMXRT1052.h
- XBARB_SEL2_SEL5_SHIFT
: MIMXRT1052.h
- XBARB_SEL3_SEL6
: MIMXRT1052.h
- XBARB_SEL3_SEL6_MASK
: MIMXRT1052.h
- XBARB_SEL3_SEL6_SHIFT
: MIMXRT1052.h
- XBARB_SEL3_SEL7
: MIMXRT1052.h
- XBARB_SEL3_SEL7_MASK
: MIMXRT1052.h
- XBARB_SEL3_SEL7_SHIFT
: MIMXRT1052.h
- XBARB_SEL4_SEL8
: MIMXRT1052.h
- XBARB_SEL4_SEL8_MASK
: MIMXRT1052.h
- XBARB_SEL4_SEL8_SHIFT
: MIMXRT1052.h
- XBARB_SEL4_SEL9
: MIMXRT1052.h
- XBARB_SEL4_SEL9_MASK
: MIMXRT1052.h
- XBARB_SEL4_SEL9_SHIFT
: MIMXRT1052.h
- XBARB_SEL5_SEL10
: MIMXRT1052.h
- XBARB_SEL5_SEL10_MASK
: MIMXRT1052.h
- XBARB_SEL5_SEL10_SHIFT
: MIMXRT1052.h
- XBARB_SEL5_SEL11
: MIMXRT1052.h
- XBARB_SEL5_SEL11_MASK
: MIMXRT1052.h
- XBARB_SEL5_SEL11_SHIFT
: MIMXRT1052.h
- XBARB_SEL6_SEL12
: MIMXRT1052.h
- XBARB_SEL6_SEL12_MASK
: MIMXRT1052.h
- XBARB_SEL6_SEL12_SHIFT
: MIMXRT1052.h
- XBARB_SEL6_SEL13
: MIMXRT1052.h
- XBARB_SEL6_SEL13_MASK
: MIMXRT1052.h
- XBARB_SEL6_SEL13_SHIFT
: MIMXRT1052.h
- XBARB_SEL7_SEL14
: MIMXRT1052.h
- XBARB_SEL7_SEL14_MASK
: MIMXRT1052.h
- XBARB_SEL7_SEL14_SHIFT
: MIMXRT1052.h
- XBARB_SEL7_SEL15
: MIMXRT1052.h
- XBARB_SEL7_SEL15_MASK
: MIMXRT1052.h
- XBARB_SEL7_SEL15_SHIFT
: MIMXRT1052.h
- xPSR_C_Msk
: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h
, stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h
, core_armv81mml.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h
, core_cm35p.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h
, stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h
, stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h
, imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h
- xPSR_C_Pos
: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h
, stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h
, core_armv81mml.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h
, core_cm35p.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h
, stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h
, stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h
, stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h
- xPSR_GE_Msk
: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h
, stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h
, stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h
, stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h
, core_armv81mml.h
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- XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_LPBG_SEL
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_LPBG_TEST
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_OSC_SEL
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK
: MIMXRT1052.h
- XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLKGATE_CTRL
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLKGATE_CTRL_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLKGATE_DELAY
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLKGATE_DELAY_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_CLKGATE_CTRL
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_CLKGATE_DELAY
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_I
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_I_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_I_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_XTALOK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_PWD
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_VBGUP
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_XTAL_24M_PWD
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_DISCON_HIGH_SNVS
: MIMXRT1052.h
- XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_I
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_I_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_I_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_XTALOK
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_XTALOK_EN
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_XTALOK_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_OSC_XTALOK_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_PWD
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_PWD_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_PWD_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_SELFBIASOFF
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_VBGADJ
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_VBGUP
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_VBGUP_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_RTC_XTAL_SOURCE
: MIMXRT1052.h
- XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_CLKGATE_CTRL
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_CLKGATE_DELAY
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_I
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_I_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_I_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_XTALOK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_XTALOK_EN
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_PWD
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_VBGADJ
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_VBGUP
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_VID_PLL_PREDIV
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_XTAL_24M_PWD
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_STOP_MODE_CONFIG
: MIMXRT1052.h
- XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_CLKGATE_CTRL
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_CLKGATE_DELAY
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_I
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_I_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_I_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_XTALOK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_PWD
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_VBGUP
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_XTAL_24M_PWD
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_VID_PLL_PREDIV
: MIMXRT1052.h
- XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT
: MIMXRT1052.h
- XTALOSC24M_MISC0_XTAL_24M_PWD
: MIMXRT1052.h
- XTALOSC24M_MISC0_XTAL_24M_PWD_MASK
: MIMXRT1052.h
- XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_BYPASS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_BYPASS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_BYPASS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_ENABLE
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_INVERT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_START
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_START_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_ENABLE
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_ENABLE_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_HYST_MINUS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_HYST_PLUS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_INVERT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_INVERT_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_BYPASS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_ENABLE
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_INVERT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_START
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_START_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_START
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_START_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_START_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_BYPASS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_ENABLE
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_INVERT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_START
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_START_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_ENABLE_1M
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_MUX_1M
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_MUX_1M
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK
: MIMXRT1052.h
- XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT
: MIMXRT1052.h