hw-libs/libchip/include/usbhs.h
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29 
32 #ifndef USBHS_H
33 #define USBHS_H
34 
38 #include <assert.h>
39 
40 #define USB_DEVICE_HS_SUPPORT
41 
43 #define USB_DEVICE_EP_CTRL_SIZE 64
44 
46 #define CHIP_USB_UDP
47 
49 #define CHIP_USB_PULLUP_INTERNAL
50 
52 #define CHIP_USB_NUMENDPOINTS 10
53 
55 #define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \
56  ((ep == 0) ? 64 : 1024)
57 
59 #define CHIP_USB_ENDPOINTS_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2))
60 
61 
62 #define CHIP_USB_ENDPOINTS_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false)
63 
65 #define CHIP_USB_ENDPOINTS_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false)
66 
68 #define DMA_MAX_FIFO_SIZE (65536/1)
69 
70 #define EPT_VIRTUAL_SIZE 8192
71 
72 
77 #define uhd_get_pipe_max_nbr() (9)
78 #define USBHS_EPT_NUM (uhd_get_pipe_max_nbr()+1)
79 #define uhd_get_pipe_bank_max_nbr(ep) ((ep == 0) ? 1 : ((ep <= 2) ? 3 : 2))
81 #define uhd_get_pipe_size_max(ep) (((ep) == 0) ? 64 : 1024)
83 #define Is_uhd_pipe_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 7)) ? true : false)
85 #define Is_uhd_pipe_high_bw_supported(ep) (((ep) >= 2) ? true : false)
87 
89 typedef enum {
90  HOST_MODE = 0,
92 } USB_Mode_t;
93 
95 #define UHD_PIPE_MAX_TRANS 0x8000
96 
108 __STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs)
109 {
110  pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
111 }
112 
118 __STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs)
119 {
120  pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK);
121 }
127 __STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable)
128 {
129 
130  if (!Enable)
131  pUsbhs->USBHS_CTRL |= (1 << 8);
132  else
133  pUsbhs->USBHS_CTRL &= ~((uint32_t)(1 << 8));
134 }
135 
142 __STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable)
143 {
144  if (Enable)
145  pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE;
146  else
147  pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE);
148 }
149 
150 
157 __STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode)
158 {
159  if (Mode)
161  else
162  pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE);
163 }
164 
165 /********************* USBHS_SR *****************/
166 
173 __STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs)
174 {
175  return ((pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14);
176 }
177 
178 
185 __STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs)
186 {
187  return (pUsbhs->USBHS_SR);
188 }
189 
196 __STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs)
197 {
198  return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk));
199 }
200 
201 
208 __STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs)
209 {
210  return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ?
211  true : false;
212 }
213 
214 
221 __STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs)
222 {
223  return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ?
224  true : false;
225 }
226 
233 __STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs)
234 {
235  return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ?
236  true : false;
237 }
238 /********************* USBHS_SCR *****************/
239 
246 __STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType)
247 {
248  pUsbhs->USBHS_SCR |= AckType;
249 }
250 
251 /********************* USBHS_SFR *****************/
252 
259 __STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus)
260 {
261  pUsbhs->USBHS_SFR |= SetStatus;
262 }
263 
264 
265 /*--------------------------------------------------------
266 * =========== USB Device functions ======================
267 *---------------------------------------------------------*/
268 
275 __STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable)
276 {
277  if (Enable)
279  else
280  pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN);
281 }
282 
289 __STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr)
290 {
291  pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr);
293 }
294 
300 __STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs)
301 {
302  return (pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk);
303 }
304 
311 __STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable)
312 {
313  if (Enable)
315  else
316  pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH);
317 
318 }
319 
326 __STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable)
327 {
328  if (Enable)
329  pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS;
330  else
331  pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS);
332 }
333 
340 __STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable)
341 {
342  uint32_t cfg = pUsbhs->USBHS_DEVCTRL;
343  cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk);
344 
345  if (Enable)
346  pUsbhs->USBHS_DEVCTRL |= cfg;
347  else
349 
350 }
351 
357 __STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs)
358 {
360 }
361 
368 __STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode)
369 {
370  pUsbhs->USBHS_DEVCTRL |= mode;
371 }
372 
373 
379 __STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs)
380 {
382 }
383 
390 __STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType)
391 {
392  return (pUsbhs->USBHS_DEVISR & IntType);
393 }
394 
401 __STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum)
402 {
403  return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_PEP_0 << EpNum));
404 }
405 
411 __STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum)
412 {
413  return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_DMA_1 << DmaNum));
414 }
415 
422 __STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType)
423 {
424  pUsbhs->USBHS_DEVICR |= IntType;
425 }
426 
434 __STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType)
435 {
436  pUsbhs->USBHS_DEVIFR |= IntType;
437 }
438 
444 __STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma)
445 {
446  assert(Dma < USBHSDEVDMA_NUMBER);
447  pUsbhs->USBHS_DEVIFR |= (USBHS_DEVIFR_DMA_1 << Dma);
448 }
449 
456 __STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType)
457 {
458  return (pUsbhs->USBHS_DEVIMR & IntType);
459 }
460 
467 __STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum)
468 {
469  return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_PEP_0 << EpNum));
470 }
471 
472 
480 __STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum)
481 {
482  return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_DMA_1 << DmaNum));
483 }
484 
485 
491 __STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType)
492 {
493  pUsbhs->USBHS_DEVIER |= IntType;
494 }
495 
501 __STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum)
502 {
503  pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_PEP_0 << EpNum);
504 }
505 
512 __STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp)
513 {
514  assert(DmaEp < USBHSDEVDMA_NUMBER);
515  pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_DMA_1 << DmaEp);
516 }
517 
524 __STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType)
525 {
526  pUsbhs->USBHS_DEVIDR |= IntType;
527 }
528 
535 __STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep)
536 {
537  pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_PEP_0 << Ep);
538 }
539 
545 __STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp)
546 {
547  assert(DmaEp < USBHSDEVDMA_NUMBER);
548  pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_DMA_1 << DmaEp);
549 }
550 
551 
558 __STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
559 {
560  if (Enable)
561  pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep);
562  else
563  pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep);
564 
565 }
566 
567 
574 __STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep)
575 {
576  pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPRST0 << Ep);
577  pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPRST0 << Ep);
578 }
579 
586 __STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep)
587 {
588  return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep));
589 }
590 
596 __STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs)
597 {
598  return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk);
599 }
600 
601 
607 __STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs)
608 {
609  return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk)
611 }
612 
618 __STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs)
619 {
620  return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15);
621 }
622 
623 /*-----------------------------------------
624 * =========== USB Device's Endpoint functions ========
625 *------------------------------------------*/
626 
631 __STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep,
632  const uint8_t Type, const uint8_t Dir,
633  const uint8_t Size, const uint8_t Bank)
634 {
635 
636  pUsbhs->USBHS_DEVEPTCFG[Ep] |=
638  pUsbhs->USBHS_DEVEPTCFG[Ep] |=
639  ((Dir << 8) & USBHS_DEVEPTCFG_EPDIR);
640  pUsbhs->USBHS_DEVEPTCFG[Ep] |=
642  pUsbhs->USBHS_DEVEPTCFG[Ep] |=
644 }
645 
646 
650 __STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep,
651  uint8_t Enable)
652 {
653  if (Enable)
655  else
656  pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW);
657 }
658 
659 
663 __STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep)
664 {
665  pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_ALLOC;
666 }
667 
668 
672 __STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep)
673 {
674  pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC);
675 }
676 
677 
681 __STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep,
682  uint32_t IntType)
683 {
684  return ((pUsbhs->USBHS_DEVEPTCFG[Ep]) & IntType);
685 }
686 
690 __STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep)
691 {
692  return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk)
694 }
695 
699 __STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep)
700 {
701  return (8 << ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk)
703 }
704 
705 
709 __STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep,
710  uint8_t nbTrans)
711 {
712  pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans);
713 }
714 
718 __STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep,
719  uint32_t EpIntType)
720 {
721  return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType);
722 }
723 
724 
728 __STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep,
729  uint32_t EpInt)
730 {
731  pUsbhs->USBHS_DEVEPTIER[Ep] |= EpInt;
732 }
733 
737 __STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep)
738 {
739  return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK);
740 }
741 
745 __STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep)
746 {
748 }
752 __STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep,
753  uint32_t EpInt)
754 {
755  pUsbhs->USBHS_DEVEPTIDR[Ep] |= EpInt;
756 }
757 
761 __STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep,
762  uint32_t EpInt)
763 {
764  pUsbhs->USBHS_DEVEPTICR[Ep] |= EpInt;
765 }
766 
770 __STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
771 {
772  pUsbhs->USBHS_DEVEPTIFR[Ep] |= EpInt;
773 }
774 
778 __STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep,
779  uint32_t EpInt)
780 {
781  return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt);
782 }
783 
787 __STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep)
788 {
789  if ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk))
790  return false;
791  else
792  return true;
793 }
794 
798 __STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep)
799 {
800  return ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)
802 }
803 
804 
808 __STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep)
809 {
810  return (uint16_t)((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk)
812 }
813 
814 /*--------------------------------------------------------
815 * =========== USB Device's Ep's DMA functions =========
816 *---------------------------------------------------------*/
817 
823 __STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc)
824 {
825  pUsbDma->USBHS_DEVDMANXTDSC = Desc;
826 }
827 
833 __STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma)
834 {
835  return (pUsbDma->USBHS_DEVDMANXTDSC);
836 }
837 
843 __STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr)
844 {
845  pUsbDma->USBHS_DEVDMAADDRESS = Addr;
846 }
847 
848 
854 __STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma)
855 {
856  return (pUsbDma->USBHS_DEVDMAADDRESS);
857 }
858 
864 __STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg)
865 {
866  pUsbDma->USBHS_DEVDMACONTROL |= Cfg;
867 }
868 
874 __STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma)
875 {
876  return (pUsbDma->USBHS_DEVDMACONTROL);
877 }
878 
879 
885 __STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status)
886 {
887  pUsbDma->USBHS_DEVDMASTATUS = Status;
888 }
889 
890 
896 __STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma)
897 {
898  return (pUsbDma->USBHS_DEVDMASTATUS);
899 }
900 
901 
907 __STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma)
908 {
911 }
912 
913 
914 /*--------------------------------------------------------
915 * =========== USB Host Functions ========================
916 *---------------------------------------------------------*/
917 
919 #define CHIP_USB_NUMPIPE 10
920 
921 #define CHIP_USB_DMA_NUMPIPE 7
922 
924 #define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \
925  ((ep == 0) ? 64 : 1024)
926 
928 #define CHIP_USB_PIPE_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2))
929 
930 
931 #define CHIP_USB_PIPE_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false)
932 
934 #define CHIP_USB_PIPE_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false)
935 
940 __STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs)
941 {
944 }
945 
950 __STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs)
951 {
954 }
955 
960 __STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs)
961 {
964 }
965 
970 __STATIC_INLINE void USBHS_Reset(void)
971 {
972  USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET;
973 }
974 
979 __STATIC_INLINE void USBHS_StopReset(void)
980 {
981  USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET;
982 }
983 
988 __STATIC_INLINE void USBHS_Resume(void)
989 {
990  USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME;
991 }
992 
997 __STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs)
998 {
1000 }
1001 
1006 __STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs)
1007 {
1008  return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8;
1009 }
1014 __STATIC_INLINE void USBHS_DisableSOF(void)
1015 {
1016  USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE;
1017 }
1018 
1023 __STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType)
1024 {
1025  return (pUsbhs->USBHS_HSTISR & IntType);
1026 }
1027 
1028 
1033 __STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
1034 {
1035  assert(PipeInt < CHIP_USB_NUMPIPE);
1036  return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_PEP_0 << PipeInt));
1037 }
1038 
1039 
1044 __STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs,
1045  uint8_t PipeInt)
1046 {
1047  assert(PipeInt);
1048  assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1049  return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_DMA_1 << PipeInt));
1050 }
1051 
1056 __STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType)
1057 {
1058  pUsbhs->USBHS_HSTICR = IntType;
1059 }
1060 
1065 __STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType)
1066 {
1067  pUsbhs->USBHS_HSTIFR = IntType;
1068 }
1069 
1074 __STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt)
1075 {
1076  assert(PipeInt);
1077  assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1078  pUsbhs->USBHS_HSTIFR = (USBHS_HSTIFR_DMA_1 << PipeInt);
1079 }
1080 
1081 /*** Interrupt Mask ****/
1086 __STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType)
1087 {
1088  return (pUsbhs->USBHS_HSTIMR & IntType);
1089 }
1090 
1095 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs,
1096  uint8_t PipeInt)
1097 {
1098  assert(PipeInt < CHIP_USB_NUMPIPE);
1099  return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt));
1100 }
1101 
1106 __STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs,
1107  uint8_t PipeInt)
1108 {
1109  assert(PipeInt);
1110  assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1111  return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt));
1112 }
1113 
1114 /*** Interrupt Disable ****/
1119 __STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType)
1120 {
1121  pUsbhs->USBHS_HSTIDR = IntType;
1122 }
1123 
1128 __STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
1129 {
1130  assert(PipeInt < CHIP_USB_NUMPIPE);
1131  pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_PEP_0 << PipeInt);
1132 }
1133 
1138 __STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
1139 {
1140  assert(PipeInt);
1141  assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1142  pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt);
1143 }
1144 
1145 /*** Interrupt Enable ****/
1146 
1151 __STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType)
1152 {
1153  pUsbhs->USBHS_HSTIER = IntType;
1154 }
1155 
1160 __STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
1161 {
1162  assert(PipeInt < CHIP_USB_NUMPIPE);
1163  pUsbhs->USBHS_HSTIER = (USBHS_HSTIER_PEP_0 << PipeInt);
1164 }
1165 
1170 __STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
1171 {
1172  assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1173  pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt);
1174 }
1175 
1180 __STATIC_INLINE uint16_t USBHS_HostGetSOF(void)
1181 {
1182  return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >>
1184 }
1185 
1190 __STATIC_INLINE uint16_t USBHS_HostGetFramePos(void)
1191 {
1192  return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FLENHIGH_Msk) >>
1194 }
1195 
1196 
1201 __STATIC_INLINE uint16_t USBHS_HostGetMSOF(void)
1202 {
1203  return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >>
1205 }
1206 
1207 __STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe,
1208  uint8_t Addr)
1209 {
1210  assert(Pipe < CHIP_USB_NUMPIPE);
1211 
1212  if (Pipe < 4)
1213  pUsbhs->USBHS_HSTADDR1 |= (Addr << (8 * Pipe));
1214  else if ((Pipe < 8) && (Pipe >= 4))
1215  pUsbhs->USBHS_HSTADDR2 |= (Addr << (8 * (Pipe - 4)));
1216  else
1217  pUsbhs->USBHS_HSTADDR3 |= (Addr << (8 * (Pipe - 8)));
1218 
1219 }
1220 
1221 __STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe)
1222 {
1223  assert(Pipe < CHIP_USB_NUMPIPE);
1224 
1225  if (Pipe < 4)
1226  return (pUsbhs->USBHS_HSTADDR1 >> (8 * Pipe));
1227  else if ((Pipe < 8) && (Pipe >= 4))
1228  return (pUsbhs->USBHS_HSTADDR2 >> (8 * (Pipe - 4)));
1229  else
1230  return (pUsbhs->USBHS_HSTADDR3 >> (8 * (Pipe - 8)));
1231 
1232 }
1233 
1238 __STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
1239 {
1240  assert(Pipe < CHIP_USB_NUMPIPE);
1241  pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe);
1242 }
1243 
1248 __STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe)
1249 {
1250  assert(Pipe < CHIP_USB_NUMPIPE);
1251  pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe);
1252 }
1253 
1258 __STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
1259 {
1260  assert(Pipe < CHIP_USB_NUMPIPE);
1261  return (pUsbhs->USBHS_HSTPIP & (USBHS_HSTPIP_PEN0 << Pipe));
1262 }
1267 __STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe)
1268 {
1269  assert(Pipe < CHIP_USB_NUMPIPE);
1270  pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe);
1271  pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe);
1272 }
1273 
1278 __STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe,
1279  uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken,
1280  uint8_t pipeEpNum, uint8_t PipeIntFreq)
1281 {
1282  assert(Pipe < CHIP_USB_NUMPIPE);
1283  pUsbhs->USBHS_HSTPIPCFG[Pipe] |= (pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE(
1284  pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) |
1285  USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq));
1286 }
1287 
1292 __STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe)
1293 {
1294  pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC;
1295 
1296 }
1297 
1302 __STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe)
1303 {
1304  pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC;
1305 
1306 }
1307 
1308 
1313 __STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe)
1314 {
1315  return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >>
1317 
1318 }
1319 
1324 __STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe,
1325  uint32_t Token)
1326 {
1327  pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk;
1328  pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token;
1329 
1330 }
1331 
1332 
1337 __STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe)
1338 {
1339  return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk);
1340 
1341 }
1342 
1343 
1348 __STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe,
1349  uint8_t PipeType)
1350 {
1351  pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk;
1352  pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType;
1353 
1354 }
1355 
1360 __STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe)
1361 {
1362  return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk);
1363 
1364 }
1365 
1366 __STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe)
1367 {
1368 
1370  return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >>
1371  USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80);
1372  else
1373  return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >>
1374  USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00);
1375 }
1376 
1377 
1378 
1383 __STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
1384 {
1385  pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW;
1386 }
1387 
1392 __STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
1393 {
1394  pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW;
1395 }
1396 
1401 __STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe,
1402  uint8_t Freq)
1403 {
1404  pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq);
1405 }
1406 
1407 
1412 __STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe)
1413 {
1414  pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN;
1415 }
1416 
1417 
1422 __STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe)
1423 {
1424  return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >>
1426 }
1427 
1428 
1433 __STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe)
1434 {
1435  return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >>
1437 }
1438 
1439 
1444 __STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe)
1445 {
1446  return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >>
1448 }
1449 
1450 
1455 __STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe)
1456 {
1457  return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >>
1459 }
1460 
1465 __STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe)
1466 {
1467  return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK);
1468 }
1469 
1474 __STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe,
1475  uint32_t intType)
1476 {
1477  return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType);
1478 }
1479 
1484 __STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
1485  uint32_t intType)
1486 {
1487  pUsbhs->USBHS_HSTPIPICR[Pipe] = intType;
1488 }
1489 
1494 __STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
1495  uint32_t intType)
1496 {
1497  pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType;
1498 }
1499 
1504 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs,
1505  uint8_t Pipe, uint32_t intType)
1506 {
1507  return (pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType);
1508 }
1509 
1514 __STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
1515  uint32_t intType)
1516 {
1517  pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType;
1518 }
1519 
1524 __STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
1525  uint32_t intType)
1526 {
1527  pUsbhs->USBHS_HSTPIPIER[Pipe] = intType;
1528 }
1529 
1534 __STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe)
1535 {
1536  pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE;
1537 }
1538 
1543 __STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe)
1544 {
1545  pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE;
1546 }
1547 
1552 __STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe)
1553 {
1554  return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8);
1555 }
1556 
1561 __STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq)
1562 {
1563  pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq - 1);
1564 }
1565 
1566 
1571 __STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
1572 {
1573  pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err;
1574 }
1575 
1580 __STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe,
1581  uint8_t Err)
1582 {
1583  return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err);
1584 }
1585 
1586 
1591 __STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe,
1592  uint8_t Err)
1593 {
1594  pUsbhs->USBHS_HSTPIPERR[Pipe] = Err;
1595 }
1596 
1597 
1598 __STATIC_INLINE uint8_t USBHS_GetInterruptPipeNum(void)
1599 {
1600  uint32_t status = USBHS->USBHS_HSTISR;
1601  uint32_t mask = USBHS->USBHS_HSTIMR;
1602  return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM));
1603 }
1604 
1605 static inline uint8_t USBHS_GetInterruptPipeDmaNum(void)
1606 {
1607  uint32_t status = USBHS->USBHS_HSTISR;
1608  uint32_t mask = USBHS->USBHS_HSTIMR;
1609  return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM - 1))) + 1);
1610 }
1611 /*--------------------------------------------------------
1612 * =========== USB Host's pipe DMA functions =========
1613 *---------------------------------------------------------*/
1614 
1620 __STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc)
1621 {
1622  pUsbDma->USBHS_HSTDMANXTDSC = Desc;
1623 }
1624 
1630 __STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma)
1631 {
1632  return (pUsbDma->USBHS_HSTDMANXTDSC);
1633 }
1634 
1640 __STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma,
1641  uint32_t Addr)
1642 {
1643  pUsbDma->USBHS_HSTDMAADDRESS = Addr;
1644 }
1645 
1646 
1652 __STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma)
1653 {
1654  return (pUsbDma->USBHS_HSTDMAADDRESS);
1655 }
1656 
1662 __STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg)
1663 {
1664  pUsbDma->USBHS_HSTDMACONTROL |= Cfg;
1665 }
1666 
1672 __STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma)
1673 {
1674  return (pUsbDma->USBHS_HSTDMACONTROL);
1675 }
1676 
1677 
1683 __STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma,
1684  uint32_t Status)
1685 {
1686  pUsbDma->USBHS_HSTDMASTATUS = Status;
1687 }
1688 
1689 
1695 __STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma)
1696 {
1697  return (pUsbDma->USBHS_HSTDMASTATUS);
1698 }
1699 
1701 #endif /* #ifndef USBHS_H */
__STATIC_INLINE void USBHS_Resume(void)
Sets USB host send Resume on USB bus.
__O uint32_t USBHS_HSTPIPICR[10]
(Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0)
__STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg)
Setup the USBHS DMA.
#define USBHS_DEVEPTCFG_EPBK_Msk
(USBHS_DEVEPTCFG[10]) Endpoint Banks
__I uint32_t USBHS_HSTPIPISR[10]
(Usbhs Offset: 0x530) Host Pipe Status Register (n = 0)
#define USBHS_DEVCTRL_LS
(USBHS_DEVCTRL) Low-Speed Mode Force
__STATIC_INLINE void USBHS_DisableSOF(void)
Sets USB host disable the Generation of Start of Frame.
#define USBHS_DEVCTRL_SPDCONF_FORCED_FS
(USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability...
__STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma)
Gets USBHS&#39;s DMA Buffer addresse.
#define USBHS_HSTPIPCFG_ALLOC
(USBHS_HSTPIPCFG[10]) Pipe Memory Allocate
__STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep)
#define USBHS_HSTPIPISR_DTSEQ_Msk
(USBHS_HSTPIPISR[10]) Data Toggle Sequence
__STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType)
Gets USB host interrupt status.
#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED
(USBHS_DEVCTRL) Forced high speed.
__STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
#define USBHS_HSTPIP_PRST0
(USBHS_HSTPIP) Pipe 0 Reset
#define USBHS_CTRL_UIMOD_DEVICE
(USBHS_CTRL) The module is in USB Device mode.
__I uint32_t USBHS_DEVEPTISR[10]
(Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0)
__O uint32_t USBHS_HSTPIPIFR[10]
(Usbhs Offset: 0x590) Host Pipe Set Register (n = 0)
__IO uint32_t USBHS_HSTPIPERR[10]
(Usbhs Offset: 0x680) Host Pipe Error Register (n = 0)
__I uint32_t USBHS_DEVIMR
(Usbhs Offset: 0x0010) Device Global Interrupt Mask Register
#define USBHS_HSTIDR_PEP_0
(USBHS_HSTIDR) Pipe 0 Interrupt Disable
__STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus)
Raise interrupt for endpoint.
__STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum)
Read status for a DMA Endpoint.
__STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
__STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma)
Get DMA configuration.
__STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType)
Read status for an interrupt.
#define USBHS_DEVCTRL_ADDEN
(USBHS_DEVCTRL) Address Enable
__O uint32_t USBHS_DEVIDR
(Usbhs Offset: 0x0014) Device Global Interrupt Disable Register
__STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma)
Gets DMA next descriptor address.
static uint8_t USBHS_GetInterruptPipeDmaNum(void)
__STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType)
Raise interrupt for endpoint.
__IO uint32_t USBHS_HSTPIP
(Usbhs Offset: 0x0041C) Host Pipe Register
__STATIC_INLINE uint16_t USBHS_HostGetFramePos(void)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_StopReset(void)
Sets USB host sends reste signal on USB Bus.
__STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma, uint32_t Addr)
Sets USBHS&#39;s DMA Buffer addresse.
__STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable)
Enable or disable USB address.
__I uint32_t USBHS_DEVEPTIMR[10]
(Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0)
__O uint32_t USBHS_HSTPIPIDR[10]
(Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0)
__STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep, const uint8_t Type, const uint8_t Dir, const uint8_t Size, const uint8_t Bank)
__STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs)
Get Frame number.
__STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
#define CHIP_USB_DMA_NUMPIPE
__STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs)
Enable or disable USB address.
#define USBHS_DEVIFR_DMA_1
(USBHS_DEVIFR) DMA Channel 1 Interrupt Set
__STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep)
Rests Endpoint.
__STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__IO uint32_t USBHS_HSTADDR2
(Usbhs Offset: 0x0428) Host Address 2 Register
__STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs)
Get MicrFrame number.
__STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum)
Check if endpoint&#39;s DMA interrupt is enabled for a given endpoint DMA number.
#define USBHS_HSTPIPINRQ_INMODE
(USBHS_HSTPIPINRQ[10]) IN Request Mode
__STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
#define USBHS_HSTFNUM_MFNUM_Msk
(USBHS_HSTFNUM) Micro Frame Number
__STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs)
Sets USB host Enable the Generation of Start of Frame.
#define CHIP_USB_NUMPIPE
__IO uint32_t USBHS_HSTDMANXTDSC
(UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register
#define USBHS_HSTCTRL_SPDCONF_Msk
(USBHS_HSTCTRL) Mode Configuration
__O uint32_t USBHS_SCR
(Usbhs Offset: 0x0808) General Status Clear Register
__STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
#define USBHS_SR_SPEED_LOW_SPEED
(USBHS_SR) Low-Speed mode
#define USBHS_DEVFNUM_FNCERR
(USBHS_DEVFNUM) Frame Number CRC Error
__STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc)
Sets DMA next descriptor address.
__STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe, uint8_t PipeType)
Gets USB host interrupt status.
__O uint32_t USBHS_HSTIDR
(Usbhs Offset: 0x0414) Host Global Interrupt Disable Register
#define USBHS_HSTPIPCFG_PTOKEN_Msk
(USBHS_HSTPIPCFG[10]) Pipe Token
#define USBHS_HSTIER_PEP_0
(USBHS_HSTIER) Pipe 0 Interrupt Enable
#define USBHS_DEVFNUM_FNUM_Msk
(USBHS_DEVFNUM) Frame Number
#define USBHS_DEVEPTIMR_KILLBK
(USBHS_DEVEPTIMR[10]) Kill IN Bank
__STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs)
Get Frame number CRC error.
__STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep)
__STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs)
Freeze or unfreeze USB clock.
__STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep)
#define USBHS_DEVIMR_PEP_0
(USBHS_DEVIMR) Endpoint 0 Interrupt Mask
__STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Addr)
#define USBHS_CTRL_USBE
(USBHS_CTRL) USBHS Enable
__STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
__IO uint32_t USBHS_CTRL
(Usbhs Offset: 0x0800) General Control Register
__STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__IO uint32_t USBHS_DEVEPT
(Usbhs Offset: 0x001C) Device Endpoint Register
__STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType)
Raise interrupt for endpoint.
__I uint32_t USBHS_DEVFNUM
(Usbhs Offset: 0x0020) Device Frame Number Register
__IO uint32_t USBHS_HSTDMASTATUS
(UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register
#define USBHS_HSTPIPISR_NBUSYBK_Msk
(USBHS_HSTPIPISR[10]) Number of Busy Banks
#define USBHS_HSTPIPCFG_AUTOSW
(USBHS_HSTPIPCFG[10]) Automatic Switch
__O uint32_t USBHS_DEVEPTIER[10]
(Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0)
#define USBHS_DEVCTRL_UADD_Msk
(USBHS_DEVCTRL) USB Address
__STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
__STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma)
Get DMA buffer&#39;s count.
__O uint32_t USBHS_HSTIER
(Usbhs Offset: 0x0418) Host Global Interrupt Enable Register
#define USBHS_SR_SPEED_FULL_SPEED
(USBHS_SR) Full-Speed mode
__STATIC_INLINE uint16_t USBHS_HostGetSOF(void)
Gets USB host interrupt status.
__STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma)
Get DMA configuration.
#define USBHS_HSTCTRL_SOFE
(USBHS_HSTCTRL) Start of Frame Generation Enable
#define true
Definition: compiler.h:425
__STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
Enables or disables endpoint.
__O uint32_t USBHS_HSTIFR
(Usbhs Offset: 0x040C) Host Global Interrupt Set Register
__STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc)
Sets DMA next descriptor address.
__IO uint32_t USBHS_DEVDMASTATUS
(UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register
#define USBHS_HSTFNUM_FLENHIGH_Msk
(USBHS_HSTFNUM) Frame Length
__STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr)
Sets USBHS&#39;s DMA Buffer addresse.
__STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs)
Raise interrupt for endpoint.
__IO uint32_t USBHS_DEVDMAADDRESS
(UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register
__STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
__STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp)
Enables DMA interrupt for a given endpoint.
__STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe)
#define USBHS_HSTCTRL_SPDCONF_NORMAL
(USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-...
#define USBHS_HSTPIPISR_PBYCT_Msk
(USBHS_HSTPIPISR[10]) Pipe Byte Count
#define USBHS_HSTCTRL_SPDCONF_FORCED_FS
(USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability...
#define USBHS_HSTIFR_DMA_1
(USBHS_HSTIFR) DMA Channel 1 Interrupt Set
__I uint32_t USBHS_HSTPIPIMR[10]
(Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0)
__STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr)
Configure USB address and enable or disable it.
__STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs)
Disable/Enables HS Test mode.
__STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma)
Raise DMA interrupt for endpoint.
#define USBHS_DEVIDR_DMA_1
(USBHS_DEVIDR) DMA Channel 1 Interrupt Disable
#define USBHS_HSTPIPCFG_PINGEN
(USBHS_HSTPIPCFG[10]) Ping Enable
__STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
__STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
#define USBHS
(USBHS ) Base Address
Definition: same70j19.h:508
__STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs)
Sets USB host Enable the Generation of Start of Frame.
__STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType)
check for interrupt of endpoint.
__STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep)
Disables interrupt for endpoint.
__STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable)
Disable/Enables High Speed mode.
#define USBHS_SR_CLKUSABLE
(USBHS_SR) UTMI Clock Usable
__STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs)
Sets USB host&#39;s speed to Normal , it sets to HS from FS.
__STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
#define USBHS_DEVEPTCFG_AUTOSW
(USBHS_DEVEPTCFG[10]) Automatic Switch
__O uint32_t USBHS_DEVIFR
(Usbhs Offset: 0x000C) Device Global Interrupt Set Register
__STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma)
Get Dma Status.
#define USBHS_SR_SPEED_Msk
(USBHS_SR) Speed Status (Device mode only)
__STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs)
Enable or disable USB address.
__STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs)
Sets USB host&#39;s speed to forced Full speed.
__STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType)
Disables interrupt for endpoint.
__STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType)
Acknowledge interrupt for endpoint.
#define USBHS_HSTPIPCFG_PEPNUM_Msk
(USBHS_HSTPIPCFG[10]) Pipe Endpoint Number
#define USBHS_DEVISR_DMA_1
(USBHS_DEVISR) DMA Channel 1 Interrupt
__STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe, uint32_t Token)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg)
Setup the USBHS DMA.
__STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
Gets USB host interrupt status.
__O uint32_t USBHS_DEVEPTIFR[10]
(Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0)
#define ctz(u)
Counts the trailing zero bits of the given value considered as a 32-bit integer.
Definition: compiler.h:623
__I uint32_t USBHS_HSTISR
(Usbhs Offset: 0x0404) Host Global Interrupt Status Register
__STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma)
Gets USBHS&#39;s DMA Buffer addresse.
__STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma, uint32_t Status)
Set DMA status.
__STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep)
#define USBHS_EPT_NUM
#define USBHS_DEVISR_PEP_0
(USBHS_DEVISR) Endpoint 0 Interrupt
__STATIC_INLINE void USBHS_Reset(void)
Sets USB host sends reste signal on USB Bus.
__I uint32_t USBHS_HSTIMR
(Usbhs Offset: 0x0410) Host Global Interrupt Mask Register
__STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep, uint8_t nbTrans)
#define USBHS_DEVEPTCFG_EPSIZE_Msk
(USBHS_DEVEPTCFG[10]) Endpoint Size
__O uint32_t USBHS_DEVICR
(Usbhs Offset: 0x0008) Device Global Interrupt Clear Register
__O uint32_t USBHS_SFR
(Usbhs Offset: 0x080C) General Status Set Register
__STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable)
Force Low Speed mode.
__STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType)
Enables Interrupt.
__STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__O uint32_t USBHS_DEVEPTIDR[10]
(Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0)
__IO uint32_t USBHS_HSTDMAADDRESS
(UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register
__STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs)
Freeze or unfreeze USB clock.
__IO uint32_t USBHS_HSTPIPCFG[10]
(Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0)
#define USBHS_DEVEPTISR_NBUSYBK_Msk
(USBHS_DEVEPTISR[10]) Number of Busy Banks
__STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs)
Enable or disable USB address.
__STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
#define USBHS_DEVCTRL_RMWKUP
(USBHS_DEVCTRL) Remote Wake-Up
__STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
#define USBHS_DEVIDR_PEP_0
(USBHS_DEVIDR) Endpoint 0 Interrupt Disable
__STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
#define USBHS_HSTPIP_PEN0
(USBHS_HSTPIP) Pipe 0 Enable
__STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum)
Check if endpoint&#39;s interrupt is enabled for a given endpoint number.
#define USBHS_CTRL_FRZCLK
(USBHS_CTRL) Freeze USB Clock
__STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep)
__STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep)
__IO uint32_t USBHS_HSTCTRL
(Usbhs Offset: 0x0400) Host General Control Register
#define USBHS_HSTISR_PEP_0
(USBHS_HSTISR) Pipe 0 Interrupt
__STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
Gets USB host interrupt status.
#define USBHS_HSTPIPCFG_PTYPE_Msk
(USBHS_HSTPIPCFG[10]) Pipe Type
#define USBHS_DEVEPTIER_KILLBKS
(USBHS_DEVEPTIER[10]) Kill IN Bank
#define USBHS_DEVFNUM_MFNUM_Msk
(USBHS_DEVFNUM) Micro Frame Number
__IO uint32_t USBHS_HSTADDR1
(Usbhs Offset: 0x0424) Host Address 1 Register
__STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
Gets USB host interrupt status.
__IO uint32_t USBHS_DEVDMANXTDSC
(UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register
#define USBHS_HSTIDR_DMA_1
(USBHS_HSTIDR) DMA Channel 1 Interrupt Disable
__STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs)
Get USB address.
__STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType)
Gets USB host interrupt status.
#define USBHS_DEVEPT_EPEN0
(USBHS_DEVEPT) Endpoint 0 Enable
#define USBHS_HSTFNUM_FNUM_Msk
(USBHS_HSTFNUM) Frame Number
__IO uint32_t USBHS_HSTADDR3
(Usbhs Offset: 0x042C) Host Address 3 Register
__STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp)
Disables DMA interrupt for endpoint.
__STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
#define USBHS_DEVEPTCFG_ALLOC
(USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate
__STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType)
Gets USB host interrupt status.
#define USBHS_SR_SPEED_HIGH_SPEED
(USBHS_SR) High-Speed mode
__STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
#define USBHS_HSTISR_DMA_1
(USBHS_HSTISR) DMA Channel 1 Interrupt
__O uint32_t USBHS_HSTICR
(Usbhs Offset: 0x0408) Host Global Interrupt Clear Register
__IO uint32_t USBHS_DEVEPTCFG[10]
(Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0)
__STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable)
Enables or disables USB.
#define USBHS_DEVEPT_EPRST0
(USBHS_DEVEPT) Endpoint 0 Reset
__STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep)
Checks if Endpoint is enable.
#define USBHS_HSTCTRL_RESUME
(USBHS_HSTCTRL) Send USB Resume
__STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe)
__STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable)
Attach or detach USB.
#define USBHS_DEVEPTISR_CFGOK
(USBHS_DEVEPTISR[10]) Configuration OK Status
#define USBHS_DEVIMR_DMA_1
(USBHS_DEVIMR) DMA Channel 1 Interrupt Mask
__O uint32_t USBHS_DEVIER
(Usbhs Offset: 0x0018) Device Global Interrupt Enable Register
#define USBHS_HSTCTRL_RESET
(USBHS_HSTCTRL) Send USB Reset
__STATIC_INLINE uint8_t USBHS_GetInterruptPipeNum(void)
__IO uint32_t USBHS_HSTDMACONTROL
(UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register
__I uint32_t USBHS_DEVISR
(Usbhs Offset: 0x0004) Device Global Interrupt Status Register
#define USBHS_DEVEPTCFG_EPTYPE_Msk
(USBHS_DEVEPTCFG[10]) Endpoint Type
__STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode)
Device or Host Mode.
#define USBHS_HSTPIPISR_CURRBK_Msk
(USBHS_HSTPIPISR[10]) Current Bank
__STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs)
Check if clock is usable or not.
__O uint32_t USBHS_HSTPIPIER[10]
(Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0)
#define USBHS_DEVEPTCFG_EPDIR
(USBHS_DEVEPTCFG[10]) Endpoint Direction
__STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep)
#define USBHS_DEVIER_PEP_0
(USBHS_DEVIER) Endpoint 0 Interrupt Enable
#define USBHS_HSTCTRL_SPDCONF_LOW_POWER
(USBHS_HSTCTRL) For a better consumption, if high speed is not needed.
__STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpIntType)
#define USBHS_DEVCTRL_SPDCONF_Msk
(USBHS_DEVCTRL) Mode Configuration
#define USBHS_HSTPIPCFG_PTOKEN_IN
(USBHS_HSTPIPCFG[10]) IN
__STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
__STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable)
Freeze or unfreeze USB clock.
#define USBHS_HSTIMR_PEP_0
(USBHS_HSTIMR) Pipe 0 Interrupt Enable
#define USBHSDEVDMA_NUMBER
Usbhs hardware registers.
#define USBHS_HSTIMR_DMA_1
(USBHS_HSTIMR) DMA Channel 1 Interrupt Enable
__IO uint32_t USBHS_HSTPIPINRQ[10]
(Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0)
#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk
(USBHS_DEVDMASTATUS) Buffer Byte Count
__STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs)
Set Remote WakeUp mode.
__STATIC_INLINE uint16_t USBHS_HostGetMSOF(void)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType)
Gets USB host interrupt status.
__IO uint32_t USBHS_DEVCTRL
(Usbhs Offset: 0x0000) Device General Control Register
__STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs)
Sets USB host&#39;s speed to Low speed.
__STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma)
Get Dma Status.
__STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe, uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken, uint8_t pipeEpNum, uint8_t PipeIntFreq)
Gets USB host interrupt status.
__STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Freq)
Gets USB host interrupt status.
#define USBHS_DEVIER_DMA_1
(USBHS_DEVIER) DMA Channel 1 Interrupt Enable
__STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
Gets USB host interrupt status.
__STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum)
Read status for an Endpoint.
__STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep)
__STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status)
Set DMA status.
__O uint32_t USBHS_DEVEPTICR[10]
(Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0)
#define USBHS_HSTPIPCFG_PSIZE_Msk
(USBHS_HSTPIPCFG[10]) Pipe Size
__I uint32_t USBHS_SR
(Usbhs Offset: 0x0804) General Status Register
#define USBHS_DEVEPTISR_BYCT_Msk
(USBHS_DEVEPTISR[10]) Byte Count
__STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep)
__IO uint32_t USBHS_DEVDMACONTROL
(UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register
__STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep, uint32_t IntType)
__STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
Gets USB host interrupt status.
__STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs)
Enable or disable USB address.
__STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum)
Enables interrupt for a given endpoint.
__STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma)
Gets DMA next descriptor address.
#define USBHS_HSTIER_DMA_1
(USBHS_HSTIER) DMA Channel 1 Interrupt Enable
__STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
__STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode)
Disable/Enables Test mode.
__STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
__STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
Gets USB host interrupt status.


inertial_sense_ros
Author(s):
autogenerated on Sun Feb 28 2021 03:17:58