USB High-Speed Interface

Classes
struct	Usbhs
struct	UsbhsDevdma
	UsbhsDevdma hardware registers. More...
struct	UsbhsHstdma
	UsbhsHstdma hardware registers. More...

Macros
#define	USBHS_CTRL_FRZCLK   (0x1u << 14)
	(USBHS_CTRL) Freeze USB Clock More...
#define	USBHS_CTRL_RDERRE   (0x1u << 4)
	(USBHS_CTRL) Remote Device Connection Error Interrupt Enable More...
#define	USBHS_CTRL_UIMOD   (0x1u << 25)
	(USBHS_CTRL) USBHS Mode More...
#define	USBHS_CTRL_UIMOD_DEVICE   (0x1u << 25)
	(USBHS_CTRL) The module is in USB Device mode. More...
#define	USBHS_CTRL_UIMOD_HOST   (0x0u << 25)
	(USBHS_CTRL) The module is in USB Host mode. More...
#define	USBHS_CTRL_USBE   (0x1u << 15)
	(USBHS_CTRL) USBHS Enable More...
#define	USBHS_CTRL_VBUSHWC   (0x1u << 8)
	(USBHS_CTRL) VBUS Hardware Control More...
#define	USBHS_DEVCTRL_ADDEN   (0x1u << 7)
	(USBHS_DEVCTRL) Address Enable More...
#define	USBHS_DEVCTRL_DETACH   (0x1u << 8)
	(USBHS_DEVCTRL) Detach More...
#define	USBHS_DEVCTRL_LS   (0x1u << 12)
	(USBHS_DEVCTRL) Low-Speed Mode Force More...
#define	USBHS_DEVCTRL_OPMODE2   (0x1u << 16)
	(USBHS_DEVCTRL) Specific Operational mode More...
#define	USBHS_DEVCTRL_RMWKUP   (0x1u << 9)
	(USBHS_DEVCTRL) Remote Wake-Up More...
#define	USBHS_DEVCTRL_SPDCONF(value)   ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))
#define	USBHS_DEVCTRL_SPDCONF_FORCED_FS   (0x3u << 10)
	(USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. More...
#define	USBHS_DEVCTRL_SPDCONF_HIGH_SPEED   (0x2u << 10)
	(USBHS_DEVCTRL) Forced high speed. More...
#define	USBHS_DEVCTRL_SPDCONF_LOW_POWER   (0x1u << 10)
	(USBHS_DEVCTRL) For a better consumption, if high speed is not needed. More...
#define	USBHS_DEVCTRL_SPDCONF_Msk   (0x3u << USBHS_DEVCTRL_SPDCONF_Pos)
	(USBHS_DEVCTRL) Mode Configuration More...
#define	USBHS_DEVCTRL_SPDCONF_NORMAL   (0x0u << 10)
	(USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. More...
#define	USBHS_DEVCTRL_SPDCONF_Pos   10
#define	USBHS_DEVCTRL_TSTJ   (0x1u << 13)
	(USBHS_DEVCTRL) Test mode J More...
#define	USBHS_DEVCTRL_TSTK   (0x1u << 14)
	(USBHS_DEVCTRL) Test mode K More...
#define	USBHS_DEVCTRL_TSTPCKT   (0x1u << 15)
	(USBHS_DEVCTRL) Test packet mode More...
#define	USBHS_DEVCTRL_UADD(value)   ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))
#define	USBHS_DEVCTRL_UADD_Msk   (0x7fu << USBHS_DEVCTRL_UADD_Pos)
	(USBHS_DEVCTRL) USB Address More...
#define	USBHS_DEVCTRL_UADD_Pos   0
#define	USBHS_DEVDMAADDRESS_BUFF_ADD(value)   ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
#define	USBHS_DEVDMAADDRESS_BUFF_ADD_Msk   (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)
	(USBHS_DEVDMAADDRESS) Buffer Address More...
#define	USBHS_DEVDMAADDRESS_BUFF_ADD_Pos   0
#define	USBHS_DEVDMACONTROL_BUFF_LENGTH(value)   ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
#define	USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk   (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)
	(USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) More...
#define	USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos   16
#define	USBHS_DEVDMACONTROL_BURST_LCK   (0x1u << 7)
	(USBHS_DEVDMACONTROL) Burst Lock Enable More...
#define	USBHS_DEVDMACONTROL_CHANN_ENB   (0x1u << 0)
	(USBHS_DEVDMACONTROL) Channel Enable Command More...
#define	USBHS_DEVDMACONTROL_DESC_LD_IT   (0x1u << 6)
	(USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable More...
#define	USBHS_DEVDMACONTROL_END_B_EN   (0x1u << 3)
	(USBHS_DEVDMACONTROL) End of Buffer Enable Control More...
#define	USBHS_DEVDMACONTROL_END_BUFFIT   (0x1u << 5)
	(USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable More...
#define	USBHS_DEVDMACONTROL_END_TR_EN   (0x1u << 2)
	(USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) More...
#define	USBHS_DEVDMACONTROL_END_TR_IT   (0x1u << 4)
	(USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable More...
#define	USBHS_DEVDMACONTROL_LDNXT_DSC   (0x1u << 1)
	(USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command More...
#define	USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value)   ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
#define	USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk   (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)
	(USBHS_DEVDMANXTDSC) Next Descriptor Address More...
#define	USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos   0
#define	USBHS_DEVDMASTATUS_BUFF_COUNT(value)   ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
#define	USBHS_DEVDMASTATUS_BUFF_COUNT_Msk   (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)
	(USBHS_DEVDMASTATUS) Buffer Byte Count More...
#define	USBHS_DEVDMASTATUS_BUFF_COUNT_Pos   16
#define	USBHS_DEVDMASTATUS_CHANN_ACT   (0x1u << 1)
	(USBHS_DEVDMASTATUS) Channel Active Status More...
#define	USBHS_DEVDMASTATUS_CHANN_ENB   (0x1u << 0)
	(USBHS_DEVDMASTATUS) Channel Enable Status More...
#define	USBHS_DEVDMASTATUS_DESC_LDST   (0x1u << 6)
	(USBHS_DEVDMASTATUS) Descriptor Loaded Status More...
#define	USBHS_DEVDMASTATUS_END_BF_ST   (0x1u << 5)
	(USBHS_DEVDMASTATUS) End of Channel Buffer Status More...
#define	USBHS_DEVDMASTATUS_END_TR_ST   (0x1u << 4)
	(USBHS_DEVDMASTATUS) End of Channel Transfer Status More...
#define	USBHS_DEVEPT_EPEN0   (0x1u << 0)
	(USBHS_DEVEPT) Endpoint 0 Enable More...
#define	USBHS_DEVEPT_EPEN1   (0x1u << 1)
	(USBHS_DEVEPT) Endpoint 1 Enable More...
#define	USBHS_DEVEPT_EPEN2   (0x1u << 2)
	(USBHS_DEVEPT) Endpoint 2 Enable More...
#define	USBHS_DEVEPT_EPEN3   (0x1u << 3)
	(USBHS_DEVEPT) Endpoint 3 Enable More...
#define	USBHS_DEVEPT_EPEN4   (0x1u << 4)
	(USBHS_DEVEPT) Endpoint 4 Enable More...
#define	USBHS_DEVEPT_EPEN5   (0x1u << 5)
	(USBHS_DEVEPT) Endpoint 5 Enable More...
#define	USBHS_DEVEPT_EPEN6   (0x1u << 6)
	(USBHS_DEVEPT) Endpoint 6 Enable More...
#define	USBHS_DEVEPT_EPEN7   (0x1u << 7)
	(USBHS_DEVEPT) Endpoint 7 Enable More...
#define	USBHS_DEVEPT_EPEN8   (0x1u << 8)
	(USBHS_DEVEPT) Endpoint 8 Enable More...
#define	USBHS_DEVEPT_EPEN9   (0x1u << 9)
	(USBHS_DEVEPT) Endpoint 9 Enable More...
#define	USBHS_DEVEPT_EPRST0   (0x1u << 16)
	(USBHS_DEVEPT) Endpoint 0 Reset More...
#define	USBHS_DEVEPT_EPRST1   (0x1u << 17)
	(USBHS_DEVEPT) Endpoint 1 Reset More...
#define	USBHS_DEVEPT_EPRST2   (0x1u << 18)
	(USBHS_DEVEPT) Endpoint 2 Reset More...
#define	USBHS_DEVEPT_EPRST3   (0x1u << 19)
	(USBHS_DEVEPT) Endpoint 3 Reset More...
#define	USBHS_DEVEPT_EPRST4   (0x1u << 20)
	(USBHS_DEVEPT) Endpoint 4 Reset More...
#define	USBHS_DEVEPT_EPRST5   (0x1u << 21)
	(USBHS_DEVEPT) Endpoint 5 Reset More...
#define	USBHS_DEVEPT_EPRST6   (0x1u << 22)
	(USBHS_DEVEPT) Endpoint 6 Reset More...
#define	USBHS_DEVEPT_EPRST7   (0x1u << 23)
	(USBHS_DEVEPT) Endpoint 7 Reset More...
#define	USBHS_DEVEPT_EPRST8   (0x1u << 24)
	(USBHS_DEVEPT) Endpoint 8 Reset More...
#define	USBHS_DEVEPT_EPRST9   (0x1u << 25)
	(USBHS_DEVEPT) Endpoint 9 Reset More...
#define	USBHS_DEVEPTCFG_ALLOC   (0x1u << 1)
	(USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate More...
#define	USBHS_DEVEPTCFG_AUTOSW   (0x1u << 9)
	(USBHS_DEVEPTCFG[10]) Automatic Switch More...
#define	USBHS_DEVEPTCFG_EPBK(value)   ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))
#define	USBHS_DEVEPTCFG_EPBK_1_BANK   (0x0u << 2)
	(USBHS_DEVEPTCFG[10]) Single-bank endpoint More...
#define	USBHS_DEVEPTCFG_EPBK_2_BANK   (0x1u << 2)
	(USBHS_DEVEPTCFG[10]) Double-bank endpoint More...
#define	USBHS_DEVEPTCFG_EPBK_3_BANK   (0x2u << 2)
	(USBHS_DEVEPTCFG[10]) Triple-bank endpoint More...
#define	USBHS_DEVEPTCFG_EPBK_Msk   (0x3u << USBHS_DEVEPTCFG_EPBK_Pos)
	(USBHS_DEVEPTCFG[10]) Endpoint Banks More...
#define	USBHS_DEVEPTCFG_EPBK_Pos   2
#define	USBHS_DEVEPTCFG_EPDIR   (0x1u << 8)
	(USBHS_DEVEPTCFG[10]) Endpoint Direction More...
#define	USBHS_DEVEPTCFG_EPDIR_IN   (0x1u << 8)
	(USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). More...
#define	USBHS_DEVEPTCFG_EPDIR_OUT   (0x0u << 8)
	(USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. More...
#define	USBHS_DEVEPTCFG_EPSIZE(value)   ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))
#define	USBHS_DEVEPTCFG_EPSIZE_1024_BYTE   (0x7u << 4)
	(USBHS_DEVEPTCFG[10]) 1024 bytes More...
#define	USBHS_DEVEPTCFG_EPSIZE_128_BYTE   (0x4u << 4)
	(USBHS_DEVEPTCFG[10]) 128 bytes More...
#define	USBHS_DEVEPTCFG_EPSIZE_16_BYTE   (0x1u << 4)
	(USBHS_DEVEPTCFG[10]) 16 bytes More...
#define	USBHS_DEVEPTCFG_EPSIZE_256_BYTE   (0x5u << 4)
	(USBHS_DEVEPTCFG[10]) 256 bytes More...
#define	USBHS_DEVEPTCFG_EPSIZE_32_BYTE   (0x2u << 4)
	(USBHS_DEVEPTCFG[10]) 32 bytes More...
#define	USBHS_DEVEPTCFG_EPSIZE_512_BYTE   (0x6u << 4)
	(USBHS_DEVEPTCFG[10]) 512 bytes More...
#define	USBHS_DEVEPTCFG_EPSIZE_64_BYTE   (0x3u << 4)
	(USBHS_DEVEPTCFG[10]) 64 bytes More...
#define	USBHS_DEVEPTCFG_EPSIZE_8_BYTE   (0x0u << 4)
	(USBHS_DEVEPTCFG[10]) 8 bytes More...
#define	USBHS_DEVEPTCFG_EPSIZE_Msk   (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos)
	(USBHS_DEVEPTCFG[10]) Endpoint Size More...
#define	USBHS_DEVEPTCFG_EPSIZE_Pos   4
#define	USBHS_DEVEPTCFG_EPTYPE(value)   ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))
#define	USBHS_DEVEPTCFG_EPTYPE_BLK   (0x2u << 11)
	(USBHS_DEVEPTCFG[10]) Bulk More...
#define	USBHS_DEVEPTCFG_EPTYPE_CTRL   (0x0u << 11)
	(USBHS_DEVEPTCFG[10]) Control More...
#define	USBHS_DEVEPTCFG_EPTYPE_INTRPT   (0x3u << 11)
	(USBHS_DEVEPTCFG[10]) Interrupt More...
#define	USBHS_DEVEPTCFG_EPTYPE_ISO   (0x1u << 11)
	(USBHS_DEVEPTCFG[10]) Isochronous More...
#define	USBHS_DEVEPTCFG_EPTYPE_Msk   (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos)
	(USBHS_DEVEPTCFG[10]) Endpoint Type More...
#define	USBHS_DEVEPTCFG_EPTYPE_Pos   11
#define	USBHS_DEVEPTCFG_NBTRANS(value)   ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))
#define	USBHS_DEVEPTCFG_NBTRANS_0_TRANS   (0x0u << 13)
	(USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. More...
#define	USBHS_DEVEPTCFG_NBTRANS_1_TRANS   (0x1u << 13)
	(USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. More...
#define	USBHS_DEVEPTCFG_NBTRANS_2_TRANS   (0x2u << 13)
	(USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. More...
#define	USBHS_DEVEPTCFG_NBTRANS_3_TRANS   (0x3u << 13)
	(USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. More...
#define	USBHS_DEVEPTCFG_NBTRANS_Msk   (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos)
	(USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint More...
#define	USBHS_DEVEPTCFG_NBTRANS_Pos   13
#define	USBHS_DEVEPTICR_CRCERRIC   (0x1u << 6)
	(USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear More...
#define	USBHS_DEVEPTICR_HBISOFLUSHIC   (0x1u << 4)
	(USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear More...
#define	USBHS_DEVEPTICR_HBISOINERRIC   (0x1u << 3)
	(USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear More...
#define	USBHS_DEVEPTICR_NAKINIC   (0x1u << 4)
	(USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear More...
#define	USBHS_DEVEPTICR_NAKOUTIC   (0x1u << 3)
	(USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear More...
#define	USBHS_DEVEPTICR_OVERFIC   (0x1u << 5)
	(USBHS_DEVEPTICR[10]) Overflow Interrupt Clear More...
#define	USBHS_DEVEPTICR_RXOUTIC   (0x1u << 1)
	(USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear More...
#define	USBHS_DEVEPTICR_RXSTPIC   (0x1u << 2)
	(USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear More...
#define	USBHS_DEVEPTICR_SHORTPACKETC   (0x1u << 7)
	(USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear More...
#define	USBHS_DEVEPTICR_STALLEDIC   (0x1u << 6)
	(USBHS_DEVEPTICR[10]) STALLed Interrupt Clear More...
#define	USBHS_DEVEPTICR_TXINIC   (0x1u << 0)
	(USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear More...
#define	USBHS_DEVEPTICR_UNDERFIC   (0x1u << 2)
	(USBHS_DEVEPTICR[10]) Underflow Interrupt Clear More...
#define	USBHS_DEVEPTIDR_CRCERREC   (0x1u << 6)
	(USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear More...
#define	USBHS_DEVEPTIDR_DATAXEC   (0x1u << 9)
	(USBHS_DEVEPTIDR[10]) DataX Interrupt Clear More...
#define	USBHS_DEVEPTIDR_EPDISHDMAC   (0x1u << 16)
	(USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear More...
#define	USBHS_DEVEPTIDR_ERRORTRANSEC   (0x1u << 10)
	(USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear More...
#define	USBHS_DEVEPTIDR_FIFOCONC   (0x1u << 14)
	(USBHS_DEVEPTIDR[10]) FIFO Control Clear More...
#define	USBHS_DEVEPTIDR_HBISOFLUSHEC   (0x1u << 4)
	(USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear More...
#define	USBHS_DEVEPTIDR_HBISOINERREC   (0x1u << 3)
	(USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear More...
#define	USBHS_DEVEPTIDR_MDATEC   (0x1u << 8)
	(USBHS_DEVEPTIDR[10]) MData Interrupt Clear More...
#define	USBHS_DEVEPTIDR_NAKINEC   (0x1u << 4)
	(USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear More...
#define	USBHS_DEVEPTIDR_NAKOUTEC   (0x1u << 3)
	(USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear More...
#define	USBHS_DEVEPTIDR_NBUSYBKEC   (0x1u << 12)
	(USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear More...
#define	USBHS_DEVEPTIDR_NYETDISC   (0x1u << 17)
	(USBHS_DEVEPTIDR[10]) NYET Token Disable Clear More...
#define	USBHS_DEVEPTIDR_OVERFEC   (0x1u << 5)
	(USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear More...
#define	USBHS_DEVEPTIDR_RXOUTEC   (0x1u << 1)
	(USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear More...
#define	USBHS_DEVEPTIDR_RXSTPEC   (0x1u << 2)
	(USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear More...
#define	USBHS_DEVEPTIDR_SHORTPACKETEC   (0x1u << 7)
	(USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear More...
#define	USBHS_DEVEPTIDR_STALLEDEC   (0x1u << 6)
	(USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear More...
#define	USBHS_DEVEPTIDR_STALLRQC   (0x1u << 19)
	(USBHS_DEVEPTIDR[10]) STALL Request Clear More...
#define	USBHS_DEVEPTIDR_TXINEC   (0x1u << 0)
	(USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear More...
#define	USBHS_DEVEPTIDR_UNDERFEC   (0x1u << 2)
	(USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear More...
#define	USBHS_DEVEPTIER_CRCERRES   (0x1u << 6)
	(USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable More...
#define	USBHS_DEVEPTIER_DATAXES   (0x1u << 9)
	(USBHS_DEVEPTIER[10]) DataX Interrupt Enable More...
#define	USBHS_DEVEPTIER_EPDISHDMAS   (0x1u << 16)
	(USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable More...
#define	USBHS_DEVEPTIER_ERRORTRANSES   (0x1u << 10)
	(USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable More...
#define	USBHS_DEVEPTIER_FIFOCONS   (0x1u << 14)
	(USBHS_DEVEPTIER[10]) FIFO Control More...
#define	USBHS_DEVEPTIER_HBISOFLUSHES   (0x1u << 4)
	(USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable More...
#define	USBHS_DEVEPTIER_HBISOINERRES   (0x1u << 3)
	(USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable More...
#define	USBHS_DEVEPTIER_KILLBKS   (0x1u << 13)
	(USBHS_DEVEPTIER[10]) Kill IN Bank More...
#define	USBHS_DEVEPTIER_MDATAES   (0x1u << 8)
	(USBHS_DEVEPTIER[10]) MData Interrupt Enable More...
#define	USBHS_DEVEPTIER_NAKINES   (0x1u << 4)
	(USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable More...
#define	USBHS_DEVEPTIER_NAKOUTES   (0x1u << 3)
	(USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable More...
#define	USBHS_DEVEPTIER_NBUSYBKES   (0x1u << 12)
	(USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable More...
#define	USBHS_DEVEPTIER_NYETDISS   (0x1u << 17)
	(USBHS_DEVEPTIER[10]) NYET Token Disable Enable More...
#define	USBHS_DEVEPTIER_OVERFES   (0x1u << 5)
	(USBHS_DEVEPTIER[10]) Overflow Interrupt Enable More...
#define	USBHS_DEVEPTIER_RSTDTS   (0x1u << 18)
	(USBHS_DEVEPTIER[10]) Reset Data Toggle Enable More...
#define	USBHS_DEVEPTIER_RXOUTES   (0x1u << 1)
	(USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable More...
#define	USBHS_DEVEPTIER_RXSTPES   (0x1u << 2)
	(USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable More...
#define	USBHS_DEVEPTIER_SHORTPACKETES   (0x1u << 7)
	(USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable More...
#define	USBHS_DEVEPTIER_STALLEDES   (0x1u << 6)
	(USBHS_DEVEPTIER[10]) STALLed Interrupt Enable More...
#define	USBHS_DEVEPTIER_STALLRQS   (0x1u << 19)
	(USBHS_DEVEPTIER[10]) STALL Request Enable More...
#define	USBHS_DEVEPTIER_TXINES   (0x1u << 0)
	(USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable More...
#define	USBHS_DEVEPTIER_UNDERFES   (0x1u << 2)
	(USBHS_DEVEPTIER[10]) Underflow Interrupt Enable More...
#define	USBHS_DEVEPTIFR_CRCERRIS   (0x1u << 6)
	(USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set More...
#define	USBHS_DEVEPTIFR_HBISOFLUSHIS   (0x1u << 4)
	(USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set More...
#define	USBHS_DEVEPTIFR_HBISOINERRIS   (0x1u << 3)
	(USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set More...
#define	USBHS_DEVEPTIFR_NAKINIS   (0x1u << 4)
	(USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set More...
#define	USBHS_DEVEPTIFR_NAKOUTIS   (0x1u << 3)
	(USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set More...
#define	USBHS_DEVEPTIFR_NBUSYBKS   (0x1u << 12)
	(USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set More...
#define	USBHS_DEVEPTIFR_OVERFIS   (0x1u << 5)
	(USBHS_DEVEPTIFR[10]) Overflow Interrupt Set More...
#define	USBHS_DEVEPTIFR_RXOUTIS   (0x1u << 1)
	(USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set More...
#define	USBHS_DEVEPTIFR_RXSTPIS   (0x1u << 2)
	(USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set More...
#define	USBHS_DEVEPTIFR_SHORTPACKETS   (0x1u << 7)
	(USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set More...
#define	USBHS_DEVEPTIFR_STALLEDIS   (0x1u << 6)
	(USBHS_DEVEPTIFR[10]) STALLed Interrupt Set More...
#define	USBHS_DEVEPTIFR_TXINIS   (0x1u << 0)
	(USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set More...
#define	USBHS_DEVEPTIFR_UNDERFIS   (0x1u << 2)
	(USBHS_DEVEPTIFR[10]) Underflow Interrupt Set More...
#define	USBHS_DEVEPTIMR_CRCERRE   (0x1u << 6)
	(USBHS_DEVEPTIMR[10]) CRC Error Interrupt More...
#define	USBHS_DEVEPTIMR_DATAXE   (0x1u << 9)
	(USBHS_DEVEPTIMR[10]) DataX Interrupt More...
#define	USBHS_DEVEPTIMR_EPDISHDMA   (0x1u << 16)
	(USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request More...
#define	USBHS_DEVEPTIMR_ERRORTRANSE   (0x1u << 10)
	(USBHS_DEVEPTIMR[10]) Transaction Error Interrupt More...
#define	USBHS_DEVEPTIMR_FIFOCON   (0x1u << 14)
	(USBHS_DEVEPTIMR[10]) FIFO Control More...
#define	USBHS_DEVEPTIMR_HBISOFLUSHE   (0x1u << 4)
	(USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt More...
#define	USBHS_DEVEPTIMR_HBISOINERRE   (0x1u << 3)
	(USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt More...
#define	USBHS_DEVEPTIMR_KILLBK   (0x1u << 13)
	(USBHS_DEVEPTIMR[10]) Kill IN Bank More...
#define	USBHS_DEVEPTIMR_MDATAE   (0x1u << 8)
	(USBHS_DEVEPTIMR[10]) MData Interrupt More...
#define	USBHS_DEVEPTIMR_NAKINE   (0x1u << 4)
	(USBHS_DEVEPTIMR[10]) NAKed IN Interrupt More...
#define	USBHS_DEVEPTIMR_NAKOUTE   (0x1u << 3)
	(USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt More...
#define	USBHS_DEVEPTIMR_NBUSYBKE   (0x1u << 12)
	(USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt More...
#define	USBHS_DEVEPTIMR_NYETDIS   (0x1u << 17)
	(USBHS_DEVEPTIMR[10]) NYET Token Disable More...
#define	USBHS_DEVEPTIMR_OVERFE   (0x1u << 5)
	(USBHS_DEVEPTIMR[10]) Overflow Interrupt More...
#define	USBHS_DEVEPTIMR_RSTDT   (0x1u << 18)
	(USBHS_DEVEPTIMR[10]) Reset Data Toggle More...
#define	USBHS_DEVEPTIMR_RXOUTE   (0x1u << 1)
	(USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt More...
#define	USBHS_DEVEPTIMR_RXSTPE   (0x1u << 2)
	(USBHS_DEVEPTIMR[10]) Received SETUP Interrupt More...
#define	USBHS_DEVEPTIMR_SHORTPACKETE   (0x1u << 7)
	(USBHS_DEVEPTIMR[10]) Short Packet Interrupt More...
#define	USBHS_DEVEPTIMR_STALLEDE   (0x1u << 6)
	(USBHS_DEVEPTIMR[10]) STALLed Interrupt More...
#define	USBHS_DEVEPTIMR_STALLRQ   (0x1u << 19)
	(USBHS_DEVEPTIMR[10]) STALL Request More...
#define	USBHS_DEVEPTIMR_TXINE   (0x1u << 0)
	(USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt More...
#define	USBHS_DEVEPTIMR_UNDERFE   (0x1u << 2)
	(USBHS_DEVEPTIMR[10]) Underflow Interrupt More...
#define	USBHS_DEVEPTISR_BYCT_Msk   (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos)
	(USBHS_DEVEPTISR[10]) Byte Count More...
#define	USBHS_DEVEPTISR_BYCT_Pos   20
#define	USBHS_DEVEPTISR_CFGOK   (0x1u << 18)
	(USBHS_DEVEPTISR[10]) Configuration OK Status More...
#define	USBHS_DEVEPTISR_CRCERRI   (0x1u << 6)
	(USBHS_DEVEPTISR[10]) CRC Error Interrupt More...
#define	USBHS_DEVEPTISR_CTRLDIR   (0x1u << 17)
	(USBHS_DEVEPTISR[10]) Control Direction More...
#define	USBHS_DEVEPTISR_CURRBK_BANK0   (0x0u << 14)
	(USBHS_DEVEPTISR[10]) Current bank is bank0 More...
#define	USBHS_DEVEPTISR_CURRBK_BANK1   (0x1u << 14)
	(USBHS_DEVEPTISR[10]) Current bank is bank1 More...
#define	USBHS_DEVEPTISR_CURRBK_BANK2   (0x2u << 14)
	(USBHS_DEVEPTISR[10]) Current bank is bank2 More...
#define	USBHS_DEVEPTISR_CURRBK_Msk   (0x3u << USBHS_DEVEPTISR_CURRBK_Pos)
	(USBHS_DEVEPTISR[10]) Current Bank More...
#define	USBHS_DEVEPTISR_CURRBK_Pos   14
#define	USBHS_DEVEPTISR_DTSEQ_DATA0   (0x0u << 8)
	(USBHS_DEVEPTISR[10]) Data0 toggle sequence More...
#define	USBHS_DEVEPTISR_DTSEQ_DATA1   (0x1u << 8)
	(USBHS_DEVEPTISR[10]) Data1 toggle sequence More...
#define	USBHS_DEVEPTISR_DTSEQ_DATA2   (0x2u << 8)
	(USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint More...
#define	USBHS_DEVEPTISR_DTSEQ_MDATA   (0x3u << 8)
	(USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint More...
#define	USBHS_DEVEPTISR_DTSEQ_Msk   (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos)
	(USBHS_DEVEPTISR[10]) Data Toggle Sequence More...
#define	USBHS_DEVEPTISR_DTSEQ_Pos   8
#define	USBHS_DEVEPTISR_ERRORTRANS   (0x1u << 10)
	(USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt More...
#define	USBHS_DEVEPTISR_HBISOFLUSHI   (0x1u << 4)
	(USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt More...
#define	USBHS_DEVEPTISR_HBISOINERRI   (0x1u << 3)
	(USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt More...
#define	USBHS_DEVEPTISR_NAKINI   (0x1u << 4)
	(USBHS_DEVEPTISR[10]) NAKed IN Interrupt More...
#define	USBHS_DEVEPTISR_NAKOUTI   (0x1u << 3)
	(USBHS_DEVEPTISR[10]) NAKed OUT Interrupt More...
#define	USBHS_DEVEPTISR_NBUSYBK_0_BUSY   (0x0u << 12)
	(USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) More...
#define	USBHS_DEVEPTISR_NBUSYBK_1_BUSY   (0x1u << 12)
	(USBHS_DEVEPTISR[10]) 1 busy bank More...
#define	USBHS_DEVEPTISR_NBUSYBK_2_BUSY   (0x2u << 12)
	(USBHS_DEVEPTISR[10]) 2 busy banks More...
#define	USBHS_DEVEPTISR_NBUSYBK_3_BUSY   (0x3u << 12)
	(USBHS_DEVEPTISR[10]) 3 busy banks More...
#define	USBHS_DEVEPTISR_NBUSYBK_Msk   (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos)
	(USBHS_DEVEPTISR[10]) Number of Busy Banks More...
#define	USBHS_DEVEPTISR_NBUSYBK_Pos   12
#define	USBHS_DEVEPTISR_OVERFI   (0x1u << 5)
	(USBHS_DEVEPTISR[10]) Overflow Interrupt More...
#define	USBHS_DEVEPTISR_RWALL   (0x1u << 16)
	(USBHS_DEVEPTISR[10]) Read/Write Allowed More...
#define	USBHS_DEVEPTISR_RXOUTI   (0x1u << 1)
	(USBHS_DEVEPTISR[10]) Received OUT Data Interrupt More...
#define	USBHS_DEVEPTISR_RXSTPI   (0x1u << 2)
	(USBHS_DEVEPTISR[10]) Received SETUP Interrupt More...
#define	USBHS_DEVEPTISR_SHORTPACKET   (0x1u << 7)
	(USBHS_DEVEPTISR[10]) Short Packet Interrupt More...
#define	USBHS_DEVEPTISR_STALLEDI   (0x1u << 6)
	(USBHS_DEVEPTISR[10]) STALLed Interrupt More...
#define	USBHS_DEVEPTISR_TXINI   (0x1u << 0)
	(USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt More...
#define	USBHS_DEVEPTISR_UNDERFI   (0x1u << 2)
	(USBHS_DEVEPTISR[10]) Underflow Interrupt More...
#define	USBHS_DEVFNUM_FNCERR   (0x1u << 15)
	(USBHS_DEVFNUM) Frame Number CRC Error More...
#define	USBHS_DEVFNUM_FNUM_Msk   (0x7ffu << USBHS_DEVFNUM_FNUM_Pos)
	(USBHS_DEVFNUM) Frame Number More...
#define	USBHS_DEVFNUM_FNUM_Pos   3
#define	USBHS_DEVFNUM_MFNUM_Msk   (0x7u << USBHS_DEVFNUM_MFNUM_Pos)
	(USBHS_DEVFNUM) Micro Frame Number More...
#define	USBHS_DEVFNUM_MFNUM_Pos   0
#define	USBHS_DEVICR_EORSMC   (0x1u << 5)
	(USBHS_DEVICR) End of Resume Interrupt Clear More...
#define	USBHS_DEVICR_EORSTC   (0x1u << 3)
	(USBHS_DEVICR) End of Reset Interrupt Clear More...
#define	USBHS_DEVICR_MSOFC   (0x1u << 1)
	(USBHS_DEVICR) Micro Start of Frame Interrupt Clear More...
#define	USBHS_DEVICR_SOFC   (0x1u << 2)
	(USBHS_DEVICR) Start of Frame Interrupt Clear More...
#define	USBHS_DEVICR_SUSPC   (0x1u << 0)
	(USBHS_DEVICR) Suspend Interrupt Clear More...
#define	USBHS_DEVICR_UPRSMC   (0x1u << 6)
	(USBHS_DEVICR) Upstream Resume Interrupt Clear More...
#define	USBHS_DEVICR_WAKEUPC   (0x1u << 4)
	(USBHS_DEVICR) Wake-Up Interrupt Clear More...
#define	USBHS_DEVIDR_DMA_1   (0x1u << 25)
	(USBHS_DEVIDR) DMA Channel 1 Interrupt Disable More...
#define	USBHS_DEVIDR_DMA_2   (0x1u << 26)
	(USBHS_DEVIDR) DMA Channel 2 Interrupt Disable More...
#define	USBHS_DEVIDR_DMA_3   (0x1u << 27)
	(USBHS_DEVIDR) DMA Channel 3 Interrupt Disable More...
#define	USBHS_DEVIDR_DMA_4   (0x1u << 28)
	(USBHS_DEVIDR) DMA Channel 4 Interrupt Disable More...
#define	USBHS_DEVIDR_DMA_5   (0x1u << 29)
	(USBHS_DEVIDR) DMA Channel 5 Interrupt Disable More...
#define	USBHS_DEVIDR_DMA_6   (0x1u << 30)
	(USBHS_DEVIDR) DMA Channel 6 Interrupt Disable More...
#define	USBHS_DEVIDR_DMA_7   (0x1u << 31)
	(USBHS_DEVIDR) DMA Channel 7 Interrupt Disable More...
#define	USBHS_DEVIDR_EORSMEC   (0x1u << 5)
	(USBHS_DEVIDR) End of Resume Interrupt Disable More...
#define	USBHS_DEVIDR_EORSTEC   (0x1u << 3)
	(USBHS_DEVIDR) End of Reset Interrupt Disable More...
#define	USBHS_DEVIDR_MSOFEC   (0x1u << 1)
	(USBHS_DEVIDR) Micro Start of Frame Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_0   (0x1u << 12)
	(USBHS_DEVIDR) Endpoint 0 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_1   (0x1u << 13)
	(USBHS_DEVIDR) Endpoint 1 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_2   (0x1u << 14)
	(USBHS_DEVIDR) Endpoint 2 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_3   (0x1u << 15)
	(USBHS_DEVIDR) Endpoint 3 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_4   (0x1u << 16)
	(USBHS_DEVIDR) Endpoint 4 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_5   (0x1u << 17)
	(USBHS_DEVIDR) Endpoint 5 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_6   (0x1u << 18)
	(USBHS_DEVIDR) Endpoint 6 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_7   (0x1u << 19)
	(USBHS_DEVIDR) Endpoint 7 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_8   (0x1u << 20)
	(USBHS_DEVIDR) Endpoint 8 Interrupt Disable More...
#define	USBHS_DEVIDR_PEP_9   (0x1u << 21)
	(USBHS_DEVIDR) Endpoint 9 Interrupt Disable More...
#define	USBHS_DEVIDR_SOFEC   (0x1u << 2)
	(USBHS_DEVIDR) Start of Frame Interrupt Disable More...
#define	USBHS_DEVIDR_SUSPEC   (0x1u << 0)
	(USBHS_DEVIDR) Suspend Interrupt Disable More...
#define	USBHS_DEVIDR_UPRSMEC   (0x1u << 6)
	(USBHS_DEVIDR) Upstream Resume Interrupt Disable More...
#define	USBHS_DEVIDR_WAKEUPEC   (0x1u << 4)
	(USBHS_DEVIDR) Wake-Up Interrupt Disable More...
#define	USBHS_DEVIER_DMA_1   (0x1u << 25)
	(USBHS_DEVIER) DMA Channel 1 Interrupt Enable More...
#define	USBHS_DEVIER_DMA_2   (0x1u << 26)
	(USBHS_DEVIER) DMA Channel 2 Interrupt Enable More...
#define	USBHS_DEVIER_DMA_3   (0x1u << 27)
	(USBHS_DEVIER) DMA Channel 3 Interrupt Enable More...
#define	USBHS_DEVIER_DMA_4   (0x1u << 28)
	(USBHS_DEVIER) DMA Channel 4 Interrupt Enable More...
#define	USBHS_DEVIER_DMA_5   (0x1u << 29)
	(USBHS_DEVIER) DMA Channel 5 Interrupt Enable More...
#define	USBHS_DEVIER_DMA_6   (0x1u << 30)
	(USBHS_DEVIER) DMA Channel 6 Interrupt Enable More...
#define	USBHS_DEVIER_DMA_7   (0x1u << 31)
	(USBHS_DEVIER) DMA Channel 7 Interrupt Enable More...
#define	USBHS_DEVIER_EORSMES   (0x1u << 5)
	(USBHS_DEVIER) End of Resume Interrupt Enable More...
#define	USBHS_DEVIER_EORSTES   (0x1u << 3)
	(USBHS_DEVIER) End of Reset Interrupt Enable More...
#define	USBHS_DEVIER_MSOFES   (0x1u << 1)
	(USBHS_DEVIER) Micro Start of Frame Interrupt Enable More...
#define	USBHS_DEVIER_PEP_0   (0x1u << 12)
	(USBHS_DEVIER) Endpoint 0 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_1   (0x1u << 13)
	(USBHS_DEVIER) Endpoint 1 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_2   (0x1u << 14)
	(USBHS_DEVIER) Endpoint 2 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_3   (0x1u << 15)
	(USBHS_DEVIER) Endpoint 3 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_4   (0x1u << 16)
	(USBHS_DEVIER) Endpoint 4 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_5   (0x1u << 17)
	(USBHS_DEVIER) Endpoint 5 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_6   (0x1u << 18)
	(USBHS_DEVIER) Endpoint 6 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_7   (0x1u << 19)
	(USBHS_DEVIER) Endpoint 7 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_8   (0x1u << 20)
	(USBHS_DEVIER) Endpoint 8 Interrupt Enable More...
#define	USBHS_DEVIER_PEP_9   (0x1u << 21)
	(USBHS_DEVIER) Endpoint 9 Interrupt Enable More...
#define	USBHS_DEVIER_SOFES   (0x1u << 2)
	(USBHS_DEVIER) Start of Frame Interrupt Enable More...
#define	USBHS_DEVIER_SUSPES   (0x1u << 0)
	(USBHS_DEVIER) Suspend Interrupt Enable More...
#define	USBHS_DEVIER_UPRSMES   (0x1u << 6)
	(USBHS_DEVIER) Upstream Resume Interrupt Enable More...
#define	USBHS_DEVIER_WAKEUPES   (0x1u << 4)
	(USBHS_DEVIER) Wake-Up Interrupt Enable More...
#define	USBHS_DEVIFR_DMA_1   (0x1u << 25)
	(USBHS_DEVIFR) DMA Channel 1 Interrupt Set More...
#define	USBHS_DEVIFR_DMA_2   (0x1u << 26)
	(USBHS_DEVIFR) DMA Channel 2 Interrupt Set More...
#define	USBHS_DEVIFR_DMA_3   (0x1u << 27)
	(USBHS_DEVIFR) DMA Channel 3 Interrupt Set More...
#define	USBHS_DEVIFR_DMA_4   (0x1u << 28)
	(USBHS_DEVIFR) DMA Channel 4 Interrupt Set More...
#define	USBHS_DEVIFR_DMA_5   (0x1u << 29)
	(USBHS_DEVIFR) DMA Channel 5 Interrupt Set More...
#define	USBHS_DEVIFR_DMA_6   (0x1u << 30)
	(USBHS_DEVIFR) DMA Channel 6 Interrupt Set More...
#define	USBHS_DEVIFR_DMA_7   (0x1u << 31)
	(USBHS_DEVIFR) DMA Channel 7 Interrupt Set More...
#define	USBHS_DEVIFR_EORSMS   (0x1u << 5)
	(USBHS_DEVIFR) End of Resume Interrupt Set More...
#define	USBHS_DEVIFR_EORSTS   (0x1u << 3)
	(USBHS_DEVIFR) End of Reset Interrupt Set More...
#define	USBHS_DEVIFR_MSOFS   (0x1u << 1)
	(USBHS_DEVIFR) Micro Start of Frame Interrupt Set More...
#define	USBHS_DEVIFR_SOFS   (0x1u << 2)
	(USBHS_DEVIFR) Start of Frame Interrupt Set More...
#define	USBHS_DEVIFR_SUSPS   (0x1u << 0)
	(USBHS_DEVIFR) Suspend Interrupt Set More...
#define	USBHS_DEVIFR_UPRSMS   (0x1u << 6)
	(USBHS_DEVIFR) Upstream Resume Interrupt Set More...
#define	USBHS_DEVIFR_WAKEUPS   (0x1u << 4)
	(USBHS_DEVIFR) Wake-Up Interrupt Set More...
#define	USBHS_DEVIMR_DMA_1   (0x1u << 25)
	(USBHS_DEVIMR) DMA Channel 1 Interrupt Mask More...
#define	USBHS_DEVIMR_DMA_2   (0x1u << 26)
	(USBHS_DEVIMR) DMA Channel 2 Interrupt Mask More...
#define	USBHS_DEVIMR_DMA_3   (0x1u << 27)
	(USBHS_DEVIMR) DMA Channel 3 Interrupt Mask More...
#define	USBHS_DEVIMR_DMA_4   (0x1u << 28)
	(USBHS_DEVIMR) DMA Channel 4 Interrupt Mask More...
#define	USBHS_DEVIMR_DMA_5   (0x1u << 29)
	(USBHS_DEVIMR) DMA Channel 5 Interrupt Mask More...
#define	USBHS_DEVIMR_DMA_6   (0x1u << 30)
	(USBHS_DEVIMR) DMA Channel 6 Interrupt Mask More...
#define	USBHS_DEVIMR_DMA_7   (0x1u << 31)
	(USBHS_DEVIMR) DMA Channel 7 Interrupt Mask More...
#define	USBHS_DEVIMR_EORSME   (0x1u << 5)
	(USBHS_DEVIMR) End of Resume Interrupt Mask More...
#define	USBHS_DEVIMR_EORSTE   (0x1u << 3)
	(USBHS_DEVIMR) End of Reset Interrupt Mask More...
#define	USBHS_DEVIMR_MSOFE   (0x1u << 1)
	(USBHS_DEVIMR) Micro Start of Frame Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_0   (0x1u << 12)
	(USBHS_DEVIMR) Endpoint 0 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_1   (0x1u << 13)
	(USBHS_DEVIMR) Endpoint 1 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_2   (0x1u << 14)
	(USBHS_DEVIMR) Endpoint 2 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_3   (0x1u << 15)
	(USBHS_DEVIMR) Endpoint 3 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_4   (0x1u << 16)
	(USBHS_DEVIMR) Endpoint 4 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_5   (0x1u << 17)
	(USBHS_DEVIMR) Endpoint 5 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_6   (0x1u << 18)
	(USBHS_DEVIMR) Endpoint 6 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_7   (0x1u << 19)
	(USBHS_DEVIMR) Endpoint 7 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_8   (0x1u << 20)
	(USBHS_DEVIMR) Endpoint 8 Interrupt Mask More...
#define	USBHS_DEVIMR_PEP_9   (0x1u << 21)
	(USBHS_DEVIMR) Endpoint 9 Interrupt Mask More...
#define	USBHS_DEVIMR_SOFE   (0x1u << 2)
	(USBHS_DEVIMR) Start of Frame Interrupt Mask More...
#define	USBHS_DEVIMR_SUSPE   (0x1u << 0)
	(USBHS_DEVIMR) Suspend Interrupt Mask More...
#define	USBHS_DEVIMR_UPRSME   (0x1u << 6)
	(USBHS_DEVIMR) Upstream Resume Interrupt Mask More...
#define	USBHS_DEVIMR_WAKEUPE   (0x1u << 4)
	(USBHS_DEVIMR) Wake-Up Interrupt Mask More...
#define	USBHS_DEVISR_DMA_1   (0x1u << 25)
	(USBHS_DEVISR) DMA Channel 1 Interrupt More...
#define	USBHS_DEVISR_DMA_2   (0x1u << 26)
	(USBHS_DEVISR) DMA Channel 2 Interrupt More...
#define	USBHS_DEVISR_DMA_3   (0x1u << 27)
	(USBHS_DEVISR) DMA Channel 3 Interrupt More...
#define	USBHS_DEVISR_DMA_4   (0x1u << 28)
	(USBHS_DEVISR) DMA Channel 4 Interrupt More...
#define	USBHS_DEVISR_DMA_5   (0x1u << 29)
	(USBHS_DEVISR) DMA Channel 5 Interrupt More...
#define	USBHS_DEVISR_DMA_6   (0x1u << 30)
	(USBHS_DEVISR) DMA Channel 6 Interrupt More...
#define	USBHS_DEVISR_DMA_7   (0x1u << 31)
	(USBHS_DEVISR) DMA Channel 7 Interrupt More...
#define	USBHS_DEVISR_EORSM   (0x1u << 5)
	(USBHS_DEVISR) End of Resume Interrupt More...
#define	USBHS_DEVISR_EORST   (0x1u << 3)
	(USBHS_DEVISR) End of Reset Interrupt More...
#define	USBHS_DEVISR_MSOF   (0x1u << 1)
	(USBHS_DEVISR) Micro Start of Frame Interrupt More...
#define	USBHS_DEVISR_PEP_0   (0x1u << 12)
	(USBHS_DEVISR) Endpoint 0 Interrupt More...
#define	USBHS_DEVISR_PEP_1   (0x1u << 13)
	(USBHS_DEVISR) Endpoint 1 Interrupt More...
#define	USBHS_DEVISR_PEP_2   (0x1u << 14)
	(USBHS_DEVISR) Endpoint 2 Interrupt More...
#define	USBHS_DEVISR_PEP_3   (0x1u << 15)
	(USBHS_DEVISR) Endpoint 3 Interrupt More...
#define	USBHS_DEVISR_PEP_4   (0x1u << 16)
	(USBHS_DEVISR) Endpoint 4 Interrupt More...
#define	USBHS_DEVISR_PEP_5   (0x1u << 17)
	(USBHS_DEVISR) Endpoint 5 Interrupt More...
#define	USBHS_DEVISR_PEP_6   (0x1u << 18)
	(USBHS_DEVISR) Endpoint 6 Interrupt More...
#define	USBHS_DEVISR_PEP_7   (0x1u << 19)
	(USBHS_DEVISR) Endpoint 7 Interrupt More...
#define	USBHS_DEVISR_PEP_8   (0x1u << 20)
	(USBHS_DEVISR) Endpoint 8 Interrupt More...
#define	USBHS_DEVISR_PEP_9   (0x1u << 21)
	(USBHS_DEVISR) Endpoint 9 Interrupt More...
#define	USBHS_DEVISR_SOF   (0x1u << 2)
	(USBHS_DEVISR) Start of Frame Interrupt More...
#define	USBHS_DEVISR_SUSP   (0x1u << 0)
	(USBHS_DEVISR) Suspend Interrupt More...
#define	USBHS_DEVISR_UPRSM   (0x1u << 6)
	(USBHS_DEVISR) Upstream Resume Interrupt More...
#define	USBHS_DEVISR_WAKEUP   (0x1u << 4)
	(USBHS_DEVISR) Wake-Up Interrupt More...
#define	USBHS_FSM_DRDSTATE_A_HOST   (0x3u << 0)
	(USBHS_FSM) In this state, the A-device that operates in Host mode is operational. More...
#define	USBHS_FSM_DRDSTATE_A_IDLESTATE   (0x0u << 0)
	(USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) More...
#define	USBHS_FSM_DRDSTATE_A_PERIPHERAL   (0x5u << 0)
	(USBHS_FSM) The A-device operates as a peripheral. More...
#define	USBHS_FSM_DRDSTATE_A_SUSPEND   (0x4u << 0)
	(USBHS_FSM) The A-device operating as a host is in the Suspend mode. More...
#define	USBHS_FSM_DRDSTATE_A_VBUS_ERR   (0x7u << 0)
	(USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. More...
#define	USBHS_FSM_DRDSTATE_A_WAIT_BCON   (0x2u << 0)
	(USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. More...
#define	USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE   (0x8u << 0)
	(USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). More...
#define	USBHS_FSM_DRDSTATE_A_WAIT_VFALL   (0x6u << 0)
	(USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). More...
#define	USBHS_FSM_DRDSTATE_A_WAIT_VRISE   (0x1u << 0)
	(USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). More...
#define	USBHS_FSM_DRDSTATE_B_HOST   (0xEu << 0)
	(USBHS_FSM) In this state, the B-device acts as the Host. More...
#define	USBHS_FSM_DRDSTATE_B_IDLE   (0x9u << 0)
	(USBHS_FSM) This is the start state for B-device (when the ID pin is 1). More...
#define	USBHS_FSM_DRDSTATE_B_PERIPHERAL   (0xAu << 0)
	(USBHS_FSM) In this state, the B-device acts as the peripheral. More...
#define	USBHS_FSM_DRDSTATE_B_SRP_INIT   (0xFu << 0)
	(USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. More...
#define	USBHS_FSM_DRDSTATE_B_WAIT_ACON   (0xDu << 0)
	(USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. More...
#define	USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP   (0xBu << 0)
	(USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. More...
#define	USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE   (0xCu << 0)
	(USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. More...
#define	USBHS_FSM_DRDSTATE_Msk   (0xfu << USBHS_FSM_DRDSTATE_Pos)
	(USBHS_FSM) Dual Role Device State More...
#define	USBHS_FSM_DRDSTATE_Pos   0
#define	USBHS_HSTADDR1_HSTADDRP0(value)   ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))
#define	USBHS_HSTADDR1_HSTADDRP0_Msk   (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos)
	(USBHS_HSTADDR1) USB Host Address More...
#define	USBHS_HSTADDR1_HSTADDRP0_Pos   0
#define	USBHS_HSTADDR1_HSTADDRP1(value)   ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))
#define	USBHS_HSTADDR1_HSTADDRP1_Msk   (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos)
	(USBHS_HSTADDR1) USB Host Address More...
#define	USBHS_HSTADDR1_HSTADDRP1_Pos   8
#define	USBHS_HSTADDR1_HSTADDRP2(value)   ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))
#define	USBHS_HSTADDR1_HSTADDRP2_Msk   (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos)
	(USBHS_HSTADDR1) USB Host Address More...
#define	USBHS_HSTADDR1_HSTADDRP2_Pos   16
#define	USBHS_HSTADDR1_HSTADDRP3(value)   ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))
#define	USBHS_HSTADDR1_HSTADDRP3_Msk   (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos)
	(USBHS_HSTADDR1) USB Host Address More...
#define	USBHS_HSTADDR1_HSTADDRP3_Pos   24
#define	USBHS_HSTADDR2_HSTADDRP4(value)   ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))
#define	USBHS_HSTADDR2_HSTADDRP4_Msk   (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos)
	(USBHS_HSTADDR2) USB Host Address More...
#define	USBHS_HSTADDR2_HSTADDRP4_Pos   0
#define	USBHS_HSTADDR2_HSTADDRP5(value)   ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))
#define	USBHS_HSTADDR2_HSTADDRP5_Msk   (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos)
	(USBHS_HSTADDR2) USB Host Address More...
#define	USBHS_HSTADDR2_HSTADDRP5_Pos   8
#define	USBHS_HSTADDR2_HSTADDRP6(value)   ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))
#define	USBHS_HSTADDR2_HSTADDRP6_Msk   (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos)
	(USBHS_HSTADDR2) USB Host Address More...
#define	USBHS_HSTADDR2_HSTADDRP6_Pos   16
#define	USBHS_HSTADDR2_HSTADDRP7(value)   ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))
#define	USBHS_HSTADDR2_HSTADDRP7_Msk   (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos)
	(USBHS_HSTADDR2) USB Host Address More...
#define	USBHS_HSTADDR2_HSTADDRP7_Pos   24
#define	USBHS_HSTADDR3_HSTADDRP8(value)   ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))
#define	USBHS_HSTADDR3_HSTADDRP8_Msk   (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos)
	(USBHS_HSTADDR3) USB Host Address More...
#define	USBHS_HSTADDR3_HSTADDRP8_Pos   0
#define	USBHS_HSTADDR3_HSTADDRP9(value)   ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))
#define	USBHS_HSTADDR3_HSTADDRP9_Msk   (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos)
	(USBHS_HSTADDR3) USB Host Address More...
#define	USBHS_HSTADDR3_HSTADDRP9_Pos   8
#define	USBHS_HSTCTRL_RESET   (0x1u << 9)
	(USBHS_HSTCTRL) Send USB Reset More...
#define	USBHS_HSTCTRL_RESUME   (0x1u << 10)
	(USBHS_HSTCTRL) Send USB Resume More...
#define	USBHS_HSTCTRL_SOFE   (0x1u << 8)
	(USBHS_HSTCTRL) Start of Frame Generation Enable More...
#define	USBHS_HSTCTRL_SPDCONF(value)   ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))
#define	USBHS_HSTCTRL_SPDCONF_FORCED_FS   (0x3u << 12)
	(USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. More...
#define	USBHS_HSTCTRL_SPDCONF_HIGH_SPEED   (0x2u << 12)
	(USBHS_HSTCTRL) Forced high speed. More...
#define	USBHS_HSTCTRL_SPDCONF_LOW_POWER   (0x1u << 12)
	(USBHS_HSTCTRL) For a better consumption, if high speed is not needed. More...
#define	USBHS_HSTCTRL_SPDCONF_Msk   (0x3u << USBHS_HSTCTRL_SPDCONF_Pos)
	(USBHS_HSTCTRL) Mode Configuration More...
#define	USBHS_HSTCTRL_SPDCONF_NORMAL   (0x0u << 12)
	(USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. More...
#define	USBHS_HSTCTRL_SPDCONF_Pos   12
#define	USBHS_HSTDMAADDRESS_BUFF_ADD(value)   ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
#define	USBHS_HSTDMAADDRESS_BUFF_ADD_Msk   (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)
	(USBHS_HSTDMAADDRESS) Buffer Address More...
#define	USBHS_HSTDMAADDRESS_BUFF_ADD_Pos   0
#define	USBHS_HSTDMACONTROL_BUFF_LENGTH(value)   ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
#define	USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk   (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)
	(USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) More...
#define	USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos   16
#define	USBHS_HSTDMACONTROL_BURST_LCK   (0x1u << 7)
	(USBHS_HSTDMACONTROL) Burst Lock Enable More...
#define	USBHS_HSTDMACONTROL_CHANN_ENB   (0x1u << 0)
	(USBHS_HSTDMACONTROL) Channel Enable Command More...
#define	USBHS_HSTDMACONTROL_DESC_LD_IT   (0x1u << 6)
	(USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable More...
#define	USBHS_HSTDMACONTROL_END_B_EN   (0x1u << 3)
	(USBHS_HSTDMACONTROL) End of Buffer Enable Control More...
#define	USBHS_HSTDMACONTROL_END_BUFFIT   (0x1u << 5)
	(USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable More...
#define	USBHS_HSTDMACONTROL_END_TR_EN   (0x1u << 2)
	(USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) More...
#define	USBHS_HSTDMACONTROL_END_TR_IT   (0x1u << 4)
	(USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable More...
#define	USBHS_HSTDMACONTROL_LDNXT_DSC   (0x1u << 1)
	(USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command More...
#define	USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value)   ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
#define	USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk   (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)
	(USBHS_HSTDMANXTDSC) Next Descriptor Address More...
#define	USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos   0
#define	USBHS_HSTDMASTATUS_BUFF_COUNT(value)   ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
#define	USBHS_HSTDMASTATUS_BUFF_COUNT_Msk   (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)
	(USBHS_HSTDMASTATUS) Buffer Byte Count More...
#define	USBHS_HSTDMASTATUS_BUFF_COUNT_Pos   16
#define	USBHS_HSTDMASTATUS_CHANN_ACT   (0x1u << 1)
	(USBHS_HSTDMASTATUS) Channel Active Status More...
#define	USBHS_HSTDMASTATUS_CHANN_ENB   (0x1u << 0)
	(USBHS_HSTDMASTATUS) Channel Enable Status More...
#define	USBHS_HSTDMASTATUS_DESC_LDST   (0x1u << 6)
	(USBHS_HSTDMASTATUS) Descriptor Loaded Status More...
#define	USBHS_HSTDMASTATUS_END_BF_ST   (0x1u << 5)
	(USBHS_HSTDMASTATUS) End of Channel Buffer Status More...
#define	USBHS_HSTDMASTATUS_END_TR_ST   (0x1u << 4)
	(USBHS_HSTDMASTATUS) End of Channel Transfer Status More...
#define	USBHS_HSTFNUM_FLENHIGH(value)   ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))
#define	USBHS_HSTFNUM_FLENHIGH_Msk   (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos)
	(USBHS_HSTFNUM) Frame Length More...
#define	USBHS_HSTFNUM_FLENHIGH_Pos   16
#define	USBHS_HSTFNUM_FNUM(value)   ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))
#define	USBHS_HSTFNUM_FNUM_Msk   (0x7ffu << USBHS_HSTFNUM_FNUM_Pos)
	(USBHS_HSTFNUM) Frame Number More...
#define	USBHS_HSTFNUM_FNUM_Pos   3
#define	USBHS_HSTFNUM_MFNUM(value)   ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))
#define	USBHS_HSTFNUM_MFNUM_Msk   (0x7u << USBHS_HSTFNUM_MFNUM_Pos)
	(USBHS_HSTFNUM) Micro Frame Number More...
#define	USBHS_HSTFNUM_MFNUM_Pos   0
#define	USBHS_HSTICR_DCONNIC   (0x1u << 0)
	(USBHS_HSTICR) Device Connection Interrupt Clear More...
#define	USBHS_HSTICR_DDISCIC   (0x1u << 1)
	(USBHS_HSTICR) Device Disconnection Interrupt Clear More...
#define	USBHS_HSTICR_HSOFIC   (0x1u << 5)
	(USBHS_HSTICR) Host Start of Frame Interrupt Clear More...
#define	USBHS_HSTICR_HWUPIC   (0x1u << 6)
	(USBHS_HSTICR) Host Wake-Up Interrupt Clear More...
#define	USBHS_HSTICR_RSMEDIC   (0x1u << 3)
	(USBHS_HSTICR) Downstream Resume Sent Interrupt Clear More...
#define	USBHS_HSTICR_RSTIC   (0x1u << 2)
	(USBHS_HSTICR) USB Reset Sent Interrupt Clear More...
#define	USBHS_HSTICR_RXRSMIC   (0x1u << 4)
	(USBHS_HSTICR) Upstream Resume Received Interrupt Clear More...
#define	USBHS_HSTIDR_DCONNIEC   (0x1u << 0)
	(USBHS_HSTIDR) Device Connection Interrupt Disable More...
#define	USBHS_HSTIDR_DDISCIEC   (0x1u << 1)
	(USBHS_HSTIDR) Device Disconnection Interrupt Disable More...
#define	USBHS_HSTIDR_DMA_1   (0x1u << 25)
	(USBHS_HSTIDR) DMA Channel 1 Interrupt Disable More...
#define	USBHS_HSTIDR_DMA_2   (0x1u << 26)
	(USBHS_HSTIDR) DMA Channel 2 Interrupt Disable More...
#define	USBHS_HSTIDR_DMA_3   (0x1u << 27)
	(USBHS_HSTIDR) DMA Channel 3 Interrupt Disable More...
#define	USBHS_HSTIDR_DMA_4   (0x1u << 28)
	(USBHS_HSTIDR) DMA Channel 4 Interrupt Disable More...
#define	USBHS_HSTIDR_DMA_5   (0x1u << 29)
	(USBHS_HSTIDR) DMA Channel 5 Interrupt Disable More...
#define	USBHS_HSTIDR_DMA_6   (0x1u << 30)
	(USBHS_HSTIDR) DMA Channel 6 Interrupt Disable More...
#define	USBHS_HSTIDR_DMA_7   (0x1u << 31)
	(USBHS_HSTIDR) DMA Channel 7 Interrupt Disable More...
#define	USBHS_HSTIDR_HSOFIEC   (0x1u << 5)
	(USBHS_HSTIDR) Host Start of Frame Interrupt Disable More...
#define	USBHS_HSTIDR_HWUPIEC   (0x1u << 6)
	(USBHS_HSTIDR) Host Wake-Up Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_0   (0x1u << 8)
	(USBHS_HSTIDR) Pipe 0 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_1   (0x1u << 9)
	(USBHS_HSTIDR) Pipe 1 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_2   (0x1u << 10)
	(USBHS_HSTIDR) Pipe 2 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_3   (0x1u << 11)
	(USBHS_HSTIDR) Pipe 3 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_4   (0x1u << 12)
	(USBHS_HSTIDR) Pipe 4 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_5   (0x1u << 13)
	(USBHS_HSTIDR) Pipe 5 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_6   (0x1u << 14)
	(USBHS_HSTIDR) Pipe 6 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_7   (0x1u << 15)
	(USBHS_HSTIDR) Pipe 7 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_8   (0x1u << 16)
	(USBHS_HSTIDR) Pipe 8 Interrupt Disable More...
#define	USBHS_HSTIDR_PEP_9   (0x1u << 17)
	(USBHS_HSTIDR) Pipe 9 Interrupt Disable More...
#define	USBHS_HSTIDR_RSMEDIEC   (0x1u << 3)
	(USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable More...
#define	USBHS_HSTIDR_RSTIEC   (0x1u << 2)
	(USBHS_HSTIDR) USB Reset Sent Interrupt Disable More...
#define	USBHS_HSTIDR_RXRSMIEC   (0x1u << 4)
	(USBHS_HSTIDR) Upstream Resume Received Interrupt Disable More...
#define	USBHS_HSTIER_DCONNIES   (0x1u << 0)
	(USBHS_HSTIER) Device Connection Interrupt Enable More...
#define	USBHS_HSTIER_DDISCIES   (0x1u << 1)
	(USBHS_HSTIER) Device Disconnection Interrupt Enable More...
#define	USBHS_HSTIER_DMA_1   (0x1u << 25)
	(USBHS_HSTIER) DMA Channel 1 Interrupt Enable More...
#define	USBHS_HSTIER_DMA_2   (0x1u << 26)
	(USBHS_HSTIER) DMA Channel 2 Interrupt Enable More...
#define	USBHS_HSTIER_DMA_3   (0x1u << 27)
	(USBHS_HSTIER) DMA Channel 3 Interrupt Enable More...
#define	USBHS_HSTIER_DMA_4   (0x1u << 28)
	(USBHS_HSTIER) DMA Channel 4 Interrupt Enable More...
#define	USBHS_HSTIER_DMA_5   (0x1u << 29)
	(USBHS_HSTIER) DMA Channel 5 Interrupt Enable More...
#define	USBHS_HSTIER_DMA_6   (0x1u << 30)
	(USBHS_HSTIER) DMA Channel 6 Interrupt Enable More...
#define	USBHS_HSTIER_DMA_7   (0x1u << 31)
	(USBHS_HSTIER) DMA Channel 7 Interrupt Enable More...
#define	USBHS_HSTIER_HSOFIES   (0x1u << 5)
	(USBHS_HSTIER) Host Start of Frame Interrupt Enable More...
#define	USBHS_HSTIER_HWUPIES   (0x1u << 6)
	(USBHS_HSTIER) Host Wake-Up Interrupt Enable More...
#define	USBHS_HSTIER_PEP_0   (0x1u << 8)
	(USBHS_HSTIER) Pipe 0 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_1   (0x1u << 9)
	(USBHS_HSTIER) Pipe 1 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_2   (0x1u << 10)
	(USBHS_HSTIER) Pipe 2 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_3   (0x1u << 11)
	(USBHS_HSTIER) Pipe 3 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_4   (0x1u << 12)
	(USBHS_HSTIER) Pipe 4 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_5   (0x1u << 13)
	(USBHS_HSTIER) Pipe 5 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_6   (0x1u << 14)
	(USBHS_HSTIER) Pipe 6 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_7   (0x1u << 15)
	(USBHS_HSTIER) Pipe 7 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_8   (0x1u << 16)
	(USBHS_HSTIER) Pipe 8 Interrupt Enable More...
#define	USBHS_HSTIER_PEP_9   (0x1u << 17)
	(USBHS_HSTIER) Pipe 9 Interrupt Enable More...
#define	USBHS_HSTIER_RSMEDIES   (0x1u << 3)
	(USBHS_HSTIER) Downstream Resume Sent Interrupt Enable More...
#define	USBHS_HSTIER_RSTIES   (0x1u << 2)
	(USBHS_HSTIER) USB Reset Sent Interrupt Enable More...
#define	USBHS_HSTIER_RXRSMIES   (0x1u << 4)
	(USBHS_HSTIER) Upstream Resume Received Interrupt Enable More...
#define	USBHS_HSTIFR_DCONNIS   (0x1u << 0)
	(USBHS_HSTIFR) Device Connection Interrupt Set More...
#define	USBHS_HSTIFR_DDISCIS   (0x1u << 1)
	(USBHS_HSTIFR) Device Disconnection Interrupt Set More...
#define	USBHS_HSTIFR_DMA_1   (0x1u << 25)
	(USBHS_HSTIFR) DMA Channel 1 Interrupt Set More...
#define	USBHS_HSTIFR_DMA_2   (0x1u << 26)
	(USBHS_HSTIFR) DMA Channel 2 Interrupt Set More...
#define	USBHS_HSTIFR_DMA_3   (0x1u << 27)
	(USBHS_HSTIFR) DMA Channel 3 Interrupt Set More...
#define	USBHS_HSTIFR_DMA_4   (0x1u << 28)
	(USBHS_HSTIFR) DMA Channel 4 Interrupt Set More...
#define	USBHS_HSTIFR_DMA_5   (0x1u << 29)
	(USBHS_HSTIFR) DMA Channel 5 Interrupt Set More...
#define	USBHS_HSTIFR_DMA_6   (0x1u << 30)
	(USBHS_HSTIFR) DMA Channel 6 Interrupt Set More...
#define	USBHS_HSTIFR_DMA_7   (0x1u << 31)
	(USBHS_HSTIFR) DMA Channel 7 Interrupt Set More...
#define	USBHS_HSTIFR_HSOFIS   (0x1u << 5)
	(USBHS_HSTIFR) Host Start of Frame Interrupt Set More...
#define	USBHS_HSTIFR_HWUPIS   (0x1u << 6)
	(USBHS_HSTIFR) Host Wake-Up Interrupt Set More...
#define	USBHS_HSTIFR_RSMEDIS   (0x1u << 3)
	(USBHS_HSTIFR) Downstream Resume Sent Interrupt Set More...
#define	USBHS_HSTIFR_RSTIS   (0x1u << 2)
	(USBHS_HSTIFR) USB Reset Sent Interrupt Set More...
#define	USBHS_HSTIFR_RXRSMIS   (0x1u << 4)
	(USBHS_HSTIFR) Upstream Resume Received Interrupt Set More...
#define	USBHS_HSTIMR_DCONNIE   (0x1u << 0)
	(USBHS_HSTIMR) Device Connection Interrupt Enable More...
#define	USBHS_HSTIMR_DDISCIE   (0x1u << 1)
	(USBHS_HSTIMR) Device Disconnection Interrupt Enable More...
#define	USBHS_HSTIMR_DMA_1   (0x1u << 25)
	(USBHS_HSTIMR) DMA Channel 1 Interrupt Enable More...
#define	USBHS_HSTIMR_DMA_2   (0x1u << 26)
	(USBHS_HSTIMR) DMA Channel 2 Interrupt Enable More...
#define	USBHS_HSTIMR_DMA_3   (0x1u << 27)
	(USBHS_HSTIMR) DMA Channel 3 Interrupt Enable More...
#define	USBHS_HSTIMR_DMA_4   (0x1u << 28)
	(USBHS_HSTIMR) DMA Channel 4 Interrupt Enable More...
#define	USBHS_HSTIMR_DMA_5   (0x1u << 29)
	(USBHS_HSTIMR) DMA Channel 5 Interrupt Enable More...
#define	USBHS_HSTIMR_DMA_6   (0x1u << 30)
	(USBHS_HSTIMR) DMA Channel 6 Interrupt Enable More...
#define	USBHS_HSTIMR_DMA_7   (0x1u << 31)
	(USBHS_HSTIMR) DMA Channel 7 Interrupt Enable More...
#define	USBHS_HSTIMR_HSOFIE   (0x1u << 5)
	(USBHS_HSTIMR) Host Start of Frame Interrupt Enable More...
#define	USBHS_HSTIMR_HWUPIE   (0x1u << 6)
	(USBHS_HSTIMR) Host Wake-Up Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_0   (0x1u << 8)
	(USBHS_HSTIMR) Pipe 0 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_1   (0x1u << 9)
	(USBHS_HSTIMR) Pipe 1 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_2   (0x1u << 10)
	(USBHS_HSTIMR) Pipe 2 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_3   (0x1u << 11)
	(USBHS_HSTIMR) Pipe 3 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_4   (0x1u << 12)
	(USBHS_HSTIMR) Pipe 4 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_5   (0x1u << 13)
	(USBHS_HSTIMR) Pipe 5 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_6   (0x1u << 14)
	(USBHS_HSTIMR) Pipe 6 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_7   (0x1u << 15)
	(USBHS_HSTIMR) Pipe 7 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_8   (0x1u << 16)
	(USBHS_HSTIMR) Pipe 8 Interrupt Enable More...
#define	USBHS_HSTIMR_PEP_9   (0x1u << 17)
	(USBHS_HSTIMR) Pipe 9 Interrupt Enable More...
#define	USBHS_HSTIMR_RSMEDIE   (0x1u << 3)
	(USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable More...
#define	USBHS_HSTIMR_RSTIE   (0x1u << 2)
	(USBHS_HSTIMR) USB Reset Sent Interrupt Enable More...
#define	USBHS_HSTIMR_RXRSMIE   (0x1u << 4)
	(USBHS_HSTIMR) Upstream Resume Received Interrupt Enable More...
#define	USBHS_HSTISR_DCONNI   (0x1u << 0)
	(USBHS_HSTISR) Device Connection Interrupt More...
#define	USBHS_HSTISR_DDISCI   (0x1u << 1)
	(USBHS_HSTISR) Device Disconnection Interrupt More...
#define	USBHS_HSTISR_DMA_1   (0x1u << 25)
	(USBHS_HSTISR) DMA Channel 1 Interrupt More...
#define	USBHS_HSTISR_DMA_2   (0x1u << 26)
	(USBHS_HSTISR) DMA Channel 2 Interrupt More...
#define	USBHS_HSTISR_DMA_3   (0x1u << 27)
	(USBHS_HSTISR) DMA Channel 3 Interrupt More...
#define	USBHS_HSTISR_DMA_4   (0x1u << 28)
	(USBHS_HSTISR) DMA Channel 4 Interrupt More...
#define	USBHS_HSTISR_DMA_5   (0x1u << 29)
	(USBHS_HSTISR) DMA Channel 5 Interrupt More...
#define	USBHS_HSTISR_DMA_6   (0x1u << 30)
	(USBHS_HSTISR) DMA Channel 6 Interrupt More...
#define	USBHS_HSTISR_DMA_7   (0x1u << 31)
	(USBHS_HSTISR) DMA Channel 7 Interrupt More...
#define	USBHS_HSTISR_HSOFI   (0x1u << 5)
	(USBHS_HSTISR) Host Start of Frame Interrupt More...
#define	USBHS_HSTISR_HWUPI   (0x1u << 6)
	(USBHS_HSTISR) Host Wake-Up Interrupt More...
#define	USBHS_HSTISR_PEP_0   (0x1u << 8)
	(USBHS_HSTISR) Pipe 0 Interrupt More...
#define	USBHS_HSTISR_PEP_1   (0x1u << 9)
	(USBHS_HSTISR) Pipe 1 Interrupt More...
#define	USBHS_HSTISR_PEP_2   (0x1u << 10)
	(USBHS_HSTISR) Pipe 2 Interrupt More...
#define	USBHS_HSTISR_PEP_3   (0x1u << 11)
	(USBHS_HSTISR) Pipe 3 Interrupt More...
#define	USBHS_HSTISR_PEP_4   (0x1u << 12)
	(USBHS_HSTISR) Pipe 4 Interrupt More...
#define	USBHS_HSTISR_PEP_5   (0x1u << 13)
	(USBHS_HSTISR) Pipe 5 Interrupt More...
#define	USBHS_HSTISR_PEP_6   (0x1u << 14)
	(USBHS_HSTISR) Pipe 6 Interrupt More...
#define	USBHS_HSTISR_PEP_7   (0x1u << 15)
	(USBHS_HSTISR) Pipe 7 Interrupt More...
#define	USBHS_HSTISR_PEP_8   (0x1u << 16)
	(USBHS_HSTISR) Pipe 8 Interrupt More...
#define	USBHS_HSTISR_PEP_9   (0x1u << 17)
	(USBHS_HSTISR) Pipe 9 Interrupt More...
#define	USBHS_HSTISR_RSMEDI   (0x1u << 3)
	(USBHS_HSTISR) Downstream Resume Sent Interrupt More...
#define	USBHS_HSTISR_RSTI   (0x1u << 2)
	(USBHS_HSTISR) USB Reset Sent Interrupt More...
#define	USBHS_HSTISR_RXRSMI   (0x1u << 4)
	(USBHS_HSTISR) Upstream Resume Received Interrupt More...
#define	USBHS_HSTPIP_PEN0   (0x1u << 0)
	(USBHS_HSTPIP) Pipe 0 Enable More...
#define	USBHS_HSTPIP_PEN1   (0x1u << 1)
	(USBHS_HSTPIP) Pipe 1 Enable More...
#define	USBHS_HSTPIP_PEN2   (0x1u << 2)
	(USBHS_HSTPIP) Pipe 2 Enable More...
#define	USBHS_HSTPIP_PEN3   (0x1u << 3)
	(USBHS_HSTPIP) Pipe 3 Enable More...
#define	USBHS_HSTPIP_PEN4   (0x1u << 4)
	(USBHS_HSTPIP) Pipe 4 Enable More...
#define	USBHS_HSTPIP_PEN5   (0x1u << 5)
	(USBHS_HSTPIP) Pipe 5 Enable More...
#define	USBHS_HSTPIP_PEN6   (0x1u << 6)
	(USBHS_HSTPIP) Pipe 6 Enable More...
#define	USBHS_HSTPIP_PEN7   (0x1u << 7)
	(USBHS_HSTPIP) Pipe 7 Enable More...
#define	USBHS_HSTPIP_PEN8   (0x1u << 8)
	(USBHS_HSTPIP) Pipe 8 Enable More...
#define	USBHS_HSTPIP_PRST0   (0x1u << 16)
	(USBHS_HSTPIP) Pipe 0 Reset More...
#define	USBHS_HSTPIP_PRST1   (0x1u << 17)
	(USBHS_HSTPIP) Pipe 1 Reset More...
#define	USBHS_HSTPIP_PRST2   (0x1u << 18)
	(USBHS_HSTPIP) Pipe 2 Reset More...
#define	USBHS_HSTPIP_PRST3   (0x1u << 19)
	(USBHS_HSTPIP) Pipe 3 Reset More...
#define	USBHS_HSTPIP_PRST4   (0x1u << 20)
	(USBHS_HSTPIP) Pipe 4 Reset More...
#define	USBHS_HSTPIP_PRST5   (0x1u << 21)
	(USBHS_HSTPIP) Pipe 5 Reset More...
#define	USBHS_HSTPIP_PRST6   (0x1u << 22)
	(USBHS_HSTPIP) Pipe 6 Reset More...
#define	USBHS_HSTPIP_PRST7   (0x1u << 23)
	(USBHS_HSTPIP) Pipe 7 Reset More...
#define	USBHS_HSTPIP_PRST8   (0x1u << 24)
	(USBHS_HSTPIP) Pipe 8 Reset More...
#define	USBHS_HSTPIPCFG_ALLOC   (0x1u << 1)
	(USBHS_HSTPIPCFG[10]) Pipe Memory Allocate More...
#define	USBHS_HSTPIPCFG_AUTOSW   (0x1u << 10)
	(USBHS_HSTPIPCFG[10]) Automatic Switch More...
#define	USBHS_HSTPIPCFG_BINTERVAL(value)   ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))
#define	USBHS_HSTPIPCFG_BINTERVAL_Msk   (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos)
	(USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction More...
#define	USBHS_HSTPIPCFG_BINTERVAL_Pos   24
#define	USBHS_HSTPIPCFG_INTFRQ(value)   ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))
#define	USBHS_HSTPIPCFG_INTFRQ_Msk   (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency More...
#define	USBHS_HSTPIPCFG_INTFRQ_Pos   24
#define	USBHS_HSTPIPCFG_PBK(value)   ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))
#define	USBHS_HSTPIPCFG_PBK_1_BANK   (0x0u << 2)
	(USBHS_HSTPIPCFG[10]) Single-bank pipe More...
#define	USBHS_HSTPIPCFG_PBK_2_BANK   (0x1u << 2)
	(USBHS_HSTPIPCFG[10]) Double-bank pipe More...
#define	USBHS_HSTPIPCFG_PBK_3_BANK   (0x2u << 2)
	(USBHS_HSTPIPCFG[10]) Triple-bank pipe More...
#define	USBHS_HSTPIPCFG_PBK_Msk   (0x3u << USBHS_HSTPIPCFG_PBK_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Banks More...
#define	USBHS_HSTPIPCFG_PBK_Pos   2
#define	USBHS_HSTPIPCFG_PEPNUM(value)   ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))
#define	USBHS_HSTPIPCFG_PEPNUM_Msk   (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Endpoint Number More...
#define	USBHS_HSTPIPCFG_PEPNUM_Pos   16
#define	USBHS_HSTPIPCFG_PINGEN   (0x1u << 20)
	(USBHS_HSTPIPCFG[10]) Ping Enable More...
#define	USBHS_HSTPIPCFG_PSIZE(value)   ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))
#define	USBHS_HSTPIPCFG_PSIZE_1024_BYTE   (0x7u << 4)
	(USBHS_HSTPIPCFG[10]) 1024 bytes More...
#define	USBHS_HSTPIPCFG_PSIZE_128_BYTE   (0x4u << 4)
	(USBHS_HSTPIPCFG[10]) 128 bytes More...
#define	USBHS_HSTPIPCFG_PSIZE_16_BYTE   (0x1u << 4)
	(USBHS_HSTPIPCFG[10]) 16 bytes More...
#define	USBHS_HSTPIPCFG_PSIZE_256_BYTE   (0x5u << 4)
	(USBHS_HSTPIPCFG[10]) 256 bytes More...
#define	USBHS_HSTPIPCFG_PSIZE_32_BYTE   (0x2u << 4)
	(USBHS_HSTPIPCFG[10]) 32 bytes More...
#define	USBHS_HSTPIPCFG_PSIZE_512_BYTE   (0x6u << 4)
	(USBHS_HSTPIPCFG[10]) 512 bytes More...
#define	USBHS_HSTPIPCFG_PSIZE_64_BYTE   (0x3u << 4)
	(USBHS_HSTPIPCFG[10]) 64 bytes More...
#define	USBHS_HSTPIPCFG_PSIZE_8_BYTE   (0x0u << 4)
	(USBHS_HSTPIPCFG[10]) 8 bytes More...
#define	USBHS_HSTPIPCFG_PSIZE_Msk   (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Size More...
#define	USBHS_HSTPIPCFG_PSIZE_Pos   4
#define	USBHS_HSTPIPCFG_PTOKEN(value)   ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))
#define	USBHS_HSTPIPCFG_PTOKEN_IN   (0x1u << 8)
	(USBHS_HSTPIPCFG[10]) IN More...
#define	USBHS_HSTPIPCFG_PTOKEN_Msk   (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Token More...
#define	USBHS_HSTPIPCFG_PTOKEN_OUT   (0x2u << 8)
	(USBHS_HSTPIPCFG[10]) OUT More...
#define	USBHS_HSTPIPCFG_PTOKEN_Pos   8
#define	USBHS_HSTPIPCFG_PTOKEN_SETUP   (0x0u << 8)
	(USBHS_HSTPIPCFG[10]) SETUP More...
#define	USBHS_HSTPIPCFG_PTYPE(value)   ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))
#define	USBHS_HSTPIPCFG_PTYPE_BLK   (0x2u << 12)
	(USBHS_HSTPIPCFG[10]) Bulk More...
#define	USBHS_HSTPIPCFG_PTYPE_CTRL   (0x0u << 12)
	(USBHS_HSTPIPCFG[10]) Control More...
#define	USBHS_HSTPIPCFG_PTYPE_INTRPT   (0x3u << 12)
	(USBHS_HSTPIPCFG[10]) Interrupt More...
#define	USBHS_HSTPIPCFG_PTYPE_ISO   (0x1u << 12)
	(USBHS_HSTPIPCFG[10]) Isochronous More...
#define	USBHS_HSTPIPCFG_PTYPE_Msk   (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Type More...
#define	USBHS_HSTPIPCFG_PTYPE_Pos   12
#define	USBHS_HSTPIPERR_COUNTER(value)   ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))
#define	USBHS_HSTPIPERR_COUNTER_Msk   (0x3u << USBHS_HSTPIPERR_COUNTER_Pos)
	(USBHS_HSTPIPERR[10]) Error Counter More...
#define	USBHS_HSTPIPERR_COUNTER_Pos   5
#define	USBHS_HSTPIPERR_CRC16   (0x1u << 4)
	(USBHS_HSTPIPERR[10]) CRC16 Error More...
#define	USBHS_HSTPIPERR_DATAPID   (0x1u << 1)
	(USBHS_HSTPIPERR[10]) Data PID Error More...
#define	USBHS_HSTPIPERR_DATATGL   (0x1u << 0)
	(USBHS_HSTPIPERR[10]) Data Toggle Error More...
#define	USBHS_HSTPIPERR_PID   (0x1u << 2)
	(USBHS_HSTPIPERR[10]) Data PID Error More...
#define	USBHS_HSTPIPERR_TIMEOUT   (0x1u << 3)
	(USBHS_HSTPIPERR[10]) Time-Out Error More...
#define	USBHS_HSTPIPICR_CRCERRIC   (0x1u << 6)
	(USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear More...
#define	USBHS_HSTPIPICR_NAKEDIC   (0x1u << 4)
	(USBHS_HSTPIPICR[10]) NAKed Interrupt Clear More...
#define	USBHS_HSTPIPICR_OVERFIC   (0x1u << 5)
	(USBHS_HSTPIPICR[10]) Overflow Interrupt Clear More...
#define	USBHS_HSTPIPICR_RXINIC   (0x1u << 0)
	(USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear More...
#define	USBHS_HSTPIPICR_RXSTALLDIC   (0x1u << 6)
	(USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear More...
#define	USBHS_HSTPIPICR_SHORTPACKETIC   (0x1u << 7)
	(USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear More...
#define	USBHS_HSTPIPICR_TXOUTIC   (0x1u << 1)
	(USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear More...
#define	USBHS_HSTPIPICR_TXSTPIC   (0x1u << 2)
	(USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear More...
#define	USBHS_HSTPIPICR_UNDERFIC   (0x1u << 2)
	(USBHS_HSTPIPICR[10]) Underflow Interrupt Clear More...
#define	USBHS_HSTPIPIDR_CRCERREC   (0x1u << 6)
	(USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable More...
#define	USBHS_HSTPIPIDR_FIFOCONC   (0x1u << 14)
	(USBHS_HSTPIPIDR[10]) FIFO Control Disable More...
#define	USBHS_HSTPIPIDR_NAKEDEC   (0x1u << 4)
	(USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable More...
#define	USBHS_HSTPIPIDR_NBUSYBKEC   (0x1u << 12)
	(USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable More...
#define	USBHS_HSTPIPIDR_OVERFIEC   (0x1u << 5)
	(USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable More...
#define	USBHS_HSTPIPIDR_PDISHDMAC   (0x1u << 16)
	(USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable More...
#define	USBHS_HSTPIPIDR_PERREC   (0x1u << 3)
	(USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable More...
#define	USBHS_HSTPIPIDR_PFREEZEC   (0x1u << 17)
	(USBHS_HSTPIPIDR[10]) Pipe Freeze Disable More...
#define	USBHS_HSTPIPIDR_RXINEC   (0x1u << 0)
	(USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable More...
#define	USBHS_HSTPIPIDR_RXSTALLDEC   (0x1u << 6)
	(USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable More...
#define	USBHS_HSTPIPIDR_SHORTPACKETIEC   (0x1u << 7)
	(USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable More...
#define	USBHS_HSTPIPIDR_TXOUTEC   (0x1u << 1)
	(USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable More...
#define	USBHS_HSTPIPIDR_TXSTPEC   (0x1u << 2)
	(USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable More...
#define	USBHS_HSTPIPIDR_UNDERFIEC   (0x1u << 2)
	(USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable More...
#define	USBHS_HSTPIPIER_CRCERRES   (0x1u << 6)
	(USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable More...
#define	USBHS_HSTPIPIER_NAKEDES   (0x1u << 4)
	(USBHS_HSTPIPIER[10]) NAKed Interrupt Enable More...
#define	USBHS_HSTPIPIER_NBUSYBKES   (0x1u << 12)
	(USBHS_HSTPIPIER[10]) Number of Busy Banks Enable More...
#define	USBHS_HSTPIPIER_OVERFIES   (0x1u << 5)
	(USBHS_HSTPIPIER[10]) Overflow Interrupt Enable More...
#define	USBHS_HSTPIPIER_PDISHDMAS   (0x1u << 16)
	(USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable More...
#define	USBHS_HSTPIPIER_PERRES   (0x1u << 3)
	(USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable More...
#define	USBHS_HSTPIPIER_PFREEZES   (0x1u << 17)
	(USBHS_HSTPIPIER[10]) Pipe Freeze Enable More...
#define	USBHS_HSTPIPIER_RSTDTS   (0x1u << 18)
	(USBHS_HSTPIPIER[10]) Reset Data Toggle Enable More...
#define	USBHS_HSTPIPIER_RXINES   (0x1u << 0)
	(USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable More...
#define	USBHS_HSTPIPIER_RXSTALLDES   (0x1u << 6)
	(USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable More...
#define	USBHS_HSTPIPIER_SHORTPACKETIES   (0x1u << 7)
	(USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable More...
#define	USBHS_HSTPIPIER_TXOUTES   (0x1u << 1)
	(USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable More...
#define	USBHS_HSTPIPIER_TXSTPES   (0x1u << 2)
	(USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable More...
#define	USBHS_HSTPIPIER_UNDERFIES   (0x1u << 2)
	(USBHS_HSTPIPIER[10]) Underflow Interrupt Enable More...
#define	USBHS_HSTPIPIFR_CRCERRIS   (0x1u << 6)
	(USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set More...
#define	USBHS_HSTPIPIFR_NAKEDIS   (0x1u << 4)
	(USBHS_HSTPIPIFR[10]) NAKed Interrupt Set More...
#define	USBHS_HSTPIPIFR_NBUSYBKS   (0x1u << 12)
	(USBHS_HSTPIPIFR[10]) Number of Busy Banks Set More...
#define	USBHS_HSTPIPIFR_OVERFIS   (0x1u << 5)
	(USBHS_HSTPIPIFR[10]) Overflow Interrupt Set More...
#define	USBHS_HSTPIPIFR_PERRIS   (0x1u << 3)
	(USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set More...
#define	USBHS_HSTPIPIFR_RXINIS   (0x1u << 0)
	(USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set More...
#define	USBHS_HSTPIPIFR_RXSTALLDIS   (0x1u << 6)
	(USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set More...
#define	USBHS_HSTPIPIFR_SHORTPACKETIS   (0x1u << 7)
	(USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set More...
#define	USBHS_HSTPIPIFR_TXOUTIS   (0x1u << 1)
	(USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set More...
#define	USBHS_HSTPIPIFR_TXSTPIS   (0x1u << 2)
	(USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set More...
#define	USBHS_HSTPIPIFR_UNDERFIS   (0x1u << 2)
	(USBHS_HSTPIPIFR[10]) Underflow Interrupt Set More...
#define	USBHS_HSTPIPIMR_CRCERRE   (0x1u << 6)
	(USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable More...
#define	USBHS_HSTPIPIMR_FIFOCON   (0x1u << 14)
	(USBHS_HSTPIPIMR[10]) FIFO Control More...
#define	USBHS_HSTPIPIMR_NAKEDE   (0x1u << 4)
	(USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable More...
#define	USBHS_HSTPIPIMR_NBUSYBKE   (0x1u << 12)
	(USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable More...
#define	USBHS_HSTPIPIMR_OVERFIE   (0x1u << 5)
	(USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable More...
#define	USBHS_HSTPIPIMR_PDISHDMA   (0x1u << 16)
	(USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable More...
#define	USBHS_HSTPIPIMR_PERRE   (0x1u << 3)
	(USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable More...
#define	USBHS_HSTPIPIMR_PFREEZE   (0x1u << 17)
	(USBHS_HSTPIPIMR[10]) Pipe Freeze More...
#define	USBHS_HSTPIPIMR_RSTDT   (0x1u << 18)
	(USBHS_HSTPIPIMR[10]) Reset Data Toggle More...
#define	USBHS_HSTPIPIMR_RXINE   (0x1u << 0)
	(USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable More...
#define	USBHS_HSTPIPIMR_RXSTALLDE   (0x1u << 6)
	(USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable More...
#define	USBHS_HSTPIPIMR_SHORTPACKETIE   (0x1u << 7)
	(USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable More...
#define	USBHS_HSTPIPIMR_TXOUTE   (0x1u << 1)
	(USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable More...
#define	USBHS_HSTPIPIMR_TXSTPE   (0x1u << 2)
	(USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable More...
#define	USBHS_HSTPIPIMR_UNDERFIE   (0x1u << 2)
	(USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable More...
#define	USBHS_HSTPIPINRQ_INMODE   (0x1u << 8)
	(USBHS_HSTPIPINRQ[10]) IN Request Mode More...
#define	USBHS_HSTPIPINRQ_INRQ(value)   ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))
#define	USBHS_HSTPIPINRQ_INRQ_Msk   (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos)
	(USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze More...
#define	USBHS_HSTPIPINRQ_INRQ_Pos   0
#define	USBHS_HSTPIPISR_CFGOK   (0x1u << 18)
	(USBHS_HSTPIPISR[10]) Configuration OK Status More...
#define	USBHS_HSTPIPISR_CRCERRI   (0x1u << 6)
	(USBHS_HSTPIPISR[10]) CRC Error Interrupt More...
#define	USBHS_HSTPIPISR_CURRBK_BANK0   (0x0u << 14)
	(USBHS_HSTPIPISR[10]) Current bank is bank0 More...
#define	USBHS_HSTPIPISR_CURRBK_BANK1   (0x1u << 14)
	(USBHS_HSTPIPISR[10]) Current bank is bank1 More...
#define	USBHS_HSTPIPISR_CURRBK_BANK2   (0x2u << 14)
	(USBHS_HSTPIPISR[10]) Current bank is bank2 More...
#define	USBHS_HSTPIPISR_CURRBK_Msk   (0x3u << USBHS_HSTPIPISR_CURRBK_Pos)
	(USBHS_HSTPIPISR[10]) Current Bank More...
#define	USBHS_HSTPIPISR_CURRBK_Pos   14
#define	USBHS_HSTPIPISR_DTSEQ_DATA0   (0x0u << 8)
	(USBHS_HSTPIPISR[10]) Data0 toggle sequence More...
#define	USBHS_HSTPIPISR_DTSEQ_DATA1   (0x1u << 8)
	(USBHS_HSTPIPISR[10]) Data1 toggle sequence More...
#define	USBHS_HSTPIPISR_DTSEQ_Msk   (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos)
	(USBHS_HSTPIPISR[10]) Data Toggle Sequence More...
#define	USBHS_HSTPIPISR_DTSEQ_Pos   8
#define	USBHS_HSTPIPISR_NAKEDI   (0x1u << 4)
	(USBHS_HSTPIPISR[10]) NAKed Interrupt More...
#define	USBHS_HSTPIPISR_NBUSYBK_0_BUSY   (0x0u << 12)
	(USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) More...
#define	USBHS_HSTPIPISR_NBUSYBK_1_BUSY   (0x1u << 12)
	(USBHS_HSTPIPISR[10]) 1 busy bank More...
#define	USBHS_HSTPIPISR_NBUSYBK_2_BUSY   (0x2u << 12)
	(USBHS_HSTPIPISR[10]) 2 busy banks More...
#define	USBHS_HSTPIPISR_NBUSYBK_3_BUSY   (0x3u << 12)
	(USBHS_HSTPIPISR[10]) 3 busy banks More...
#define	USBHS_HSTPIPISR_NBUSYBK_Msk   (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos)
	(USBHS_HSTPIPISR[10]) Number of Busy Banks More...
#define	USBHS_HSTPIPISR_NBUSYBK_Pos   12
#define	USBHS_HSTPIPISR_OVERFI   (0x1u << 5)
	(USBHS_HSTPIPISR[10]) Overflow Interrupt More...
#define	USBHS_HSTPIPISR_PBYCT_Msk   (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos)
	(USBHS_HSTPIPISR[10]) Pipe Byte Count More...
#define	USBHS_HSTPIPISR_PBYCT_Pos   20
#define	USBHS_HSTPIPISR_PERRI   (0x1u << 3)
	(USBHS_HSTPIPISR[10]) Pipe Error Interrupt More...
#define	USBHS_HSTPIPISR_RWALL   (0x1u << 16)
	(USBHS_HSTPIPISR[10]) Read/Write Allowed More...
#define	USBHS_HSTPIPISR_RXINI   (0x1u << 0)
	(USBHS_HSTPIPISR[10]) Received IN Data Interrupt More...
#define	USBHS_HSTPIPISR_RXSTALLDI   (0x1u << 6)
	(USBHS_HSTPIPISR[10]) Received STALLed Interrupt More...
#define	USBHS_HSTPIPISR_SHORTPACKETI   (0x1u << 7)
	(USBHS_HSTPIPISR[10]) Short Packet Interrupt More...
#define	USBHS_HSTPIPISR_TXOUTI   (0x1u << 1)
	(USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt More...
#define	USBHS_HSTPIPISR_TXSTPI   (0x1u << 2)
	(USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt More...
#define	USBHS_HSTPIPISR_UNDERFI   (0x1u << 2)
	(USBHS_HSTPIPISR[10]) Underflow Interrupt More...
#define	USBHS_SCR_RDERRIC   (0x1u << 4)
	(USBHS_SCR) Remote Device Connection Error Interrupt Clear More...
#define	USBHS_SCR_VBUSRQC   (0x1u << 9)
	(USBHS_SCR) VBus Request Clear More...
#define	USBHS_SFR_RDERRIS   (0x1u << 4)
	(USBHS_SFR) Remote Device Connection Error Interrupt Set More...
#define	USBHS_SFR_VBUSRQS   (0x1u << 9)
	(USBHS_SFR) VBus Request Set More...
#define	USBHS_SR_CLKUSABLE   (0x1u << 14)
	(USBHS_SR) UTMI Clock Usable More...
#define	USBHS_SR_RDERRI   (0x1u << 4)
	(USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) More...
#define	USBHS_SR_SPEED_FULL_SPEED   (0x0u << 12)
	(USBHS_SR) Full-Speed mode More...
#define	USBHS_SR_SPEED_HIGH_SPEED   (0x1u << 12)
	(USBHS_SR) High-Speed mode More...
#define	USBHS_SR_SPEED_LOW_SPEED   (0x2u << 12)
	(USBHS_SR) Low-Speed mode More...
#define	USBHS_SR_SPEED_Msk   (0x3u << USBHS_SR_SPEED_Pos)
	(USBHS_SR) Speed Status (Device mode only) More...
#define	USBHS_SR_SPEED_Pos   12
#define	USBHS_SR_VBUSRQ   (0x1u << 9)
	(USBHS_SR) VBus Request (Host mode only) More...
#define	USBHS_TSTA1_CounterA(value)   ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos)))
#define	USBHS_TSTA1_CounterA_Msk   (0x7fffu << USBHS_TSTA1_CounterA_Pos)
	(USBHS_TSTA1) Counter A More...
#define	USBHS_TSTA1_CounterA_Pos   0
#define	USBHS_TSTA1_CounterB(value)   ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos)))
#define	USBHS_TSTA1_CounterB_Msk   (0x3fu << USBHS_TSTA1_CounterB_Pos)
	(USBHS_TSTA1) Counter B More...
#define	USBHS_TSTA1_CounterB_Pos   16
#define	USBHS_TSTA1_LoadCntA   (0x1u << 15)
	(USBHS_TSTA1) Load CounterA More...
#define	USBHS_TSTA1_LoadCntB   (0x1u << 23)
	(USBHS_TSTA1) Load CounterB More...
#define	USBHS_TSTA1_LoadSOFCnt   (0x1u << 31)
	(USBHS_TSTA1) Load SOF Counter More...
#define	USBHS_TSTA1_SOFCntMa1(value)   ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos)))
#define	USBHS_TSTA1_SOFCntMa1_Msk   (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos)
	(USBHS_TSTA1) SOF Counter Max More...
#define	USBHS_TSTA1_SOFCntMa1_Pos   24
#define	USBHS_TSTA2_ByPassDpll   (0x1u << 5)
	(USBHS_TSTA2) Bypass DPLL More...
#define	USBHS_TSTA2_DisableGatedClock   (0x1u << 3)
	(USBHS_TSTA2) Disable Gated Clock More...
#define	USBHS_TSTA2_ForceHSRst_50ms   (0x1u << 7)
	(USBHS_TSTA2) Force HS Reset to 50 ms More...
#define	USBHS_TSTA2_ForceSuspendMTo1   (0x1u << 4)
	(USBHS_TSTA2) Force SuspendM to 1 More...
#define	USBHS_TSTA2_FullDetachEn   (0x1u << 0)
	(USBHS_TSTA2) Full Detach Enable More...
#define	USBHS_TSTA2_HostHSDisconnectDisable   (0x1u << 6)
	(USBHS_TSTA2) Host HS Disconnect Disable More...
#define	USBHS_TSTA2_HSSerialMode   (0x1u << 1)
	(USBHS_TSTA2) HS Serial Mode More...
#define	USBHS_TSTA2_LoopBackMode   (0x1u << 2)
	(USBHS_TSTA2) Loop-back Mode More...
#define	USBHS_TSTA2_RemovePUWhenTX   (0x1u << 9)
	(USBHS_TSTA2) Remove Pull-up When TX More...
#define	USBHS_VERSION_MFN_Msk   (0xfu << USBHS_VERSION_MFN_Pos)
	(USBHS_VERSION) Metal Fix Number More...
#define	USBHS_VERSION_MFN_Pos   16
#define	USBHS_VERSION_VERSION_Msk   (0xfffu << USBHS_VERSION_VERSION_Pos)
	(USBHS_VERSION) Version Number More...
#define	USBHS_VERSION_VERSION_Pos   0
#define	USBHSDEVDMA_NUMBER   7
	Usbhs hardware registers. More...
#define	USBHSHSTDMA_NUMBER   7

Detailed Description

SOFTWARE API DEFINITION FOR USB High-Speed Interface

Macro Definition Documentation

USBHS_CTRL_FRZCLK

#define USBHS_CTRL_FRZCLK   (0x1u << 14)

(USBHS_CTRL) Freeze USB Clock

Definition at line 881 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_CTRL_RDERRE

#define USBHS_CTRL_RDERRE   (0x1u << 4)

(USBHS_CTRL) Remote Device Connection Error Interrupt Enable

Definition at line 879 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_CTRL_UIMOD

#define USBHS_CTRL_UIMOD   (0x1u << 25)

(USBHS_CTRL) USBHS Mode

Definition at line 883 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_CTRL_UIMOD_DEVICE

#define USBHS_CTRL_UIMOD_DEVICE   (0x1u << 25)

(USBHS_CTRL) The module is in USB Device mode.

Definition at line 885 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_CTRL_UIMOD_HOST

#define USBHS_CTRL_UIMOD_HOST   (0x0u << 25)

(USBHS_CTRL) The module is in USB Host mode.

Definition at line 884 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_CTRL_USBE

#define USBHS_CTRL_USBE   (0x1u << 15)

(USBHS_CTRL) USBHS Enable

Definition at line 882 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_CTRL_VBUSHWC

#define USBHS_CTRL_VBUSHWC   (0x1u << 8)

(USBHS_CTRL) VBUS Hardware Control

Definition at line 880 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_ADDEN

#define USBHS_DEVCTRL_ADDEN   (0x1u << 7)

(USBHS_DEVCTRL) Address Enable

Definition at line 137 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_DETACH

#define USBHS_DEVCTRL_DETACH   (0x1u << 8)

(USBHS_DEVCTRL) Detach

Definition at line 138 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_LS

#define USBHS_DEVCTRL_LS   (0x1u << 12)

(USBHS_DEVCTRL) Low-Speed Mode Force

Definition at line 147 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_OPMODE2

#define USBHS_DEVCTRL_OPMODE2   (0x1u << 16)

(USBHS_DEVCTRL) Specific Operational mode

Definition at line 151 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_RMWKUP

#define USBHS_DEVCTRL_RMWKUP   (0x1u << 9)

(USBHS_DEVCTRL) Remote Wake-Up

Definition at line 139 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_SPDCONF

#define USBHS_DEVCTRL_SPDCONF

(

value

)

((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))

Definition at line 142 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_SPDCONF_FORCED_FS

#define USBHS_DEVCTRL_SPDCONF_FORCED_FS   (0x3u << 10)

(USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability.

Definition at line 146 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_SPDCONF_HIGH_SPEED

#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED   (0x2u << 10)

(USBHS_DEVCTRL) Forced high speed.

Definition at line 145 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_SPDCONF_LOW_POWER

#define USBHS_DEVCTRL_SPDCONF_LOW_POWER   (0x1u << 10)

(USBHS_DEVCTRL) For a better consumption, if high speed is not needed.

Definition at line 144 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_SPDCONF_Msk

#define USBHS_DEVCTRL_SPDCONF_Msk   (0x3u << USBHS_DEVCTRL_SPDCONF_Pos)

(USBHS_DEVCTRL) Mode Configuration

Definition at line 141 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_SPDCONF_NORMAL

#define USBHS_DEVCTRL_SPDCONF_NORMAL   (0x0u << 10)

(USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable.

Definition at line 143 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_SPDCONF_Pos

#define USBHS_DEVCTRL_SPDCONF_Pos   10

Definition at line 140 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_TSTJ

#define USBHS_DEVCTRL_TSTJ   (0x1u << 13)

(USBHS_DEVCTRL) Test mode J

Definition at line 148 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_TSTK

#define USBHS_DEVCTRL_TSTK   (0x1u << 14)

(USBHS_DEVCTRL) Test mode K

Definition at line 149 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_TSTPCKT

#define USBHS_DEVCTRL_TSTPCKT   (0x1u << 15)

(USBHS_DEVCTRL) Test packet mode

Definition at line 150 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_UADD

#define USBHS_DEVCTRL_UADD

(

value

)

((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))

Definition at line 136 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_UADD_Msk

#define USBHS_DEVCTRL_UADD_Msk   (0x7fu << USBHS_DEVCTRL_UADD_Pos)

(USBHS_DEVCTRL) USB Address

Definition at line 135 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVCTRL_UADD_Pos

#define USBHS_DEVCTRL_UADD_Pos   0

Definition at line 134 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMAADDRESS_BUFF_ADD

#define USBHS_DEVDMAADDRESS_BUFF_ADD

(

value

)

((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))

Definition at line 476 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMAADDRESS_BUFF_ADD_Msk

#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk   (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)

(USBHS_DEVDMAADDRESS) Buffer Address

Definition at line 475 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMAADDRESS_BUFF_ADD_Pos

#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos   0

Definition at line 474 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_BUFF_LENGTH

#define USBHS_DEVDMACONTROL_BUFF_LENGTH

(

value

)

((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))

Definition at line 488 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk

#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk   (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)

(USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only)

Definition at line 487 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos

#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos   16

Definition at line 486 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_BURST_LCK

#define USBHS_DEVDMACONTROL_BURST_LCK   (0x1u << 7)

(USBHS_DEVDMACONTROL) Burst Lock Enable

Definition at line 485 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_CHANN_ENB

#define USBHS_DEVDMACONTROL_CHANN_ENB   (0x1u << 0)

(USBHS_DEVDMACONTROL) Channel Enable Command

Definition at line 478 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_DESC_LD_IT

#define USBHS_DEVDMACONTROL_DESC_LD_IT   (0x1u << 6)

(USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable

Definition at line 484 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_END_B_EN

#define USBHS_DEVDMACONTROL_END_B_EN   (0x1u << 3)

(USBHS_DEVDMACONTROL) End of Buffer Enable Control

Definition at line 481 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_END_BUFFIT

#define USBHS_DEVDMACONTROL_END_BUFFIT   (0x1u << 5)

(USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable

Definition at line 483 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_END_TR_EN

#define USBHS_DEVDMACONTROL_END_TR_EN   (0x1u << 2)

(USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only)

Definition at line 480 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_END_TR_IT

#define USBHS_DEVDMACONTROL_END_TR_IT   (0x1u << 4)

(USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable

Definition at line 482 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMACONTROL_LDNXT_DSC

#define USBHS_DEVDMACONTROL_LDNXT_DSC   (0x1u << 1)

(USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command

Definition at line 479 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMANXTDSC_NXT_DSC_ADD

#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD

(

value

)

((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))

Definition at line 472 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk

#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk   (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)

(USBHS_DEVDMANXTDSC) Next Descriptor Address

Definition at line 471 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos

#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos   0

Definition at line 470 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMASTATUS_BUFF_COUNT

#define USBHS_DEVDMASTATUS_BUFF_COUNT

(

value

)

((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))

Definition at line 497 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMASTATUS_BUFF_COUNT_Msk

#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk   (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)

(USBHS_DEVDMASTATUS) Buffer Byte Count

Definition at line 496 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMASTATUS_BUFF_COUNT_Pos

#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos   16

Definition at line 495 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMASTATUS_CHANN_ACT

#define USBHS_DEVDMASTATUS_CHANN_ACT   (0x1u << 1)

(USBHS_DEVDMASTATUS) Channel Active Status

Definition at line 491 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMASTATUS_CHANN_ENB

#define USBHS_DEVDMASTATUS_CHANN_ENB   (0x1u << 0)

(USBHS_DEVDMASTATUS) Channel Enable Status

Definition at line 490 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMASTATUS_DESC_LDST

#define USBHS_DEVDMASTATUS_DESC_LDST   (0x1u << 6)

(USBHS_DEVDMASTATUS) Descriptor Loaded Status

Definition at line 494 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMASTATUS_END_BF_ST

#define USBHS_DEVDMASTATUS_END_BF_ST   (0x1u << 5)

(USBHS_DEVDMASTATUS) End of Channel Buffer Status

Definition at line 493 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVDMASTATUS_END_TR_ST

#define USBHS_DEVDMASTATUS_END_TR_ST   (0x1u << 4)

(USBHS_DEVDMASTATUS) End of Channel Transfer Status

Definition at line 492 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN0

#define USBHS_DEVEPT_EPEN0   (0x1u << 0)

(USBHS_DEVEPT) Endpoint 0 Enable

Definition at line 276 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN1

#define USBHS_DEVEPT_EPEN1   (0x1u << 1)

(USBHS_DEVEPT) Endpoint 1 Enable

Definition at line 277 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN2

#define USBHS_DEVEPT_EPEN2   (0x1u << 2)

(USBHS_DEVEPT) Endpoint 2 Enable

Definition at line 278 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN3

#define USBHS_DEVEPT_EPEN3   (0x1u << 3)

(USBHS_DEVEPT) Endpoint 3 Enable

Definition at line 279 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN4

#define USBHS_DEVEPT_EPEN4   (0x1u << 4)

(USBHS_DEVEPT) Endpoint 4 Enable

Definition at line 280 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN5

#define USBHS_DEVEPT_EPEN5   (0x1u << 5)

(USBHS_DEVEPT) Endpoint 5 Enable

Definition at line 281 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN6

#define USBHS_DEVEPT_EPEN6   (0x1u << 6)

(USBHS_DEVEPT) Endpoint 6 Enable

Definition at line 282 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN7

#define USBHS_DEVEPT_EPEN7   (0x1u << 7)

(USBHS_DEVEPT) Endpoint 7 Enable

Definition at line 283 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN8

#define USBHS_DEVEPT_EPEN8   (0x1u << 8)

(USBHS_DEVEPT) Endpoint 8 Enable

Definition at line 284 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPEN9

#define USBHS_DEVEPT_EPEN9   (0x1u << 9)

(USBHS_DEVEPT) Endpoint 9 Enable

Definition at line 285 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST0

#define USBHS_DEVEPT_EPRST0   (0x1u << 16)

(USBHS_DEVEPT) Endpoint 0 Reset

Definition at line 286 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST1

#define USBHS_DEVEPT_EPRST1   (0x1u << 17)

(USBHS_DEVEPT) Endpoint 1 Reset

Definition at line 287 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST2

#define USBHS_DEVEPT_EPRST2   (0x1u << 18)

(USBHS_DEVEPT) Endpoint 2 Reset

Definition at line 288 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST3

#define USBHS_DEVEPT_EPRST3   (0x1u << 19)

(USBHS_DEVEPT) Endpoint 3 Reset

Definition at line 289 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST4

#define USBHS_DEVEPT_EPRST4   (0x1u << 20)

(USBHS_DEVEPT) Endpoint 4 Reset

Definition at line 290 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST5

#define USBHS_DEVEPT_EPRST5   (0x1u << 21)

(USBHS_DEVEPT) Endpoint 5 Reset

Definition at line 291 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST6

#define USBHS_DEVEPT_EPRST6   (0x1u << 22)

(USBHS_DEVEPT) Endpoint 6 Reset

Definition at line 292 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST7

#define USBHS_DEVEPT_EPRST7   (0x1u << 23)

(USBHS_DEVEPT) Endpoint 7 Reset

Definition at line 293 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST8

#define USBHS_DEVEPT_EPRST8   (0x1u << 24)

(USBHS_DEVEPT) Endpoint 8 Reset

Definition at line 294 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPT_EPRST9

#define USBHS_DEVEPT_EPRST9   (0x1u << 25)

(USBHS_DEVEPT) Endpoint 9 Reset

Definition at line 295 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_ALLOC

#define USBHS_DEVEPTCFG_ALLOC   (0x1u << 1)

(USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate

Definition at line 303 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_AUTOSW

#define USBHS_DEVEPTCFG_AUTOSW   (0x1u << 9)

(USBHS_DEVEPTCFG[10]) Automatic Switch

Definition at line 324 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPBK

#define USBHS_DEVEPTCFG_EPBK

(

value

)

((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))

Definition at line 306 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPBK_1_BANK

#define USBHS_DEVEPTCFG_EPBK_1_BANK   (0x0u << 2)

(USBHS_DEVEPTCFG[10]) Single-bank endpoint

Definition at line 307 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPBK_2_BANK

#define USBHS_DEVEPTCFG_EPBK_2_BANK   (0x1u << 2)

(USBHS_DEVEPTCFG[10]) Double-bank endpoint

Definition at line 308 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPBK_3_BANK

#define USBHS_DEVEPTCFG_EPBK_3_BANK   (0x2u << 2)

(USBHS_DEVEPTCFG[10]) Triple-bank endpoint

Definition at line 309 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPBK_Msk

#define USBHS_DEVEPTCFG_EPBK_Msk   (0x3u << USBHS_DEVEPTCFG_EPBK_Pos)

(USBHS_DEVEPTCFG[10]) Endpoint Banks

Definition at line 305 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPBK_Pos

#define USBHS_DEVEPTCFG_EPBK_Pos   2

Definition at line 304 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPDIR

#define USBHS_DEVEPTCFG_EPDIR   (0x1u << 8)

(USBHS_DEVEPTCFG[10]) Endpoint Direction

Definition at line 321 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPDIR_IN

#define USBHS_DEVEPTCFG_EPDIR_IN   (0x1u << 8)

(USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints).

Definition at line 323 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPDIR_OUT

#define USBHS_DEVEPTCFG_EPDIR_OUT   (0x0u << 8)

(USBHS_DEVEPTCFG[10]) The endpoint direction is OUT.

Definition at line 322 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE

#define USBHS_DEVEPTCFG_EPSIZE

(

value

)

((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))

Definition at line 312 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_1024_BYTE

#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE   (0x7u << 4)

(USBHS_DEVEPTCFG[10]) 1024 bytes

Definition at line 320 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_128_BYTE

#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE   (0x4u << 4)

(USBHS_DEVEPTCFG[10]) 128 bytes

Definition at line 317 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_16_BYTE

#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE   (0x1u << 4)

(USBHS_DEVEPTCFG[10]) 16 bytes

Definition at line 314 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_256_BYTE

#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE   (0x5u << 4)

(USBHS_DEVEPTCFG[10]) 256 bytes

Definition at line 318 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_32_BYTE

#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE   (0x2u << 4)

(USBHS_DEVEPTCFG[10]) 32 bytes

Definition at line 315 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_512_BYTE

#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE   (0x6u << 4)

(USBHS_DEVEPTCFG[10]) 512 bytes

Definition at line 319 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_64_BYTE

#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE   (0x3u << 4)

(USBHS_DEVEPTCFG[10]) 64 bytes

Definition at line 316 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_8_BYTE

#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE   (0x0u << 4)

(USBHS_DEVEPTCFG[10]) 8 bytes

Definition at line 313 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_Msk

#define USBHS_DEVEPTCFG_EPSIZE_Msk   (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos)

(USBHS_DEVEPTCFG[10]) Endpoint Size

Definition at line 311 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPSIZE_Pos

#define USBHS_DEVEPTCFG_EPSIZE_Pos   4

Definition at line 310 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPTYPE

#define USBHS_DEVEPTCFG_EPTYPE

(

value

)

((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))

Definition at line 327 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPTYPE_BLK

#define USBHS_DEVEPTCFG_EPTYPE_BLK   (0x2u << 11)

(USBHS_DEVEPTCFG[10]) Bulk

Definition at line 330 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPTYPE_CTRL

#define USBHS_DEVEPTCFG_EPTYPE_CTRL   (0x0u << 11)

(USBHS_DEVEPTCFG[10]) Control

Definition at line 328 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPTYPE_INTRPT

#define USBHS_DEVEPTCFG_EPTYPE_INTRPT   (0x3u << 11)

(USBHS_DEVEPTCFG[10]) Interrupt

Definition at line 331 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPTYPE_ISO

#define USBHS_DEVEPTCFG_EPTYPE_ISO   (0x1u << 11)

(USBHS_DEVEPTCFG[10]) Isochronous

Definition at line 329 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPTYPE_Msk

#define USBHS_DEVEPTCFG_EPTYPE_Msk   (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos)

(USBHS_DEVEPTCFG[10]) Endpoint Type

Definition at line 326 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_EPTYPE_Pos

#define USBHS_DEVEPTCFG_EPTYPE_Pos   11

Definition at line 325 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_NBTRANS

#define USBHS_DEVEPTCFG_NBTRANS

(

value

)

((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))

Definition at line 334 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_NBTRANS_0_TRANS

#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS   (0x0u << 13)

(USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability.

Definition at line 335 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_NBTRANS_1_TRANS

#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS   (0x1u << 13)

(USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe.

Definition at line 336 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_NBTRANS_2_TRANS

#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS   (0x2u << 13)

(USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank.

Definition at line 337 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_NBTRANS_3_TRANS

#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS   (0x3u << 13)

(USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank.

Definition at line 338 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_NBTRANS_Msk

#define USBHS_DEVEPTCFG_NBTRANS_Msk   (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos)

(USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint

Definition at line 333 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTCFG_NBTRANS_Pos

#define USBHS_DEVEPTCFG_NBTRANS_Pos   13

Definition at line 332 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_CRCERRIC

#define USBHS_DEVEPTICR_CRCERRIC   (0x1u << 6)

(USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear

Definition at line 387 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_HBISOFLUSHIC

#define USBHS_DEVEPTICR_HBISOFLUSHIC   (0x1u << 4)

(USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear

Definition at line 386 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_HBISOINERRIC

#define USBHS_DEVEPTICR_HBISOINERRIC   (0x1u << 3)

(USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear

Definition at line 385 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_NAKINIC

#define USBHS_DEVEPTICR_NAKINIC   (0x1u << 4)

(USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear

Definition at line 380 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_NAKOUTIC

#define USBHS_DEVEPTICR_NAKOUTIC   (0x1u << 3)

(USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear

Definition at line 379 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_OVERFIC

#define USBHS_DEVEPTICR_OVERFIC   (0x1u << 5)

(USBHS_DEVEPTICR[10]) Overflow Interrupt Clear

Definition at line 381 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_RXOUTIC

#define USBHS_DEVEPTICR_RXOUTIC   (0x1u << 1)

(USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear

Definition at line 377 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_RXSTPIC

#define USBHS_DEVEPTICR_RXSTPIC   (0x1u << 2)

(USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear

Definition at line 378 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_SHORTPACKETC

#define USBHS_DEVEPTICR_SHORTPACKETC   (0x1u << 7)

(USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear

Definition at line 383 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_STALLEDIC

#define USBHS_DEVEPTICR_STALLEDIC   (0x1u << 6)

(USBHS_DEVEPTICR[10]) STALLed Interrupt Clear

Definition at line 382 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_TXINIC

#define USBHS_DEVEPTICR_TXINIC   (0x1u << 0)

(USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear

Definition at line 376 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTICR_UNDERFIC

#define USBHS_DEVEPTICR_UNDERFIC   (0x1u << 2)

(USBHS_DEVEPTICR[10]) Underflow Interrupt Clear

Definition at line 384 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_CRCERREC

#define USBHS_DEVEPTIDR_CRCERREC   (0x1u << 6)

(USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear

Definition at line 465 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_DATAXEC

#define USBHS_DEVEPTIDR_DATAXEC   (0x1u << 9)

(USBHS_DEVEPTIDR[10]) DataX Interrupt Clear

Definition at line 467 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_EPDISHDMAC

#define USBHS_DEVEPTIDR_EPDISHDMAC   (0x1u << 16)

(USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear

Definition at line 459 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_ERRORTRANSEC

#define USBHS_DEVEPTIDR_ERRORTRANSEC   (0x1u << 10)

(USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear

Definition at line 468 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_FIFOCONC

#define USBHS_DEVEPTIDR_FIFOCONC   (0x1u << 14)

(USBHS_DEVEPTIDR[10]) FIFO Control Clear

Definition at line 458 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_HBISOFLUSHEC

#define USBHS_DEVEPTIDR_HBISOFLUSHEC   (0x1u << 4)

(USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear

Definition at line 464 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_HBISOINERREC

#define USBHS_DEVEPTIDR_HBISOINERREC   (0x1u << 3)

(USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear

Definition at line 463 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_MDATEC

#define USBHS_DEVEPTIDR_MDATEC   (0x1u << 8)

(USBHS_DEVEPTIDR[10]) MData Interrupt Clear

Definition at line 466 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_NAKINEC

#define USBHS_DEVEPTIDR_NAKINEC   (0x1u << 4)

(USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear

Definition at line 453 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_NAKOUTEC

#define USBHS_DEVEPTIDR_NAKOUTEC   (0x1u << 3)

(USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear

Definition at line 452 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_NBUSYBKEC

#define USBHS_DEVEPTIDR_NBUSYBKEC   (0x1u << 12)

(USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear

Definition at line 457 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_NYETDISC

#define USBHS_DEVEPTIDR_NYETDISC   (0x1u << 17)

(USBHS_DEVEPTIDR[10]) NYET Token Disable Clear

Definition at line 460 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_OVERFEC

#define USBHS_DEVEPTIDR_OVERFEC   (0x1u << 5)

(USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear

Definition at line 454 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_RXOUTEC

#define USBHS_DEVEPTIDR_RXOUTEC   (0x1u << 1)

(USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear

Definition at line 450 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_RXSTPEC

#define USBHS_DEVEPTIDR_RXSTPEC   (0x1u << 2)

(USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear

Definition at line 451 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_SHORTPACKETEC

#define USBHS_DEVEPTIDR_SHORTPACKETEC   (0x1u << 7)

(USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear

Definition at line 456 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_STALLEDEC

#define USBHS_DEVEPTIDR_STALLEDEC   (0x1u << 6)

(USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear

Definition at line 455 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_STALLRQC

#define USBHS_DEVEPTIDR_STALLRQC   (0x1u << 19)

(USBHS_DEVEPTIDR[10]) STALL Request Clear

Definition at line 461 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_TXINEC

#define USBHS_DEVEPTIDR_TXINEC   (0x1u << 0)

(USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear

Definition at line 449 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIDR_UNDERFEC

#define USBHS_DEVEPTIDR_UNDERFEC   (0x1u << 2)

(USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear

Definition at line 462 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_CRCERRES

#define USBHS_DEVEPTIER_CRCERRES   (0x1u << 6)

(USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable

Definition at line 444 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_DATAXES

#define USBHS_DEVEPTIER_DATAXES   (0x1u << 9)

(USBHS_DEVEPTIER[10]) DataX Interrupt Enable

Definition at line 446 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_EPDISHDMAS

#define USBHS_DEVEPTIER_EPDISHDMAS   (0x1u << 16)

(USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable

Definition at line 437 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_ERRORTRANSES

#define USBHS_DEVEPTIER_ERRORTRANSES   (0x1u << 10)

(USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable

Definition at line 447 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_FIFOCONS

#define USBHS_DEVEPTIER_FIFOCONS   (0x1u << 14)

(USBHS_DEVEPTIER[10]) FIFO Control

Definition at line 436 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_HBISOFLUSHES

#define USBHS_DEVEPTIER_HBISOFLUSHES   (0x1u << 4)

(USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable

Definition at line 443 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_HBISOINERRES

#define USBHS_DEVEPTIER_HBISOINERRES   (0x1u << 3)

(USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable

Definition at line 442 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_KILLBKS

#define USBHS_DEVEPTIER_KILLBKS   (0x1u << 13)

(USBHS_DEVEPTIER[10]) Kill IN Bank

Definition at line 435 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_MDATAES

#define USBHS_DEVEPTIER_MDATAES   (0x1u << 8)

(USBHS_DEVEPTIER[10]) MData Interrupt Enable

Definition at line 445 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_NAKINES

#define USBHS_DEVEPTIER_NAKINES   (0x1u << 4)

(USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable

Definition at line 430 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_NAKOUTES

#define USBHS_DEVEPTIER_NAKOUTES   (0x1u << 3)

(USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable

Definition at line 429 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_NBUSYBKES

#define USBHS_DEVEPTIER_NBUSYBKES   (0x1u << 12)

(USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable

Definition at line 434 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_NYETDISS

#define USBHS_DEVEPTIER_NYETDISS   (0x1u << 17)

(USBHS_DEVEPTIER[10]) NYET Token Disable Enable

Definition at line 438 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_OVERFES

#define USBHS_DEVEPTIER_OVERFES   (0x1u << 5)

(USBHS_DEVEPTIER[10]) Overflow Interrupt Enable

Definition at line 431 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_RSTDTS

#define USBHS_DEVEPTIER_RSTDTS   (0x1u << 18)

(USBHS_DEVEPTIER[10]) Reset Data Toggle Enable

Definition at line 439 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_RXOUTES

#define USBHS_DEVEPTIER_RXOUTES   (0x1u << 1)

(USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable

Definition at line 427 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_RXSTPES

#define USBHS_DEVEPTIER_RXSTPES   (0x1u << 2)

(USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable

Definition at line 428 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_SHORTPACKETES

#define USBHS_DEVEPTIER_SHORTPACKETES   (0x1u << 7)

(USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable

Definition at line 433 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_STALLEDES

#define USBHS_DEVEPTIER_STALLEDES   (0x1u << 6)

(USBHS_DEVEPTIER[10]) STALLed Interrupt Enable

Definition at line 432 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_STALLRQS

#define USBHS_DEVEPTIER_STALLRQS   (0x1u << 19)

(USBHS_DEVEPTIER[10]) STALL Request Enable

Definition at line 440 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_TXINES

#define USBHS_DEVEPTIER_TXINES   (0x1u << 0)

(USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable

Definition at line 426 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIER_UNDERFES

#define USBHS_DEVEPTIER_UNDERFES   (0x1u << 2)

(USBHS_DEVEPTIER[10]) Underflow Interrupt Enable

Definition at line 441 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_CRCERRIS

#define USBHS_DEVEPTIFR_CRCERRIS   (0x1u << 6)

(USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set

Definition at line 401 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_HBISOFLUSHIS

#define USBHS_DEVEPTIFR_HBISOFLUSHIS   (0x1u << 4)

(USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set

Definition at line 400 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_HBISOINERRIS

#define USBHS_DEVEPTIFR_HBISOINERRIS   (0x1u << 3)

(USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set

Definition at line 399 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_NAKINIS

#define USBHS_DEVEPTIFR_NAKINIS   (0x1u << 4)

(USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set

Definition at line 393 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_NAKOUTIS

#define USBHS_DEVEPTIFR_NAKOUTIS   (0x1u << 3)

(USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set

Definition at line 392 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_NBUSYBKS

#define USBHS_DEVEPTIFR_NBUSYBKS   (0x1u << 12)

(USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set

Definition at line 397 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_OVERFIS

#define USBHS_DEVEPTIFR_OVERFIS   (0x1u << 5)

(USBHS_DEVEPTIFR[10]) Overflow Interrupt Set

Definition at line 394 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_RXOUTIS

#define USBHS_DEVEPTIFR_RXOUTIS   (0x1u << 1)

(USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set

Definition at line 390 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_RXSTPIS

#define USBHS_DEVEPTIFR_RXSTPIS   (0x1u << 2)

(USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set

Definition at line 391 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_SHORTPACKETS

#define USBHS_DEVEPTIFR_SHORTPACKETS   (0x1u << 7)

(USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set

Definition at line 396 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_STALLEDIS

#define USBHS_DEVEPTIFR_STALLEDIS   (0x1u << 6)

(USBHS_DEVEPTIFR[10]) STALLed Interrupt Set

Definition at line 395 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_TXINIS

#define USBHS_DEVEPTIFR_TXINIS   (0x1u << 0)

(USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set

Definition at line 389 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIFR_UNDERFIS

#define USBHS_DEVEPTIFR_UNDERFIS   (0x1u << 2)

(USBHS_DEVEPTIFR[10]) Underflow Interrupt Set

Definition at line 398 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_CRCERRE

#define USBHS_DEVEPTIMR_CRCERRE   (0x1u << 6)

(USBHS_DEVEPTIMR[10]) CRC Error Interrupt

Definition at line 421 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_DATAXE

#define USBHS_DEVEPTIMR_DATAXE   (0x1u << 9)

(USBHS_DEVEPTIMR[10]) DataX Interrupt

Definition at line 423 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_EPDISHDMA

#define USBHS_DEVEPTIMR_EPDISHDMA   (0x1u << 16)

(USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request

Definition at line 414 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_ERRORTRANSE

#define USBHS_DEVEPTIMR_ERRORTRANSE   (0x1u << 10)

(USBHS_DEVEPTIMR[10]) Transaction Error Interrupt

Definition at line 424 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_FIFOCON

#define USBHS_DEVEPTIMR_FIFOCON   (0x1u << 14)

(USBHS_DEVEPTIMR[10]) FIFO Control

Definition at line 413 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_HBISOFLUSHE

#define USBHS_DEVEPTIMR_HBISOFLUSHE   (0x1u << 4)

(USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt

Definition at line 420 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_HBISOINERRE

#define USBHS_DEVEPTIMR_HBISOINERRE   (0x1u << 3)

(USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt

Definition at line 419 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_KILLBK

#define USBHS_DEVEPTIMR_KILLBK   (0x1u << 13)

(USBHS_DEVEPTIMR[10]) Kill IN Bank

Definition at line 412 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_MDATAE

#define USBHS_DEVEPTIMR_MDATAE   (0x1u << 8)

(USBHS_DEVEPTIMR[10]) MData Interrupt

Definition at line 422 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_NAKINE

#define USBHS_DEVEPTIMR_NAKINE   (0x1u << 4)

(USBHS_DEVEPTIMR[10]) NAKed IN Interrupt

Definition at line 407 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_NAKOUTE

#define USBHS_DEVEPTIMR_NAKOUTE   (0x1u << 3)

(USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt

Definition at line 406 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_NBUSYBKE

#define USBHS_DEVEPTIMR_NBUSYBKE   (0x1u << 12)

(USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt

Definition at line 411 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_NYETDIS

#define USBHS_DEVEPTIMR_NYETDIS   (0x1u << 17)

(USBHS_DEVEPTIMR[10]) NYET Token Disable

Definition at line 415 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_OVERFE

#define USBHS_DEVEPTIMR_OVERFE   (0x1u << 5)

(USBHS_DEVEPTIMR[10]) Overflow Interrupt

Definition at line 408 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_RSTDT

#define USBHS_DEVEPTIMR_RSTDT   (0x1u << 18)

(USBHS_DEVEPTIMR[10]) Reset Data Toggle

Definition at line 416 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_RXOUTE

#define USBHS_DEVEPTIMR_RXOUTE   (0x1u << 1)

(USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt

Definition at line 404 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_RXSTPE

#define USBHS_DEVEPTIMR_RXSTPE   (0x1u << 2)

(USBHS_DEVEPTIMR[10]) Received SETUP Interrupt

Definition at line 405 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_SHORTPACKETE

#define USBHS_DEVEPTIMR_SHORTPACKETE   (0x1u << 7)

(USBHS_DEVEPTIMR[10]) Short Packet Interrupt

Definition at line 410 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_STALLEDE

#define USBHS_DEVEPTIMR_STALLEDE   (0x1u << 6)

(USBHS_DEVEPTIMR[10]) STALLed Interrupt

Definition at line 409 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_STALLRQ

#define USBHS_DEVEPTIMR_STALLRQ   (0x1u << 19)

(USBHS_DEVEPTIMR[10]) STALL Request

Definition at line 417 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_TXINE

#define USBHS_DEVEPTIMR_TXINE   (0x1u << 0)

(USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt

Definition at line 403 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTIMR_UNDERFE

#define USBHS_DEVEPTIMR_UNDERFE   (0x1u << 2)

(USBHS_DEVEPTIMR[10]) Underflow Interrupt

Definition at line 418 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_BYCT_Msk

#define USBHS_DEVEPTISR_BYCT_Msk   (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos)

(USBHS_DEVEPTISR[10]) Byte Count

Definition at line 369 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_BYCT_Pos

#define USBHS_DEVEPTISR_BYCT_Pos   20

Definition at line 368 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_CFGOK

#define USBHS_DEVEPTISR_CFGOK   (0x1u << 18)

(USBHS_DEVEPTISR[10]) Configuration OK Status

Definition at line 367 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_CRCERRI

#define USBHS_DEVEPTISR_CRCERRI   (0x1u << 6)

(USBHS_DEVEPTISR[10]) CRC Error Interrupt

Definition at line 373 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_CTRLDIR

#define USBHS_DEVEPTISR_CTRLDIR   (0x1u << 17)

(USBHS_DEVEPTISR[10]) Control Direction

Definition at line 366 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_CURRBK_BANK0

#define USBHS_DEVEPTISR_CURRBK_BANK0   (0x0u << 14)

(USBHS_DEVEPTISR[10]) Current bank is bank0

Definition at line 362 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_CURRBK_BANK1

#define USBHS_DEVEPTISR_CURRBK_BANK1   (0x1u << 14)

(USBHS_DEVEPTISR[10]) Current bank is bank1

Definition at line 363 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_CURRBK_BANK2

#define USBHS_DEVEPTISR_CURRBK_BANK2   (0x2u << 14)

(USBHS_DEVEPTISR[10]) Current bank is bank2

Definition at line 364 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_CURRBK_Msk

#define USBHS_DEVEPTISR_CURRBK_Msk   (0x3u << USBHS_DEVEPTISR_CURRBK_Pos)

(USBHS_DEVEPTISR[10]) Current Bank

Definition at line 361 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_CURRBK_Pos

#define USBHS_DEVEPTISR_CURRBK_Pos   14

Definition at line 360 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_DTSEQ_DATA0

#define USBHS_DEVEPTISR_DTSEQ_DATA0   (0x0u << 8)

(USBHS_DEVEPTISR[10]) Data0 toggle sequence

Definition at line 350 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_DTSEQ_DATA1

#define USBHS_DEVEPTISR_DTSEQ_DATA1   (0x1u << 8)

(USBHS_DEVEPTISR[10]) Data1 toggle sequence

Definition at line 351 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_DTSEQ_DATA2

#define USBHS_DEVEPTISR_DTSEQ_DATA2   (0x2u << 8)

(USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint

Definition at line 352 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_DTSEQ_MDATA

#define USBHS_DEVEPTISR_DTSEQ_MDATA   (0x3u << 8)

(USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint

Definition at line 353 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_DTSEQ_Msk

#define USBHS_DEVEPTISR_DTSEQ_Msk   (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos)

(USBHS_DEVEPTISR[10]) Data Toggle Sequence

Definition at line 349 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_DTSEQ_Pos

#define USBHS_DEVEPTISR_DTSEQ_Pos   8

Definition at line 348 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_ERRORTRANS

#define USBHS_DEVEPTISR_ERRORTRANS   (0x1u << 10)

(USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt

Definition at line 374 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_HBISOFLUSHI

#define USBHS_DEVEPTISR_HBISOFLUSHI   (0x1u << 4)

(USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt

Definition at line 372 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_HBISOINERRI

#define USBHS_DEVEPTISR_HBISOINERRI   (0x1u << 3)

(USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt

Definition at line 371 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_NAKINI

#define USBHS_DEVEPTISR_NAKINI   (0x1u << 4)

(USBHS_DEVEPTISR[10]) NAKed IN Interrupt

Definition at line 344 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_NAKOUTI

#define USBHS_DEVEPTISR_NAKOUTI   (0x1u << 3)

(USBHS_DEVEPTISR[10]) NAKed OUT Interrupt

Definition at line 343 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_NBUSYBK_0_BUSY

#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY   (0x0u << 12)

(USBHS_DEVEPTISR[10]) 0 busy bank (all banks free)

Definition at line 356 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_NBUSYBK_1_BUSY

#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY   (0x1u << 12)

(USBHS_DEVEPTISR[10]) 1 busy bank

Definition at line 357 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_NBUSYBK_2_BUSY

#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY   (0x2u << 12)

(USBHS_DEVEPTISR[10]) 2 busy banks

Definition at line 358 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_NBUSYBK_3_BUSY

#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY   (0x3u << 12)

(USBHS_DEVEPTISR[10]) 3 busy banks

Definition at line 359 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_NBUSYBK_Msk

#define USBHS_DEVEPTISR_NBUSYBK_Msk   (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos)

(USBHS_DEVEPTISR[10]) Number of Busy Banks

Definition at line 355 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_NBUSYBK_Pos

#define USBHS_DEVEPTISR_NBUSYBK_Pos   12

Definition at line 354 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_OVERFI

#define USBHS_DEVEPTISR_OVERFI   (0x1u << 5)

(USBHS_DEVEPTISR[10]) Overflow Interrupt

Definition at line 345 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_RWALL

#define USBHS_DEVEPTISR_RWALL   (0x1u << 16)

(USBHS_DEVEPTISR[10]) Read/Write Allowed

Definition at line 365 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_RXOUTI

#define USBHS_DEVEPTISR_RXOUTI   (0x1u << 1)

(USBHS_DEVEPTISR[10]) Received OUT Data Interrupt

Definition at line 341 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_RXSTPI

#define USBHS_DEVEPTISR_RXSTPI   (0x1u << 2)

(USBHS_DEVEPTISR[10]) Received SETUP Interrupt

Definition at line 342 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_SHORTPACKET

#define USBHS_DEVEPTISR_SHORTPACKET   (0x1u << 7)

(USBHS_DEVEPTISR[10]) Short Packet Interrupt

Definition at line 347 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_STALLEDI

#define USBHS_DEVEPTISR_STALLEDI   (0x1u << 6)

(USBHS_DEVEPTISR[10]) STALLed Interrupt

Definition at line 346 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_TXINI

#define USBHS_DEVEPTISR_TXINI   (0x1u << 0)

(USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt

Definition at line 340 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVEPTISR_UNDERFI

#define USBHS_DEVEPTISR_UNDERFI   (0x1u << 2)

(USBHS_DEVEPTISR[10]) Underflow Interrupt

Definition at line 370 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVFNUM_FNCERR

#define USBHS_DEVFNUM_FNCERR   (0x1u << 15)

(USBHS_DEVFNUM) Frame Number CRC Error

Definition at line 301 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVFNUM_FNUM_Msk

#define USBHS_DEVFNUM_FNUM_Msk   (0x7ffu << USBHS_DEVFNUM_FNUM_Pos)

(USBHS_DEVFNUM) Frame Number

Definition at line 300 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVFNUM_FNUM_Pos

#define USBHS_DEVFNUM_FNUM_Pos   3

Definition at line 299 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVFNUM_MFNUM_Msk

#define USBHS_DEVFNUM_MFNUM_Msk   (0x7u << USBHS_DEVFNUM_MFNUM_Pos)

(USBHS_DEVFNUM) Micro Frame Number

Definition at line 298 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVFNUM_MFNUM_Pos

#define USBHS_DEVFNUM_MFNUM_Pos   0

Definition at line 297 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVICR_EORSMC

#define USBHS_DEVICR_EORSMC   (0x1u << 5)

(USBHS_DEVICR) End of Resume Interrupt Clear

Definition at line 183 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVICR_EORSTC

#define USBHS_DEVICR_EORSTC   (0x1u << 3)

(USBHS_DEVICR) End of Reset Interrupt Clear

Definition at line 181 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVICR_MSOFC

#define USBHS_DEVICR_MSOFC   (0x1u << 1)

(USBHS_DEVICR) Micro Start of Frame Interrupt Clear

Definition at line 179 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVICR_SOFC

#define USBHS_DEVICR_SOFC   (0x1u << 2)

(USBHS_DEVICR) Start of Frame Interrupt Clear

Definition at line 180 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVICR_SUSPC

#define USBHS_DEVICR_SUSPC   (0x1u << 0)

(USBHS_DEVICR) Suspend Interrupt Clear

Definition at line 178 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVICR_UPRSMC

#define USBHS_DEVICR_UPRSMC   (0x1u << 6)

(USBHS_DEVICR) Upstream Resume Interrupt Clear

Definition at line 184 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVICR_WAKEUPC

#define USBHS_DEVICR_WAKEUPC   (0x1u << 4)

(USBHS_DEVICR) Wake-Up Interrupt Clear

Definition at line 182 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_DMA_1

#define USBHS_DEVIDR_DMA_1   (0x1u << 25)

(USBHS_DEVIDR) DMA Channel 1 Interrupt Disable

Definition at line 243 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_DMA_2

#define USBHS_DEVIDR_DMA_2   (0x1u << 26)

(USBHS_DEVIDR) DMA Channel 2 Interrupt Disable

Definition at line 244 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_DMA_3

#define USBHS_DEVIDR_DMA_3   (0x1u << 27)

(USBHS_DEVIDR) DMA Channel 3 Interrupt Disable

Definition at line 245 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_DMA_4

#define USBHS_DEVIDR_DMA_4   (0x1u << 28)

(USBHS_DEVIDR) DMA Channel 4 Interrupt Disable

Definition at line 246 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_DMA_5

#define USBHS_DEVIDR_DMA_5   (0x1u << 29)

(USBHS_DEVIDR) DMA Channel 5 Interrupt Disable

Definition at line 247 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_DMA_6

#define USBHS_DEVIDR_DMA_6   (0x1u << 30)

(USBHS_DEVIDR) DMA Channel 6 Interrupt Disable

Definition at line 248 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_DMA_7

#define USBHS_DEVIDR_DMA_7   (0x1u << 31)

(USBHS_DEVIDR) DMA Channel 7 Interrupt Disable

Definition at line 249 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_EORSMEC

#define USBHS_DEVIDR_EORSMEC   (0x1u << 5)

(USBHS_DEVIDR) End of Resume Interrupt Disable

Definition at line 231 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_EORSTEC

#define USBHS_DEVIDR_EORSTEC   (0x1u << 3)

(USBHS_DEVIDR) End of Reset Interrupt Disable

Definition at line 229 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_MSOFEC

#define USBHS_DEVIDR_MSOFEC   (0x1u << 1)

(USBHS_DEVIDR) Micro Start of Frame Interrupt Disable

Definition at line 227 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_0

#define USBHS_DEVIDR_PEP_0   (0x1u << 12)

(USBHS_DEVIDR) Endpoint 0 Interrupt Disable

Definition at line 233 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_1

#define USBHS_DEVIDR_PEP_1   (0x1u << 13)

(USBHS_DEVIDR) Endpoint 1 Interrupt Disable

Definition at line 234 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_2

#define USBHS_DEVIDR_PEP_2   (0x1u << 14)

(USBHS_DEVIDR) Endpoint 2 Interrupt Disable

Definition at line 235 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_3

#define USBHS_DEVIDR_PEP_3   (0x1u << 15)

(USBHS_DEVIDR) Endpoint 3 Interrupt Disable

Definition at line 236 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_4

#define USBHS_DEVIDR_PEP_4   (0x1u << 16)

(USBHS_DEVIDR) Endpoint 4 Interrupt Disable

Definition at line 237 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_5

#define USBHS_DEVIDR_PEP_5   (0x1u << 17)

(USBHS_DEVIDR) Endpoint 5 Interrupt Disable

Definition at line 238 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_6

#define USBHS_DEVIDR_PEP_6   (0x1u << 18)

(USBHS_DEVIDR) Endpoint 6 Interrupt Disable

Definition at line 239 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_7

#define USBHS_DEVIDR_PEP_7   (0x1u << 19)

(USBHS_DEVIDR) Endpoint 7 Interrupt Disable

Definition at line 240 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_8

#define USBHS_DEVIDR_PEP_8   (0x1u << 20)

(USBHS_DEVIDR) Endpoint 8 Interrupt Disable

Definition at line 241 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_PEP_9

#define USBHS_DEVIDR_PEP_9   (0x1u << 21)

(USBHS_DEVIDR) Endpoint 9 Interrupt Disable

Definition at line 242 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_SOFEC

#define USBHS_DEVIDR_SOFEC   (0x1u << 2)

(USBHS_DEVIDR) Start of Frame Interrupt Disable

Definition at line 228 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_SUSPEC

#define USBHS_DEVIDR_SUSPEC   (0x1u << 0)

(USBHS_DEVIDR) Suspend Interrupt Disable

Definition at line 226 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_UPRSMEC

#define USBHS_DEVIDR_UPRSMEC   (0x1u << 6)

(USBHS_DEVIDR) Upstream Resume Interrupt Disable

Definition at line 232 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIDR_WAKEUPEC

#define USBHS_DEVIDR_WAKEUPEC   (0x1u << 4)

(USBHS_DEVIDR) Wake-Up Interrupt Disable

Definition at line 230 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_DMA_1

#define USBHS_DEVIER_DMA_1   (0x1u << 25)

(USBHS_DEVIER) DMA Channel 1 Interrupt Enable

Definition at line 268 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_DMA_2

#define USBHS_DEVIER_DMA_2   (0x1u << 26)

(USBHS_DEVIER) DMA Channel 2 Interrupt Enable

Definition at line 269 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_DMA_3

#define USBHS_DEVIER_DMA_3   (0x1u << 27)

(USBHS_DEVIER) DMA Channel 3 Interrupt Enable

Definition at line 270 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_DMA_4

#define USBHS_DEVIER_DMA_4   (0x1u << 28)

(USBHS_DEVIER) DMA Channel 4 Interrupt Enable

Definition at line 271 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_DMA_5

#define USBHS_DEVIER_DMA_5   (0x1u << 29)

(USBHS_DEVIER) DMA Channel 5 Interrupt Enable

Definition at line 272 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_DMA_6

#define USBHS_DEVIER_DMA_6   (0x1u << 30)

(USBHS_DEVIER) DMA Channel 6 Interrupt Enable

Definition at line 273 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_DMA_7

#define USBHS_DEVIER_DMA_7   (0x1u << 31)

(USBHS_DEVIER) DMA Channel 7 Interrupt Enable

Definition at line 274 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_EORSMES

#define USBHS_DEVIER_EORSMES   (0x1u << 5)

(USBHS_DEVIER) End of Resume Interrupt Enable

Definition at line 256 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_EORSTES

#define USBHS_DEVIER_EORSTES   (0x1u << 3)

(USBHS_DEVIER) End of Reset Interrupt Enable

Definition at line 254 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_MSOFES

#define USBHS_DEVIER_MSOFES   (0x1u << 1)

(USBHS_DEVIER) Micro Start of Frame Interrupt Enable

Definition at line 252 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_0

#define USBHS_DEVIER_PEP_0   (0x1u << 12)

(USBHS_DEVIER) Endpoint 0 Interrupt Enable

Definition at line 258 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_1

#define USBHS_DEVIER_PEP_1   (0x1u << 13)

(USBHS_DEVIER) Endpoint 1 Interrupt Enable

Definition at line 259 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_2

#define USBHS_DEVIER_PEP_2   (0x1u << 14)

(USBHS_DEVIER) Endpoint 2 Interrupt Enable

Definition at line 260 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_3

#define USBHS_DEVIER_PEP_3   (0x1u << 15)

(USBHS_DEVIER) Endpoint 3 Interrupt Enable

Definition at line 261 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_4

#define USBHS_DEVIER_PEP_4   (0x1u << 16)

(USBHS_DEVIER) Endpoint 4 Interrupt Enable

Definition at line 262 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_5

#define USBHS_DEVIER_PEP_5   (0x1u << 17)

(USBHS_DEVIER) Endpoint 5 Interrupt Enable

Definition at line 263 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_6

#define USBHS_DEVIER_PEP_6   (0x1u << 18)

(USBHS_DEVIER) Endpoint 6 Interrupt Enable

Definition at line 264 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_7

#define USBHS_DEVIER_PEP_7   (0x1u << 19)

(USBHS_DEVIER) Endpoint 7 Interrupt Enable

Definition at line 265 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_8

#define USBHS_DEVIER_PEP_8   (0x1u << 20)

(USBHS_DEVIER) Endpoint 8 Interrupt Enable

Definition at line 266 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_PEP_9

#define USBHS_DEVIER_PEP_9   (0x1u << 21)

(USBHS_DEVIER) Endpoint 9 Interrupt Enable

Definition at line 267 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_SOFES

#define USBHS_DEVIER_SOFES   (0x1u << 2)

(USBHS_DEVIER) Start of Frame Interrupt Enable

Definition at line 253 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_SUSPES

#define USBHS_DEVIER_SUSPES   (0x1u << 0)

(USBHS_DEVIER) Suspend Interrupt Enable

Definition at line 251 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_UPRSMES

#define USBHS_DEVIER_UPRSMES   (0x1u << 6)

(USBHS_DEVIER) Upstream Resume Interrupt Enable

Definition at line 257 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIER_WAKEUPES

#define USBHS_DEVIER_WAKEUPES   (0x1u << 4)

(USBHS_DEVIER) Wake-Up Interrupt Enable

Definition at line 255 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_DMA_1

#define USBHS_DEVIFR_DMA_1   (0x1u << 25)

(USBHS_DEVIFR) DMA Channel 1 Interrupt Set

Definition at line 193 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_DMA_2

#define USBHS_DEVIFR_DMA_2   (0x1u << 26)

(USBHS_DEVIFR) DMA Channel 2 Interrupt Set

Definition at line 194 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_DMA_3

#define USBHS_DEVIFR_DMA_3   (0x1u << 27)

(USBHS_DEVIFR) DMA Channel 3 Interrupt Set

Definition at line 195 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_DMA_4

#define USBHS_DEVIFR_DMA_4   (0x1u << 28)

(USBHS_DEVIFR) DMA Channel 4 Interrupt Set

Definition at line 196 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_DMA_5

#define USBHS_DEVIFR_DMA_5   (0x1u << 29)

(USBHS_DEVIFR) DMA Channel 5 Interrupt Set

Definition at line 197 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_DMA_6

#define USBHS_DEVIFR_DMA_6   (0x1u << 30)

(USBHS_DEVIFR) DMA Channel 6 Interrupt Set

Definition at line 198 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_DMA_7

#define USBHS_DEVIFR_DMA_7   (0x1u << 31)

(USBHS_DEVIFR) DMA Channel 7 Interrupt Set

Definition at line 199 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_EORSMS

#define USBHS_DEVIFR_EORSMS   (0x1u << 5)

(USBHS_DEVIFR) End of Resume Interrupt Set

Definition at line 191 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_EORSTS

#define USBHS_DEVIFR_EORSTS   (0x1u << 3)

(USBHS_DEVIFR) End of Reset Interrupt Set

Definition at line 189 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_MSOFS

#define USBHS_DEVIFR_MSOFS   (0x1u << 1)

(USBHS_DEVIFR) Micro Start of Frame Interrupt Set

Definition at line 187 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_SOFS

#define USBHS_DEVIFR_SOFS   (0x1u << 2)

(USBHS_DEVIFR) Start of Frame Interrupt Set

Definition at line 188 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_SUSPS

#define USBHS_DEVIFR_SUSPS   (0x1u << 0)

(USBHS_DEVIFR) Suspend Interrupt Set

Definition at line 186 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_UPRSMS

#define USBHS_DEVIFR_UPRSMS   (0x1u << 6)

(USBHS_DEVIFR) Upstream Resume Interrupt Set

Definition at line 192 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIFR_WAKEUPS

#define USBHS_DEVIFR_WAKEUPS   (0x1u << 4)

(USBHS_DEVIFR) Wake-Up Interrupt Set

Definition at line 190 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_DMA_1

#define USBHS_DEVIMR_DMA_1   (0x1u << 25)

(USBHS_DEVIMR) DMA Channel 1 Interrupt Mask

Definition at line 218 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_DMA_2

#define USBHS_DEVIMR_DMA_2   (0x1u << 26)

(USBHS_DEVIMR) DMA Channel 2 Interrupt Mask

Definition at line 219 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_DMA_3

#define USBHS_DEVIMR_DMA_3   (0x1u << 27)

(USBHS_DEVIMR) DMA Channel 3 Interrupt Mask

Definition at line 220 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_DMA_4

#define USBHS_DEVIMR_DMA_4   (0x1u << 28)

(USBHS_DEVIMR) DMA Channel 4 Interrupt Mask

Definition at line 221 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_DMA_5

#define USBHS_DEVIMR_DMA_5   (0x1u << 29)

(USBHS_DEVIMR) DMA Channel 5 Interrupt Mask

Definition at line 222 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_DMA_6

#define USBHS_DEVIMR_DMA_6   (0x1u << 30)

(USBHS_DEVIMR) DMA Channel 6 Interrupt Mask

Definition at line 223 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_DMA_7

#define USBHS_DEVIMR_DMA_7   (0x1u << 31)

(USBHS_DEVIMR) DMA Channel 7 Interrupt Mask

Definition at line 224 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_EORSME

#define USBHS_DEVIMR_EORSME   (0x1u << 5)

(USBHS_DEVIMR) End of Resume Interrupt Mask

Definition at line 206 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_EORSTE

#define USBHS_DEVIMR_EORSTE   (0x1u << 3)

(USBHS_DEVIMR) End of Reset Interrupt Mask

Definition at line 204 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_MSOFE

#define USBHS_DEVIMR_MSOFE   (0x1u << 1)

(USBHS_DEVIMR) Micro Start of Frame Interrupt Mask

Definition at line 202 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_0

#define USBHS_DEVIMR_PEP_0   (0x1u << 12)

(USBHS_DEVIMR) Endpoint 0 Interrupt Mask

Definition at line 208 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_1

#define USBHS_DEVIMR_PEP_1   (0x1u << 13)

(USBHS_DEVIMR) Endpoint 1 Interrupt Mask

Definition at line 209 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_2

#define USBHS_DEVIMR_PEP_2   (0x1u << 14)

(USBHS_DEVIMR) Endpoint 2 Interrupt Mask

Definition at line 210 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_3

#define USBHS_DEVIMR_PEP_3   (0x1u << 15)

(USBHS_DEVIMR) Endpoint 3 Interrupt Mask

Definition at line 211 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_4

#define USBHS_DEVIMR_PEP_4   (0x1u << 16)

(USBHS_DEVIMR) Endpoint 4 Interrupt Mask

Definition at line 212 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_5

#define USBHS_DEVIMR_PEP_5   (0x1u << 17)

(USBHS_DEVIMR) Endpoint 5 Interrupt Mask

Definition at line 213 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_6

#define USBHS_DEVIMR_PEP_6   (0x1u << 18)

(USBHS_DEVIMR) Endpoint 6 Interrupt Mask

Definition at line 214 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_7

#define USBHS_DEVIMR_PEP_7   (0x1u << 19)

(USBHS_DEVIMR) Endpoint 7 Interrupt Mask

Definition at line 215 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_8

#define USBHS_DEVIMR_PEP_8   (0x1u << 20)

(USBHS_DEVIMR) Endpoint 8 Interrupt Mask

Definition at line 216 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_PEP_9

#define USBHS_DEVIMR_PEP_9   (0x1u << 21)

(USBHS_DEVIMR) Endpoint 9 Interrupt Mask

Definition at line 217 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_SOFE

#define USBHS_DEVIMR_SOFE   (0x1u << 2)

(USBHS_DEVIMR) Start of Frame Interrupt Mask

Definition at line 203 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_SUSPE

#define USBHS_DEVIMR_SUSPE   (0x1u << 0)

(USBHS_DEVIMR) Suspend Interrupt Mask

Definition at line 201 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_UPRSME

#define USBHS_DEVIMR_UPRSME   (0x1u << 6)

(USBHS_DEVIMR) Upstream Resume Interrupt Mask

Definition at line 207 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVIMR_WAKEUPE

#define USBHS_DEVIMR_WAKEUPE   (0x1u << 4)

(USBHS_DEVIMR) Wake-Up Interrupt Mask

Definition at line 205 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_DMA_1

#define USBHS_DEVISR_DMA_1   (0x1u << 25)

(USBHS_DEVISR) DMA Channel 1 Interrupt

Definition at line 170 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_DMA_2

#define USBHS_DEVISR_DMA_2   (0x1u << 26)

(USBHS_DEVISR) DMA Channel 2 Interrupt

Definition at line 171 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_DMA_3

#define USBHS_DEVISR_DMA_3   (0x1u << 27)

(USBHS_DEVISR) DMA Channel 3 Interrupt

Definition at line 172 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_DMA_4

#define USBHS_DEVISR_DMA_4   (0x1u << 28)

(USBHS_DEVISR) DMA Channel 4 Interrupt

Definition at line 173 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_DMA_5

#define USBHS_DEVISR_DMA_5   (0x1u << 29)

(USBHS_DEVISR) DMA Channel 5 Interrupt

Definition at line 174 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_DMA_6

#define USBHS_DEVISR_DMA_6   (0x1u << 30)

(USBHS_DEVISR) DMA Channel 6 Interrupt

Definition at line 175 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_DMA_7

#define USBHS_DEVISR_DMA_7   (0x1u << 31)

(USBHS_DEVISR) DMA Channel 7 Interrupt

Definition at line 176 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_EORSM

#define USBHS_DEVISR_EORSM   (0x1u << 5)

(USBHS_DEVISR) End of Resume Interrupt

Definition at line 158 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_EORST

#define USBHS_DEVISR_EORST   (0x1u << 3)

(USBHS_DEVISR) End of Reset Interrupt

Definition at line 156 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_MSOF

#define USBHS_DEVISR_MSOF   (0x1u << 1)

(USBHS_DEVISR) Micro Start of Frame Interrupt

Definition at line 154 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_0

#define USBHS_DEVISR_PEP_0   (0x1u << 12)

(USBHS_DEVISR) Endpoint 0 Interrupt

Definition at line 160 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_1

#define USBHS_DEVISR_PEP_1   (0x1u << 13)

(USBHS_DEVISR) Endpoint 1 Interrupt

Definition at line 161 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_2

#define USBHS_DEVISR_PEP_2   (0x1u << 14)

(USBHS_DEVISR) Endpoint 2 Interrupt

Definition at line 162 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_3

#define USBHS_DEVISR_PEP_3   (0x1u << 15)

(USBHS_DEVISR) Endpoint 3 Interrupt

Definition at line 163 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_4

#define USBHS_DEVISR_PEP_4   (0x1u << 16)

(USBHS_DEVISR) Endpoint 4 Interrupt

Definition at line 164 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_5

#define USBHS_DEVISR_PEP_5   (0x1u << 17)

(USBHS_DEVISR) Endpoint 5 Interrupt

Definition at line 165 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_6

#define USBHS_DEVISR_PEP_6   (0x1u << 18)

(USBHS_DEVISR) Endpoint 6 Interrupt

Definition at line 166 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_7

#define USBHS_DEVISR_PEP_7   (0x1u << 19)

(USBHS_DEVISR) Endpoint 7 Interrupt

Definition at line 167 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_8

#define USBHS_DEVISR_PEP_8   (0x1u << 20)

(USBHS_DEVISR) Endpoint 8 Interrupt

Definition at line 168 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_PEP_9

#define USBHS_DEVISR_PEP_9   (0x1u << 21)

(USBHS_DEVISR) Endpoint 9 Interrupt

Definition at line 169 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_SOF

#define USBHS_DEVISR_SOF   (0x1u << 2)

(USBHS_DEVISR) Start of Frame Interrupt

Definition at line 155 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_SUSP

#define USBHS_DEVISR_SUSP   (0x1u << 0)

(USBHS_DEVISR) Suspend Interrupt

Definition at line 153 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_UPRSM

#define USBHS_DEVISR_UPRSM   (0x1u << 6)

(USBHS_DEVISR) Upstream Resume Interrupt

Definition at line 159 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_DEVISR_WAKEUP

#define USBHS_DEVISR_WAKEUP   (0x1u << 4)

(USBHS_DEVISR) Wake-Up Interrupt

Definition at line 157 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_HOST

#define USBHS_FSM_DRDSTATE_A_HOST   (0x3u << 0)

(USBHS_FSM) In this state, the A-device that operates in Host mode is operational.

Definition at line 935 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_IDLESTATE

#define USBHS_FSM_DRDSTATE_A_IDLESTATE   (0x0u << 0)

(USBHS_FSM) This is the start state for A-devices (when the ID pin is 0)

Definition at line 932 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_PERIPHERAL

#define USBHS_FSM_DRDSTATE_A_PERIPHERAL   (0x5u << 0)

(USBHS_FSM) The A-device operates as a peripheral.

Definition at line 937 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_SUSPEND

#define USBHS_FSM_DRDSTATE_A_SUSPEND   (0x4u << 0)

(USBHS_FSM) The A-device operating as a host is in the Suspend mode.

Definition at line 936 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_VBUS_ERR

#define USBHS_FSM_DRDSTATE_A_VBUS_ERR   (0x7u << 0)

(USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state.

Definition at line 939 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_WAIT_BCON

#define USBHS_FSM_DRDSTATE_A_WAIT_BCON   (0x2u << 0)

(USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection.

Definition at line 934 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE

#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE   (0x8u << 0)

(USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us).

Definition at line 940 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_WAIT_VFALL

#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL   (0x6u << 0)

(USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V).

Definition at line 938 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_A_WAIT_VRISE

#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE   (0x1u << 0)

(USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V).

Definition at line 933 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_B_HOST

#define USBHS_FSM_DRDSTATE_B_HOST   (0xEu << 0)

(USBHS_FSM) In this state, the B-device acts as the Host.

Definition at line 946 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_B_IDLE

#define USBHS_FSM_DRDSTATE_B_IDLE   (0x9u << 0)

(USBHS_FSM) This is the start state for B-device (when the ID pin is 1).

Definition at line 941 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_B_PERIPHERAL

#define USBHS_FSM_DRDSTATE_B_PERIPHERAL   (0xAu << 0)

(USBHS_FSM) In this state, the B-device acts as the peripheral.

Definition at line 942 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_B_SRP_INIT

#define USBHS_FSM_DRDSTATE_B_SRP_INIT   (0xFu << 0)

(USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol.

Definition at line 947 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_B_WAIT_ACON

#define USBHS_FSM_DRDSTATE_B_WAIT_ACON   (0xDu << 0)

(USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host.

Definition at line 945 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP

#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP   (0xBu << 0)

(USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested.

Definition at line 943 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE

#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE   (0xCu << 0)

(USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host.

Definition at line 944 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_Msk

#define USBHS_FSM_DRDSTATE_Msk   (0xfu << USBHS_FSM_DRDSTATE_Pos)

(USBHS_FSM) Dual Role Device State

Definition at line 931 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_FSM_DRDSTATE_Pos

#define USBHS_FSM_DRDSTATE_Pos   0

Definition at line 930 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP0

#define USBHS_HSTADDR1_HSTADDRP0

(

value

)

((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))

Definition at line 664 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP0_Msk

#define USBHS_HSTADDR1_HSTADDRP0_Msk   (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos)

(USBHS_HSTADDR1) USB Host Address

Definition at line 663 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP0_Pos

#define USBHS_HSTADDR1_HSTADDRP0_Pos   0

Definition at line 662 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP1

#define USBHS_HSTADDR1_HSTADDRP1

(

value

)

((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))

Definition at line 667 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP1_Msk

#define USBHS_HSTADDR1_HSTADDRP1_Msk   (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos)

(USBHS_HSTADDR1) USB Host Address

Definition at line 666 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP1_Pos

#define USBHS_HSTADDR1_HSTADDRP1_Pos   8

Definition at line 665 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP2

#define USBHS_HSTADDR1_HSTADDRP2

(

value

)

((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))

Definition at line 670 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP2_Msk

#define USBHS_HSTADDR1_HSTADDRP2_Msk   (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos)

(USBHS_HSTADDR1) USB Host Address

Definition at line 669 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP2_Pos

#define USBHS_HSTADDR1_HSTADDRP2_Pos   16

Definition at line 668 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP3

#define USBHS_HSTADDR1_HSTADDRP3

(

value

)

((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))

Definition at line 673 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP3_Msk

#define USBHS_HSTADDR1_HSTADDRP3_Msk   (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos)

(USBHS_HSTADDR1) USB Host Address

Definition at line 672 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR1_HSTADDRP3_Pos

#define USBHS_HSTADDR1_HSTADDRP3_Pos   24

Definition at line 671 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP4

#define USBHS_HSTADDR2_HSTADDRP4

(

value

)

((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))

Definition at line 677 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP4_Msk

#define USBHS_HSTADDR2_HSTADDRP4_Msk   (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos)

(USBHS_HSTADDR2) USB Host Address

Definition at line 676 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP4_Pos

#define USBHS_HSTADDR2_HSTADDRP4_Pos   0

Definition at line 675 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP5

#define USBHS_HSTADDR2_HSTADDRP5

(

value

)

((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))

Definition at line 680 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP5_Msk

#define USBHS_HSTADDR2_HSTADDRP5_Msk   (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos)

(USBHS_HSTADDR2) USB Host Address

Definition at line 679 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP5_Pos

#define USBHS_HSTADDR2_HSTADDRP5_Pos   8

Definition at line 678 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP6

#define USBHS_HSTADDR2_HSTADDRP6

(

value

)

((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))

Definition at line 683 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP6_Msk

#define USBHS_HSTADDR2_HSTADDRP6_Msk   (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos)

(USBHS_HSTADDR2) USB Host Address

Definition at line 682 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP6_Pos

#define USBHS_HSTADDR2_HSTADDRP6_Pos   16

Definition at line 681 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP7

#define USBHS_HSTADDR2_HSTADDRP7

(

value

)

((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))

Definition at line 686 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP7_Msk

#define USBHS_HSTADDR2_HSTADDRP7_Msk   (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos)

(USBHS_HSTADDR2) USB Host Address

Definition at line 685 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR2_HSTADDRP7_Pos

#define USBHS_HSTADDR2_HSTADDRP7_Pos   24

Definition at line 684 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR3_HSTADDRP8

#define USBHS_HSTADDR3_HSTADDRP8

(

value

)

((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))

Definition at line 690 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR3_HSTADDRP8_Msk

#define USBHS_HSTADDR3_HSTADDRP8_Msk   (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos)

(USBHS_HSTADDR3) USB Host Address

Definition at line 689 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR3_HSTADDRP8_Pos

#define USBHS_HSTADDR3_HSTADDRP8_Pos   0

Definition at line 688 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR3_HSTADDRP9

#define USBHS_HSTADDR3_HSTADDRP9

(

value

)

((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))

Definition at line 693 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR3_HSTADDRP9_Msk

#define USBHS_HSTADDR3_HSTADDRP9_Msk   (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos)

(USBHS_HSTADDR3) USB Host Address

Definition at line 692 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTADDR3_HSTADDRP9_Pos

#define USBHS_HSTADDR3_HSTADDRP9_Pos   8

Definition at line 691 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_RESET

#define USBHS_HSTCTRL_RESET   (0x1u << 9)

(USBHS_HSTCTRL) Send USB Reset

Definition at line 500 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_RESUME

#define USBHS_HSTCTRL_RESUME   (0x1u << 10)

(USBHS_HSTCTRL) Send USB Resume

Definition at line 501 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_SOFE

#define USBHS_HSTCTRL_SOFE   (0x1u << 8)

(USBHS_HSTCTRL) Start of Frame Generation Enable

Definition at line 499 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_SPDCONF

#define USBHS_HSTCTRL_SPDCONF

(

value

)

((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))

Definition at line 504 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_SPDCONF_FORCED_FS

#define USBHS_HSTCTRL_SPDCONF_FORCED_FS   (0x3u << 12)

(USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability.

Definition at line 508 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_SPDCONF_HIGH_SPEED

#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED   (0x2u << 12)

(USBHS_HSTCTRL) Forced high speed.

Definition at line 507 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_SPDCONF_LOW_POWER

#define USBHS_HSTCTRL_SPDCONF_LOW_POWER   (0x1u << 12)

(USBHS_HSTCTRL) For a better consumption, if high speed is not needed.

Definition at line 506 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_SPDCONF_Msk

#define USBHS_HSTCTRL_SPDCONF_Msk   (0x3u << USBHS_HSTCTRL_SPDCONF_Pos)

(USBHS_HSTCTRL) Mode Configuration

Definition at line 503 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_SPDCONF_NORMAL

#define USBHS_HSTCTRL_SPDCONF_NORMAL   (0x0u << 12)

(USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable.

Definition at line 505 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTCTRL_SPDCONF_Pos

#define USBHS_HSTCTRL_SPDCONF_Pos   12

Definition at line 502 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMAADDRESS_BUFF_ADD

#define USBHS_HSTDMAADDRESS_BUFF_ADD

(

value

)

((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))

Definition at line 856 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMAADDRESS_BUFF_ADD_Msk

#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk   (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)

(USBHS_HSTDMAADDRESS) Buffer Address

Definition at line 855 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMAADDRESS_BUFF_ADD_Pos

#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos   0

Definition at line 854 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_BUFF_LENGTH

#define USBHS_HSTDMACONTROL_BUFF_LENGTH

(

value

)

((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))

Definition at line 868 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk

#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk   (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)

(USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only)

Definition at line 867 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos

#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos   16

Definition at line 866 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_BURST_LCK

#define USBHS_HSTDMACONTROL_BURST_LCK   (0x1u << 7)

(USBHS_HSTDMACONTROL) Burst Lock Enable

Definition at line 865 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_CHANN_ENB

#define USBHS_HSTDMACONTROL_CHANN_ENB   (0x1u << 0)

(USBHS_HSTDMACONTROL) Channel Enable Command

Definition at line 858 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_DESC_LD_IT

#define USBHS_HSTDMACONTROL_DESC_LD_IT   (0x1u << 6)

(USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable

Definition at line 864 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_END_B_EN

#define USBHS_HSTDMACONTROL_END_B_EN   (0x1u << 3)

(USBHS_HSTDMACONTROL) End of Buffer Enable Control

Definition at line 861 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_END_BUFFIT

#define USBHS_HSTDMACONTROL_END_BUFFIT   (0x1u << 5)

(USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable

Definition at line 863 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_END_TR_EN

#define USBHS_HSTDMACONTROL_END_TR_EN   (0x1u << 2)

(USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only)

Definition at line 860 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_END_TR_IT

#define USBHS_HSTDMACONTROL_END_TR_IT   (0x1u << 4)

(USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable

Definition at line 862 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMACONTROL_LDNXT_DSC

#define USBHS_HSTDMACONTROL_LDNXT_DSC   (0x1u << 1)

(USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command

Definition at line 859 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMANXTDSC_NXT_DSC_ADD

#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD

(

value

)

((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))

Definition at line 852 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk

#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk   (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)

(USBHS_HSTDMANXTDSC) Next Descriptor Address

Definition at line 851 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos

#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos   0

Definition at line 850 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMASTATUS_BUFF_COUNT

#define USBHS_HSTDMASTATUS_BUFF_COUNT

(

value

)

((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))

Definition at line 877 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMASTATUS_BUFF_COUNT_Msk

#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk   (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)

(USBHS_HSTDMASTATUS) Buffer Byte Count

Definition at line 876 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMASTATUS_BUFF_COUNT_Pos

#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos   16

Definition at line 875 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMASTATUS_CHANN_ACT

#define USBHS_HSTDMASTATUS_CHANN_ACT   (0x1u << 1)

(USBHS_HSTDMASTATUS) Channel Active Status

Definition at line 871 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMASTATUS_CHANN_ENB

#define USBHS_HSTDMASTATUS_CHANN_ENB   (0x1u << 0)

(USBHS_HSTDMASTATUS) Channel Enable Status

Definition at line 870 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMASTATUS_DESC_LDST

#define USBHS_HSTDMASTATUS_DESC_LDST   (0x1u << 6)

(USBHS_HSTDMASTATUS) Descriptor Loaded Status

Definition at line 874 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMASTATUS_END_BF_ST

#define USBHS_HSTDMASTATUS_END_BF_ST   (0x1u << 5)

(USBHS_HSTDMASTATUS) End of Channel Buffer Status

Definition at line 873 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTDMASTATUS_END_TR_ST

#define USBHS_HSTDMASTATUS_END_TR_ST   (0x1u << 4)

(USBHS_HSTDMASTATUS) End of Channel Transfer Status

Definition at line 872 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_FLENHIGH

#define USBHS_HSTFNUM_FLENHIGH

(

value

)

((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))

Definition at line 660 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_FLENHIGH_Msk

#define USBHS_HSTFNUM_FLENHIGH_Msk   (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos)

(USBHS_HSTFNUM) Frame Length

Definition at line 659 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_FLENHIGH_Pos

#define USBHS_HSTFNUM_FLENHIGH_Pos   16

Definition at line 658 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_FNUM

#define USBHS_HSTFNUM_FNUM

(

value

)

((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))

Definition at line 657 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_FNUM_Msk

#define USBHS_HSTFNUM_FNUM_Msk   (0x7ffu << USBHS_HSTFNUM_FNUM_Pos)

(USBHS_HSTFNUM) Frame Number

Definition at line 656 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_FNUM_Pos

#define USBHS_HSTFNUM_FNUM_Pos   3

Definition at line 655 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_MFNUM

#define USBHS_HSTFNUM_MFNUM

(

value

)

((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))

Definition at line 654 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_MFNUM_Msk

#define USBHS_HSTFNUM_MFNUM_Msk   (0x7u << USBHS_HSTFNUM_MFNUM_Pos)

(USBHS_HSTFNUM) Micro Frame Number

Definition at line 653 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTFNUM_MFNUM_Pos

#define USBHS_HSTFNUM_MFNUM_Pos   0

Definition at line 652 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTICR_DCONNIC

#define USBHS_HSTICR_DCONNIC   (0x1u << 0)

(USBHS_HSTICR) Device Connection Interrupt Clear

Definition at line 535 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTICR_DDISCIC

#define USBHS_HSTICR_DDISCIC   (0x1u << 1)

(USBHS_HSTICR) Device Disconnection Interrupt Clear

Definition at line 536 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTICR_HSOFIC

#define USBHS_HSTICR_HSOFIC   (0x1u << 5)

(USBHS_HSTICR) Host Start of Frame Interrupt Clear

Definition at line 540 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTICR_HWUPIC

#define USBHS_HSTICR_HWUPIC   (0x1u << 6)

(USBHS_HSTICR) Host Wake-Up Interrupt Clear

Definition at line 541 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTICR_RSMEDIC

#define USBHS_HSTICR_RSMEDIC   (0x1u << 3)

(USBHS_HSTICR) Downstream Resume Sent Interrupt Clear

Definition at line 538 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTICR_RSTIC

#define USBHS_HSTICR_RSTIC   (0x1u << 2)

(USBHS_HSTICR) USB Reset Sent Interrupt Clear

Definition at line 537 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTICR_RXRSMIC

#define USBHS_HSTICR_RXRSMIC   (0x1u << 4)

(USBHS_HSTICR) Upstream Resume Received Interrupt Clear

Definition at line 539 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DCONNIEC

#define USBHS_HSTIDR_DCONNIEC   (0x1u << 0)

(USBHS_HSTIDR) Device Connection Interrupt Disable

Definition at line 583 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DDISCIEC

#define USBHS_HSTIDR_DDISCIEC   (0x1u << 1)

(USBHS_HSTIDR) Device Disconnection Interrupt Disable

Definition at line 584 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DMA_1

#define USBHS_HSTIDR_DMA_1   (0x1u << 25)

(USBHS_HSTIDR) DMA Channel 1 Interrupt Disable

Definition at line 600 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DMA_2

#define USBHS_HSTIDR_DMA_2   (0x1u << 26)

(USBHS_HSTIDR) DMA Channel 2 Interrupt Disable

Definition at line 601 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DMA_3

#define USBHS_HSTIDR_DMA_3   (0x1u << 27)

(USBHS_HSTIDR) DMA Channel 3 Interrupt Disable

Definition at line 602 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DMA_4

#define USBHS_HSTIDR_DMA_4   (0x1u << 28)

(USBHS_HSTIDR) DMA Channel 4 Interrupt Disable

Definition at line 603 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DMA_5

#define USBHS_HSTIDR_DMA_5   (0x1u << 29)

(USBHS_HSTIDR) DMA Channel 5 Interrupt Disable

Definition at line 604 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DMA_6

#define USBHS_HSTIDR_DMA_6   (0x1u << 30)

(USBHS_HSTIDR) DMA Channel 6 Interrupt Disable

Definition at line 605 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_DMA_7

#define USBHS_HSTIDR_DMA_7   (0x1u << 31)

(USBHS_HSTIDR) DMA Channel 7 Interrupt Disable

Definition at line 606 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_HSOFIEC

#define USBHS_HSTIDR_HSOFIEC   (0x1u << 5)

(USBHS_HSTIDR) Host Start of Frame Interrupt Disable

Definition at line 588 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_HWUPIEC

#define USBHS_HSTIDR_HWUPIEC   (0x1u << 6)

(USBHS_HSTIDR) Host Wake-Up Interrupt Disable

Definition at line 589 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_0

#define USBHS_HSTIDR_PEP_0   (0x1u << 8)

(USBHS_HSTIDR) Pipe 0 Interrupt Disable

Definition at line 590 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_1

#define USBHS_HSTIDR_PEP_1   (0x1u << 9)

(USBHS_HSTIDR) Pipe 1 Interrupt Disable

Definition at line 591 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_2

#define USBHS_HSTIDR_PEP_2   (0x1u << 10)

(USBHS_HSTIDR) Pipe 2 Interrupt Disable

Definition at line 592 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_3

#define USBHS_HSTIDR_PEP_3   (0x1u << 11)

(USBHS_HSTIDR) Pipe 3 Interrupt Disable

Definition at line 593 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_4

#define USBHS_HSTIDR_PEP_4   (0x1u << 12)

(USBHS_HSTIDR) Pipe 4 Interrupt Disable

Definition at line 594 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_5

#define USBHS_HSTIDR_PEP_5   (0x1u << 13)

(USBHS_HSTIDR) Pipe 5 Interrupt Disable

Definition at line 595 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_6

#define USBHS_HSTIDR_PEP_6   (0x1u << 14)

(USBHS_HSTIDR) Pipe 6 Interrupt Disable

Definition at line 596 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_7

#define USBHS_HSTIDR_PEP_7   (0x1u << 15)

(USBHS_HSTIDR) Pipe 7 Interrupt Disable

Definition at line 597 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_8

#define USBHS_HSTIDR_PEP_8   (0x1u << 16)

(USBHS_HSTIDR) Pipe 8 Interrupt Disable

Definition at line 598 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_PEP_9

#define USBHS_HSTIDR_PEP_9   (0x1u << 17)

(USBHS_HSTIDR) Pipe 9 Interrupt Disable

Definition at line 599 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_RSMEDIEC

#define USBHS_HSTIDR_RSMEDIEC   (0x1u << 3)

(USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable

Definition at line 586 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_RSTIEC

#define USBHS_HSTIDR_RSTIEC   (0x1u << 2)

(USBHS_HSTIDR) USB Reset Sent Interrupt Disable

Definition at line 585 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIDR_RXRSMIEC

#define USBHS_HSTIDR_RXRSMIEC   (0x1u << 4)

(USBHS_HSTIDR) Upstream Resume Received Interrupt Disable

Definition at line 587 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DCONNIES

#define USBHS_HSTIER_DCONNIES   (0x1u << 0)

(USBHS_HSTIER) Device Connection Interrupt Enable

Definition at line 608 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DDISCIES

#define USBHS_HSTIER_DDISCIES   (0x1u << 1)

(USBHS_HSTIER) Device Disconnection Interrupt Enable

Definition at line 609 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DMA_1

#define USBHS_HSTIER_DMA_1   (0x1u << 25)

(USBHS_HSTIER) DMA Channel 1 Interrupt Enable

Definition at line 625 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DMA_2

#define USBHS_HSTIER_DMA_2   (0x1u << 26)

(USBHS_HSTIER) DMA Channel 2 Interrupt Enable

Definition at line 626 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DMA_3

#define USBHS_HSTIER_DMA_3   (0x1u << 27)

(USBHS_HSTIER) DMA Channel 3 Interrupt Enable

Definition at line 627 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DMA_4

#define USBHS_HSTIER_DMA_4   (0x1u << 28)

(USBHS_HSTIER) DMA Channel 4 Interrupt Enable

Definition at line 628 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DMA_5

#define USBHS_HSTIER_DMA_5   (0x1u << 29)

(USBHS_HSTIER) DMA Channel 5 Interrupt Enable

Definition at line 629 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DMA_6

#define USBHS_HSTIER_DMA_6   (0x1u << 30)

(USBHS_HSTIER) DMA Channel 6 Interrupt Enable

Definition at line 630 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_DMA_7

#define USBHS_HSTIER_DMA_7   (0x1u << 31)

(USBHS_HSTIER) DMA Channel 7 Interrupt Enable

Definition at line 631 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_HSOFIES

#define USBHS_HSTIER_HSOFIES   (0x1u << 5)

(USBHS_HSTIER) Host Start of Frame Interrupt Enable

Definition at line 613 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_HWUPIES

#define USBHS_HSTIER_HWUPIES   (0x1u << 6)

(USBHS_HSTIER) Host Wake-Up Interrupt Enable

Definition at line 614 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_0

#define USBHS_HSTIER_PEP_0   (0x1u << 8)

(USBHS_HSTIER) Pipe 0 Interrupt Enable

Definition at line 615 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_1

#define USBHS_HSTIER_PEP_1   (0x1u << 9)

(USBHS_HSTIER) Pipe 1 Interrupt Enable

Definition at line 616 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_2

#define USBHS_HSTIER_PEP_2   (0x1u << 10)

(USBHS_HSTIER) Pipe 2 Interrupt Enable

Definition at line 617 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_3

#define USBHS_HSTIER_PEP_3   (0x1u << 11)

(USBHS_HSTIER) Pipe 3 Interrupt Enable

Definition at line 618 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_4

#define USBHS_HSTIER_PEP_4   (0x1u << 12)

(USBHS_HSTIER) Pipe 4 Interrupt Enable

Definition at line 619 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_5

#define USBHS_HSTIER_PEP_5   (0x1u << 13)

(USBHS_HSTIER) Pipe 5 Interrupt Enable

Definition at line 620 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_6

#define USBHS_HSTIER_PEP_6   (0x1u << 14)

(USBHS_HSTIER) Pipe 6 Interrupt Enable

Definition at line 621 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_7

#define USBHS_HSTIER_PEP_7   (0x1u << 15)

(USBHS_HSTIER) Pipe 7 Interrupt Enable

Definition at line 622 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_8

#define USBHS_HSTIER_PEP_8   (0x1u << 16)

(USBHS_HSTIER) Pipe 8 Interrupt Enable

Definition at line 623 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_PEP_9

#define USBHS_HSTIER_PEP_9   (0x1u << 17)

(USBHS_HSTIER) Pipe 9 Interrupt Enable

Definition at line 624 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_RSMEDIES

#define USBHS_HSTIER_RSMEDIES   (0x1u << 3)

(USBHS_HSTIER) Downstream Resume Sent Interrupt Enable

Definition at line 611 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_RSTIES

#define USBHS_HSTIER_RSTIES   (0x1u << 2)

(USBHS_HSTIER) USB Reset Sent Interrupt Enable

Definition at line 610 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIER_RXRSMIES

#define USBHS_HSTIER_RXRSMIES   (0x1u << 4)

(USBHS_HSTIER) Upstream Resume Received Interrupt Enable

Definition at line 612 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DCONNIS

#define USBHS_HSTIFR_DCONNIS   (0x1u << 0)

(USBHS_HSTIFR) Device Connection Interrupt Set

Definition at line 543 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DDISCIS

#define USBHS_HSTIFR_DDISCIS   (0x1u << 1)

(USBHS_HSTIFR) Device Disconnection Interrupt Set

Definition at line 544 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DMA_1

#define USBHS_HSTIFR_DMA_1   (0x1u << 25)

(USBHS_HSTIFR) DMA Channel 1 Interrupt Set

Definition at line 550 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DMA_2

#define USBHS_HSTIFR_DMA_2   (0x1u << 26)

(USBHS_HSTIFR) DMA Channel 2 Interrupt Set

Definition at line 551 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DMA_3

#define USBHS_HSTIFR_DMA_3   (0x1u << 27)

(USBHS_HSTIFR) DMA Channel 3 Interrupt Set

Definition at line 552 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DMA_4

#define USBHS_HSTIFR_DMA_4   (0x1u << 28)

(USBHS_HSTIFR) DMA Channel 4 Interrupt Set

Definition at line 553 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DMA_5

#define USBHS_HSTIFR_DMA_5   (0x1u << 29)

(USBHS_HSTIFR) DMA Channel 5 Interrupt Set

Definition at line 554 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DMA_6

#define USBHS_HSTIFR_DMA_6   (0x1u << 30)

(USBHS_HSTIFR) DMA Channel 6 Interrupt Set

Definition at line 555 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_DMA_7

#define USBHS_HSTIFR_DMA_7   (0x1u << 31)

(USBHS_HSTIFR) DMA Channel 7 Interrupt Set

Definition at line 556 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_HSOFIS

#define USBHS_HSTIFR_HSOFIS   (0x1u << 5)

(USBHS_HSTIFR) Host Start of Frame Interrupt Set

Definition at line 548 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_HWUPIS

#define USBHS_HSTIFR_HWUPIS   (0x1u << 6)

(USBHS_HSTIFR) Host Wake-Up Interrupt Set

Definition at line 549 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_RSMEDIS

#define USBHS_HSTIFR_RSMEDIS   (0x1u << 3)

(USBHS_HSTIFR) Downstream Resume Sent Interrupt Set

Definition at line 546 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_RSTIS

#define USBHS_HSTIFR_RSTIS   (0x1u << 2)

(USBHS_HSTIFR) USB Reset Sent Interrupt Set

Definition at line 545 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIFR_RXRSMIS

#define USBHS_HSTIFR_RXRSMIS   (0x1u << 4)

(USBHS_HSTIFR) Upstream Resume Received Interrupt Set

Definition at line 547 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DCONNIE

#define USBHS_HSTIMR_DCONNIE   (0x1u << 0)

(USBHS_HSTIMR) Device Connection Interrupt Enable

Definition at line 558 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DDISCIE

#define USBHS_HSTIMR_DDISCIE   (0x1u << 1)

(USBHS_HSTIMR) Device Disconnection Interrupt Enable

Definition at line 559 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DMA_1

#define USBHS_HSTIMR_DMA_1   (0x1u << 25)

(USBHS_HSTIMR) DMA Channel 1 Interrupt Enable

Definition at line 575 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DMA_2

#define USBHS_HSTIMR_DMA_2   (0x1u << 26)

(USBHS_HSTIMR) DMA Channel 2 Interrupt Enable

Definition at line 576 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DMA_3

#define USBHS_HSTIMR_DMA_3   (0x1u << 27)

(USBHS_HSTIMR) DMA Channel 3 Interrupt Enable

Definition at line 577 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DMA_4

#define USBHS_HSTIMR_DMA_4   (0x1u << 28)

(USBHS_HSTIMR) DMA Channel 4 Interrupt Enable

Definition at line 578 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DMA_5

#define USBHS_HSTIMR_DMA_5   (0x1u << 29)

(USBHS_HSTIMR) DMA Channel 5 Interrupt Enable

Definition at line 579 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DMA_6

#define USBHS_HSTIMR_DMA_6   (0x1u << 30)

(USBHS_HSTIMR) DMA Channel 6 Interrupt Enable

Definition at line 580 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_DMA_7

#define USBHS_HSTIMR_DMA_7   (0x1u << 31)

(USBHS_HSTIMR) DMA Channel 7 Interrupt Enable

Definition at line 581 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_HSOFIE

#define USBHS_HSTIMR_HSOFIE   (0x1u << 5)

(USBHS_HSTIMR) Host Start of Frame Interrupt Enable

Definition at line 563 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_HWUPIE

#define USBHS_HSTIMR_HWUPIE   (0x1u << 6)

(USBHS_HSTIMR) Host Wake-Up Interrupt Enable

Definition at line 564 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_0

#define USBHS_HSTIMR_PEP_0   (0x1u << 8)

(USBHS_HSTIMR) Pipe 0 Interrupt Enable

Definition at line 565 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_1

#define USBHS_HSTIMR_PEP_1   (0x1u << 9)

(USBHS_HSTIMR) Pipe 1 Interrupt Enable

Definition at line 566 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_2

#define USBHS_HSTIMR_PEP_2   (0x1u << 10)

(USBHS_HSTIMR) Pipe 2 Interrupt Enable

Definition at line 567 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_3

#define USBHS_HSTIMR_PEP_3   (0x1u << 11)

(USBHS_HSTIMR) Pipe 3 Interrupt Enable

Definition at line 568 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_4

#define USBHS_HSTIMR_PEP_4   (0x1u << 12)

(USBHS_HSTIMR) Pipe 4 Interrupt Enable

Definition at line 569 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_5

#define USBHS_HSTIMR_PEP_5   (0x1u << 13)

(USBHS_HSTIMR) Pipe 5 Interrupt Enable

Definition at line 570 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_6

#define USBHS_HSTIMR_PEP_6   (0x1u << 14)

(USBHS_HSTIMR) Pipe 6 Interrupt Enable

Definition at line 571 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_7

#define USBHS_HSTIMR_PEP_7   (0x1u << 15)

(USBHS_HSTIMR) Pipe 7 Interrupt Enable

Definition at line 572 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_8

#define USBHS_HSTIMR_PEP_8   (0x1u << 16)

(USBHS_HSTIMR) Pipe 8 Interrupt Enable

Definition at line 573 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_PEP_9

#define USBHS_HSTIMR_PEP_9   (0x1u << 17)

(USBHS_HSTIMR) Pipe 9 Interrupt Enable

Definition at line 574 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_RSMEDIE

#define USBHS_HSTIMR_RSMEDIE   (0x1u << 3)

(USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable

Definition at line 561 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_RSTIE

#define USBHS_HSTIMR_RSTIE   (0x1u << 2)

(USBHS_HSTIMR) USB Reset Sent Interrupt Enable

Definition at line 560 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTIMR_RXRSMIE

#define USBHS_HSTIMR_RXRSMIE   (0x1u << 4)

(USBHS_HSTIMR) Upstream Resume Received Interrupt Enable

Definition at line 562 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DCONNI

#define USBHS_HSTISR_DCONNI   (0x1u << 0)

(USBHS_HSTISR) Device Connection Interrupt

Definition at line 510 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DDISCI

#define USBHS_HSTISR_DDISCI   (0x1u << 1)

(USBHS_HSTISR) Device Disconnection Interrupt

Definition at line 511 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DMA_1

#define USBHS_HSTISR_DMA_1   (0x1u << 25)

(USBHS_HSTISR) DMA Channel 1 Interrupt

Definition at line 527 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DMA_2

#define USBHS_HSTISR_DMA_2   (0x1u << 26)

(USBHS_HSTISR) DMA Channel 2 Interrupt

Definition at line 528 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DMA_3

#define USBHS_HSTISR_DMA_3   (0x1u << 27)

(USBHS_HSTISR) DMA Channel 3 Interrupt

Definition at line 529 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DMA_4

#define USBHS_HSTISR_DMA_4   (0x1u << 28)

(USBHS_HSTISR) DMA Channel 4 Interrupt

Definition at line 530 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DMA_5

#define USBHS_HSTISR_DMA_5   (0x1u << 29)

(USBHS_HSTISR) DMA Channel 5 Interrupt

Definition at line 531 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DMA_6

#define USBHS_HSTISR_DMA_6   (0x1u << 30)

(USBHS_HSTISR) DMA Channel 6 Interrupt

Definition at line 532 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_DMA_7

#define USBHS_HSTISR_DMA_7   (0x1u << 31)

(USBHS_HSTISR) DMA Channel 7 Interrupt

Definition at line 533 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_HSOFI

#define USBHS_HSTISR_HSOFI   (0x1u << 5)

(USBHS_HSTISR) Host Start of Frame Interrupt

Definition at line 515 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_HWUPI

#define USBHS_HSTISR_HWUPI   (0x1u << 6)

(USBHS_HSTISR) Host Wake-Up Interrupt

Definition at line 516 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_0

#define USBHS_HSTISR_PEP_0   (0x1u << 8)

(USBHS_HSTISR) Pipe 0 Interrupt

Definition at line 517 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_1

#define USBHS_HSTISR_PEP_1   (0x1u << 9)

(USBHS_HSTISR) Pipe 1 Interrupt

Definition at line 518 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_2

#define USBHS_HSTISR_PEP_2   (0x1u << 10)

(USBHS_HSTISR) Pipe 2 Interrupt

Definition at line 519 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_3

#define USBHS_HSTISR_PEP_3   (0x1u << 11)

(USBHS_HSTISR) Pipe 3 Interrupt

Definition at line 520 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_4

#define USBHS_HSTISR_PEP_4   (0x1u << 12)

(USBHS_HSTISR) Pipe 4 Interrupt

Definition at line 521 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_5

#define USBHS_HSTISR_PEP_5   (0x1u << 13)

(USBHS_HSTISR) Pipe 5 Interrupt

Definition at line 522 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_6

#define USBHS_HSTISR_PEP_6   (0x1u << 14)

(USBHS_HSTISR) Pipe 6 Interrupt

Definition at line 523 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_7

#define USBHS_HSTISR_PEP_7   (0x1u << 15)

(USBHS_HSTISR) Pipe 7 Interrupt

Definition at line 524 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_8

#define USBHS_HSTISR_PEP_8   (0x1u << 16)

(USBHS_HSTISR) Pipe 8 Interrupt

Definition at line 525 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_PEP_9

#define USBHS_HSTISR_PEP_9   (0x1u << 17)

(USBHS_HSTISR) Pipe 9 Interrupt

Definition at line 526 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_RSMEDI

#define USBHS_HSTISR_RSMEDI   (0x1u << 3)

(USBHS_HSTISR) Downstream Resume Sent Interrupt

Definition at line 513 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_RSTI

#define USBHS_HSTISR_RSTI   (0x1u << 2)

(USBHS_HSTISR) USB Reset Sent Interrupt

Definition at line 512 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTISR_RXRSMI

#define USBHS_HSTISR_RXRSMI   (0x1u << 4)

(USBHS_HSTISR) Upstream Resume Received Interrupt

Definition at line 514 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN0

#define USBHS_HSTPIP_PEN0   (0x1u << 0)

(USBHS_HSTPIP) Pipe 0 Enable

Definition at line 633 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN1

#define USBHS_HSTPIP_PEN1   (0x1u << 1)

(USBHS_HSTPIP) Pipe 1 Enable

Definition at line 634 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN2

#define USBHS_HSTPIP_PEN2   (0x1u << 2)

(USBHS_HSTPIP) Pipe 2 Enable

Definition at line 635 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN3

#define USBHS_HSTPIP_PEN3   (0x1u << 3)

(USBHS_HSTPIP) Pipe 3 Enable

Definition at line 636 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN4

#define USBHS_HSTPIP_PEN4   (0x1u << 4)

(USBHS_HSTPIP) Pipe 4 Enable

Definition at line 637 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN5

#define USBHS_HSTPIP_PEN5   (0x1u << 5)

(USBHS_HSTPIP) Pipe 5 Enable

Definition at line 638 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN6

#define USBHS_HSTPIP_PEN6   (0x1u << 6)

(USBHS_HSTPIP) Pipe 6 Enable

Definition at line 639 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN7

#define USBHS_HSTPIP_PEN7   (0x1u << 7)

(USBHS_HSTPIP) Pipe 7 Enable

Definition at line 640 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PEN8

#define USBHS_HSTPIP_PEN8   (0x1u << 8)

(USBHS_HSTPIP) Pipe 8 Enable

Definition at line 641 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST0

#define USBHS_HSTPIP_PRST0   (0x1u << 16)

(USBHS_HSTPIP) Pipe 0 Reset

Definition at line 642 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST1

#define USBHS_HSTPIP_PRST1   (0x1u << 17)

(USBHS_HSTPIP) Pipe 1 Reset

Definition at line 643 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST2

#define USBHS_HSTPIP_PRST2   (0x1u << 18)

(USBHS_HSTPIP) Pipe 2 Reset

Definition at line 644 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST3

#define USBHS_HSTPIP_PRST3   (0x1u << 19)

(USBHS_HSTPIP) Pipe 3 Reset

Definition at line 645 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST4

#define USBHS_HSTPIP_PRST4   (0x1u << 20)

(USBHS_HSTPIP) Pipe 4 Reset

Definition at line 646 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST5

#define USBHS_HSTPIP_PRST5   (0x1u << 21)

(USBHS_HSTPIP) Pipe 5 Reset

Definition at line 647 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST6

#define USBHS_HSTPIP_PRST6   (0x1u << 22)

(USBHS_HSTPIP) Pipe 6 Reset

Definition at line 648 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST7

#define USBHS_HSTPIP_PRST7   (0x1u << 23)

(USBHS_HSTPIP) Pipe 7 Reset

Definition at line 649 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIP_PRST8

#define USBHS_HSTPIP_PRST8   (0x1u << 24)

(USBHS_HSTPIP) Pipe 8 Reset

Definition at line 650 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_ALLOC

#define USBHS_HSTPIPCFG_ALLOC   (0x1u << 1)

(USBHS_HSTPIPCFG[10]) Pipe Memory Allocate

Definition at line 695 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_AUTOSW

#define USBHS_HSTPIPCFG_AUTOSW   (0x1u << 10)

(USBHS_HSTPIPCFG[10]) Automatic Switch

Definition at line 719 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_BINTERVAL

#define USBHS_HSTPIPCFG_BINTERVAL

(

value

)

((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))

Definition at line 736 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_BINTERVAL_Msk

#define USBHS_HSTPIPCFG_BINTERVAL_Msk   (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos)

(USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction

Definition at line 735 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_BINTERVAL_Pos

#define USBHS_HSTPIPCFG_BINTERVAL_Pos   24

Definition at line 734 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_INTFRQ

#define USBHS_HSTPIPCFG_INTFRQ

(

value

)

((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))

Definition at line 732 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_INTFRQ_Msk

#define USBHS_HSTPIPCFG_INTFRQ_Msk   (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos)

(USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency

Definition at line 731 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_INTFRQ_Pos

#define USBHS_HSTPIPCFG_INTFRQ_Pos   24

Definition at line 730 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PBK

#define USBHS_HSTPIPCFG_PBK

(

value

)

((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))

Definition at line 698 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PBK_1_BANK

#define USBHS_HSTPIPCFG_PBK_1_BANK   (0x0u << 2)

(USBHS_HSTPIPCFG[10]) Single-bank pipe

Definition at line 699 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PBK_2_BANK

#define USBHS_HSTPIPCFG_PBK_2_BANK   (0x1u << 2)

(USBHS_HSTPIPCFG[10]) Double-bank pipe

Definition at line 700 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PBK_3_BANK

#define USBHS_HSTPIPCFG_PBK_3_BANK   (0x2u << 2)

(USBHS_HSTPIPCFG[10]) Triple-bank pipe

Definition at line 701 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PBK_Msk

#define USBHS_HSTPIPCFG_PBK_Msk   (0x3u << USBHS_HSTPIPCFG_PBK_Pos)

(USBHS_HSTPIPCFG[10]) Pipe Banks

Definition at line 697 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PBK_Pos

#define USBHS_HSTPIPCFG_PBK_Pos   2

Definition at line 696 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PEPNUM

#define USBHS_HSTPIPCFG_PEPNUM

(

value

)

((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))

Definition at line 729 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PEPNUM_Msk

#define USBHS_HSTPIPCFG_PEPNUM_Msk   (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos)

(USBHS_HSTPIPCFG[10]) Pipe Endpoint Number

Definition at line 728 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PEPNUM_Pos

#define USBHS_HSTPIPCFG_PEPNUM_Pos   16

Definition at line 727 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PINGEN

#define USBHS_HSTPIPCFG_PINGEN   (0x1u << 20)

(USBHS_HSTPIPCFG[10]) Ping Enable

Definition at line 733 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE

#define USBHS_HSTPIPCFG_PSIZE

(

value

)

((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))

Definition at line 704 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_1024_BYTE

#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE   (0x7u << 4)

(USBHS_HSTPIPCFG[10]) 1024 bytes

Definition at line 712 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_128_BYTE

#define USBHS_HSTPIPCFG_PSIZE_128_BYTE   (0x4u << 4)

(USBHS_HSTPIPCFG[10]) 128 bytes

Definition at line 709 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_16_BYTE

#define USBHS_HSTPIPCFG_PSIZE_16_BYTE   (0x1u << 4)

(USBHS_HSTPIPCFG[10]) 16 bytes

Definition at line 706 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_256_BYTE

#define USBHS_HSTPIPCFG_PSIZE_256_BYTE   (0x5u << 4)

(USBHS_HSTPIPCFG[10]) 256 bytes

Definition at line 710 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_32_BYTE

#define USBHS_HSTPIPCFG_PSIZE_32_BYTE   (0x2u << 4)

(USBHS_HSTPIPCFG[10]) 32 bytes

Definition at line 707 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_512_BYTE

#define USBHS_HSTPIPCFG_PSIZE_512_BYTE   (0x6u << 4)

(USBHS_HSTPIPCFG[10]) 512 bytes

Definition at line 711 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_64_BYTE

#define USBHS_HSTPIPCFG_PSIZE_64_BYTE   (0x3u << 4)

(USBHS_HSTPIPCFG[10]) 64 bytes

Definition at line 708 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_8_BYTE

#define USBHS_HSTPIPCFG_PSIZE_8_BYTE   (0x0u << 4)

(USBHS_HSTPIPCFG[10]) 8 bytes

Definition at line 705 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_Msk

#define USBHS_HSTPIPCFG_PSIZE_Msk   (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos)

(USBHS_HSTPIPCFG[10]) Pipe Size

Definition at line 703 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PSIZE_Pos

#define USBHS_HSTPIPCFG_PSIZE_Pos   4

Definition at line 702 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTOKEN

#define USBHS_HSTPIPCFG_PTOKEN

(

value

)

((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))

Definition at line 715 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTOKEN_IN

#define USBHS_HSTPIPCFG_PTOKEN_IN   (0x1u << 8)

(USBHS_HSTPIPCFG[10]) IN

Definition at line 717 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTOKEN_Msk

#define USBHS_HSTPIPCFG_PTOKEN_Msk   (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos)

(USBHS_HSTPIPCFG[10]) Pipe Token

Definition at line 714 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTOKEN_OUT

#define USBHS_HSTPIPCFG_PTOKEN_OUT   (0x2u << 8)

(USBHS_HSTPIPCFG[10]) OUT

Definition at line 718 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTOKEN_Pos

#define USBHS_HSTPIPCFG_PTOKEN_Pos   8

Definition at line 713 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTOKEN_SETUP

#define USBHS_HSTPIPCFG_PTOKEN_SETUP   (0x0u << 8)

(USBHS_HSTPIPCFG[10]) SETUP

Definition at line 716 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTYPE

#define USBHS_HSTPIPCFG_PTYPE

(

value

)

((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))

Definition at line 722 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTYPE_BLK

#define USBHS_HSTPIPCFG_PTYPE_BLK   (0x2u << 12)

(USBHS_HSTPIPCFG[10]) Bulk

Definition at line 725 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTYPE_CTRL

#define USBHS_HSTPIPCFG_PTYPE_CTRL   (0x0u << 12)

(USBHS_HSTPIPCFG[10]) Control

Definition at line 723 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTYPE_INTRPT

#define USBHS_HSTPIPCFG_PTYPE_INTRPT   (0x3u << 12)

(USBHS_HSTPIPCFG[10]) Interrupt

Definition at line 726 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTYPE_ISO

#define USBHS_HSTPIPCFG_PTYPE_ISO   (0x1u << 12)

(USBHS_HSTPIPCFG[10]) Isochronous

Definition at line 724 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTYPE_Msk

#define USBHS_HSTPIPCFG_PTYPE_Msk   (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos)

(USBHS_HSTPIPCFG[10]) Pipe Type

Definition at line 721 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPCFG_PTYPE_Pos

#define USBHS_HSTPIPCFG_PTYPE_Pos   12

Definition at line 720 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPERR_COUNTER

#define USBHS_HSTPIPERR_COUNTER

(

value

)

((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))

Definition at line 848 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPERR_COUNTER_Msk

#define USBHS_HSTPIPERR_COUNTER_Msk   (0x3u << USBHS_HSTPIPERR_COUNTER_Pos)

(USBHS_HSTPIPERR[10]) Error Counter

Definition at line 847 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPERR_COUNTER_Pos

#define USBHS_HSTPIPERR_COUNTER_Pos   5

Definition at line 846 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPERR_CRC16

#define USBHS_HSTPIPERR_CRC16   (0x1u << 4)

(USBHS_HSTPIPERR[10]) CRC16 Error

Definition at line 845 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPERR_DATAPID

#define USBHS_HSTPIPERR_DATAPID   (0x1u << 1)

(USBHS_HSTPIPERR[10]) Data PID Error

Definition at line 842 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPERR_DATATGL

#define USBHS_HSTPIPERR_DATATGL   (0x1u << 0)

(USBHS_HSTPIPERR[10]) Data Toggle Error

Definition at line 841 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPERR_PID

#define USBHS_HSTPIPERR_PID   (0x1u << 2)

(USBHS_HSTPIPERR[10]) Data PID Error

Definition at line 843 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPERR_TIMEOUT

#define USBHS_HSTPIPERR_TIMEOUT   (0x1u << 3)

(USBHS_HSTPIPERR[10]) Time-Out Error

Definition at line 844 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_CRCERRIC

#define USBHS_HSTPIPICR_CRCERRIC   (0x1u << 6)

(USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear

Definition at line 776 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_NAKEDIC

#define USBHS_HSTPIPICR_NAKEDIC   (0x1u << 4)

(USBHS_HSTPIPICR[10]) NAKed Interrupt Clear

Definition at line 771 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_OVERFIC

#define USBHS_HSTPIPICR_OVERFIC   (0x1u << 5)

(USBHS_HSTPIPICR[10]) Overflow Interrupt Clear

Definition at line 772 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_RXINIC

#define USBHS_HSTPIPICR_RXINIC   (0x1u << 0)

(USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear

Definition at line 768 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_RXSTALLDIC

#define USBHS_HSTPIPICR_RXSTALLDIC   (0x1u << 6)

(USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear

Definition at line 773 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_SHORTPACKETIC

#define USBHS_HSTPIPICR_SHORTPACKETIC   (0x1u << 7)

(USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear

Definition at line 774 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_TXOUTIC

#define USBHS_HSTPIPICR_TXOUTIC   (0x1u << 1)

(USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear

Definition at line 769 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_TXSTPIC

#define USBHS_HSTPIPICR_TXSTPIC   (0x1u << 2)

(USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear

Definition at line 770 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPICR_UNDERFIC

#define USBHS_HSTPIPICR_UNDERFIC   (0x1u << 2)

(USBHS_HSTPIPICR[10]) Underflow Interrupt Clear

Definition at line 775 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_CRCERREC

#define USBHS_HSTPIPIDR_CRCERREC   (0x1u << 6)

(USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable

Definition at line 834 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_FIFOCONC

#define USBHS_HSTPIPIDR_FIFOCONC   (0x1u << 14)

(USBHS_HSTPIPIDR[10]) FIFO Control Disable

Definition at line 830 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_NAKEDEC

#define USBHS_HSTPIPIDR_NAKEDEC   (0x1u << 4)

(USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable

Definition at line 825 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_NBUSYBKEC

#define USBHS_HSTPIPIDR_NBUSYBKEC   (0x1u << 12)

(USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable

Definition at line 829 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_OVERFIEC

#define USBHS_HSTPIPIDR_OVERFIEC   (0x1u << 5)

(USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable

Definition at line 826 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_PDISHDMAC

#define USBHS_HSTPIPIDR_PDISHDMAC   (0x1u << 16)

(USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable

Definition at line 831 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_PERREC

#define USBHS_HSTPIPIDR_PERREC   (0x1u << 3)

(USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable

Definition at line 824 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_PFREEZEC

#define USBHS_HSTPIPIDR_PFREEZEC   (0x1u << 17)

(USBHS_HSTPIPIDR[10]) Pipe Freeze Disable

Definition at line 832 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_RXINEC

#define USBHS_HSTPIPIDR_RXINEC   (0x1u << 0)

(USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable

Definition at line 821 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_RXSTALLDEC

#define USBHS_HSTPIPIDR_RXSTALLDEC   (0x1u << 6)

(USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable

Definition at line 827 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_SHORTPACKETIEC

#define USBHS_HSTPIPIDR_SHORTPACKETIEC   (0x1u << 7)

(USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable

Definition at line 828 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_TXOUTEC

#define USBHS_HSTPIPIDR_TXOUTEC   (0x1u << 1)

(USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable

Definition at line 822 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_TXSTPEC

#define USBHS_HSTPIPIDR_TXSTPEC   (0x1u << 2)

(USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable

Definition at line 823 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIDR_UNDERFIEC

#define USBHS_HSTPIPIDR_UNDERFIEC   (0x1u << 2)

(USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable

Definition at line 833 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_CRCERRES

#define USBHS_HSTPIPIER_CRCERRES   (0x1u << 6)

(USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable

Definition at line 819 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_NAKEDES

#define USBHS_HSTPIPIER_NAKEDES   (0x1u << 4)

(USBHS_HSTPIPIER[10]) NAKed Interrupt Enable

Definition at line 810 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_NBUSYBKES

#define USBHS_HSTPIPIER_NBUSYBKES   (0x1u << 12)

(USBHS_HSTPIPIER[10]) Number of Busy Banks Enable

Definition at line 814 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_OVERFIES

#define USBHS_HSTPIPIER_OVERFIES   (0x1u << 5)

(USBHS_HSTPIPIER[10]) Overflow Interrupt Enable

Definition at line 811 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_PDISHDMAS

#define USBHS_HSTPIPIER_PDISHDMAS   (0x1u << 16)

(USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable

Definition at line 815 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_PERRES

#define USBHS_HSTPIPIER_PERRES   (0x1u << 3)

(USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable

Definition at line 809 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_PFREEZES

#define USBHS_HSTPIPIER_PFREEZES   (0x1u << 17)

(USBHS_HSTPIPIER[10]) Pipe Freeze Enable

Definition at line 816 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_RSTDTS

#define USBHS_HSTPIPIER_RSTDTS   (0x1u << 18)

(USBHS_HSTPIPIER[10]) Reset Data Toggle Enable

Definition at line 817 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_RXINES

#define USBHS_HSTPIPIER_RXINES   (0x1u << 0)

(USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable

Definition at line 806 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_RXSTALLDES

#define USBHS_HSTPIPIER_RXSTALLDES   (0x1u << 6)

(USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable

Definition at line 812 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_SHORTPACKETIES

#define USBHS_HSTPIPIER_SHORTPACKETIES   (0x1u << 7)

(USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable

Definition at line 813 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_TXOUTES

#define USBHS_HSTPIPIER_TXOUTES   (0x1u << 1)

(USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable

Definition at line 807 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_TXSTPES

#define USBHS_HSTPIPIER_TXSTPES   (0x1u << 2)

(USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable

Definition at line 808 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIER_UNDERFIES

#define USBHS_HSTPIPIER_UNDERFIES   (0x1u << 2)

(USBHS_HSTPIPIER[10]) Underflow Interrupt Enable

Definition at line 818 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_CRCERRIS

#define USBHS_HSTPIPIFR_CRCERRIS   (0x1u << 6)

(USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set

Definition at line 788 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_NAKEDIS

#define USBHS_HSTPIPIFR_NAKEDIS   (0x1u << 4)

(USBHS_HSTPIPIFR[10]) NAKed Interrupt Set

Definition at line 782 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_NBUSYBKS

#define USBHS_HSTPIPIFR_NBUSYBKS   (0x1u << 12)

(USBHS_HSTPIPIFR[10]) Number of Busy Banks Set

Definition at line 786 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_OVERFIS

#define USBHS_HSTPIPIFR_OVERFIS   (0x1u << 5)

(USBHS_HSTPIPIFR[10]) Overflow Interrupt Set

Definition at line 783 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_PERRIS

#define USBHS_HSTPIPIFR_PERRIS   (0x1u << 3)

(USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set

Definition at line 781 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_RXINIS

#define USBHS_HSTPIPIFR_RXINIS   (0x1u << 0)

(USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set

Definition at line 778 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_RXSTALLDIS

#define USBHS_HSTPIPIFR_RXSTALLDIS   (0x1u << 6)

(USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set

Definition at line 784 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_SHORTPACKETIS

#define USBHS_HSTPIPIFR_SHORTPACKETIS   (0x1u << 7)

(USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set

Definition at line 785 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_TXOUTIS

#define USBHS_HSTPIPIFR_TXOUTIS   (0x1u << 1)

(USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set

Definition at line 779 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_TXSTPIS

#define USBHS_HSTPIPIFR_TXSTPIS   (0x1u << 2)

(USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set

Definition at line 780 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIFR_UNDERFIS

#define USBHS_HSTPIPIFR_UNDERFIS   (0x1u << 2)

(USBHS_HSTPIPIFR[10]) Underflow Interrupt Set

Definition at line 787 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_CRCERRE

#define USBHS_HSTPIPIMR_CRCERRE   (0x1u << 6)

(USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable

Definition at line 804 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_FIFOCON

#define USBHS_HSTPIPIMR_FIFOCON   (0x1u << 14)

(USBHS_HSTPIPIMR[10]) FIFO Control

Definition at line 799 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_NAKEDE

#define USBHS_HSTPIPIMR_NAKEDE   (0x1u << 4)

(USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable

Definition at line 794 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_NBUSYBKE

#define USBHS_HSTPIPIMR_NBUSYBKE   (0x1u << 12)

(USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable

Definition at line 798 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_OVERFIE

#define USBHS_HSTPIPIMR_OVERFIE   (0x1u << 5)

(USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable

Definition at line 795 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_PDISHDMA

#define USBHS_HSTPIPIMR_PDISHDMA   (0x1u << 16)

(USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable

Definition at line 800 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_PERRE

#define USBHS_HSTPIPIMR_PERRE   (0x1u << 3)

(USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable

Definition at line 793 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_PFREEZE

#define USBHS_HSTPIPIMR_PFREEZE   (0x1u << 17)

(USBHS_HSTPIPIMR[10]) Pipe Freeze

Definition at line 801 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_RSTDT

#define USBHS_HSTPIPIMR_RSTDT   (0x1u << 18)

(USBHS_HSTPIPIMR[10]) Reset Data Toggle

Definition at line 802 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_RXINE

#define USBHS_HSTPIPIMR_RXINE   (0x1u << 0)

(USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable

Definition at line 790 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_RXSTALLDE

#define USBHS_HSTPIPIMR_RXSTALLDE   (0x1u << 6)

(USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable

Definition at line 796 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_SHORTPACKETIE

#define USBHS_HSTPIPIMR_SHORTPACKETIE   (0x1u << 7)

(USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable

Definition at line 797 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_TXOUTE

#define USBHS_HSTPIPIMR_TXOUTE   (0x1u << 1)

(USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable

Definition at line 791 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_TXSTPE

#define USBHS_HSTPIPIMR_TXSTPE   (0x1u << 2)

(USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable

Definition at line 792 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPIMR_UNDERFIE

#define USBHS_HSTPIPIMR_UNDERFIE   (0x1u << 2)

(USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable

Definition at line 803 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPINRQ_INMODE

#define USBHS_HSTPIPINRQ_INMODE   (0x1u << 8)

(USBHS_HSTPIPINRQ[10]) IN Request Mode

Definition at line 839 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPINRQ_INRQ

#define USBHS_HSTPIPINRQ_INRQ

(

value

)

((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))

Definition at line 838 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPINRQ_INRQ_Msk

#define USBHS_HSTPIPINRQ_INRQ_Msk   (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos)

(USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze

Definition at line 837 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPINRQ_INRQ_Pos

#define USBHS_HSTPIPINRQ_INRQ_Pos   0

Definition at line 836 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_CFGOK

#define USBHS_HSTPIPISR_CFGOK   (0x1u << 18)

(USBHS_HSTPIPISR[10]) Configuration OK Status

Definition at line 762 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_CRCERRI

#define USBHS_HSTPIPISR_CRCERRI   (0x1u << 6)

(USBHS_HSTPIPISR[10]) CRC Error Interrupt

Definition at line 766 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_CURRBK_BANK0

#define USBHS_HSTPIPISR_CURRBK_BANK0   (0x0u << 14)

(USBHS_HSTPIPISR[10]) Current bank is bank0

Definition at line 758 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_CURRBK_BANK1

#define USBHS_HSTPIPISR_CURRBK_BANK1   (0x1u << 14)

(USBHS_HSTPIPISR[10]) Current bank is bank1

Definition at line 759 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_CURRBK_BANK2

#define USBHS_HSTPIPISR_CURRBK_BANK2   (0x2u << 14)

(USBHS_HSTPIPISR[10]) Current bank is bank2

Definition at line 760 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_CURRBK_Msk

#define USBHS_HSTPIPISR_CURRBK_Msk   (0x3u << USBHS_HSTPIPISR_CURRBK_Pos)

(USBHS_HSTPIPISR[10]) Current Bank

Definition at line 757 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_CURRBK_Pos

#define USBHS_HSTPIPISR_CURRBK_Pos   14

Definition at line 756 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_DTSEQ_DATA0

#define USBHS_HSTPIPISR_DTSEQ_DATA0   (0x0u << 8)

(USBHS_HSTPIPISR[10]) Data0 toggle sequence

Definition at line 748 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_DTSEQ_DATA1

#define USBHS_HSTPIPISR_DTSEQ_DATA1   (0x1u << 8)

(USBHS_HSTPIPISR[10]) Data1 toggle sequence

Definition at line 749 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_DTSEQ_Msk

#define USBHS_HSTPIPISR_DTSEQ_Msk   (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos)

(USBHS_HSTPIPISR[10]) Data Toggle Sequence

Definition at line 747 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_DTSEQ_Pos

#define USBHS_HSTPIPISR_DTSEQ_Pos   8

Definition at line 746 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_NAKEDI

#define USBHS_HSTPIPISR_NAKEDI   (0x1u << 4)

(USBHS_HSTPIPISR[10]) NAKed Interrupt

Definition at line 742 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_NBUSYBK_0_BUSY

#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY   (0x0u << 12)

(USBHS_HSTPIPISR[10]) 0 busy bank (all banks free)

Definition at line 752 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_NBUSYBK_1_BUSY

#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY   (0x1u << 12)

(USBHS_HSTPIPISR[10]) 1 busy bank

Definition at line 753 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_NBUSYBK_2_BUSY

#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY   (0x2u << 12)

(USBHS_HSTPIPISR[10]) 2 busy banks

Definition at line 754 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_NBUSYBK_3_BUSY

#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY   (0x3u << 12)

(USBHS_HSTPIPISR[10]) 3 busy banks

Definition at line 755 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_NBUSYBK_Msk

#define USBHS_HSTPIPISR_NBUSYBK_Msk   (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos)

(USBHS_HSTPIPISR[10]) Number of Busy Banks

Definition at line 751 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_NBUSYBK_Pos

#define USBHS_HSTPIPISR_NBUSYBK_Pos   12

Definition at line 750 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_OVERFI

#define USBHS_HSTPIPISR_OVERFI   (0x1u << 5)

(USBHS_HSTPIPISR[10]) Overflow Interrupt

Definition at line 743 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_PBYCT_Msk

#define USBHS_HSTPIPISR_PBYCT_Msk   (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos)

(USBHS_HSTPIPISR[10]) Pipe Byte Count

Definition at line 764 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_PBYCT_Pos

#define USBHS_HSTPIPISR_PBYCT_Pos   20

Definition at line 763 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_PERRI

#define USBHS_HSTPIPISR_PERRI   (0x1u << 3)

(USBHS_HSTPIPISR[10]) Pipe Error Interrupt

Definition at line 741 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_RWALL

#define USBHS_HSTPIPISR_RWALL   (0x1u << 16)

(USBHS_HSTPIPISR[10]) Read/Write Allowed

Definition at line 761 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_RXINI

#define USBHS_HSTPIPISR_RXINI   (0x1u << 0)

(USBHS_HSTPIPISR[10]) Received IN Data Interrupt

Definition at line 738 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_RXSTALLDI

#define USBHS_HSTPIPISR_RXSTALLDI   (0x1u << 6)

(USBHS_HSTPIPISR[10]) Received STALLed Interrupt

Definition at line 744 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_SHORTPACKETI

#define USBHS_HSTPIPISR_SHORTPACKETI   (0x1u << 7)

(USBHS_HSTPIPISR[10]) Short Packet Interrupt

Definition at line 745 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_TXOUTI

#define USBHS_HSTPIPISR_TXOUTI   (0x1u << 1)

(USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt

Definition at line 739 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_TXSTPI

#define USBHS_HSTPIPISR_TXSTPI   (0x1u << 2)

(USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt

Definition at line 740 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_HSTPIPISR_UNDERFI

#define USBHS_HSTPIPISR_UNDERFI   (0x1u << 2)

(USBHS_HSTPIPISR[10]) Underflow Interrupt

Definition at line 765 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SCR_RDERRIC

#define USBHS_SCR_RDERRIC   (0x1u << 4)

(USBHS_SCR) Remote Device Connection Error Interrupt Clear

Definition at line 896 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SCR_VBUSRQC

#define USBHS_SCR_VBUSRQC   (0x1u << 9)

(USBHS_SCR) VBus Request Clear

Definition at line 897 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SFR_RDERRIS

#define USBHS_SFR_RDERRIS   (0x1u << 4)

(USBHS_SFR) Remote Device Connection Error Interrupt Set

Definition at line 899 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SFR_VBUSRQS

#define USBHS_SFR_VBUSRQS   (0x1u << 9)

(USBHS_SFR) VBus Request Set

Definition at line 900 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SR_CLKUSABLE

#define USBHS_SR_CLKUSABLE   (0x1u << 14)

(USBHS_SR) UTMI Clock Usable

Definition at line 894 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SR_RDERRI

#define USBHS_SR_RDERRI   (0x1u << 4)

(USBHS_SR) Remote Device Connection Error Interrupt (Host mode only)

Definition at line 887 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SR_SPEED_FULL_SPEED

#define USBHS_SR_SPEED_FULL_SPEED   (0x0u << 12)

(USBHS_SR) Full-Speed mode

Definition at line 891 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SR_SPEED_HIGH_SPEED

#define USBHS_SR_SPEED_HIGH_SPEED   (0x1u << 12)

(USBHS_SR) High-Speed mode

Definition at line 892 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SR_SPEED_LOW_SPEED

#define USBHS_SR_SPEED_LOW_SPEED   (0x2u << 12)

(USBHS_SR) Low-Speed mode

Definition at line 893 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SR_SPEED_Msk

#define USBHS_SR_SPEED_Msk   (0x3u << USBHS_SR_SPEED_Pos)

(USBHS_SR) Speed Status (Device mode only)

Definition at line 890 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SR_SPEED_Pos

#define USBHS_SR_SPEED_Pos   12

Definition at line 889 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_SR_VBUSRQ

#define USBHS_SR_VBUSRQ   (0x1u << 9)

(USBHS_SR) VBus Request (Host mode only)

Definition at line 888 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_CounterA

#define USBHS_TSTA1_CounterA

(

value

)

((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos)))

Definition at line 904 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_CounterA_Msk

#define USBHS_TSTA1_CounterA_Msk   (0x7fffu << USBHS_TSTA1_CounterA_Pos)

(USBHS_TSTA1) Counter A

Definition at line 903 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_CounterA_Pos

#define USBHS_TSTA1_CounterA_Pos   0

Definition at line 902 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_CounterB

#define USBHS_TSTA1_CounterB

(

value

)

((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos)))

Definition at line 908 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_CounterB_Msk

#define USBHS_TSTA1_CounterB_Msk   (0x3fu << USBHS_TSTA1_CounterB_Pos)

(USBHS_TSTA1) Counter B

Definition at line 907 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_CounterB_Pos

#define USBHS_TSTA1_CounterB_Pos   16

Definition at line 906 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_LoadCntA

#define USBHS_TSTA1_LoadCntA   (0x1u << 15)

(USBHS_TSTA1) Load CounterA

Definition at line 905 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_LoadCntB

#define USBHS_TSTA1_LoadCntB   (0x1u << 23)

(USBHS_TSTA1) Load CounterB

Definition at line 909 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_LoadSOFCnt

#define USBHS_TSTA1_LoadSOFCnt   (0x1u << 31)

(USBHS_TSTA1) Load SOF Counter

Definition at line 913 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_SOFCntMa1

#define USBHS_TSTA1_SOFCntMa1

(

value

)

((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos)))

Definition at line 912 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_SOFCntMa1_Msk

#define USBHS_TSTA1_SOFCntMa1_Msk   (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos)

(USBHS_TSTA1) SOF Counter Max

Definition at line 911 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA1_SOFCntMa1_Pos

#define USBHS_TSTA1_SOFCntMa1_Pos   24

Definition at line 910 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_ByPassDpll

#define USBHS_TSTA2_ByPassDpll   (0x1u << 5)

(USBHS_TSTA2) Bypass DPLL

Definition at line 920 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_DisableGatedClock

#define USBHS_TSTA2_DisableGatedClock   (0x1u << 3)

(USBHS_TSTA2) Disable Gated Clock

Definition at line 918 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_ForceHSRst_50ms

#define USBHS_TSTA2_ForceHSRst_50ms   (0x1u << 7)

(USBHS_TSTA2) Force HS Reset to 50 ms

Definition at line 922 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_ForceSuspendMTo1

#define USBHS_TSTA2_ForceSuspendMTo1   (0x1u << 4)

(USBHS_TSTA2) Force SuspendM to 1

Definition at line 919 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_FullDetachEn

#define USBHS_TSTA2_FullDetachEn   (0x1u << 0)

(USBHS_TSTA2) Full Detach Enable

Definition at line 915 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_HostHSDisconnectDisable

#define USBHS_TSTA2_HostHSDisconnectDisable   (0x1u << 6)

(USBHS_TSTA2) Host HS Disconnect Disable

Definition at line 921 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_HSSerialMode

#define USBHS_TSTA2_HSSerialMode   (0x1u << 1)

(USBHS_TSTA2) HS Serial Mode

Definition at line 916 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_LoopBackMode

#define USBHS_TSTA2_LoopBackMode   (0x1u << 2)

(USBHS_TSTA2) Loop-back Mode

Definition at line 917 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_TSTA2_RemovePUWhenTX

#define USBHS_TSTA2_RemovePUWhenTX   (0x1u << 9)

(USBHS_TSTA2) Remove Pull-up When TX

Definition at line 923 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_VERSION_MFN_Msk

#define USBHS_VERSION_MFN_Msk   (0xfu << USBHS_VERSION_MFN_Pos)

(USBHS_VERSION) Metal Fix Number

Definition at line 928 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_VERSION_MFN_Pos

#define USBHS_VERSION_MFN_Pos   16

Definition at line 927 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_VERSION_VERSION_Msk

#define USBHS_VERSION_VERSION_Msk   (0xfffu << USBHS_VERSION_VERSION_Pos)

(USBHS_VERSION) Version Number

Definition at line 926 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHS_VERSION_VERSION_Pos

#define USBHS_VERSION_VERSION_Pos   0

Definition at line 925 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHSDEVDMA_NUMBER

#define USBHSDEVDMA_NUMBER   7

Usbhs hardware registers.

Definition at line 60 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.

USBHSHSTDMA_NUMBER

#define USBHSHSTDMA_NUMBER   7

Definition at line 61 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h.