CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F10x Connectivity line, High density, High density value line, Medium density, Medium density Value line, Low density, Low density Value line and XL-density devices. More...
Go to the source code of this file.
Classes | |
struct | ADC_TypeDef |
Analog to Digital Converter. More... | |
struct | AFIO_TypeDef |
Alternate Function I/O. More... | |
struct | BKP_TypeDef |
Backup Registers. More... | |
struct | CAN_FIFOMailBox_TypeDef |
Controller Area Network FIFOMailBox. More... | |
struct | CAN_FilterRegister_TypeDef |
Controller Area Network FilterRegister. More... | |
struct | CAN_TxMailBox_TypeDef |
Controller Area Network TxMailBox. More... | |
struct | CAN_TypeDef |
Controller Area Network. More... | |
struct | CEC_TypeDef |
Consumer Electronics Control (CEC) More... | |
struct | CRC_TypeDef |
CRC calculation unit. More... | |
struct | DAC_TypeDef |
Digital to Analog Converter. More... | |
struct | DBGMCU_TypeDef |
Debug MCU. More... | |
struct | DMA_Channel_TypeDef |
DMA Controller. More... | |
struct | DMA_TypeDef |
struct | ETH_TypeDef |
Ethernet MAC. More... | |
struct | EXTI_TypeDef |
External Interrupt/Event Controller. More... | |
struct | FLASH_TypeDef |
FLASH Registers. More... | |
struct | FSMC_Bank1_TypeDef |
Flexible Static Memory Controller. More... | |
struct | FSMC_Bank1E_TypeDef |
Flexible Static Memory Controller Bank1E. More... | |
struct | FSMC_Bank2_TypeDef |
Flexible Static Memory Controller Bank2. More... | |
struct | FSMC_Bank3_TypeDef |
Flexible Static Memory Controller Bank3. More... | |
struct | FSMC_Bank4_TypeDef |
Flexible Static Memory Controller Bank4. More... | |
struct | GPIO_TypeDef |
General Purpose I/O. More... | |
struct | I2C_TypeDef |
Inter-integrated Circuit Interface. More... | |
struct | IWDG_TypeDef |
Independent WATCHDOG. More... | |
struct | OB_TypeDef |
Option Bytes Registers. More... | |
struct | PWR_TypeDef |
Power Control. More... | |
struct | RCC_TypeDef |
Reset and Clock Control. More... | |
struct | RTC_TypeDef |
Real-Time Clock. More... | |
struct | SDIO_TypeDef |
SD host Interface. More... | |
struct | SPI_TypeDef |
Serial Peripheral Interface. More... | |
struct | TIM_TypeDef |
TIM. More... | |
struct | USART_TypeDef |
Universal Synchronous Asynchronous Receiver Transmitter. More... | |
struct | WWDG_TypeDef |
Window WATCHDOG. More... | |
Macros | |
#define | __MPU_PRESENT 0 |
Configuration of the Cortex-M3 Processor and Core Peripherals. More... | |
#define | __NVIC_PRIO_BITS 4 |
#define | __STM32F10X_STDPERIPH_VERSION |
#define | __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) |
STM32F10x Standard Peripheral Library version number. More... | |
#define | __STM32F10X_STDPERIPH_VERSION_RC (0x00) |
#define | __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) |
#define | __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) |
#define | __Vendor_SysTickConfig 0 |
#define | ADC1 ((ADC_TypeDef *) ADC1_BASE) |
#define | ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
#define | ADC2 ((ADC_TypeDef *) ADC2_BASE) |
#define | ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
#define | ADC3 ((ADC_TypeDef *) ADC3_BASE) |
#define | ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
#define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
#define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
#define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
#define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
#define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
#define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
#define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
#define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
#define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
#define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
#define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
#define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
#define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
#define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
#define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
#define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
#define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
#define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
#define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
#define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
#define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
#define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
#define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
#define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
#define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
#define | ADC_CR2_ADON ((uint32_t)0x00000001) |
#define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
#define | ADC_CR2_CAL ((uint32_t)0x00000004) |
#define | ADC_CR2_CONT ((uint32_t)0x00000002) |
#define | ADC_CR2_DMA ((uint32_t)0x00000100) |
#define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
#define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
#define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
#define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
#define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
#define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
#define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
#define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
#define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
#define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
#define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
#define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
#define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
#define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
#define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
#define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
#define | ADC_HTR_HT ((uint16_t)0x0FFF) |
#define | ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
#define | ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
#define | ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
#define | ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
#define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
#define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
#define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
#define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
#define | ADC_JSQR_JL ((uint32_t)0x00300000) |
#define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
#define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
#define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
#define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
#define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
#define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
#define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
#define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
#define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
#define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
#define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
#define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
#define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
#define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
#define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
#define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
#define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
#define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
#define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
#define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
#define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
#define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
#define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
#define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
#define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
#define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
#define | ADC_LTR_LT ((uint16_t)0x0FFF) |
#define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
#define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
#define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
#define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
#define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
#define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
#define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
#define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
#define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
#define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
#define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
#define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
#define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
#define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
#define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
#define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
#define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
#define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
#define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
#define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
#define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
#define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
#define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
#define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
#define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
#define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
#define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
#define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
#define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
#define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
#define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
#define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
#define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
#define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
#define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
#define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
#define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
#define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
#define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
#define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
#define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
#define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
#define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
#define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
#define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
#define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
#define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
#define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
#define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
#define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
#define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
#define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
#define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
#define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
#define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
#define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
#define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
#define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
#define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
#define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
#define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
#define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
#define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
#define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
#define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
#define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
#define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
#define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
#define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
#define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
#define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
#define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
#define | ADC_SQR1_L ((uint32_t)0x00F00000) |
#define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
#define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
#define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
#define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
#define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
#define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
#define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
#define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
#define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
#define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
#define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
#define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
#define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
#define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
#define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
#define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
#define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
#define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
#define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
#define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
#define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
#define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
#define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
#define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
#define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
#define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
#define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
#define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
#define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
#define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
#define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
#define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
#define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
#define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
#define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
#define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
#define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
#define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
#define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
#define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
#define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
#define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
#define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
#define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
#define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
#define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
#define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
#define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
#define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
#define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
#define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
#define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
#define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
#define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
#define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
#define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
#define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
#define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
#define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
#define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
#define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
#define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
#define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
#define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
#define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
#define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
#define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
#define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
#define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
#define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
#define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
#define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
#define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
#define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
#define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
#define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
#define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
#define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
#define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
#define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
#define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
#define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
#define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
#define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
#define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
#define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
#define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
#define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
#define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
#define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
#define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
#define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
#define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
#define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
#define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
#define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
#define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
#define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
#define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
#define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
#define | ADC_SR_AWD ((uint8_t)0x01) |
#define | ADC_SR_EOC ((uint8_t)0x02) |
#define | ADC_SR_JEOC ((uint8_t)0x04) |
#define | ADC_SR_JSTRT ((uint8_t)0x08) |
#define | ADC_SR_STRT ((uint8_t)0x10) |
#define | AFIO ((AFIO_TypeDef *) AFIO_BASE) |
#define | AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
#define | AFIO_EVCR_EVOE ((uint8_t)0x80) |
#define | AFIO_EVCR_PIN ((uint8_t)0x0F) |
#define | AFIO_EVCR_PIN_0 ((uint8_t)0x01) |
#define | AFIO_EVCR_PIN_1 ((uint8_t)0x02) |
#define | AFIO_EVCR_PIN_2 ((uint8_t)0x04) |
#define | AFIO_EVCR_PIN_3 ((uint8_t)0x08) |
#define | AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) |
#define | AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) |
#define | AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) |
#define | AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) |
#define | AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) |
#define | AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) |
#define | AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) |
#define | AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) |
#define | AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) |
#define | AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) |
#define | AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) |
#define | AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) |
#define | AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) |
#define | AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) |
#define | AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) |
#define | AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) |
#define | AFIO_EVCR_PORT ((uint8_t)0x70) |
#define | AFIO_EVCR_PORT_0 ((uint8_t)0x10) |
#define | AFIO_EVCR_PORT_1 ((uint8_t)0x20) |
#define | AFIO_EVCR_PORT_2 ((uint8_t)0x40) |
#define | AFIO_EVCR_PORT_PA ((uint8_t)0x00) |
#define | AFIO_EVCR_PORT_PB ((uint8_t)0x10) |
#define | AFIO_EVCR_PORT_PC ((uint8_t)0x20) |
#define | AFIO_EVCR_PORT_PD ((uint8_t)0x30) |
#define | AFIO_EVCR_PORT_PE ((uint8_t)0x40) |
#define | AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) |
#define | AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
#define | AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
#define | AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
#define | AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
#define | AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
#define | AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) |
#define | AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
#define | AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
#define | AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
#define | AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
#define | AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
#define | AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
#define | AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) |
#define | AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
#define | AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
#define | AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
#define | AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
#define | AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
#define | AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
#define | AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) |
#define | AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) |
#define | AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
#define | AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
#define | AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
#define | AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
#define | AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) |
#define | AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) |
#define | AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) |
#define | AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
#define | AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
#define | AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
#define | AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
#define | AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
#define | AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) |
#define | AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
#define | AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
#define | AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
#define | AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
#define | AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
#define | AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) |
#define | AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) |
#define | AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
#define | AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
#define | AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
#define | AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
#define | AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
#define | AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
#define | AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) |
#define | AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) |
#define | AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
#define | AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
#define | AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
#define | AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
#define | AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) |
#define | AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) |
#define | AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
#define | AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
#define | AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
#define | AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
#define | AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
#define | AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
#define | AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) |
#define | AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) |
#define | AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
#define | AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
#define | AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
#define | AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
#define | AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) |
#define | AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) |
#define | AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) |
#define | AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
#define | AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
#define | AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
#define | AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
#define | AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) |
#define | AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) |
#define | AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
#define | AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
#define | AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
#define | AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
#define | AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
#define | AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
#define | AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) |
#define | AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) |
#define | AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
#define | AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
#define | AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
#define | AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
#define | AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) |
#define | AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) |
#define | AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
#define | AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
#define | AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
#define | AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
#define | AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
#define | AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) |
#define | AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) |
#define | AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
#define | AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
#define | AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
#define | AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
#define | AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
#define | AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) |
#define | AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) |
#define | AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) |
#define | AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
#define | AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
#define | AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
#define | AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
#define | AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
#define | AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) |
#define | AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) |
#define | AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) |
#define | AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) |
#define | AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) |
#define | AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) |
#define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
#define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
#define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
#define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
#define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
#define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
#define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
#define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
#define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
#define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
#define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
#define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
#define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
#define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
#define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
#define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
#define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
#define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
#define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
#define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
#define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
#define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
#define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
#define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
#define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
#define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
#define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
#define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
#define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
#define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
#define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
#define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
#define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
#define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
#define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
#define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
#define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
#define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
#define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
#define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
#define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
#define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
#define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
#define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
#define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
#define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
#define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
#define | APB1PERIPH_BASE PERIPH_BASE |
#define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
#define | BKP ((BKP_TypeDef *) BKP_BASE) |
#define | BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
#define | BKP_CR_TPAL ((uint8_t)0x02) |
#define | BKP_CR_TPE ((uint8_t)0x01) |
#define | BKP_CSR_CTE ((uint16_t)0x0001) |
#define | BKP_CSR_CTI ((uint16_t)0x0002) |
#define | BKP_CSR_TEF ((uint16_t)0x0100) |
#define | BKP_CSR_TIF ((uint16_t)0x0200) |
#define | BKP_CSR_TPIE ((uint16_t)0x0004) |
#define | BKP_DR10_D ((uint16_t)0xFFFF) |
#define | BKP_DR11_D ((uint16_t)0xFFFF) |
#define | BKP_DR12_D ((uint16_t)0xFFFF) |
#define | BKP_DR13_D ((uint16_t)0xFFFF) |
#define | BKP_DR14_D ((uint16_t)0xFFFF) |
#define | BKP_DR15_D ((uint16_t)0xFFFF) |
#define | BKP_DR16_D ((uint16_t)0xFFFF) |
#define | BKP_DR17_D ((uint16_t)0xFFFF) |
#define | BKP_DR18_D ((uint16_t)0xFFFF) |
#define | BKP_DR19_D ((uint16_t)0xFFFF) |
#define | BKP_DR1_D ((uint16_t)0xFFFF) |
#define | BKP_DR20_D ((uint16_t)0xFFFF) |
#define | BKP_DR21_D ((uint16_t)0xFFFF) |
#define | BKP_DR22_D ((uint16_t)0xFFFF) |
#define | BKP_DR23_D ((uint16_t)0xFFFF) |
#define | BKP_DR24_D ((uint16_t)0xFFFF) |
#define | BKP_DR25_D ((uint16_t)0xFFFF) |
#define | BKP_DR26_D ((uint16_t)0xFFFF) |
#define | BKP_DR27_D ((uint16_t)0xFFFF) |
#define | BKP_DR28_D ((uint16_t)0xFFFF) |
#define | BKP_DR29_D ((uint16_t)0xFFFF) |
#define | BKP_DR2_D ((uint16_t)0xFFFF) |
#define | BKP_DR30_D ((uint16_t)0xFFFF) |
#define | BKP_DR31_D ((uint16_t)0xFFFF) |
#define | BKP_DR32_D ((uint16_t)0xFFFF) |
#define | BKP_DR33_D ((uint16_t)0xFFFF) |
#define | BKP_DR34_D ((uint16_t)0xFFFF) |
#define | BKP_DR35_D ((uint16_t)0xFFFF) |
#define | BKP_DR36_D ((uint16_t)0xFFFF) |
#define | BKP_DR37_D ((uint16_t)0xFFFF) |
#define | BKP_DR38_D ((uint16_t)0xFFFF) |
#define | BKP_DR39_D ((uint16_t)0xFFFF) |
#define | BKP_DR3_D ((uint16_t)0xFFFF) |
#define | BKP_DR40_D ((uint16_t)0xFFFF) |
#define | BKP_DR41_D ((uint16_t)0xFFFF) |
#define | BKP_DR42_D ((uint16_t)0xFFFF) |
#define | BKP_DR4_D ((uint16_t)0xFFFF) |
#define | BKP_DR5_D ((uint16_t)0xFFFF) |
#define | BKP_DR6_D ((uint16_t)0xFFFF) |
#define | BKP_DR7_D ((uint16_t)0xFFFF) |
#define | BKP_DR8_D ((uint16_t)0xFFFF) |
#define | BKP_DR9_D ((uint16_t)0xFFFF) |
#define | BKP_RTCCR_ASOE ((uint16_t)0x0100) |
#define | BKP_RTCCR_ASOS ((uint16_t)0x0200) |
#define | BKP_RTCCR_CAL ((uint16_t)0x007F) |
#define | BKP_RTCCR_CCO ((uint16_t)0x0080) |
#define | CAN1 ((CAN_TypeDef *) CAN1_BASE) |
#define | CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
#define | CAN2 ((CAN_TypeDef *) CAN2_BASE) |
#define | CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
#define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
#define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
#define | CAN_BTR_SILM ((uint32_t)0x80000000) |
#define | CAN_BTR_SJW ((uint32_t)0x03000000) |
#define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
#define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
#define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
#define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
#define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
#define | CAN_ESR_LEC ((uint32_t)0x00000070) |
#define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
#define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
#define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
#define | CAN_ESR_REC ((uint32_t)0xFF000000) |
#define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
#define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
#define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
#define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
#define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
#define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
#define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
#define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
#define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
#define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
#define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
#define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
#define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
#define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
#define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
#define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
#define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
#define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
#define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
#define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
#define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
#define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
#define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
#define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
#define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
#define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
#define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
#define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
#define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
#define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
#define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
#define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
#define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
#define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
#define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
#define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
#define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
#define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
#define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
#define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
#define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
#define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
#define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
#define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
#define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
#define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
#define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
#define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
#define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
#define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
#define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
#define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
#define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
#define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
#define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
#define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
#define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
#define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
#define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
#define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
#define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
#define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
#define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
#define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
#define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
#define | CAN_FA1R_FACT ((uint16_t)0x3FFF) |
#define | CAN_FA1R_FACT0 ((uint16_t)0x0001) |
#define | CAN_FA1R_FACT1 ((uint16_t)0x0002) |
#define | CAN_FA1R_FACT10 ((uint16_t)0x0400) |
#define | CAN_FA1R_FACT11 ((uint16_t)0x0800) |
#define | CAN_FA1R_FACT12 ((uint16_t)0x1000) |
#define | CAN_FA1R_FACT13 ((uint16_t)0x2000) |
#define | CAN_FA1R_FACT2 ((uint16_t)0x0004) |
#define | CAN_FA1R_FACT3 ((uint16_t)0x0008) |
#define | CAN_FA1R_FACT4 ((uint16_t)0x0010) |
#define | CAN_FA1R_FACT5 ((uint16_t)0x0020) |
#define | CAN_FA1R_FACT6 ((uint16_t)0x0040) |
#define | CAN_FA1R_FACT7 ((uint16_t)0x0080) |
#define | CAN_FA1R_FACT8 ((uint16_t)0x0100) |
#define | CAN_FA1R_FACT9 ((uint16_t)0x0200) |
#define | CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
#define | CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
#define | CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
#define | CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
#define | CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
#define | CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
#define | CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
#define | CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
#define | CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
#define | CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
#define | CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
#define | CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
#define | CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
#define | CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
#define | CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
#define | CAN_FM1R_FBM ((uint16_t)0x3FFF) |
#define | CAN_FM1R_FBM0 ((uint16_t)0x0001) |
#define | CAN_FM1R_FBM1 ((uint16_t)0x0002) |
#define | CAN_FM1R_FBM10 ((uint16_t)0x0400) |
#define | CAN_FM1R_FBM11 ((uint16_t)0x0800) |
#define | CAN_FM1R_FBM12 ((uint16_t)0x1000) |
#define | CAN_FM1R_FBM13 ((uint16_t)0x2000) |
#define | CAN_FM1R_FBM2 ((uint16_t)0x0004) |
#define | CAN_FM1R_FBM3 ((uint16_t)0x0008) |
#define | CAN_FM1R_FBM4 ((uint16_t)0x0010) |
#define | CAN_FM1R_FBM5 ((uint16_t)0x0020) |
#define | CAN_FM1R_FBM6 ((uint16_t)0x0040) |
#define | CAN_FM1R_FBM7 ((uint16_t)0x0080) |
#define | CAN_FM1R_FBM8 ((uint16_t)0x0100) |
#define | CAN_FM1R_FBM9 ((uint16_t)0x0200) |
#define | CAN_FMR_FINIT ((uint8_t)0x01) |
#define | CAN_FS1R_FSC ((uint16_t)0x3FFF) |
#define | CAN_FS1R_FSC0 ((uint16_t)0x0001) |
#define | CAN_FS1R_FSC1 ((uint16_t)0x0002) |
#define | CAN_FS1R_FSC10 ((uint16_t)0x0400) |
#define | CAN_FS1R_FSC11 ((uint16_t)0x0800) |
#define | CAN_FS1R_FSC12 ((uint16_t)0x1000) |
#define | CAN_FS1R_FSC13 ((uint16_t)0x2000) |
#define | CAN_FS1R_FSC2 ((uint16_t)0x0004) |
#define | CAN_FS1R_FSC3 ((uint16_t)0x0008) |
#define | CAN_FS1R_FSC4 ((uint16_t)0x0010) |
#define | CAN_FS1R_FSC5 ((uint16_t)0x0020) |
#define | CAN_FS1R_FSC6 ((uint16_t)0x0040) |
#define | CAN_FS1R_FSC7 ((uint16_t)0x0080) |
#define | CAN_FS1R_FSC8 ((uint16_t)0x0100) |
#define | CAN_FS1R_FSC9 ((uint16_t)0x0200) |
#define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
#define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
#define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
#define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
#define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
#define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
#define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
#define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
#define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
#define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
#define | CAN_IER_LECIE ((uint32_t)0x00000800) |
#define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
#define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
#define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
#define | CAN_MCR_ABOM ((uint16_t)0x0040) |
#define | CAN_MCR_AWUM ((uint16_t)0x0020) |
#define | CAN_MCR_INRQ ((uint16_t)0x0001) |
#define | CAN_MCR_NART ((uint16_t)0x0010) |
#define | CAN_MCR_RESET ((uint16_t)0x8000) |
#define | CAN_MCR_RFLM ((uint16_t)0x0008) |
#define | CAN_MCR_SLEEP ((uint16_t)0x0002) |
#define | CAN_MCR_TTCM ((uint16_t)0x0080) |
#define | CAN_MCR_TXFP ((uint16_t)0x0004) |
#define | CAN_MSR_ERRI ((uint16_t)0x0004) |
#define | CAN_MSR_INAK ((uint16_t)0x0001) |
#define | CAN_MSR_RX ((uint16_t)0x0800) |
#define | CAN_MSR_RXM ((uint16_t)0x0200) |
#define | CAN_MSR_SAMP ((uint16_t)0x0400) |
#define | CAN_MSR_SLAK ((uint16_t)0x0002) |
#define | CAN_MSR_SLAKI ((uint16_t)0x0010) |
#define | CAN_MSR_TXM ((uint16_t)0x0100) |
#define | CAN_MSR_WKUI ((uint16_t)0x0008) |
#define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
#define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
#define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
#define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
#define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
#define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
#define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
#define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
#define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
#define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
#define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
#define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
#define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
#define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
#define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
#define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
#define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
#define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
#define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
#define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
#define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
#define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
#define | CAN_RF0R_FMP0 ((uint8_t)0x03) |
#define | CAN_RF0R_FOVR0 ((uint8_t)0x10) |
#define | CAN_RF0R_FULL0 ((uint8_t)0x08) |
#define | CAN_RF0R_RFOM0 ((uint8_t)0x20) |
#define | CAN_RF1R_FMP1 ((uint8_t)0x03) |
#define | CAN_RF1R_FOVR1 ((uint8_t)0x10) |
#define | CAN_RF1R_FULL1 ((uint8_t)0x08) |
#define | CAN_RF1R_RFOM1 ((uint8_t)0x20) |
#define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
#define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
#define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
#define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
#define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
#define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
#define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
#define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
#define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
#define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
#define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
#define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
#define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
#define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
#define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
#define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
#define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
#define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
#define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
#define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
#define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
#define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
#define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
#define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
#define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
#define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
#define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
#define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
#define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
#define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
#define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
#define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
#define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
#define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
#define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
#define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
#define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
#define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
#define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
#define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
#define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
#define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
#define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
#define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
#define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
#define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
#define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
#define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
#define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
#define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
#define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
#define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
#define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
#define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
#define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
#define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
#define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
#define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
#define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
#define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
#define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
#define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
#define | CAN_TSR_CODE ((uint32_t)0x03000000) |
#define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
#define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
#define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
#define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
#define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
#define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
#define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
#define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
#define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
#define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
#define | CAN_TSR_TME ((uint32_t)0x1C000000) |
#define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
#define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
#define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
#define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
#define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
#define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
#define | CEC ((CEC_TypeDef *) CEC_BASE) |
#define | CEC_BASE (APB1PERIPH_BASE + 0x7800) |
#define | CEC_CFGR_BPEM ((uint16_t)0x0008) |
#define | CEC_CFGR_BTEM ((uint16_t)0x0004) |
#define | CEC_CFGR_IE ((uint16_t)0x0002) |
#define | CEC_CFGR_PE ((uint16_t)0x0001) |
#define | CEC_CSR_RBTF ((uint16_t)0x0080) |
#define | CEC_CSR_REOM ((uint16_t)0x0020) |
#define | CEC_CSR_RERR ((uint16_t)0x0040) |
#define | CEC_CSR_RSOM ((uint16_t)0x0010) |
#define | CEC_CSR_TBTRF ((uint16_t)0x0008) |
#define | CEC_CSR_TEOM ((uint16_t)0x0002) |
#define | CEC_CSR_TERR ((uint16_t)0x0004) |
#define | CEC_CSR_TSOM ((uint16_t)0x0001) |
#define | CEC_ESR_ACKE ((uint16_t)0x0010) |
#define | CEC_ESR_BPE ((uint16_t)0x0002) |
#define | CEC_ESR_BTE ((uint16_t)0x0001) |
#define | CEC_ESR_LINE ((uint16_t)0x0020) |
#define | CEC_ESR_RBTFE ((uint16_t)0x0004) |
#define | CEC_ESR_SBE ((uint16_t)0x0008) |
#define | CEC_ESR_TBTFE ((uint16_t)0x0040) |
#define | CEC_OAR_OA ((uint16_t)0x000F) |
#define | CEC_OAR_OA_0 ((uint16_t)0x0001) |
#define | CEC_OAR_OA_1 ((uint16_t)0x0002) |
#define | CEC_OAR_OA_2 ((uint16_t)0x0004) |
#define | CEC_OAR_OA_3 ((uint16_t)0x0008) |
#define | CEC_PRES_PRES ((uint16_t)0x3FFF) |
#define | CEC_RXD_RXD ((uint16_t)0x00FF) |
#define | CEC_TXD_TXD ((uint16_t)0x00FF) |
#define | CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
#define | CLEAR_REG(REG) ((REG) = (0x0)) |
#define | CRC ((CRC_TypeDef *) CRC_BASE) |
#define | CRC_BASE (AHBPERIPH_BASE + 0x3000) |
#define | CRC_CR_RESET ((uint8_t)0x01) |
#define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
#define | CRC_IDR_IDR ((uint8_t)0xFF) |
#define | DAC ((DAC_TypeDef *) DAC_BASE) |
#define | DAC_BASE (APB1PERIPH_BASE + 0x7400) |
#define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
#define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
#define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
#define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
#define | DAC_CR_EN1 ((uint32_t)0x00000001) |
#define | DAC_CR_EN2 ((uint32_t)0x00010000) |
#define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
#define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
#define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
#define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
#define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
#define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
#define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
#define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
#define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
#define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
#define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
#define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
#define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
#define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
#define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
#define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
#define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
#define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
#define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
#define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
#define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
#define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
#define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
#define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
#define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
#define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
#define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
#define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
#define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
#define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
#define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
#define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
#define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
#define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
#define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
#define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
#define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
#define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
#define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
#define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
#define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
#define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
#define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
#define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
#define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
#define | DBGMCU_BASE ((uint32_t)0xE0042000) |
#define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) |
#define | DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) |
#define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
#define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
#define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
#define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
#define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
#define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
#define | DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) |
#define | DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) |
#define | DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) |
#define | DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) |
#define | DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) |
#define | DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) |
#define | DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) |
#define | DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) |
#define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
#define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
#define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
#define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
#define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
#define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
#define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
#define | DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) |
#define | DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) |
#define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
#define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
#define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
#define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
#define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
#define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
#define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
#define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
#define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
#define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
#define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
#define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
#define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
#define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
#define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
#define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
#define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
#define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
#define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
#define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
#define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
#define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
#define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
#define | DMA1 ((DMA_TypeDef *) DMA1_BASE) |
#define | DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
#define | DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
#define | DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
#define | DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
#define | DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
#define | DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
#define | DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
#define | DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
#define | DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
#define | DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
#define | DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
#define | DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
#define | DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
#define | DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
#define | DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
#define | DMA2 ((DMA_TypeDef *) DMA2_BASE) |
#define | DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
#define | DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
#define | DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
#define | DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
#define | DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
#define | DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
#define | DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
#define | DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
#define | DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
#define | DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
#define | DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
#define | DMA_CCR1_CIRC ((uint16_t)0x0020) |
#define | DMA_CCR1_DIR ((uint16_t)0x0010) |
#define | DMA_CCR1_EN ((uint16_t)0x0001) |
#define | DMA_CCR1_HTIE ((uint16_t)0x0004) |
#define | DMA_CCR1_MEM2MEM ((uint16_t)0x4000) |
#define | DMA_CCR1_MINC ((uint16_t)0x0080) |
#define | DMA_CCR1_MSIZE ((uint16_t)0x0C00) |
#define | DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) |
#define | DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) |
#define | DMA_CCR1_PINC ((uint16_t)0x0040) |
#define | DMA_CCR1_PL ((uint16_t)0x3000) |
#define | DMA_CCR1_PL_0 ((uint16_t)0x1000) |
#define | DMA_CCR1_PL_1 ((uint16_t)0x2000) |
#define | DMA_CCR1_PSIZE ((uint16_t)0x0300) |
#define | DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) |
#define | DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) |
#define | DMA_CCR1_TCIE ((uint16_t)0x0002) |
#define | DMA_CCR1_TEIE ((uint16_t)0x0008) |
#define | DMA_CCR2_CIRC ((uint16_t)0x0020) |
#define | DMA_CCR2_DIR ((uint16_t)0x0010) |
#define | DMA_CCR2_EN ((uint16_t)0x0001) |
#define | DMA_CCR2_HTIE ((uint16_t)0x0004) |
#define | DMA_CCR2_MEM2MEM ((uint16_t)0x4000) |
#define | DMA_CCR2_MINC ((uint16_t)0x0080) |
#define | DMA_CCR2_MSIZE ((uint16_t)0x0C00) |
#define | DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) |
#define | DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) |
#define | DMA_CCR2_PINC ((uint16_t)0x0040) |
#define | DMA_CCR2_PL ((uint16_t)0x3000) |
#define | DMA_CCR2_PL_0 ((uint16_t)0x1000) |
#define | DMA_CCR2_PL_1 ((uint16_t)0x2000) |
#define | DMA_CCR2_PSIZE ((uint16_t)0x0300) |
#define | DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) |
#define | DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) |
#define | DMA_CCR2_TCIE ((uint16_t)0x0002) |
#define | DMA_CCR2_TEIE ((uint16_t)0x0008) |
#define | DMA_CCR3_CIRC ((uint16_t)0x0020) |
#define | DMA_CCR3_DIR ((uint16_t)0x0010) |
#define | DMA_CCR3_EN ((uint16_t)0x0001) |
#define | DMA_CCR3_HTIE ((uint16_t)0x0004) |
#define | DMA_CCR3_MEM2MEM ((uint16_t)0x4000) |
#define | DMA_CCR3_MINC ((uint16_t)0x0080) |
#define | DMA_CCR3_MSIZE ((uint16_t)0x0C00) |
#define | DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) |
#define | DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) |
#define | DMA_CCR3_PINC ((uint16_t)0x0040) |
#define | DMA_CCR3_PL ((uint16_t)0x3000) |
#define | DMA_CCR3_PL_0 ((uint16_t)0x1000) |
#define | DMA_CCR3_PL_1 ((uint16_t)0x2000) |
#define | DMA_CCR3_PSIZE ((uint16_t)0x0300) |
#define | DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) |
#define | DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) |
#define | DMA_CCR3_TCIE ((uint16_t)0x0002) |
#define | DMA_CCR3_TEIE ((uint16_t)0x0008) |
#define | DMA_CCR4_CIRC ((uint16_t)0x0020) |
#define | DMA_CCR4_DIR ((uint16_t)0x0010) |
#define | DMA_CCR4_EN ((uint16_t)0x0001) |
#define | DMA_CCR4_HTIE ((uint16_t)0x0004) |
#define | DMA_CCR4_MEM2MEM ((uint16_t)0x4000) |
#define | DMA_CCR4_MINC ((uint16_t)0x0080) |
#define | DMA_CCR4_MSIZE ((uint16_t)0x0C00) |
#define | DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) |
#define | DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) |
#define | DMA_CCR4_PINC ((uint16_t)0x0040) |
#define | DMA_CCR4_PL ((uint16_t)0x3000) |
#define | DMA_CCR4_PL_0 ((uint16_t)0x1000) |
#define | DMA_CCR4_PL_1 ((uint16_t)0x2000) |
#define | DMA_CCR4_PSIZE ((uint16_t)0x0300) |
#define | DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) |
#define | DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) |
#define | DMA_CCR4_TCIE ((uint16_t)0x0002) |
#define | DMA_CCR4_TEIE ((uint16_t)0x0008) |
#define | DMA_CCR5_CIRC ((uint16_t)0x0020) |
#define | DMA_CCR5_DIR ((uint16_t)0x0010) |
#define | DMA_CCR5_EN ((uint16_t)0x0001) |
#define | DMA_CCR5_HTIE ((uint16_t)0x0004) |
#define | DMA_CCR5_MEM2MEM ((uint16_t)0x4000) |
#define | DMA_CCR5_MINC ((uint16_t)0x0080) |
#define | DMA_CCR5_MSIZE ((uint16_t)0x0C00) |
#define | DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) |
#define | DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) |
#define | DMA_CCR5_PINC ((uint16_t)0x0040) |
#define | DMA_CCR5_PL ((uint16_t)0x3000) |
#define | DMA_CCR5_PL_0 ((uint16_t)0x1000) |
#define | DMA_CCR5_PL_1 ((uint16_t)0x2000) |
#define | DMA_CCR5_PSIZE ((uint16_t)0x0300) |
#define | DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) |
#define | DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) |
#define | DMA_CCR5_TCIE ((uint16_t)0x0002) |
#define | DMA_CCR5_TEIE ((uint16_t)0x0008) |
#define | DMA_CCR6_CIRC ((uint16_t)0x0020) |
#define | DMA_CCR6_DIR ((uint16_t)0x0010) |
#define | DMA_CCR6_EN ((uint16_t)0x0001) |
#define | DMA_CCR6_HTIE ((uint16_t)0x0004) |
#define | DMA_CCR6_MEM2MEM ((uint16_t)0x4000) |
#define | DMA_CCR6_MINC ((uint16_t)0x0080) |
#define | DMA_CCR6_MSIZE ((uint16_t)0x0C00) |
#define | DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) |
#define | DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) |
#define | DMA_CCR6_PINC ((uint16_t)0x0040) |
#define | DMA_CCR6_PL ((uint16_t)0x3000) |
#define | DMA_CCR6_PL_0 ((uint16_t)0x1000) |
#define | DMA_CCR6_PL_1 ((uint16_t)0x2000) |
#define | DMA_CCR6_PSIZE ((uint16_t)0x0300) |
#define | DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) |
#define | DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) |
#define | DMA_CCR6_TCIE ((uint16_t)0x0002) |
#define | DMA_CCR6_TEIE ((uint16_t)0x0008) |
#define | DMA_CCR7_CIRC ((uint16_t)0x0020) |
#define | DMA_CCR7_DIR ((uint16_t)0x0010) |
#define | DMA_CCR7_EN ((uint16_t)0x0001) |
#define | DMA_CCR7_HTIE ((uint16_t)0x0004) |
#define | DMA_CCR7_MEM2MEM ((uint16_t)0x4000) |
#define | DMA_CCR7_MINC ((uint16_t)0x0080) |
#define | DMA_CCR7_MSIZE ((uint16_t)0x0C00) |
#define | DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) |
#define | DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) |
#define | DMA_CCR7_PINC ((uint16_t)0x0040) |
#define | DMA_CCR7_PL ((uint16_t)0x3000) |
#define | DMA_CCR7_PL_0 ((uint16_t)0x1000) |
#define | DMA_CCR7_PL_1 ((uint16_t)0x2000) |
#define | DMA_CCR7_PSIZE , ((uint16_t)0x0300) |
#define | DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) |
#define | DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) |
#define | DMA_CCR7_TCIE ((uint16_t)0x0002) |
#define | DMA_CCR7_TEIE ((uint16_t)0x0008) |
#define | DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CNDTR1_NDT ((uint16_t)0xFFFF) |
#define | DMA_CNDTR2_NDT ((uint16_t)0xFFFF) |
#define | DMA_CNDTR3_NDT ((uint16_t)0xFFFF) |
#define | DMA_CNDTR4_NDT ((uint16_t)0xFFFF) |
#define | DMA_CNDTR5_NDT ((uint16_t)0xFFFF) |
#define | DMA_CNDTR6_NDT ((uint16_t)0xFFFF) |
#define | DMA_CNDTR7_NDT ((uint16_t)0xFFFF) |
#define | DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) |
#define | DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) |
#define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
#define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
#define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
#define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
#define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
#define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
#define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
#define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
#define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
#define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
#define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
#define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
#define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
#define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
#define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
#define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
#define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
#define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
#define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
#define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
#define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
#define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
#define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
#define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
#define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
#define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
#define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
#define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
#define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
#define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
#define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
#define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
#define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
#define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
#define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
#define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
#define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
#define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
#define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
#define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
#define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
#define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
#define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
#define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
#define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
#define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
#define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
#define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
#define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
#define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
#define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
#define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
#define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
#define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
#define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
#define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
#define | ETH ((ETH_TypeDef *) ETH_BASE) |
#define | ETH_BASE (AHBPERIPH_BASE + 0x8000) |
#define | ETH_DMA_BASE (ETH_BASE + 0x1000) |
#define | ETH_MAC_BASE (ETH_BASE) |
#define | ETH_MMC_BASE (ETH_BASE + 0x0100) |
#define | ETH_PTP_BASE (ETH_BASE + 0x0700) |
#define | EXTI ((EXTI_TypeDef *) EXTI_BASE) |
#define | EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
#define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
#define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
#define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
#define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
#define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
#define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
#define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
#define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
#define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
#define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
#define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
#define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
#define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
#define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
#define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
#define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
#define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
#define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
#define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
#define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
#define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
#define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
#define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
#define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
#define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
#define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
#define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
#define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
#define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
#define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
#define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
#define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
#define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
#define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
#define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
#define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
#define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
#define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
#define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
#define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
#define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
#define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
#define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
#define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
#define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
#define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
#define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
#define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
#define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
#define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
#define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
#define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
#define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
#define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
#define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
#define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
#define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
#define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
#define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
#define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
#define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
#define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
#define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
#define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
#define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
#define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
#define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
#define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
#define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
#define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
#define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
#define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
#define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
#define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
#define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
#define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
#define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
#define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
#define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
#define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
#define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
#define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
#define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
#define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
#define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
#define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
#define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
#define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
#define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
#define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
#define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
#define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
#define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
#define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
#define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
#define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
#define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
#define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
#define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
#define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
#define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
#define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
#define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
#define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
#define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
#define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
#define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
#define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
#define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
#define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
#define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
#define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
#define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
#define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
#define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
#define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
#define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
#define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
#define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
#define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
#define | FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
#define | FLASH_ACR_HLFCYA ((uint8_t)0x08) |
#define | FLASH_ACR_LATENCY ((uint8_t)0x03) |
#define | FLASH_ACR_LATENCY_0 ((uint8_t)0x00) |
#define | FLASH_ACR_LATENCY_1 ((uint8_t)0x01) |
#define | FLASH_ACR_LATENCY_2 ((uint8_t)0x02) |
#define | FLASH_ACR_PRFTBE ((uint8_t)0x10) |
#define | FLASH_ACR_PRFTBS ((uint8_t)0x20) |
#define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
#define | FLASH_BASE ((uint32_t)0x08000000) |
#define | FLASH_CR_EOPIE ((uint16_t)0x1000) |
#define | FLASH_CR_ERRIE ((uint16_t)0x0400) |
#define | FLASH_CR_LOCK ((uint16_t)0x0080) |
#define | FLASH_CR_MER ((uint16_t)0x0004) |
#define | FLASH_CR_OPTER ((uint16_t)0x0020) |
#define | FLASH_CR_OPTPG ((uint16_t)0x0010) |
#define | FLASH_CR_OPTWRE ((uint16_t)0x0200) |
#define | FLASH_CR_PER ((uint16_t)0x0002) |
#define | FLASH_CR_PG ((uint16_t)0x0001) |
#define | FLASH_CR_STRT ((uint16_t)0x0040) |
#define | FLASH_Data0_Data0 ((uint32_t)0x000000FF) |
#define | FLASH_Data0_nData0 ((uint32_t)0x0000FF00) |
#define | FLASH_Data1_Data1 ((uint32_t)0x00FF0000) |
#define | FLASH_Data1_nData1 ((uint32_t)0xFF000000) |
#define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
#define | FLASH_OBR_BFB2 ((uint16_t)0x0020) |
#define | FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) |
#define | FLASH_OBR_nRST_STOP ((uint16_t)0x0008) |
#define | FLASH_OBR_OPTERR ((uint16_t)0x0001) |
#define | FLASH_OBR_RDPRT ((uint16_t)0x0002) |
#define | FLASH_OBR_USER ((uint16_t)0x03FC) |
#define | FLASH_OBR_WDG_SW ((uint16_t)0x0004) |
#define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
#define | FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) |
#define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
#define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
#define | FLASH_SR_BSY ((uint8_t)0x01) |
#define | FLASH_SR_EOP ((uint8_t)0x20) |
#define | FLASH_SR_PGERR ((uint8_t)0x04) |
#define | FLASH_SR_WRPRTERR ((uint8_t)0x10) |
#define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
#define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
#define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
#define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
#define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
#define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
#define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
#define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
#define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
#define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
#define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
#define | FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) |
#define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
#define | FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) |
#define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
#define | FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) |
#define | FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
#define | FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) |
#define | FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
#define | FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) |
#define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
#define | FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) |
#define | FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) |
#define | FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) |
#define | FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) |
#define | FSMC_BCR1_FACCEN ((uint32_t)0x00000040) |
#define | FSMC_BCR1_MBKEN ((uint32_t)0x00000001) |
#define | FSMC_BCR1_MTYP ((uint32_t)0x0000000C) |
#define | FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) |
#define | FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) |
#define | FSMC_BCR1_MUXEN ((uint32_t)0x00000002) |
#define | FSMC_BCR1_MWID ((uint32_t)0x00000030) |
#define | FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) |
#define | FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) |
#define | FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) |
#define | FSMC_BCR1_WAITEN ((uint32_t)0x00002000) |
#define | FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) |
#define | FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) |
#define | FSMC_BCR1_WREN ((uint32_t)0x00001000) |
#define | FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) |
#define | FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) |
#define | FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) |
#define | FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) |
#define | FSMC_BCR2_FACCEN ((uint32_t)0x00000040) |
#define | FSMC_BCR2_MBKEN ((uint32_t)0x00000001) |
#define | FSMC_BCR2_MTYP ((uint32_t)0x0000000C) |
#define | FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) |
#define | FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) |
#define | FSMC_BCR2_MUXEN ((uint32_t)0x00000002) |
#define | FSMC_BCR2_MWID ((uint32_t)0x00000030) |
#define | FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) |
#define | FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) |
#define | FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) |
#define | FSMC_BCR2_WAITEN ((uint32_t)0x00002000) |
#define | FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) |
#define | FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) |
#define | FSMC_BCR2_WREN ((uint32_t)0x00001000) |
#define | FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) |
#define | FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) |
#define | FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) |
#define | FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) |
#define | FSMC_BCR3_FACCEN ((uint32_t)0x00000040) |
#define | FSMC_BCR3_MBKEN ((uint32_t)0x00000001) |
#define | FSMC_BCR3_MTYP ((uint32_t)0x0000000C) |
#define | FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) |
#define | FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) |
#define | FSMC_BCR3_MUXEN ((uint32_t)0x00000002) |
#define | FSMC_BCR3_MWID ((uint32_t)0x00000030) |
#define | FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) |
#define | FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) |
#define | FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) |
#define | FSMC_BCR3_WAITEN ((uint32_t)0x00002000) |
#define | FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) |
#define | FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) |
#define | FSMC_BCR3_WREN ((uint32_t)0x00001000) |
#define | FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) |
#define | FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) |
#define | FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) |
#define | FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) |
#define | FSMC_BCR4_FACCEN ((uint32_t)0x00000040) |
#define | FSMC_BCR4_MBKEN ((uint32_t)0x00000001) |
#define | FSMC_BCR4_MTYP ((uint32_t)0x0000000C) |
#define | FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) |
#define | FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) |
#define | FSMC_BCR4_MUXEN ((uint32_t)0x00000002) |
#define | FSMC_BCR4_MWID ((uint32_t)0x00000030) |
#define | FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) |
#define | FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) |
#define | FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) |
#define | FSMC_BCR4_WAITEN ((uint32_t)0x00002000) |
#define | FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) |
#define | FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) |
#define | FSMC_BCR4_WREN ((uint32_t)0x00001000) |
#define | FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) |
#define | FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) |
#define | FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) |
#define | FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) |
#define | FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) |
#define | FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) |
#define | FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) |
#define | FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) |
#define | FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) |
#define | FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) |
#define | FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) |
#define | FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) |
#define | FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) |
#define | FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) |
#define | FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) |
#define | FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) |
#define | FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) |
#define | FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) |
#define | FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) |
#define | FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) |
#define | FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) |
#define | FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) |
#define | FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) |
#define | FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) |
#define | FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) |
#define | FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) |
#define | FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) |
#define | FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) |
#define | FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) |
#define | FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) |
#define | FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) |
#define | FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) |
#define | FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) |
#define | FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) |
#define | FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) |
#define | FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) |
#define | FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) |
#define | FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) |
#define | FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) |
#define | FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) |
#define | FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) |
#define | FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) |
#define | FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) |
#define | FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) |
#define | FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) |
#define | FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) |
#define | FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) |
#define | FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) |
#define | FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) |
#define | FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) |
#define | FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) |
#define | FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) |
#define | FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) |
#define | FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) |
#define | FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) |
#define | FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) |
#define | FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) |
#define | FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) |
#define | FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) |
#define | FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) |
#define | FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) |
#define | FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) |
#define | FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) |
#define | FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) |
#define | FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) |
#define | FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) |
#define | FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) |
#define | FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) |
#define | FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) |
#define | FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) |
#define | FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) |
#define | FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) |
#define | FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) |
#define | FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) |
#define | FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) |
#define | FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) |
#define | FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) |
#define | FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) |
#define | FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) |
#define | FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) |
#define | FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) |
#define | FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) |
#define | FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) |
#define | FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) |
#define | FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) |
#define | FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) |
#define | FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) |
#define | FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) |
#define | FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) |
#define | FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) |
#define | FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) |
#define | FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) |
#define | FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) |
#define | FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) |
#define | FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) |
#define | FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) |
#define | FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) |
#define | FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) |
#define | FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) |
#define | FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) |
#define | FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) |
#define | FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) |
#define | FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) |
#define | FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) |
#define | FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) |
#define | FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) |
#define | FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) |
#define | FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) |
#define | FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) |
#define | FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) |
#define | FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) |
#define | FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) |
#define | FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) |
#define | FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) |
#define | FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) |
#define | FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) |
#define | FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) |
#define | FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) |
#define | FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) |
#define | FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) |
#define | FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) |
#define | FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) |
#define | FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) |
#define | FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) |
#define | FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) |
#define | FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) |
#define | FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) |
#define | FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) |
#define | FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) |
#define | FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) |
#define | FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) |
#define | FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) |
#define | FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) |
#define | FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) |
#define | FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) |
#define | FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) |
#define | FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) |
#define | FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) |
#define | FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) |
#define | FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) |
#define | FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) |
#define | FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) |
#define | FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) |
#define | FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) |
#define | FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) |
#define | FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) |
#define | FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) |
#define | FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) |
#define | FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) |
#define | FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) |
#define | FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) |
#define | FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) |
#define | FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) |
#define | FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) |
#define | FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) |
#define | FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) |
#define | FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) |
#define | FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) |
#define | FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) |
#define | FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) |
#define | FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) |
#define | FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) |
#define | FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) |
#define | FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) |
#define | FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) |
#define | FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) |
#define | FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) |
#define | FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) |
#define | FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) |
#define | FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) |
#define | FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) |
#define | FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) |
#define | FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) |
#define | FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) |
#define | FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) |
#define | FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) |
#define | FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) |
#define | FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) |
#define | FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) |
#define | FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) |
#define | FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) |
#define | FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) |
#define | FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) |
#define | FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) |
#define | FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) |
#define | FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) |
#define | FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) |
#define | FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) |
#define | FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) |
#define | FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) |
#define | FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) |
#define | FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) |
#define | FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) |
#define | FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) |
#define | FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) |
#define | FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) |
#define | FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) |
#define | FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) |
#define | FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) |
#define | FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) |
#define | FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) |
#define | FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) |
#define | FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) |
#define | FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) |
#define | FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) |
#define | FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) |
#define | FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) |
#define | FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) |
#define | FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) |
#define | FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) |
#define | FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) |
#define | FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) |
#define | FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) |
#define | FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) |
#define | FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) |
#define | FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) |
#define | FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) |
#define | FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) |
#define | FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) |
#define | FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) |
#define | FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) |
#define | FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) |
#define | FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) |
#define | FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) |
#define | FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) |
#define | FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) |
#define | FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) |
#define | FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) |
#define | FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) |
#define | FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) |
#define | FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) |
#define | FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) |
#define | FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) |
#define | FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) |
#define | FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) |
#define | FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) |
#define | FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) |
#define | FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) |
#define | FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) |
#define | FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) |
#define | FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) |
#define | FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) |
#define | FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) |
#define | FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) |
#define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
#define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
#define | FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) |
#define | FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) |
#define | FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) |
#define | FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) |
#define | FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) |
#define | FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) |
#define | FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) |
#define | FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) |
#define | FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) |
#define | FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) |
#define | FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) |
#define | FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) |
#define | FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) |
#define | FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) |
#define | FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) |
#define | FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) |
#define | FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) |
#define | FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) |
#define | FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) |
#define | FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) |
#define | FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) |
#define | FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) |
#define | FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) |
#define | FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) |
#define | FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) |
#define | FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) |
#define | FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) |
#define | FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) |
#define | FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) |
#define | FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) |
#define | FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) |
#define | FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) |
#define | FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) |
#define | FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) |
#define | FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) |
#define | FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) |
#define | FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) |
#define | FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) |
#define | FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) |
#define | FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) |
#define | FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) |
#define | FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) |
#define | FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) |
#define | FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) |
#define | FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) |
#define | FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) |
#define | FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) |
#define | FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) |
#define | FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) |
#define | FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) |
#define | FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) |
#define | FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) |
#define | FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) |
#define | FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) |
#define | FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) |
#define | FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) |
#define | FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) |
#define | FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) |
#define | FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) |
#define | FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) |
#define | FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) |
#define | FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) |
#define | FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) |
#define | FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) |
#define | FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) |
#define | FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) |
#define | FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) |
#define | FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) |
#define | FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) |
#define | FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) |
#define | FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) |
#define | FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) |
#define | FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) |
#define | FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) |
#define | FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) |
#define | FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) |
#define | FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) |
#define | FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) |
#define | FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) |
#define | FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) |
#define | FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) |
#define | FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) |
#define | FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) |
#define | FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) |
#define | FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) |
#define | FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) |
#define | FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) |
#define | FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) |
#define | FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) |
#define | FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) |
#define | FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) |
#define | FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) |
#define | FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) |
#define | FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) |
#define | FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) |
#define | FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) |
#define | FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) |
#define | FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) |
#define | FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) |
#define | FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) |
#define | FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) |
#define | FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) |
#define | FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) |
#define | FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) |
#define | FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) |
#define | FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) |
#define | FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) |
#define | FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) |
#define | FSMC_PCR2_ECCEN ((uint32_t)0x00000040) |
#define | FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) |
#define | FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) |
#define | FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) |
#define | FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) |
#define | FSMC_PCR2_PBKEN ((uint32_t)0x00000004) |
#define | FSMC_PCR2_PTYP ((uint32_t)0x00000008) |
#define | FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) |
#define | FSMC_PCR2_PWID ((uint32_t)0x00000030) |
#define | FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) |
#define | FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) |
#define | FSMC_PCR2_TAR ((uint32_t)0x0001E000) |
#define | FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) |
#define | FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) |
#define | FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) |
#define | FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) |
#define | FSMC_PCR2_TCLR ((uint32_t)0x00001E00) |
#define | FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) |
#define | FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) |
#define | FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) |
#define | FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) |
#define | FSMC_PCR3_ECCEN ((uint32_t)0x00000040) |
#define | FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) |
#define | FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) |
#define | FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) |
#define | FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) |
#define | FSMC_PCR3_PBKEN ((uint32_t)0x00000004) |
#define | FSMC_PCR3_PTYP ((uint32_t)0x00000008) |
#define | FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) |
#define | FSMC_PCR3_PWID ((uint32_t)0x00000030) |
#define | FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) |
#define | FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) |
#define | FSMC_PCR3_TAR ((uint32_t)0x0001E000) |
#define | FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) |
#define | FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) |
#define | FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) |
#define | FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) |
#define | FSMC_PCR3_TCLR ((uint32_t)0x00001E00) |
#define | FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) |
#define | FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) |
#define | FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) |
#define | FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) |
#define | FSMC_PCR4_ECCEN ((uint32_t)0x00000040) |
#define | FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) |
#define | FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) |
#define | FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) |
#define | FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) |
#define | FSMC_PCR4_PBKEN ((uint32_t)0x00000004) |
#define | FSMC_PCR4_PTYP ((uint32_t)0x00000008) |
#define | FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) |
#define | FSMC_PCR4_PWID ((uint32_t)0x00000030) |
#define | FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) |
#define | FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) |
#define | FSMC_PCR4_TAR ((uint32_t)0x0001E000) |
#define | FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) |
#define | FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) |
#define | FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) |
#define | FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) |
#define | FSMC_PCR4_TCLR ((uint32_t)0x00001E00) |
#define | FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) |
#define | FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) |
#define | FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) |
#define | FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) |
#define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
#define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
#define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
#define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
#define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
#define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
#define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
#define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
#define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
#define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
#define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
#define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
#define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
#define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
#define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
#define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
#define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
#define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
#define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
#define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
#define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
#define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
#define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
#define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
#define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
#define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
#define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
#define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
#define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
#define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
#define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
#define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
#define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
#define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
#define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
#define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
#define | FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) |
#define | FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) |
#define | FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) |
#define | FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) |
#define | FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) |
#define | FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) |
#define | FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) |
#define | FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) |
#define | FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) |
#define | FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) |
#define | FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) |
#define | FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) |
#define | FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) |
#define | FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) |
#define | FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) |
#define | FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) |
#define | FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) |
#define | FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) |
#define | FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) |
#define | FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) |
#define | FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) |
#define | FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) |
#define | FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) |
#define | FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) |
#define | FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) |
#define | FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) |
#define | FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) |
#define | FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) |
#define | FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) |
#define | FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) |
#define | FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) |
#define | FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) |
#define | FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) |
#define | FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) |
#define | FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) |
#define | FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) |
#define | FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) |
#define | FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) |
#define | FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) |
#define | FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) |
#define | FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) |
#define | FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) |
#define | FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) |
#define | FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) |
#define | FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) |
#define | FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) |
#define | FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) |
#define | FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) |
#define | FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) |
#define | FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) |
#define | FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) |
#define | FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) |
#define | FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) |
#define | FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) |
#define | FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) |
#define | FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) |
#define | FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) |
#define | FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) |
#define | FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) |
#define | FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) |
#define | FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) |
#define | FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) |
#define | FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) |
#define | FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) |
#define | FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) |
#define | FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) |
#define | FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) |
#define | FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) |
#define | FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) |
#define | FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) |
#define | FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) |
#define | FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) |
#define | FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) |
#define | FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) |
#define | FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) |
#define | FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) |
#define | FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) |
#define | FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) |
#define | FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) |
#define | FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) |
#define | FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) |
#define | FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) |
#define | FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) |
#define | FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) |
#define | FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) |
#define | FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) |
#define | FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) |
#define | FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) |
#define | FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) |
#define | FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) |
#define | FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) |
#define | FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) |
#define | FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) |
#define | FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) |
#define | FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) |
#define | FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) |
#define | FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) |
#define | FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) |
#define | FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) |
#define | FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) |
#define | FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) |
#define | FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) |
#define | FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) |
#define | FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) |
#define | FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) |
#define | FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) |
#define | FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) |
#define | FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) |
#define | FSMC_R_BASE ((uint32_t)0xA0000000) |
#define | FSMC_SR2_FEMPT ((uint8_t)0x40) |
#define | FSMC_SR2_IFEN ((uint8_t)0x20) |
#define | FSMC_SR2_IFS ((uint8_t)0x04) |
#define | FSMC_SR2_ILEN ((uint8_t)0x10) |
#define | FSMC_SR2_ILS ((uint8_t)0x02) |
#define | FSMC_SR2_IREN ((uint8_t)0x08) |
#define | FSMC_SR2_IRS ((uint8_t)0x01) |
#define | FSMC_SR3_FEMPT ((uint8_t)0x40) |
#define | FSMC_SR3_IFEN ((uint8_t)0x20) |
#define | FSMC_SR3_IFS ((uint8_t)0x04) |
#define | FSMC_SR3_ILEN ((uint8_t)0x10) |
#define | FSMC_SR3_ILS ((uint8_t)0x02) |
#define | FSMC_SR3_IREN ((uint8_t)0x08) |
#define | FSMC_SR3_IRS ((uint8_t)0x01) |
#define | FSMC_SR4_FEMPT ((uint8_t)0x40) |
#define | FSMC_SR4_IFEN ((uint8_t)0x20) |
#define | FSMC_SR4_IFS ((uint8_t)0x04) |
#define | FSMC_SR4_ILEN ((uint8_t)0x10) |
#define | FSMC_SR4_ILS ((uint8_t)0x02) |
#define | FSMC_SR4_IREN ((uint8_t)0x08) |
#define | FSMC_SR4_IRS ((uint8_t)0x01) |
#define | GPIO_BRR_BR0 ((uint16_t)0x0001) |
#define | GPIO_BRR_BR1 ((uint16_t)0x0002) |
#define | GPIO_BRR_BR10 ((uint16_t)0x0400) |
#define | GPIO_BRR_BR11 ((uint16_t)0x0800) |
#define | GPIO_BRR_BR12 ((uint16_t)0x1000) |
#define | GPIO_BRR_BR13 ((uint16_t)0x2000) |
#define | GPIO_BRR_BR14 ((uint16_t)0x4000) |
#define | GPIO_BRR_BR15 ((uint16_t)0x8000) |
#define | GPIO_BRR_BR2 ((uint16_t)0x0004) |
#define | GPIO_BRR_BR3 ((uint16_t)0x0008) |
#define | GPIO_BRR_BR4 ((uint16_t)0x0010) |
#define | GPIO_BRR_BR5 ((uint16_t)0x0020) |
#define | GPIO_BRR_BR6 ((uint16_t)0x0040) |
#define | GPIO_BRR_BR7 ((uint16_t)0x0080) |
#define | GPIO_BRR_BR8 ((uint16_t)0x0100) |
#define | GPIO_BRR_BR9 ((uint16_t)0x0200) |
#define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
#define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
#define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
#define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
#define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
#define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
#define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
#define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
#define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
#define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
#define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
#define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
#define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
#define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
#define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
#define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
#define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
#define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
#define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
#define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
#define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
#define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
#define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
#define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
#define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
#define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
#define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
#define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
#define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
#define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
#define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
#define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
#define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
#define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
#define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
#define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
#define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
#define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
#define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
#define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
#define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
#define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
#define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
#define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
#define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
#define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
#define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
#define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
#define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
#define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
#define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
#define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
#define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
#define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
#define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
#define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
#define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
#define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
#define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
#define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
#define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
#define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
#define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
#define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
#define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
#define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
#define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
#define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
#define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
#define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
#define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
#define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
#define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
#define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
#define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
#define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
#define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
#define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
#define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
#define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
#define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
#define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
#define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
#define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
#define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
#define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
#define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
#define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
#define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
#define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
#define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
#define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
#define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
#define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
#define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
#define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
#define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
#define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
#define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
#define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
#define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
#define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
#define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
#define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
#define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
#define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
#define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
#define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
#define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
#define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
#define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
#define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
#define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
#define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
#define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
#define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
#define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
#define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
#define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
#define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
#define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
#define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
#define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
#define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
#define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
#define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
#define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
#define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
#define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
#define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
#define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
#define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
#define | GPIO_IDR_IDR0 ((uint16_t)0x0001) |
#define | GPIO_IDR_IDR1 ((uint16_t)0x0002) |
#define | GPIO_IDR_IDR10 ((uint16_t)0x0400) |
#define | GPIO_IDR_IDR11 ((uint16_t)0x0800) |
#define | GPIO_IDR_IDR12 ((uint16_t)0x1000) |
#define | GPIO_IDR_IDR13 ((uint16_t)0x2000) |
#define | GPIO_IDR_IDR14 ((uint16_t)0x4000) |
#define | GPIO_IDR_IDR15 ((uint16_t)0x8000) |
#define | GPIO_IDR_IDR2 ((uint16_t)0x0004) |
#define | GPIO_IDR_IDR3 ((uint16_t)0x0008) |
#define | GPIO_IDR_IDR4 ((uint16_t)0x0010) |
#define | GPIO_IDR_IDR5 ((uint16_t)0x0020) |
#define | GPIO_IDR_IDR6 ((uint16_t)0x0040) |
#define | GPIO_IDR_IDR7 ((uint16_t)0x0080) |
#define | GPIO_IDR_IDR8 ((uint16_t)0x0100) |
#define | GPIO_IDR_IDR9 ((uint16_t)0x0200) |
#define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
#define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
#define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
#define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
#define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
#define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
#define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
#define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
#define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
#define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
#define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
#define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
#define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
#define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
#define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
#define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
#define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
#define | GPIO_ODR_ODR0 ((uint16_t)0x0001) |
#define | GPIO_ODR_ODR1 ((uint16_t)0x0002) |
#define | GPIO_ODR_ODR10 ((uint16_t)0x0400) |
#define | GPIO_ODR_ODR11 ((uint16_t)0x0800) |
#define | GPIO_ODR_ODR12 ((uint16_t)0x1000) |
#define | GPIO_ODR_ODR13 ((uint16_t)0x2000) |
#define | GPIO_ODR_ODR14 ((uint16_t)0x4000) |
#define | GPIO_ODR_ODR15 ((uint16_t)0x8000) |
#define | GPIO_ODR_ODR2 ((uint16_t)0x0004) |
#define | GPIO_ODR_ODR3 ((uint16_t)0x0008) |
#define | GPIO_ODR_ODR4 ((uint16_t)0x0010) |
#define | GPIO_ODR_ODR5 ((uint16_t)0x0020) |
#define | GPIO_ODR_ODR6 ((uint16_t)0x0040) |
#define | GPIO_ODR_ODR7 ((uint16_t)0x0080) |
#define | GPIO_ODR_ODR8 ((uint16_t)0x0100) |
#define | GPIO_ODR_ODR9 ((uint16_t)0x0200) |
#define | GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
#define | GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
#define | GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
#define | GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
#define | GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
#define | GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
#define | GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
#define | GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
#define | GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
#define | GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
#define | GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
#define | GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
#define | GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
#define | GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
#define | HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) |
In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value. More... | |
#define | HSE_VALUE ((uint32_t)8000000) |
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers. More... | |
#define | HSE_Value HSE_VALUE |
#define | HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT |
#define | HSI_VALUE ((uint32_t)8000000) |
#define | HSI_Value HSI_VALUE |
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE) |
#define | I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
#define | I2C2 ((I2C_TypeDef *) I2C2_BASE) |
#define | I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
#define | I2C_CCR_CCR ((uint16_t)0x0FFF) |
#define | I2C_CCR_DUTY ((uint16_t)0x4000) |
#define | I2C_CCR_FS ((uint16_t)0x8000) |
#define | I2C_CR1_ACK ((uint16_t)0x0400) |
#define | I2C_CR1_ALERT ((uint16_t)0x2000) |
#define | I2C_CR1_ENARP ((uint16_t)0x0010) |
#define | I2C_CR1_ENGC ((uint16_t)0x0040) |
#define | I2C_CR1_ENPEC ((uint16_t)0x0020) |
#define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
#define | I2C_CR1_PE ((uint16_t)0x0001) |
#define | I2C_CR1_PEC ((uint16_t)0x1000) |
#define | I2C_CR1_POS ((uint16_t)0x0800) |
#define | I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
#define | I2C_CR1_SMBUS ((uint16_t)0x0002) |
#define | I2C_CR1_START ((uint16_t)0x0100) |
#define | I2C_CR1_STOP ((uint16_t)0x0200) |
#define | I2C_CR1_SWRST ((uint16_t)0x8000) |
#define | I2C_CR2_DMAEN ((uint16_t)0x0800) |
#define | I2C_CR2_FREQ ((uint16_t)0x003F) |
#define | I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
#define | I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
#define | I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
#define | I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
#define | I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
#define | I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
#define | I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
#define | I2C_CR2_ITERREN ((uint16_t)0x0100) |
#define | I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
#define | I2C_CR2_LAST ((uint16_t)0x1000) |
#define | I2C_DR_DR ((uint8_t)0xFF) |
#define | I2C_OAR1_ADD0 ((uint16_t)0x0001) |
#define | I2C_OAR1_ADD1 ((uint16_t)0x0002) |
#define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
#define | I2C_OAR1_ADD2 ((uint16_t)0x0004) |
#define | I2C_OAR1_ADD3 ((uint16_t)0x0008) |
#define | I2C_OAR1_ADD4 ((uint16_t)0x0010) |
#define | I2C_OAR1_ADD5 ((uint16_t)0x0020) |
#define | I2C_OAR1_ADD6 ((uint16_t)0x0040) |
#define | I2C_OAR1_ADD7 ((uint16_t)0x0080) |
#define | I2C_OAR1_ADD8 ((uint16_t)0x0100) |
#define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
#define | I2C_OAR1_ADD9 ((uint16_t)0x0200) |
#define | I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
#define | I2C_OAR2_ADD2 ((uint8_t)0xFE) |
#define | I2C_OAR2_ENDUAL ((uint8_t)0x01) |
#define | I2C_SR1_ADD10 ((uint16_t)0x0008) |
#define | I2C_SR1_ADDR ((uint16_t)0x0002) |
#define | I2C_SR1_AF ((uint16_t)0x0400) |
#define | I2C_SR1_ARLO ((uint16_t)0x0200) |
#define | I2C_SR1_BERR ((uint16_t)0x0100) |
#define | I2C_SR1_BTF ((uint16_t)0x0004) |
#define | I2C_SR1_OVR ((uint16_t)0x0800) |
#define | I2C_SR1_PECERR ((uint16_t)0x1000) |
#define | I2C_SR1_RXNE ((uint16_t)0x0040) |
#define | I2C_SR1_SB ((uint16_t)0x0001) |
#define | I2C_SR1_SMBALERT ((uint16_t)0x8000) |
#define | I2C_SR1_STOPF ((uint16_t)0x0010) |
#define | I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
#define | I2C_SR1_TXE ((uint16_t)0x0080) |
#define | I2C_SR2_BUSY ((uint16_t)0x0002) |
#define | I2C_SR2_DUALF ((uint16_t)0x0080) |
#define | I2C_SR2_GENCALL ((uint16_t)0x0010) |
#define | I2C_SR2_MSL ((uint16_t)0x0001) |
#define | I2C_SR2_PEC ((uint16_t)0xFF00) |
#define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
#define | I2C_SR2_SMBHOST ((uint16_t)0x0040) |
#define | I2C_SR2_TRA ((uint16_t)0x0004) |
#define | I2C_TRISE_TRISE ((uint8_t)0x3F) |
#define | IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
#define | IWDG ((IWDG_TypeDef *) IWDG_BASE) |
#define | IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
#define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
#define | IWDG_PR_PR ((uint8_t)0x07) |
#define | IWDG_PR_PR_0 ((uint8_t)0x01) |
#define | IWDG_PR_PR_1 ((uint8_t)0x02) |
#define | IWDG_PR_PR_2 ((uint8_t)0x04) |
#define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
#define | IWDG_SR_PVU ((uint8_t)0x01) |
#define | IWDG_SR_RVU ((uint8_t)0x02) |
#define | MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
#define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
#define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
#define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
#define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
#define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
#define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
#define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
#define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
#define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
#define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
#define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
#define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
#define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
#define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
#define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
#define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
#define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
#define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
#define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
#define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
#define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
#define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
#define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
#define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
#define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
#define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
#define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
#define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
#define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
#define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
#define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
#define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
#define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
#define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
#define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
#define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
#define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
#define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
#define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
#define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
#define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
#define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
#define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
#define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
#define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
#define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
#define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
#define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
#define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
#define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
#define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
#define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
#define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
#define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
#define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
#define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
#define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
#define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
#define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
#define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
#define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
#define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
#define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
#define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
#define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
#define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
#define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
#define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
#define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
#define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
#define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
#define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
#define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
#define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
#define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
#define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
#define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
#define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
#define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
#define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
#define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
#define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
#define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
#define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
#define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
#define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
#define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
#define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
#define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
#define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
#define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
#define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
#define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
#define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
#define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
#define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
#define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
#define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
#define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
#define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
#define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
#define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
#define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
#define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
#define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
#define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
#define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
#define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
#define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
#define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
#define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
#define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
#define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
#define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
#define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
#define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
#define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
#define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
#define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
#define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
#define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
#define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
#define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
#define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
#define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
#define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
#define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
#define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
#define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
#define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
#define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
#define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
#define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
#define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
#define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
#define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
#define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
#define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
#define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
#define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
#define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
#define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
#define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
#define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
#define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
#define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
#define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
#define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
#define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
#define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
#define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
#define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
#define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
#define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
#define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
#define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
#define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
#define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
#define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
#define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
#define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
#define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
#define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
#define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
#define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
#define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
#define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
#define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
#define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
#define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
#define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
#define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
#define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
#define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
#define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
#define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
#define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
#define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
#define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
#define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
#define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
#define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
#define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
#define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
#define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
#define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
#define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
#define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
#define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
#define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
#define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
#define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
#define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
#define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
#define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
#define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
#define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
#define | OB ((OB_TypeDef *) OB_BASE) |
#define | OB_BASE ((uint32_t)0x1FFFF800) |
#define | PERIPH_BASE ((uint32_t)0x40000000) |
#define | PERIPH_BB_BASE ((uint32_t)0x42000000) |
#define | PWR ((PWR_TypeDef *) PWR_BASE) |
#define | PWR_BASE (APB1PERIPH_BASE + 0x7000) |
#define | PWR_CR_CSBF ((uint16_t)0x0008) |
#define | PWR_CR_CWUF ((uint16_t)0x0004) |
#define | PWR_CR_DBP ((uint16_t)0x0100) |
#define | PWR_CR_LPDS ((uint16_t)0x0001) |
#define | PWR_CR_PDDS ((uint16_t)0x0002) |
#define | PWR_CR_PLS ((uint16_t)0x00E0) |
#define | PWR_CR_PLS_0 ((uint16_t)0x0020) |
#define | PWR_CR_PLS_1 ((uint16_t)0x0040) |
#define | PWR_CR_PLS_2 ((uint16_t)0x0080) |
#define | PWR_CR_PLS_2V2 ((uint16_t)0x0000) |
#define | PWR_CR_PLS_2V3 ((uint16_t)0x0020) |
#define | PWR_CR_PLS_2V4 ((uint16_t)0x0040) |
#define | PWR_CR_PLS_2V5 ((uint16_t)0x0060) |
#define | PWR_CR_PLS_2V6 ((uint16_t)0x0080) |
#define | PWR_CR_PLS_2V7 ((uint16_t)0x00A0) |
#define | PWR_CR_PLS_2V8 ((uint16_t)0x00C0) |
#define | PWR_CR_PLS_2V9 ((uint16_t)0x00E0) |
#define | PWR_CR_PVDE ((uint16_t)0x0010) |
#define | PWR_CSR_EWUP ((uint16_t)0x0100) |
#define | PWR_CSR_PVDO ((uint16_t)0x0004) |
#define | PWR_CSR_SBF ((uint16_t)0x0002) |
#define | PWR_CSR_WUF ((uint16_t)0x0001) |
#define | RCC ((RCC_TypeDef *) RCC_BASE) |
#define | RCC_AHBENR_CRCEN ((uint16_t)0x0040) |
#define | RCC_AHBENR_DMA1EN ((uint16_t)0x0001) |
#define | RCC_AHBENR_FLITFEN ((uint16_t)0x0010) |
#define | RCC_AHBENR_SRAMEN ((uint16_t)0x0004) |
#define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
#define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
#define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
#define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
#define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
#define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
#define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
#define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
#define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
#define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
#define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
#define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
#define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
#define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
#define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
#define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
#define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
#define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
#define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
#define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
#define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
#define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
#define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
#define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
#define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
#define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
#define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
#define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
#define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
#define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
#define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
#define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
#define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
#define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
#define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
#define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
#define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
#define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
#define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
#define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
#define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
#define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
#define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
#define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
#define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
#define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
#define | RCC_BASE (AHBPERIPH_BASE + 0x1000) |
#define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
#define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
#define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
#define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
#define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
#define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
#define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
#define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
#define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
#define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
#define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
#define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
#define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
#define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
#define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
#define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
#define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
#define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
#define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
#define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
#define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
#define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
#define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
#define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
#define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
#define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
#define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
#define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
#define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
#define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
#define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
#define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
#define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
#define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
#define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
#define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
#define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
#define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
#define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
#define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
#define | RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) |
#define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
#define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
#define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
#define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
#define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
#define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
#define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
#define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
#define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
#define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
#define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
#define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
#define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
#define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
#define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
#define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
#define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
#define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
#define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
#define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
#define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
#define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
#define | RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) |
#define | RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) |
#define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
#define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
#define | RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) |
#define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
#define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
#define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
#define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
#define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
#define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
#define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
#define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
#define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
#define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
#define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
#define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
#define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
#define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
#define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
#define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
#define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
#define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
#define | RCC_CFGR_SW ((uint32_t)0x00000003) |
#define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
#define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
#define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
#define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
#define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
#define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
#define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
#define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
#define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
#define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
#define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
#define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
#define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
#define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
#define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
#define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
#define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
#define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
#define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
#define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
#define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
#define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
#define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
#define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
#define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
#define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
#define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
#define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
#define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
#define | RCC_CR_CSSON ((uint32_t)0x00080000) |
#define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
#define | RCC_CR_HSEON ((uint32_t)0x00010000) |
#define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
#define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
#define | RCC_CR_HSION ((uint32_t)0x00000001) |
#define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
#define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
#define | RCC_CR_PLLON ((uint32_t)0x01000000) |
#define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
#define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
#define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
#define | RCC_CSR_LSION ((uint32_t)0x00000001) |
#define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
#define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
#define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
#define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
#define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
#define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
#define | READ_BIT(REG, BIT) ((REG) & (BIT)) |
#define | READ_REG(REG) ((REG)) |
#define | RTC ((RTC_TypeDef *) RTC_BASE) |
#define | RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) |
#define | RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) |
#define | RTC_BASE (APB1PERIPH_BASE + 0x2800) |
#define | RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) |
#define | RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) |
#define | RTC_CRH_ALRIE ((uint8_t)0x02) |
#define | RTC_CRH_OWIE ((uint8_t)0x04) |
#define | RTC_CRH_SECIE ((uint8_t)0x01) |
#define | RTC_CRL_ALRF ((uint8_t)0x02) |
#define | RTC_CRL_CNF ((uint8_t)0x10) |
#define | RTC_CRL_OWF ((uint8_t)0x04) |
#define | RTC_CRL_RSF ((uint8_t)0x08) |
#define | RTC_CRL_RTOFF ((uint8_t)0x20) |
#define | RTC_CRL_SECF ((uint8_t)0x01) |
#define | RTC_DIVH_RTC_DIV ((uint16_t)0x000F) |
#define | RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) |
#define | RTC_PRLH_PRL ((uint16_t)0x000F) |
#define | RTC_PRLL_PRL ((uint16_t)0xFFFF) |
#define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
#define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
#define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
#define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
#define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
#define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
#define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
#define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
#define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
#define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
#define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
#define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
#define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
#define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
#define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
#define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
#define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
#define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
#define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
#define | SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) |
#define | SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) |
#define | SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) |
#define | SCB_CCR_STKALIGN ((uint16_t)0x0200) |
#define | SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) |
#define | SCB_CCR_USERSETMPEND ((uint16_t)0x0002) |
#define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
#define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
#define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
#define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
#define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
#define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
#define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
#define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
#define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
#define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
#define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
#define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
#define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
#define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
#define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
#define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
#define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
#define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
#define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
#define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
#define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
#define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
#define | SCB_DFSR_BKPT ((uint8_t)0x02) |
#define | SCB_DFSR_DWTTRAP ((uint8_t)0x04) |
#define | SCB_DFSR_EXTERNAL ((uint8_t)0x10) |
#define | SCB_DFSR_HALTED ((uint8_t)0x01) |
#define | SCB_DFSR_VCATCH ((uint8_t)0x08) |
#define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
#define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
#define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
#define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
#define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
#define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
#define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
#define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
#define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
#define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
#define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
#define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
#define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
#define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
#define | SCB_SCR_SEVONPEND ((uint8_t)0x10) |
#define | SCB_SCR_SLEEPDEEP ((uint8_t)0x04) |
#define | SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) |
#define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
#define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
#define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
#define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
#define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
#define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
#define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
#define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
#define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
#define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
#define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
#define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
#define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
#define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
#define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
#define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
#define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
#define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
#define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
#define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
#define | SDIO ((SDIO_TypeDef *) SDIO_BASE) |
#define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
#define | SDIO_BASE (PERIPH_BASE + 0x18000) |
#define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
#define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
#define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
#define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
#define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
#define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
#define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
#define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
#define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
#define | SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
#define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
#define | SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
#define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
#define | SDIO_CMD_NIEN ((uint16_t)0x2000) |
#define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
#define | SDIO_CMD_WAITINT ((uint16_t)0x0100) |
#define | SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
#define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
#define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
#define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
#define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
#define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
#define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
#define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
#define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
#define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
#define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
#define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
#define | SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
#define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
#define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
#define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
#define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
#define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
#define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
#define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
#define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
#define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
#define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
#define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
#define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
#define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
#define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
#define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
#define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
#define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
#define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
#define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
#define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
#define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
#define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
#define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
#define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
#define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
#define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
#define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
#define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
#define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
#define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
#define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
#define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
#define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
#define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
#define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
#define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
#define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
#define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
#define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
#define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
#define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
#define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
#define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
#define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
#define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
#define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
#define | SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
#define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
#define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
#define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
#define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
#define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
#define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
#define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
#define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
#define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
#define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
#define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
#define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
#define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
#define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
#define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
#define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
#define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
#define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
#define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
#define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
#define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
#define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
#define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
#define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
#define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
#define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
#define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
#define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
#define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
#define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
#define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
#define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
#define | SET_BIT(REG, BIT) ((REG) |= (BIT)) |
#define | SPI1 ((SPI_TypeDef *) SPI1_BASE) |
#define | SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
#define | SPI2 ((SPI_TypeDef *) SPI2_BASE) |
#define | SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
#define | SPI3 ((SPI_TypeDef *) SPI3_BASE) |
#define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
#define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
#define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
#define | SPI_CR1_BR ((uint16_t)0x0038) |
#define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
#define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
#define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
#define | SPI_CR1_CPHA ((uint16_t)0x0001) |
#define | SPI_CR1_CPOL ((uint16_t)0x0002) |
#define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
#define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
#define | SPI_CR1_DFF ((uint16_t)0x0800) |
#define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
#define | SPI_CR1_MSTR ((uint16_t)0x0004) |
#define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
#define | SPI_CR1_SPE ((uint16_t)0x0040) |
#define | SPI_CR1_SSI ((uint16_t)0x0100) |
#define | SPI_CR1_SSM ((uint16_t)0x0200) |
#define | SPI_CR2_ERRIE ((uint8_t)0x20) |
#define | SPI_CR2_RXDMAEN ((uint8_t)0x01) |
#define | SPI_CR2_RXNEIE ((uint8_t)0x40) |
#define | SPI_CR2_SSOE ((uint8_t)0x04) |
#define | SPI_CR2_TXDMAEN ((uint8_t)0x02) |
#define | SPI_CR2_TXEIE ((uint8_t)0x80) |
#define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
#define | SPI_DR_DR ((uint16_t)0xFFFF) |
#define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
#define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
#define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
#define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
#define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
#define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
#define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
#define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
#define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
#define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
#define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
#define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
#define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
#define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
#define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
#define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
#define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
#define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
#define | SPI_SR_BSY ((uint8_t)0x80) |
#define | SPI_SR_CHSIDE ((uint8_t)0x04) |
#define | SPI_SR_CRCERR ((uint8_t)0x10) |
#define | SPI_SR_MODF ((uint8_t)0x20) |
#define | SPI_SR_OVR ((uint8_t)0x40) |
#define | SPI_SR_RXNE ((uint8_t)0x01) |
#define | SPI_SR_TXE ((uint8_t)0x02) |
#define | SPI_SR_UDR ((uint8_t)0x08) |
#define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
#define | SRAM_BASE ((uint32_t)0x20000000) |
#define | SRAM_BB_BASE ((uint32_t)0x22000000) |
#define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
#define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
#define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
#define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
#define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
#define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
#define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
#define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
#define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
#define | TIM1 ((TIM_TypeDef *) TIM1_BASE) |
#define | TIM10 ((TIM_TypeDef *) TIM10_BASE) |
#define | TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
#define | TIM11 ((TIM_TypeDef *) TIM11_BASE) |
#define | TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
#define | TIM12 ((TIM_TypeDef *) TIM12_BASE) |
#define | TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
#define | TIM13 ((TIM_TypeDef *) TIM13_BASE) |
#define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
#define | TIM14 ((TIM_TypeDef *) TIM14_BASE) |
#define | TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
#define | TIM15 ((TIM_TypeDef *) TIM15_BASE) |
#define | TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
#define | TIM16 ((TIM_TypeDef *) TIM16_BASE) |
#define | TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
#define | TIM17 ((TIM_TypeDef *) TIM17_BASE) |
#define | TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
#define | TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
#define | TIM2 ((TIM_TypeDef *) TIM2_BASE) |
#define | TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
#define | TIM3 ((TIM_TypeDef *) TIM3_BASE) |
#define | TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
#define | TIM4 ((TIM_TypeDef *) TIM4_BASE) |
#define | TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
#define | TIM5 ((TIM_TypeDef *) TIM5_BASE) |
#define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
#define | TIM6 ((TIM_TypeDef *) TIM6_BASE) |
#define | TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
#define | TIM7 ((TIM_TypeDef *) TIM7_BASE) |
#define | TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
#define | TIM8 ((TIM_TypeDef *) TIM8_BASE) |
#define | TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
#define | TIM9 ((TIM_TypeDef *) TIM9_BASE) |
#define | TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
#define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
#define | TIM_BDTR_AOE ((uint16_t)0x4000) |
#define | TIM_BDTR_BKE ((uint16_t)0x1000) |
#define | TIM_BDTR_BKP ((uint16_t)0x2000) |
#define | TIM_BDTR_DTG ((uint16_t)0x00FF) |
#define | TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
#define | TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
#define | TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
#define | TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
#define | TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
#define | TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
#define | TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
#define | TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
#define | TIM_BDTR_LOCK ((uint16_t)0x0300) |
#define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
#define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
#define | TIM_BDTR_MOE ((uint16_t)0x8000) |
#define | TIM_BDTR_OSSI ((uint16_t)0x0400) |
#define | TIM_BDTR_OSSR ((uint16_t)0x0800) |
#define | TIM_CCER_CC1E ((uint16_t)0x0001) |
#define | TIM_CCER_CC1NE ((uint16_t)0x0004) |
#define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
#define | TIM_CCER_CC1P ((uint16_t)0x0002) |
#define | TIM_CCER_CC2E ((uint16_t)0x0010) |
#define | TIM_CCER_CC2NE ((uint16_t)0x0040) |
#define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
#define | TIM_CCER_CC2P ((uint16_t)0x0020) |
#define | TIM_CCER_CC3E ((uint16_t)0x0100) |
#define | TIM_CCER_CC3NE ((uint16_t)0x0400) |
#define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
#define | TIM_CCER_CC3P ((uint16_t)0x0200) |
#define | TIM_CCER_CC4E ((uint16_t)0x1000) |
#define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
#define | TIM_CCER_CC4P ((uint16_t)0x2000) |
#define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
#define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
#define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
#define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
#define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
#define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
#define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
#define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
#define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
#define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
#define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
#define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
#define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
#define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
#define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
#define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
#define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
#define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
#define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
#define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
#define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
#define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
#define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
#define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
#define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
#define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
#define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
#define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
#define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
#define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
#define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
#define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
#define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
#define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
#define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
#define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
#define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
#define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
#define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
#define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
#define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
#define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
#define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
#define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
#define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
#define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
#define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
#define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
#define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
#define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
#define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
#define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
#define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
#define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
#define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
#define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
#define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
#define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
#define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
#define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
#define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
#define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
#define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
#define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
#define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
#define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
#define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
#define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
#define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
#define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
#define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
#define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
#define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
#define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
#define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
#define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
#define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
#define | TIM_CR1_ARPE ((uint16_t)0x0080) |
#define | TIM_CR1_CEN ((uint16_t)0x0001) |
#define | TIM_CR1_CKD ((uint16_t)0x0300) |
#define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
#define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
#define | TIM_CR1_CMS ((uint16_t)0x0060) |
#define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
#define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
#define | TIM_CR1_DIR ((uint16_t)0x0010) |
#define | TIM_CR1_OPM ((uint16_t)0x0008) |
#define | TIM_CR1_UDIS ((uint16_t)0x0002) |
#define | TIM_CR1_URS ((uint16_t)0x0004) |
#define | TIM_CR2_CCDS ((uint16_t)0x0008) |
#define | TIM_CR2_CCPC ((uint16_t)0x0001) |
#define | TIM_CR2_CCUS ((uint16_t)0x0004) |
#define | TIM_CR2_MMS ((uint16_t)0x0070) |
#define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
#define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
#define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
#define | TIM_CR2_OIS1 ((uint16_t)0x0100) |
#define | TIM_CR2_OIS1N ((uint16_t)0x0200) |
#define | TIM_CR2_OIS2 ((uint16_t)0x0400) |
#define | TIM_CR2_OIS2N ((uint16_t)0x0800) |
#define | TIM_CR2_OIS3 ((uint16_t)0x1000) |
#define | TIM_CR2_OIS3N ((uint16_t)0x2000) |
#define | TIM_CR2_OIS4 ((uint16_t)0x4000) |
#define | TIM_CR2_TI1S ((uint16_t)0x0080) |
#define | TIM_DCR_DBA ((uint16_t)0x001F) |
#define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
#define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
#define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
#define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
#define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
#define | TIM_DCR_DBL ((uint16_t)0x1F00) |
#define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
#define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
#define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
#define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
#define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
#define | TIM_DIER_BIE ((uint16_t)0x0080) |
#define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
#define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
#define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
#define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
#define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
#define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
#define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
#define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
#define | TIM_DIER_COMDE ((uint16_t)0x2000) |
#define | TIM_DIER_COMIE ((uint16_t)0x0020) |
#define | TIM_DIER_TDE ((uint16_t)0x4000) |
#define | TIM_DIER_TIE ((uint16_t)0x0040) |
#define | TIM_DIER_UDE ((uint16_t)0x0100) |
#define | TIM_DIER_UIE ((uint16_t)0x0001) |
#define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
#define | TIM_EGR_BG ((uint8_t)0x80) |
#define | TIM_EGR_CC1G ((uint8_t)0x02) |
#define | TIM_EGR_CC2G ((uint8_t)0x04) |
#define | TIM_EGR_CC3G ((uint8_t)0x08) |
#define | TIM_EGR_CC4G ((uint8_t)0x10) |
#define | TIM_EGR_COMG ((uint8_t)0x20) |
#define | TIM_EGR_TG ((uint8_t)0x40) |
#define | TIM_EGR_UG ((uint8_t)0x01) |
#define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
#define | TIM_RCR_REP ((uint8_t)0xFF) |
#define | TIM_SMCR_ECE ((uint16_t)0x4000) |
#define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
#define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
#define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
#define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
#define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
#define | TIM_SMCR_ETP ((uint16_t)0x8000) |
#define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
#define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
#define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
#define | TIM_SMCR_MSM ((uint16_t)0x0080) |
#define | TIM_SMCR_SMS ((uint16_t)0x0007) |
#define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
#define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
#define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
#define | TIM_SMCR_TS ((uint16_t)0x0070) |
#define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
#define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
#define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
#define | TIM_SR_BIF ((uint16_t)0x0080) |
#define | TIM_SR_CC1IF ((uint16_t)0x0002) |
#define | TIM_SR_CC1OF ((uint16_t)0x0200) |
#define | TIM_SR_CC2IF ((uint16_t)0x0004) |
#define | TIM_SR_CC2OF ((uint16_t)0x0400) |
#define | TIM_SR_CC3IF ((uint16_t)0x0008) |
#define | TIM_SR_CC3OF ((uint16_t)0x0800) |
#define | TIM_SR_CC4IF ((uint16_t)0x0010) |
#define | TIM_SR_CC4OF ((uint16_t)0x1000) |
#define | TIM_SR_COMIF ((uint16_t)0x0020) |
#define | TIM_SR_TIF ((uint16_t)0x0040) |
#define | TIM_SR_UIF ((uint16_t)0x0001) |
#define | UART4 ((USART_TypeDef *) UART4_BASE) |
#define | UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
#define | UART5 ((USART_TypeDef *) UART5_BASE) |
#define | UART5_BASE (APB1PERIPH_BASE + 0x5000) |
#define | USART1 ((USART_TypeDef *) USART1_BASE) |
#define | USART1_BASE (APB2PERIPH_BASE + 0x3800) |
#define | USART2 ((USART_TypeDef *) USART2_BASE) |
#define | USART2_BASE (APB1PERIPH_BASE + 0x4400) |
#define | USART3 ((USART_TypeDef *) USART3_BASE) |
#define | USART3_BASE (APB1PERIPH_BASE + 0x4800) |
#define | USART_BRR_DIV_Fraction ((uint16_t)0x000F) |
#define | USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) |
#define | USART_CR1_IDLEIE ((uint16_t)0x0010) |
#define | USART_CR1_M ((uint16_t)0x1000) |
#define | USART_CR1_OVER8 ((uint16_t)0x8000) |
#define | USART_CR1_PCE ((uint16_t)0x0400) |
#define | USART_CR1_PEIE ((uint16_t)0x0100) |
#define | USART_CR1_PS ((uint16_t)0x0200) |
#define | USART_CR1_RE ((uint16_t)0x0004) |
#define | USART_CR1_RWU ((uint16_t)0x0002) |
#define | USART_CR1_RXNEIE ((uint16_t)0x0020) |
#define | USART_CR1_SBK ((uint16_t)0x0001) |
#define | USART_CR1_TCIE ((uint16_t)0x0040) |
#define | USART_CR1_TE ((uint16_t)0x0008) |
#define | USART_CR1_TXEIE ((uint16_t)0x0080) |
#define | USART_CR1_UE ((uint16_t)0x2000) |
#define | USART_CR1_WAKE ((uint16_t)0x0800) |
#define | USART_CR2_ADD ((uint16_t)0x000F) |
#define | USART_CR2_CLKEN ((uint16_t)0x0800) |
#define | USART_CR2_CPHA ((uint16_t)0x0200) |
#define | USART_CR2_CPOL ((uint16_t)0x0400) |
#define | USART_CR2_LBCL ((uint16_t)0x0100) |
#define | USART_CR2_LBDIE ((uint16_t)0x0040) |
#define | USART_CR2_LBDL ((uint16_t)0x0020) |
#define | USART_CR2_LINEN ((uint16_t)0x4000) |
#define | USART_CR2_STOP ((uint16_t)0x3000) |
#define | USART_CR2_STOP_0 ((uint16_t)0x1000) |
#define | USART_CR2_STOP_1 ((uint16_t)0x2000) |
#define | USART_CR3_CTSE ((uint16_t)0x0200) |
#define | USART_CR3_CTSIE ((uint16_t)0x0400) |
#define | USART_CR3_DMAR ((uint16_t)0x0040) |
#define | USART_CR3_DMAT ((uint16_t)0x0080) |
#define | USART_CR3_EIE ((uint16_t)0x0001) |
#define | USART_CR3_HDSEL ((uint16_t)0x0008) |
#define | USART_CR3_IREN ((uint16_t)0x0002) |
#define | USART_CR3_IRLP ((uint16_t)0x0004) |
#define | USART_CR3_NACK ((uint16_t)0x0010) |
#define | USART_CR3_ONEBIT ((uint16_t)0x0800) |
#define | USART_CR3_RTSE ((uint16_t)0x0100) |
#define | USART_CR3_SCEN ((uint16_t)0x0020) |
#define | USART_DR_DR ((uint16_t)0x01FF) |
#define | USART_GTPR_GT ((uint16_t)0xFF00) |
#define | USART_GTPR_PSC ((uint16_t)0x00FF) |
#define | USART_GTPR_PSC_0 ((uint16_t)0x0001) |
#define | USART_GTPR_PSC_1 ((uint16_t)0x0002) |
#define | USART_GTPR_PSC_2 ((uint16_t)0x0004) |
#define | USART_GTPR_PSC_3 ((uint16_t)0x0008) |
#define | USART_GTPR_PSC_4 ((uint16_t)0x0010) |
#define | USART_GTPR_PSC_5 ((uint16_t)0x0020) |
#define | USART_GTPR_PSC_6 ((uint16_t)0x0040) |
#define | USART_GTPR_PSC_7 ((uint16_t)0x0080) |
#define | USART_SR_CTS ((uint16_t)0x0200) |
#define | USART_SR_FE ((uint16_t)0x0002) |
#define | USART_SR_IDLE ((uint16_t)0x0010) |
#define | USART_SR_LBD ((uint16_t)0x0100) |
#define | USART_SR_NE ((uint16_t)0x0004) |
#define | USART_SR_ORE ((uint16_t)0x0008) |
#define | USART_SR_PE ((uint16_t)0x0001) |
#define | USART_SR_RXNE ((uint16_t)0x0020) |
#define | USART_SR_TC ((uint16_t)0x0040) |
#define | USART_SR_TXE ((uint16_t)0x0080) |
#define | USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) |
#define | USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) |
#define | USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) |
#define | USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) |
#define | USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) |
#define | USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) |
#define | USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) |
#define | USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) |
#define | USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) |
#define | USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) |
#define | USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) |
#define | USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) |
#define | USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) |
#define | USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) |
#define | USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) |
#define | USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) |
#define | USB_BTABLE_BTABLE ((uint16_t)0xFFF8) |
#define | USB_CNTR_CTRM ((uint16_t)0x8000) |
#define | USB_CNTR_ERRM ((uint16_t)0x2000) |
#define | USB_CNTR_ESOFM ((uint16_t)0x0100) |
#define | USB_CNTR_FRES ((uint16_t)0x0001) |
#define | USB_CNTR_FSUSP ((uint16_t)0x0008) |
#define | USB_CNTR_LP_MODE ((uint16_t)0x0004) |
#define | USB_CNTR_PDWN ((uint16_t)0x0002) |
#define | USB_CNTR_PMAOVRM ((uint16_t)0x4000) |
#define | USB_CNTR_RESETM ((uint16_t)0x0400) |
#define | USB_CNTR_RESUME ((uint16_t)0x0010) |
#define | USB_CNTR_SOFM ((uint16_t)0x0200) |
#define | USB_CNTR_SUSPM ((uint16_t)0x0800) |
#define | USB_CNTR_WKUPM ((uint16_t)0x1000) |
#define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
#define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
#define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
#define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
#define | USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) |
#define | USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) |
#define | USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) |
#define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
#define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
#define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
#define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
#define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
#define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) |
#define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
#define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
#define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
#define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
#define | USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) |
#define | USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) |
#define | USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) |
#define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
#define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
#define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
#define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
#define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
#define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) |
#define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
#define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
#define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
#define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
#define | USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) |
#define | USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) |
#define | USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) |
#define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
#define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
#define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
#define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
#define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
#define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) |
#define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
#define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
#define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
#define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
#define | USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) |
#define | USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) |
#define | USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) |
#define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
#define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
#define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
#define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
#define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
#define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) |
#define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) |
#define | USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) |
#define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
#define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
#define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
#define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
#define | USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) |
#define | USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) |
#define | USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) |
#define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
#define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
#define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
#define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
#define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
#define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) |
#define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
#define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
#define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
#define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
#define | USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) |
#define | USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) |
#define | USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) |
#define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
#define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
#define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
#define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
#define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
#define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) |
#define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
#define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
#define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
#define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
#define | USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) |
#define | USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) |
#define | USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) |
#define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
#define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
#define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
#define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
#define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
#define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) |
#define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
#define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
#define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
#define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
#define | USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) |
#define | USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) |
#define | USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) |
#define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
#define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
#define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
#define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
#define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
#define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
#define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
#define | USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) |
#define | USB_DADDR_ADD ((uint8_t)0x7F) |
#define | USB_DADDR_ADD0 ((uint8_t)0x01) |
#define | USB_DADDR_ADD1 ((uint8_t)0x02) |
#define | USB_DADDR_ADD2 ((uint8_t)0x04) |
#define | USB_DADDR_ADD3 ((uint8_t)0x08) |
#define | USB_DADDR_ADD4 ((uint8_t)0x10) |
#define | USB_DADDR_ADD5 ((uint8_t)0x20) |
#define | USB_DADDR_ADD6 ((uint8_t)0x40) |
#define | USB_DADDR_EF ((uint8_t)0x80) |
#define | USB_EP0R_CTR_RX ((uint16_t)0x8000) |
#define | USB_EP0R_CTR_TX ((uint16_t)0x0080) |
#define | USB_EP0R_DTOG_RX ((uint16_t)0x4000) |
#define | USB_EP0R_DTOG_TX ((uint16_t)0x0040) |
#define | USB_EP0R_EA ((uint16_t)0x000F) |
#define | USB_EP0R_EP_KIND ((uint16_t)0x0100) |
#define | USB_EP0R_EP_TYPE ((uint16_t)0x0600) |
#define | USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) |
#define | USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) |
#define | USB_EP0R_SETUP ((uint16_t)0x0800) |
#define | USB_EP0R_STAT_RX ((uint16_t)0x3000) |
#define | USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) |
#define | USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) |
#define | USB_EP0R_STAT_TX ((uint16_t)0x0030) |
#define | USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) |
#define | USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) |
#define | USB_EP1R_CTR_RX ((uint16_t)0x8000) |
#define | USB_EP1R_CTR_TX ((uint16_t)0x0080) |
#define | USB_EP1R_DTOG_RX ((uint16_t)0x4000) |
#define | USB_EP1R_DTOG_TX ((uint16_t)0x0040) |
#define | USB_EP1R_EA ((uint16_t)0x000F) |
#define | USB_EP1R_EP_KIND ((uint16_t)0x0100) |
#define | USB_EP1R_EP_TYPE ((uint16_t)0x0600) |
#define | USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) |
#define | USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) |
#define | USB_EP1R_SETUP ((uint16_t)0x0800) |
#define | USB_EP1R_STAT_RX ((uint16_t)0x3000) |
#define | USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) |
#define | USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) |
#define | USB_EP1R_STAT_TX ((uint16_t)0x0030) |
#define | USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) |
#define | USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) |
#define | USB_EP2R_CTR_RX ((uint16_t)0x8000) |
#define | USB_EP2R_CTR_TX ((uint16_t)0x0080) |
#define | USB_EP2R_DTOG_RX ((uint16_t)0x4000) |
#define | USB_EP2R_DTOG_TX ((uint16_t)0x0040) |
#define | USB_EP2R_EA ((uint16_t)0x000F) |
#define | USB_EP2R_EP_KIND ((uint16_t)0x0100) |
#define | USB_EP2R_EP_TYPE ((uint16_t)0x0600) |
#define | USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) |
#define | USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) |
#define | USB_EP2R_SETUP ((uint16_t)0x0800) |
#define | USB_EP2R_STAT_RX ((uint16_t)0x3000) |
#define | USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) |
#define | USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) |
#define | USB_EP2R_STAT_TX ((uint16_t)0x0030) |
#define | USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) |
#define | USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) |
#define | USB_EP3R_CTR_RX ((uint16_t)0x8000) |
#define | USB_EP3R_CTR_TX ((uint16_t)0x0080) |
#define | USB_EP3R_DTOG_RX ((uint16_t)0x4000) |
#define | USB_EP3R_DTOG_TX ((uint16_t)0x0040) |
#define | USB_EP3R_EA ((uint16_t)0x000F) |
#define | USB_EP3R_EP_KIND ((uint16_t)0x0100) |
#define | USB_EP3R_EP_TYPE ((uint16_t)0x0600) |
#define | USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) |
#define | USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) |
#define | USB_EP3R_SETUP ((uint16_t)0x0800) |
#define | USB_EP3R_STAT_RX ((uint16_t)0x3000) |
#define | USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) |
#define | USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) |
#define | USB_EP3R_STAT_TX ((uint16_t)0x0030) |
#define | USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) |
#define | USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) |
#define | USB_EP4R_CTR_RX ((uint16_t)0x8000) |
#define | USB_EP4R_CTR_TX ((uint16_t)0x0080) |
#define | USB_EP4R_DTOG_RX ((uint16_t)0x4000) |
#define | USB_EP4R_DTOG_TX ((uint16_t)0x0040) |
#define | USB_EP4R_EA ((uint16_t)0x000F) |
#define | USB_EP4R_EP_KIND ((uint16_t)0x0100) |
#define | USB_EP4R_EP_TYPE ((uint16_t)0x0600) |
#define | USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) |
#define | USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) |
#define | USB_EP4R_SETUP ((uint16_t)0x0800) |
#define | USB_EP4R_STAT_RX ((uint16_t)0x3000) |
#define | USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) |
#define | USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) |
#define | USB_EP4R_STAT_TX ((uint16_t)0x0030) |
#define | USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) |
#define | USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) |
#define | USB_EP5R_CTR_RX ((uint16_t)0x8000) |
#define | USB_EP5R_CTR_TX ((uint16_t)0x0080) |
#define | USB_EP5R_DTOG_RX ((uint16_t)0x4000) |
#define | USB_EP5R_DTOG_TX ((uint16_t)0x0040) |
#define | USB_EP5R_EA ((uint16_t)0x000F) |
#define | USB_EP5R_EP_KIND ((uint16_t)0x0100) |
#define | USB_EP5R_EP_TYPE ((uint16_t)0x0600) |
#define | USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) |
#define | USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) |
#define | USB_EP5R_SETUP ((uint16_t)0x0800) |
#define | USB_EP5R_STAT_RX ((uint16_t)0x3000) |
#define | USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) |
#define | USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) |
#define | USB_EP5R_STAT_TX ((uint16_t)0x0030) |
#define | USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) |
#define | USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) |
#define | USB_EP6R_CTR_RX ((uint16_t)0x8000) |
#define | USB_EP6R_CTR_TX ((uint16_t)0x0080) |
#define | USB_EP6R_DTOG_RX ((uint16_t)0x4000) |
#define | USB_EP6R_DTOG_TX ((uint16_t)0x0040) |
#define | USB_EP6R_EA ((uint16_t)0x000F) |
#define | USB_EP6R_EP_KIND ((uint16_t)0x0100) |
#define | USB_EP6R_EP_TYPE ((uint16_t)0x0600) |
#define | USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) |
#define | USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) |
#define | USB_EP6R_SETUP ((uint16_t)0x0800) |
#define | USB_EP6R_STAT_RX ((uint16_t)0x3000) |
#define | USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) |
#define | USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) |
#define | USB_EP6R_STAT_TX ((uint16_t)0x0030) |
#define | USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) |
#define | USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) |
#define | USB_EP7R_CTR_RX ((uint16_t)0x8000) |
#define | USB_EP7R_CTR_TX ((uint16_t)0x0080) |
#define | USB_EP7R_DTOG_RX ((uint16_t)0x4000) |
#define | USB_EP7R_DTOG_TX ((uint16_t)0x0040) |
#define | USB_EP7R_EA ((uint16_t)0x000F) |
#define | USB_EP7R_EP_KIND ((uint16_t)0x0100) |
#define | USB_EP7R_EP_TYPE ((uint16_t)0x0600) |
#define | USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) |
#define | USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) |
#define | USB_EP7R_SETUP ((uint16_t)0x0800) |
#define | USB_EP7R_STAT_RX ((uint16_t)0x3000) |
#define | USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) |
#define | USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) |
#define | USB_EP7R_STAT_TX ((uint16_t)0x0030) |
#define | USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) |
#define | USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) |
#define | USB_FNR_FN ((uint16_t)0x07FF) |
#define | USB_FNR_LCK ((uint16_t)0x2000) |
#define | USB_FNR_LSOF ((uint16_t)0x1800) |
#define | USB_FNR_RXDM ((uint16_t)0x4000) |
#define | USB_FNR_RXDP ((uint16_t)0x8000) |
#define | USB_ISTR_CTR ((uint16_t)0x8000) |
#define | USB_ISTR_DIR ((uint16_t)0x0010) |
#define | USB_ISTR_EP_ID ((uint16_t)0x000F) |
#define | USB_ISTR_ERR ((uint16_t)0x2000) |
#define | USB_ISTR_ESOF ((uint16_t)0x0100) |
#define | USB_ISTR_PMAOVR ((uint16_t)0x4000) |
#define | USB_ISTR_RESET ((uint16_t)0x0400) |
#define | USB_ISTR_SOF ((uint16_t)0x0200) |
#define | USB_ISTR_SUSP ((uint16_t)0x0800) |
#define | USB_ISTR_WKUP ((uint16_t)0x1000) |
#define | WRITE_REG(REG, VAL) ((REG) = (VAL)) |
#define | WWDG ((WWDG_TypeDef *) WWDG_BASE) |
#define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
#define | WWDG_CFR_EWI ((uint16_t)0x0200) |
#define | WWDG_CFR_W ((uint16_t)0x007F) |
#define | WWDG_CFR_W0 ((uint16_t)0x0001) |
#define | WWDG_CFR_W1 ((uint16_t)0x0002) |
#define | WWDG_CFR_W2 ((uint16_t)0x0004) |
#define | WWDG_CFR_W3 ((uint16_t)0x0008) |
#define | WWDG_CFR_W4 ((uint16_t)0x0010) |
#define | WWDG_CFR_W5 ((uint16_t)0x0020) |
#define | WWDG_CFR_W6 ((uint16_t)0x0040) |
#define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
#define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
#define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
#define | WWDG_CR_T ((uint8_t)0x7F) |
#define | WWDG_CR_T0 ((uint8_t)0x01) |
#define | WWDG_CR_T1 ((uint8_t)0x02) |
#define | WWDG_CR_T2 ((uint8_t)0x04) |
#define | WWDG_CR_T3 ((uint8_t)0x08) |
#define | WWDG_CR_T4 ((uint8_t)0x10) |
#define | WWDG_CR_T5 ((uint8_t)0x20) |
#define | WWDG_CR_T6 ((uint8_t)0x40) |
#define | WWDG_CR_WDGA ((uint8_t)0x80) |
#define | WWDG_SR_EWIF ((uint8_t)0x01) |
Typedefs | |
typedef enum IRQn | IRQn_Type |
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section. More... | |
typedef enum FlagStatus | ITStatus |
typedef int16_t | s16 |
typedef int32_t | s32 |
typedef int8_t | s8 |
typedef const int16_t | sc16 |
typedef const int32_t | sc32 |
typedef const int8_t | sc8 |
typedef uint16_t | u16 |
typedef uint32_t | u32 |
typedef uint8_t | u8 |
typedef const uint16_t | uc16 |
typedef const uint32_t | uc32 |
typedef const uint8_t | uc8 |
typedef __IO int16_t | vs16 |
typedef __IO int32_t | vs32 |
typedef __IO int8_t | vs8 |
typedef __I int16_t | vsc16 |
typedef __I int32_t | vsc32 |
typedef __I int8_t | vsc8 |
typedef __IO uint16_t | vu16 |
typedef __IO uint32_t | vu32 |
typedef __IO uint8_t | vu8 |
typedef __I uint16_t | vuc16 |
typedef __I uint32_t | vuc32 |
typedef __I uint8_t | vuc8 |
CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F10x Connectivity line, High density, High density value line, Medium density, Medium density Value line, Low density, Low density Value line and XL-density devices.
THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
Definition in file stm32f10x.h.