RCC driver modules. More...
Classes | |
struct | RCC_ClocksTypeDef |
Functions | |
void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue) |
Adjusts the Internal High Speed oscillator (HSI) calibration value. More... | |
void | RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Enables or disables the AHB1 peripheral clock. More... | |
void | RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. More... | |
void | RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Forces or releases AHB1 peripheral reset. More... | |
void | RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Enables or disables the AHB2 peripheral clock. More... | |
void | RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. More... | |
void | RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Forces or releases AHB2 peripheral reset. More... | |
void | RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Enables or disables the AHB3 peripheral clock. More... | |
void | RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. More... | |
void | RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Forces or releases AHB3 peripheral reset. More... | |
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Enables or disables the Low Speed APB (APB1) peripheral clock. More... | |
void | RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. More... | |
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Forces or releases Low Speed APB (APB1) peripheral reset. More... | |
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Enables or disables the High Speed APB (APB2) peripheral clock. More... | |
void | RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. More... | |
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Forces or releases High Speed APB (APB2) peripheral reset. More... | |
void | RCC_BackupResetCmd (FunctionalState NewState) |
Forces or releases the Backup domain reset. More... | |
void | RCC_ClearFlag (void) |
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More... | |
void | RCC_ClearITPendingBit (uint8_t RCC_IT) |
Clears the RCC's interrupt pending bits. More... | |
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState) |
Enables or disables the Clock Security System. More... | |
void | RCC_DeInit (void) |
Resets the RCC clock configuration to the default reset state. More... | |
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks) |
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More... | |
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG) |
Checks whether the specified RCC flag is set or not. More... | |
ITStatus | RCC_GetITStatus (uint8_t RCC_IT) |
Checks whether the specified RCC interrupt has occurred or not. More... | |
uint8_t | RCC_GetSYSCLKSource (void) |
Returns the clock source used as system clock. More... | |
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK) |
Configures the AHB clock (HCLK). More... | |
void | RCC_HSEConfig (uint8_t RCC_HSE) |
Configures the External High Speed oscillator (HSE). More... | |
void | RCC_HSICmd (FunctionalState NewState) |
Enables or disables the Internal High Speed oscillator (HSI). More... | |
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState) |
Enables or disables the specified RCC interrupts. More... | |
void | RCC_LSEConfig (uint8_t RCC_LSE) |
Configures the External Low Speed oscillator (LSE). More... | |
void | RCC_LSEModeConfig (uint8_t RCC_Mode) |
Configures the External Low Speed oscillator mode (LSE mode). More... | |
void | RCC_LSICmd (FunctionalState NewState) |
Enables or disables the Internal Low Speed oscillator (LSI). More... | |
void | RCC_LTDCCLKDivConfig (uint32_t RCC_PLLSAIDivR) |
Configures the LTDC clock Divider coming from PLLSAI. More... | |
void | RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) |
Selects the clock source to output on MCO1 pin(PA8). More... | |
void | RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) |
Selects the clock source to output on MCO2 pin(PC9). More... | |
void | RCC_PCLK1Config (uint32_t RCC_HCLK) |
Configures the Low Speed APB clock (PCLK1). More... | |
void | RCC_PCLK2Config (uint32_t RCC_HCLK) |
Configures the High Speed APB clock (PCLK2). More... | |
void | RCC_PLLCmd (FunctionalState NewState) |
Enables or disables the main PLL. More... | |
void | RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) |
Configures the main PLL clock source, multiplication and division factors. More... | |
void | RCC_PLLI2SCmd (FunctionalState NewState) |
Enables or disables the PLLI2S. More... | |
void | RCC_PLLI2SConfig (uint32_t PLLI2SN, uint32_t PLLI2SR) |
Configures the PLLI2S clock multiplication and division factors. More... | |
void | RCC_PLLSAICmd (FunctionalState NewState) |
Enables or disables the PLLSAI. More... | |
void | RCC_RTCCLKCmd (FunctionalState NewState) |
Enables or disables the RTC clock. More... | |
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource) |
Configures the RTC clock (RTCCLK). More... | |
void | RCC_SAIPLLI2SClkDivConfig (uint32_t RCC_PLLI2SDivQ) |
Configures the SAI clock Divider coming from PLLI2S. More... | |
void | RCC_SAIPLLSAIClkDivConfig (uint32_t RCC_PLLSAIDivQ) |
Configures the SAI clock Divider coming from PLLSAI. More... | |
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource) |
Configures the system clock (SYSCLK). More... | |
void | RCC_TIMCLKPresConfig (uint32_t RCC_TIMCLKPrescaler) |
Configures the Timers clocks prescalers selection. More... | |
ErrorStatus | RCC_WaitForHSEStartUp (void) |
Waits for HSE start-up. More... | |
Variables | |
static __I uint16_t | ADCPrescTable [16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 } |
static __I uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9} |
static __I uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9} |
static __I uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9} |
RCC driver modules.
#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
Definition at line 133 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
Definition at line 149 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
Definition at line 102 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
Definition at line 106 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
Definition at line 107 of file stm32f30x_rcc.c.
#define BDCR_OFFSET (RCC_OFFSET + 0x70) |
Definition at line 97 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define BDCR_OFFSET (RCC_OFFSET + 0x70) |
Definition at line 101 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define BDCR_OFFSET (RCC_OFFSET + 0x20) |
Definition at line 101 of file stm32f30x_rcc.c.
#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
Definition at line 99 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
Definition at line 103 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
Definition at line 103 of file stm32f30x_rcc.c.
#define BDRST_BitNumber 0x10 |
Definition at line 101 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define BDRST_BitNumber 0x10 |
Definition at line 105 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define BDRST_BitNumber 0x10 |
Definition at line 106 of file stm32f30x_rcc.c.
#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007) |
Definition at line 121 of file stm32f30x_rcc.c.
#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) |
Definition at line 93 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) |
Definition at line 96 of file stm32f30x_rcc.c.
#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) |
Definition at line 97 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) |
Definition at line 118 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) |
Definition at line 134 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) |
Definition at line 117 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) |
Definition at line 133 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CFGR_OFFSET (RCC_OFFSET + 0x04) |
Definition at line 91 of file stm32f30x_rcc.c.
#define CFGR_OFFSET (RCC_OFFSET + 0x08) |
Definition at line 91 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CFGR_OFFSET (RCC_OFFSET + 0x08) |
Definition at line 95 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) |
Definition at line 93 of file stm32f30x_rcc.c.
#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) |
Definition at line 124 of file stm32f30x_rcc.c.
#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) |
Definition at line 127 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) |
Definition at line 143 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) |
Definition at line 127 of file stm32f30x_rcc.c.
#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) |
Definition at line 130 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) |
Definition at line 146 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002) |
Definition at line 130 of file stm32f30x_rcc.c.
#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) |
Definition at line 124 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) |
Definition at line 140 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
Definition at line 81 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
Definition at line 81 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
Definition at line 87 of file stm32f30x_rcc.c.
#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
Definition at line 78 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
Definition at line 78 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
Definition at line 79 of file stm32f30x_rcc.c.
#define CR_OFFSET (RCC_OFFSET + 0x00) |
Definition at line 76 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CR_OFFSET (RCC_OFFSET + 0x00) |
Definition at line 76 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CR_OFFSET (RCC_OFFSET + 0x00) |
Definition at line 77 of file stm32f30x_rcc.c.
#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) |
Definition at line 87 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) |
Definition at line 87 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
Definition at line 83 of file stm32f30x_rcc.c.
#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
Definition at line 84 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
Definition at line 84 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) |
Definition at line 91 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
Definition at line 108 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
Definition at line 112 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
Definition at line 114 of file stm32f30x_rcc.c.
#define CSR_OFFSET (RCC_OFFSET + 0x74) |
Definition at line 106 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CSR_OFFSET (RCC_OFFSET + 0x74) |
Definition at line 110 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CSR_OFFSET (RCC_OFFSET + 0x24) |
Definition at line 112 of file stm32f30x_rcc.c.
#define CSSON_BitNumber 0x13 |
Definition at line 80 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define CSSON_BitNumber 0x13 |
Definition at line 80 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define CSSON_BitNumber 0x13 |
Definition at line 86 of file stm32f30x_rcc.c.
#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) |
Definition at line 112 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) |
Definition at line 116 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) |
Definition at line 114 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) |
Definition at line 118 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define FLAG_MASK ((uint8_t)0x1F) |
Definition at line 118 of file stm32f30x_rcc.c.
#define FLAG_MASK ((uint8_t)0x1F) |
Definition at line 121 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define FLAG_MASK ((uint8_t)0x1F) |
Definition at line 137 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define HSION_BitNumber 0x00 |
Definition at line 77 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define HSION_BitNumber 0x00 |
Definition at line 77 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define HSION_BitNumber 0x00 |
Definition at line 78 of file stm32f30x_rcc.c.
#define I2SSRC_BitNumber 0x17 |
Definition at line 92 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define I2SSRC_BitNumber 0x17 |
Definition at line 95 of file stm32f30x_rcc.c.
#define I2SSRC_BitNumber 0x17 |
Definition at line 96 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define LSION_BitNumber 0x00 |
Definition at line 107 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define LSION_BitNumber 0x00 |
Definition at line 111 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define LSION_BitNumber 0x00 |
Definition at line 113 of file stm32f30x_rcc.c.
#define PLLI2SON_BitNumber 0x1A |
Definition at line 86 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define PLLI2SON_BitNumber 0x1A |
Definition at line 86 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define PLLON_BitNumber 0x18 |
Definition at line 82 of file stm32f30x_rcc.c.
#define PLLON_BitNumber 0x18 |
Definition at line 83 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define PLLON_BitNumber 0x18 |
Definition at line 83 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define PLLSAION_BitNumber 0x1C |
Definition at line 90 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) |
Definition at line 121 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
Definition at line 72 of file stm32f30x_rcc.c.
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
Definition at line 73 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
Definition at line 73 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define RTCEN_BitNumber 0x0F |
Definition at line 98 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define RTCEN_BitNumber 0x0F |
Definition at line 102 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define RTCEN_BitNumber 0x0F |
Definition at line 102 of file stm32f30x_rcc.c.
#define TIMPRE_BitNumber 0x18 |
Definition at line 113 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
#define TIMPRE_BitNumber 0x18 |
Definition at line 117 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
#define USBPRE_BitNumber 0x16 |
Definition at line 92 of file stm32f30x_rcc.c.
void RCC_AdjustHSICalibrationValue | ( | uint8_t | HSICalibrationValue | ) |
Adjusts the Internal High Speed oscillator (HSI) calibration value.
HSICalibrationValue | specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F. |
None |
HSICalibrationValue | specifies the HSI calibration trimming value. This parameter must be a number between 0 and 0x1F. |
None |
HSICalibrationValue | specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F. |
None |
Definition at line 339 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_AHB1PeriphClockCmd | ( | uint32_t | RCC_AHB1Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB1 peripheral clock.
RCC_AHBPeriph | specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_AHBPeriph | specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 1885 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_AHB1PeriphClockLPModeCmd | ( | uint32_t | RCC_AHB1Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
RCC_AHBPeriph | specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_AHBPeriph | specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2296 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_AHB1PeriphResetCmd | ( | uint32_t | RCC_AHB1Periph, |
FunctionalState | NewState | ||
) |
Forces or releases AHB1 peripheral reset.
RCC_AHB1Periph | specifies the AHB1 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
RCC_AHB1Periph | specifies the AHB1 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2094 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_AHB2PeriphClockCmd | ( | uint32_t | RCC_AHB2Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB2 peripheral clock.
RCC_AHBPeriph | specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 1917 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_AHB2PeriphClockLPModeCmd | ( | uint32_t | RCC_AHB2Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
RCC_AHBPeriph | specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2328 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_AHB2PeriphResetCmd | ( | uint32_t | RCC_AHB2Periph, |
FunctionalState | NewState | ||
) |
Forces or releases AHB2 peripheral reset.
RCC_AHB2Periph | specifies the AHB2 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
RCC_AHB2Periph | specifies the AHB2 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2123 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_AHB3PeriphClockCmd | ( | uint32_t | RCC_AHB3Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB3 peripheral clock.
RCC_AHBPeriph | specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC |
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 1190 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
void RCC_AHB3PeriphClockLPModeCmd | ( | uint32_t | RCC_AHB3Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
RCC_AHBPeriph | specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC |
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 1572 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
void RCC_AHB3PeriphResetCmd | ( | uint32_t | RCC_AHB3Periph, |
FunctionalState | NewState | ||
) |
Forces or releases AHB3 peripheral reset.
RCC_AHB3Periph | specifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC |
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 1378 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
void RCC_APB1PeriphClockCmd | ( | uint32_t | RCC_APB1Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the Low Speed APB (APB1) peripheral clock.
RCC_APB1Periph | specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB1Periph | specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB1Periph | specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB1Periph | specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2004 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_APB1PeriphClockLPModeCmd | ( | uint32_t | RCC_APB1Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
RCC_APB1Periph | specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB1Periph | specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2415 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_APB1PeriphResetCmd | ( | uint32_t | RCC_APB1Periph, |
FunctionalState | NewState | ||
) |
Forces or releases Low Speed APB (APB1) peripheral reset.
RCC_APB1Periph | specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB1Periph | specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB1Periph | specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB1Periph | specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2204 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_APB2PeriphClockCmd | ( | uint32_t | RCC_APB2Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the High Speed APB (APB2) peripheral clock.
RCC_APB2Periph | specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB2Periph | specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB2Periph | specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB2Periph | specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2051 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_APB2PeriphClockLPModeCmd | ( | uint32_t | RCC_APB2Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
RCC_APB2Periph | specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB2Periph | specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2462 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_APB2PeriphResetCmd | ( | uint32_t | RCC_APB2Periph, |
FunctionalState | NewState | ||
) |
Forces or releases High Speed APB (APB2) peripheral reset.
RCC_APB2Periph | specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB2Periph | specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB2Periph | specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
RCC_APB2Periph | specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
|
NewState | new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2247 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_BackupResetCmd | ( | FunctionalState | NewState | ) |
Forces or releases the Backup domain reset.
NewState | new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 1519 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_ClearFlag | ( | void | ) |
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
Clears the RCC reset flags. The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
None |
None | Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. |
None |
None |
Definition at line 2870 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_ClearITPendingBit | ( | uint8_t | RCC_IT | ) |
Clears the RCC's interrupt pending bits.
RCC_IT | specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
|
None |
RCC_IT | specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
|
None |
RCC_IT | specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
|
None |
RCC_IT | specifies the interrupt pending bit to clear. |
For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:
For other_STM32_devices, this parameter can be any combination of the following values:
None |
Definition at line 2924 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_ClockSecuritySystemCmd | ( | FunctionalState | NewState | ) |
Enables or disables the Clock Security System.
NewState | new state of the Clock Security System. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the Clock Security System.. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 879 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_DeInit | ( | void | ) |
Resets the RCC clock configuration to the default reset state.
None |
None |
None |
None |
None |
None |
Definition at line 225 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_GetClocksFreq | ( | RCC_ClocksTypeDef * | RCC_Clocks | ) |
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
RCC_Clocks | pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. |
None |
RCC_Clocks | pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. |
None | Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. |
RCC_Clocks | pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. |
None |
Definition at line 1317 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
FlagStatus RCC_GetFlagStatus | ( | uint8_t | RCC_FLAG | ) |
Checks whether the specified RCC flag is set or not.
RCC_FLAG | specifies the flag to check. This parameter can be one of the following values:
|
The | new state of RCC_FLAG (SET or RESET). |
RCC_FLAG | specifies the flag to check. This parameter can be one of the following values:
|
The | new state of RCC_FLAG (SET or RESET). |
RCC_FLAG | specifies the flag to check. This parameter can be one of the following values:
|
The | new state of RCC_FLAG (SET or RESET). |
RCC_FLAG | specifies the flag to check. |
For STM32_Connectivity_line_devices, this parameter can be one of the following values:
For other_STM32_devices, this parameter can be one of the following values:
The | new state of RCC_FLAG (SET or RESET). |
Definition at line 2825 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
ITStatus RCC_GetITStatus | ( | uint8_t | RCC_IT | ) |
Checks whether the specified RCC interrupt has occurred or not.
RCC_IT | specifies the RCC interrupt source to check. This parameter can be one of the following values:
|
The | new state of RCC_IT (SET or RESET). |
RCC_IT | specifies the RCC interrupt source to check. This parameter can be one of the following values:
|
The | new state of RCC_IT (SET or RESET). |
RCC_IT | specifies the RCC interrupt source to check. This parameter can be one of the following values:
|
The | new state of RCC_IT (SET or RESET). |
RCC_IT | specifies the RCC interrupt source to check. |
For STM32_Connectivity_line_devices, this parameter can be one of the following values:
For other_STM32_devices, this parameter can be one of the following values:
The | new state of RCC_IT (SET or RESET). |
Definition at line 2890 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
uint8_t RCC_GetSYSCLKSource | ( | void | ) |
Returns the clock source used as system clock.
None |
The | clock source used as system clock. The returned value can be one of the following:
|
None |
The | clock source used as system clock. The returned value can be one of the following:
|
None |
The | clock source used as system clock. The returned value can be one of the following values:
|
None |
The | clock source used as system clock. The returned value can be one of the following:
|
Definition at line 1178 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_HCLKConfig | ( | uint32_t | RCC_SYSCLK | ) |
Configures the AHB clock (HCLK).
RCC_SYSCLK | defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
|
None |
RCC_SYSCLK | defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
|
None |
RCC_SYSCLK | defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
|
None |
Definition at line 1203 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_HSEConfig | ( | uint8_t | RCC_HSE | ) |
Configures the External High Speed oscillator (HSE).
RCC_HSE | specifies the new state of the HSE. This parameter can be one of the following values:
|
None |
RCC_HSE | specifies the new state of the HSE. This parameter can be one of the following values:
|
None |
Definition at line 284 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_HSICmd | ( | FunctionalState | NewState | ) |
Enables or disables the Internal High Speed oscillator (HSI).
NewState | new state of the HSI. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the HSI. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the HSI. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 375 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_ITConfig | ( | uint8_t | RCC_IT, |
FunctionalState | NewState | ||
) |
Enables or disables the specified RCC interrupts.
RCC_IT | specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
|
NewState | new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE. |
None |
RCC_IT | specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
|
NewState | new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE. |
None |
RCC_IT | specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
|
NewState | new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE. |
None |
RCC_IT | specifies the RCC interrupt sources to be enabled or disabled. |
For STM32_Connectivity_line_devices, this parameter can be any combination of the following values
For other_STM32_devices, this parameter can be any combination of the following values
NewState | new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 2788 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_LSEConfig | ( | uint8_t | RCC_LSE | ) |
Configures the External Low Speed oscillator (LSE).
RCC_LSE | specifies the new state of the LSE. This parameter can be one of the following values:
|
None |
RCC_LSE | specifies the new state of the LSE. This parameter can be one of the following values:
|
None |
Definition at line 400 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_LSEModeConfig | ( | uint8_t | RCC_Mode | ) |
Configures the External Low Speed oscillator mode (LSE mode).
Mode | specifies the LSE mode. This parameter can be one of the following values:
|
None |
Definition at line 2486 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_LSICmd | ( | FunctionalState | NewState | ) |
Enables or disables the Internal Low Speed oscillator (LSI).
NewState | new state of the LSI. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the LSI. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the LSI. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 440 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_LTDCCLKDivConfig | ( | uint32_t | RCC_PLLSAIDivR | ) |
Configures the LTDC clock Divider coming from PLLSAI.
RCC_PLLSAIDivR | specifies the PLLSAI division factor for LTDC clock . LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR This parameter can be one of the following values:
|
None |
Definition at line 1806 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_MCO1Config | ( | uint32_t | RCC_MCO1Source, |
uint32_t | RCC_MCO1Div | ||
) |
Selects the clock source to output on MCO1 pin(PA8).
RCC_MCO1Source | specifies the clock source to output. This parameter can be one of the following values:
|
RCC_MCO1Div | specifies the MCO1 prescaler. This parameter can be one of the following values:
|
None |
Definition at line 904 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_MCO2Config | ( | uint32_t | RCC_MCO2Source, |
uint32_t | RCC_MCO2Div | ||
) |
Selects the clock source to output on MCO2 pin(PC9).
RCC_MCO2Source | specifies the clock source to output. This parameter can be one of the following values:
|
RCC_MCO2Div | specifies the MCO2 prescaler. This parameter can be one of the following values:
|
None |
RCC_MCO2Source | specifies the clock source to output. This parameter can be one of the following values:
|
RCC_MCO2Div | specifies the MCO2 prescaler. This parameter can be one of the following values:
|
None |
Definition at line 949 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_PCLK1Config | ( | uint32_t | RCC_HCLK | ) |
Configures the Low Speed APB clock (PCLK1).
RCC_HCLK | defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
|
None |
Definition at line 1234 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_PCLK2Config | ( | uint32_t | RCC_HCLK | ) |
Configures the High Speed APB clock (PCLK2).
RCC_HCLK | defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
|
None |
Definition at line 1265 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_PLLCmd | ( | FunctionalState | NewState | ) |
Enables or disables the main PLL.
Enables or disables the PLL.
NewState | new state of the main PLL. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the PLL. This parameter can be: ENABLE or DISABLE. |
None | Enables or disables the main PLL. |
NewState | new state of the PLL. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 563 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_PLLConfig | ( | uint32_t | RCC_PLLSource, |
uint32_t | PLLM, | ||
uint32_t | PLLN, | ||
uint32_t | PLLP, | ||
uint32_t | PLLQ | ||
) |
Configures the main PLL clock source, multiplication and division factors.
RCC_PLLSource | specifies the PLL entry clock source. This parameter can be one of the following values:
|
PLLM | specifies the division factor for PLL VCO input clock This parameter must be a number between 0 and 63. |
PLLN | specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 192 and 432. |
PLLP | specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}. |
PLLQ | specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between 4 and 15. |
None |
Definition at line 454 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
void RCC_PLLI2SCmd | ( | FunctionalState | NewState | ) |
Enables or disables the PLLI2S.
NewState | new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 732 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_PLLI2SConfig | ( | uint32_t | PLLI2SN, |
uint32_t | PLLI2SR | ||
) |
Configures the PLLI2S clock multiplication and division factors.
PLLI2SN | specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between 192 and 432. |
PLLI2SR | specifies the division factor for I2S clock This parameter must be a number between 2 and 7. |
None |
Definition at line 503 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
void RCC_PLLSAICmd | ( | FunctionalState | NewState | ) |
Enables or disables the PLLSAI.
NewState | new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 861 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_RTCCLKCmd | ( | FunctionalState | NewState | ) |
Enables or disables the RTC clock.
NewState | new state of the RTC clock. This parameter can be: ENABLE or DISABLE. |
None |
NewState | new state of the RTC clock. This parameter can be: ENABLE or DISABLE. |
None |
Definition at line 1502 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_RTCCLKConfig | ( | uint32_t | RCC_RTCCLKSource | ) |
Configures the RTC clock (RTCCLK).
RCC_RTCCLKSource | specifies the RTC clock source. This parameter can be one of the following values:
|
None |
RCC_RTCCLKSource | specifies the RTC clock source. This parameter can be one of the following values:
|
None |
RCC_RTCCLKSource | specifies the RTC clock source. This parameter can be one of the following values:
|
None |
Definition at line 1470 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_SAIPLLI2SClkDivConfig | ( | uint32_t | RCC_PLLI2SDivQ | ) |
Configures the SAI clock Divider coming from PLLI2S.
RCC_PLLI2SDivQ | specifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ |
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Definition at line 1738 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_SAIPLLSAIClkDivConfig | ( | uint32_t | RCC_PLLSAIDivQ | ) |
Configures the SAI clock Divider coming from PLLSAI.
RCC_PLLSAIDivQ | specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ |
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Definition at line 1770 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_SYSCLKConfig | ( | uint32_t | RCC_SYSCLKSource | ) |
Configures the system clock (SYSCLK).
RCC_SYSCLKSource | specifies the clock source used as system clock. This parameter can be one of the following values:
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RCC_SYSCLKSource | specifies the clock source used as system clock. This parameter can be one of the following values:
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RCC_SYSCLKSource | specifies the clock source used as system clock source This parameter can be one of the following values:
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RCC_SYSCLKSource | specifies the clock source used as system clock. This parameter can be one of the following values:
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Definition at line 1149 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
void RCC_TIMCLKPresConfig | ( | uint32_t | RCC_TIMCLKPrescaler | ) |
Configures the Timers clocks prescalers selection.
RCC_TIMCLKPrescaler | : specifies the Timers clocks prescalers selection This parameter can be one of the following values:
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RCC_TIMCLKPrescaler | : specifies the Timers clocks prescalers selection This parameter can be one of the following values:
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Definition at line 1843 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
ErrorStatus RCC_WaitForHSEStartUp | ( | void | ) |
Waits for HSE start-up.
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An | ErrorStatus enumeration value:
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An | ErrorStatus enumeration value:
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An | ErrorStatus enumuration value:
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Definition at line 308 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
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Definition at line 135 of file stm32f30x_rcc.c.
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Definition at line 134 of file stm32f30x_rcc.c.
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Definition at line 137 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.
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Definition at line 153 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.