System, AHB and APB busses clocks configuration functions. More...
Collaboration diagram for System AHB and APB busses clocks configuration functions:
|
Functions | |
| void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks) |
| Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More... | |
| uint8_t | RCC_GetSYSCLKSource (void) |
| Returns the clock source used as system clock. More... | |
| void | RCC_HCLKConfig (uint32_t RCC_SYSCLK) |
| Configures the AHB clock (HCLK). More... | |
| void | RCC_PCLK1Config (uint32_t RCC_HCLK) |
| Configures the Low Speed APB clock (PCLK1). More... | |
| void | RCC_PCLK2Config (uint32_t RCC_HCLK) |
| Configures the High Speed APB clock (PCLK2). More... | |
| void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource) |
| Configures the system clock (SYSCLK). More... | |
Detailed Description
System, AHB and APB busses clocks configuration functions.
===============================================================================
##### System, AHB and APB busses clocks configuration functions #####
===============================================================================
[..]
This section provide functions allowing to configure the System, AHB, APB1 and
APB2 busses clocks.
(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
The AHB clock (HCLK) is derived from System clock through configurable
prescaler and used to clock the CPU, memory and peripherals mapped
on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
from AHB clock through configurable prescalers and used to clock
the peripherals mapped on these busses. You can use
"RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
(+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
from an external clock mapped on the I2S_CKIN pin.
You have to use RCC_I2SCLKConfig() function to configure this clock.
(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
functions to configure this clock.
(+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
to work correctly, while the SDIO require a frequency equal or lower than
to 48. This clock is derived of the main PLL through PLLQ divider.
(+@) IWDG clock which is always the LSI clock.
(#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency
of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending
on the device voltage range, the maximum frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
+---------------|----------------|----------------|-----------------|-----------------+
(#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz,
PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
|---------------|----------------|----------------|-----------------|-----------------|
|8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
+-------------------------------------------------------------------------------------+
(#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
+-------------------------------------------------------------------------------------+
(#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
+-------------------------------------------------------------------------------------+
-@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
(++) when VOS = '0', the maximum value of fHCLK = 144MHz.
(++) when VOS = '1', the maximum value of fHCLK = 168MHz.
[..]
On STM32F42xxx/43xxx/469xx/479xx devices:
(++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
(++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
(++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
[..]
On STM32F401x devices:
(++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
(++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
On STM32F410xx/STM32F411xE devices:
(++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz.
(++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz.
(++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz.
You can use PWR_MainRegulatorModeConfig() function to control VOS bits. ===============================================================================
##### System, AHB and APB busses clocks configuration functions #####
===============================================================================
[..]
This section provide functions allowing to configure the System, AHB, APB1 and
APB2 busses clocks.
(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
The AHB clock (HCLK) is derived from System clock through configurable
prescaler and used to clock the CPU, memory and peripherals mapped
on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
from AHB clock through configurable prescalers and used to clock
the peripherals mapped on these busses. You can use
"RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
(+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
from an external clock mapped on the I2S_CKIN pin.
You have to use RCC_I2SCLKConfig() function to configure this clock.
(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
functions to configure this clock.
(+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
to work correctly, while the SDIO require a frequency equal or lower than
to 48. This clock is derived of the main PLL through PLLQ divider.
(+@) IWDG clock which is always the LSI clock.
(#) The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz
and PCLK1 42 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
+-------------------------------------------------------------------------------------+
-@- When VOS bits (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit. ===============================================================================
##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
===============================================================================
[..] This section provide functions allowing to configure the System, AHB, APB1 and
APB2 busses clocks.
(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
The AHB clock (HCLK) is derived from System clock through configurable prescaler
and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
configurable prescalers and used to clock the peripherals mapped on these busses.
You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
(#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
Depending on the maximum frequency, the FLASH wait states (WS) should be
adapted accordingly:
+---------------------------------+
| Wait states | HCLK clock |
| (Latency) | frequency (MHz) |
|-------------- |-----------------|
|0WS(1CPU cycle)| 0 < HCLK <= 24 |
|---------------|-----------------|
|1WS(2CPU cycle)|24 < HCLK <=48 |
|---------------|-----------------|
|2WS(3CPU cycle)|48 < HCLK <= 72 |
+---------------------------------+
(#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
prefetch is disabled.
[..]
(@) All the peripheral clocks are derived from the System clock (SYSCLK)
except:
(+@) The FLASH program/erase clock which is always HSI 8MHz clock.
(+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
(+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
(+@) The I2C clock which can be derived as well from HSI 8MHz clock.
(+@) The ADC clock which is derived from PLL output.
(+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
(HSE divided by a programmable prescaler). The System clock (SYSCLK)
frequency must be higher or equal to the RTC clock frequency.
(+@) IWDG clock which is always the LSI clock.
[..] It is recommended to use the following software sequences to tune the number
of wait states needed to access the Flash memory with the CPU frequency (HCLK).
(+) Increasing the CPU frequency
(++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
function
(++) Check that Flash Prefetch buffer activation is taken into account by
reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
(++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
(++) Check that the new number of WS is taken into account by reading FLASH_ACR
(++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
(++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
(++) Check that the new CPU clock source is taken into account by reading
the clock source status, using "RCC_GetSYSCLKSource()" function
(+) Decreasing the CPU frequency
(++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
(++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
(++) Check that the new CPU clock source is taken into account by reading
the clock source status, using "RCC_GetSYSCLKSource()" function
(++) Program the new number of WS, using "FLASH_SetLatency()" function
(++) Check that the new number of WS is taken into account by reading FLASH_ACR
(++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
function
(++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
using the FLASH_GetPrefetchBufferStatus() function. Function Documentation
| void RCC_GetClocksFreq | ( | RCC_ClocksTypeDef * | RCC_Clocks | ) |
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
- Note
- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
- If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
- (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
- (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
- The result of this function could be not correct when using fractional value for HSE crystal.
- Parameters
-
RCC_Clocks pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
- Note
- This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
- Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
- Return values
-
None
- Note
- This function returns the frequencies of : System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks, USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks.
- The frequency returned by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the source selected by RCC_SYSCLKConfig().
- If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
- If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
- If SYSCLK source is PLL, function returns constant HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.
- (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value 8 MHz) but the real value may vary depending on the variations in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
- (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may return wrong result.
- The result of this function could be not correct when using fractional value for HSE crystal.
- Parameters
-
RCC_Clocks pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
- Note
- This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
- Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
- Return values
-
None
Definition at line 1317 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
| uint8_t RCC_GetSYSCLKSource | ( | void | ) |
Returns the clock source used as system clock.
- Parameters
-
None
- Return values
-
The clock source used as system clock. The returned value can be one of the following: - 0x00: HSI used as system clock
- 0x04: HSE used as system clock
- 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
- 0x0C: PLL R used as system clock (only for STM32F446xx devices)
- Parameters
-
None
- Return values
-
The clock source used as system clock. The returned value can be one of the following: - 0x00: HSI used as system clock
- 0x04: HSE used as system clock
- 0x08: PLL used as system clock
- Parameters
-
None
- Return values
-
The clock source used as system clock. The returned value can be one of the following values: - 0x00: HSI used as system clock
- 0x04: HSE used as system clock
- 0x08: PLL used as system clock
Definition at line 1178 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
| void RCC_HCLKConfig | ( | uint32_t | RCC_SYSCLK | ) |
Configures the AHB clock (HCLK).
- Note
- Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
- Parameters
-
RCC_SYSCLK defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values: - RCC_SYSCLK_Div1: AHB clock = SYSCLK
- RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- Return values
-
None
- Note
- Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions").
- Parameters
-
RCC_SYSCLK defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values: - RCC_SYSCLK_Div1: AHB clock = SYSCLK
- RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- Return values
-
None
Definition at line 1203 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
| void RCC_PCLK1Config | ( | uint32_t | RCC_HCLK | ) |
Configures the Low Speed APB clock (PCLK1).
- Parameters
-
RCC_HCLK defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values: - RCC_HCLK_Div1: APB1 clock = HCLK
- RCC_HCLK_Div2: APB1 clock = HCLK/2
- RCC_HCLK_Div4: APB1 clock = HCLK/4
- RCC_HCLK_Div8: APB1 clock = HCLK/8
- RCC_HCLK_Div16: APB1 clock = HCLK/16
- Return values
-
None
Definition at line 1234 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
| void RCC_PCLK2Config | ( | uint32_t | RCC_HCLK | ) |
Configures the High Speed APB clock (PCLK2).
- Parameters
-
RCC_HCLK defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values: - RCC_HCLK_Div1: APB2 clock = HCLK
- RCC_HCLK_Div2: APB2 clock = HCLK/2
- RCC_HCLK_Div4: APB2 clock = HCLK/4
- RCC_HCLK_Div8: APB2 clock = HCLK/8
- RCC_HCLK_Div16: APB2 clock = HCLK/16
- Return values
-
None
Definition at line 1265 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.
| void RCC_SYSCLKConfig | ( | uint32_t | RCC_SYSCLKSource | ) |
Configures the system clock (SYSCLK).
- Note
- The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
- A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
- Parameters
-
RCC_SYSCLKSource specifies the clock source used as system clock. This parameter can be one of the following values: - RCC_SYSCLKSource_HSI: HSI selected as system clock source
- RCC_SYSCLKSource_HSE: HSE selected as system clock source
- RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
- RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F446xx devices
- Return values
-
None
- Note
- The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
- A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
- Parameters
-
RCC_SYSCLKSource specifies the clock source used as system clock. This parameter can be one of the following values: - RCC_SYSCLKSource_HSI: HSI selected as system clock source
- RCC_SYSCLKSource_HSE: HSE selected as system clock source
- RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- Return values
-
None
- Note
- The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
- A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
- Parameters
-
RCC_SYSCLKSource specifies the clock source used as system clock source This parameter can be one of the following values: - RCC_SYSCLKSource_HSI: HSI selected as system clock source
- RCC_SYSCLKSource_HSE: HSE selected as system clock source
- RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- Return values
-
None
Definition at line 1149 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.