stm32f7xx_hal_dma.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_HAL_DMA_H
22 #define __STM32F7xx_HAL_DMA_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
40 
49 typedef struct
50 {
51  uint32_t Channel;
54  uint32_t Direction;
58  uint32_t PeriphInc;
61  uint32_t MemInc;
64  uint32_t PeriphDataAlignment;
67  uint32_t MemDataAlignment;
70  uint32_t Mode;
75  uint32_t Priority;
78  uint32_t FIFOMode;
83  uint32_t FIFOThreshold;
86  uint32_t MemBurst;
92  uint32_t PeriphBurst;
97 }DMA_InitTypeDef;
98 
102 typedef enum
103 {
104  HAL_DMA_STATE_RESET = 0x00U,
105  HAL_DMA_STATE_READY = 0x01U,
106  HAL_DMA_STATE_BUSY = 0x02U,
107  HAL_DMA_STATE_TIMEOUT = 0x03U,
108  HAL_DMA_STATE_ERROR = 0x04U,
109  HAL_DMA_STATE_ABORT = 0x05U,
110 }HAL_DMA_StateTypeDef;
111 
115 typedef enum
116 {
117  HAL_DMA_FULL_TRANSFER = 0x00U,
118  HAL_DMA_HALF_TRANSFER = 0x01U,
119 }HAL_DMA_LevelCompleteTypeDef;
120 
124 typedef enum
125 {
126  HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
127  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
128  HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
129  HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
130  HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
131  HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
132  HAL_DMA_XFER_ALL_CB_ID = 0x06U
133 }HAL_DMA_CallbackIDTypeDef;
134 
138 typedef struct __DMA_HandleTypeDef
139 {
140  DMA_Stream_TypeDef *Instance;
142  DMA_InitTypeDef Init;
144  HAL_LockTypeDef Lock;
146  __IO HAL_DMA_StateTypeDef State;
148  void *Parent;
150  void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);
152  void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
154  void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);
156  void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
158  void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);
160  void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);
162  __IO uint32_t ErrorCode;
164  uint32_t StreamBaseAddress;
166  uint32_t StreamIndex;
168 }DMA_HandleTypeDef;
169 
175 /* Exported constants --------------------------------------------------------*/
176 
186 #define HAL_DMA_ERROR_NONE 0x00000000U
187 #define HAL_DMA_ERROR_TE 0x00000001U
188 #define HAL_DMA_ERROR_FE 0x00000002U
189 #define HAL_DMA_ERROR_DME 0x00000004U
190 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U
191 #define HAL_DMA_ERROR_PARAM 0x00000040U
192 #define HAL_DMA_ERROR_NO_XFER 0x00000080U
193 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
202 #define DMA_PERIPH_TO_MEMORY 0x00000000U
203 #define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0
204 #define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1
213 #define DMA_PINC_ENABLE DMA_SxCR_PINC
214 #define DMA_PINC_DISABLE 0x00000000U
223 #define DMA_MINC_ENABLE DMA_SxCR_MINC
224 #define DMA_MINC_DISABLE 0x00000000U
233 #define DMA_PDATAALIGN_BYTE 0x00000000U
234 #define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0
235 #define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1
244 #define DMA_MDATAALIGN_BYTE 0x00000000U
245 #define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0
246 #define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1
255 #define DMA_NORMAL 0x00000000U
256 #define DMA_CIRCULAR DMA_SxCR_CIRC
257 #define DMA_PFCTRL DMA_SxCR_PFCTRL
266 #define DMA_PRIORITY_LOW 0x00000000U
267 #define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0
268 #define DMA_PRIORITY_HIGH DMA_SxCR_PL_1
269 #define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL
278 #define DMA_FIFOMODE_DISABLE 0x00000000U
279 #define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS
288 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U
289 #define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0
290 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1
291 #define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH
300 #define DMA_MBURST_SINGLE 0x00000000U
301 #define DMA_MBURST_INC4 DMA_SxCR_MBURST_0
302 #define DMA_MBURST_INC8 DMA_SxCR_MBURST_1
303 #define DMA_MBURST_INC16 DMA_SxCR_MBURST
304 
312 #define DMA_PBURST_SINGLE 0x00000000U
313 #define DMA_PBURST_INC4 DMA_SxCR_PBURST_0
314 #define DMA_PBURST_INC8 DMA_SxCR_PBURST_1
315 #define DMA_PBURST_INC16 DMA_SxCR_PBURST
316 
324 #define DMA_IT_TC DMA_SxCR_TCIE
325 #define DMA_IT_HT DMA_SxCR_HTIE
326 #define DMA_IT_TE DMA_SxCR_TEIE
327 #define DMA_IT_DME DMA_SxCR_DMEIE
328 #define DMA_IT_FE 0x00000080U
329 
337 #define DMA_FLAG_FEIF0_4 0x00000001U
338 #define DMA_FLAG_DMEIF0_4 0x00000004U
339 #define DMA_FLAG_TEIF0_4 0x00000008U
340 #define DMA_FLAG_HTIF0_4 0x00000010U
341 #define DMA_FLAG_TCIF0_4 0x00000020U
342 #define DMA_FLAG_FEIF1_5 0x00000040U
343 #define DMA_FLAG_DMEIF1_5 0x00000100U
344 #define DMA_FLAG_TEIF1_5 0x00000200U
345 #define DMA_FLAG_HTIF1_5 0x00000400U
346 #define DMA_FLAG_TCIF1_5 0x00000800U
347 #define DMA_FLAG_FEIF2_6 0x00010000U
348 #define DMA_FLAG_DMEIF2_6 0x00040000U
349 #define DMA_FLAG_TEIF2_6 0x00080000U
350 #define DMA_FLAG_HTIF2_6 0x00100000U
351 #define DMA_FLAG_TCIF2_6 0x00200000U
352 #define DMA_FLAG_FEIF3_7 0x00400000U
353 #define DMA_FLAG_DMEIF3_7 0x01000000U
354 #define DMA_FLAG_TEIF3_7 0x02000000U
355 #define DMA_FLAG_HTIF3_7 0x04000000U
356 #define DMA_FLAG_TCIF3_7 0x08000000U
357 
365 /* Exported macro ------------------------------------------------------------*/
366 
371 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
372 
385 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
386 
392 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
393 
399 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
400 
401 /* Interrupt & Flag management */
402 
408 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
409 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
410  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
411  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
412  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
413  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
414  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
415  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
416  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
417  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
418  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
419  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
420  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
421  DMA_FLAG_TCIF3_7)
422 
428 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
429 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
430  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
431  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
432  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
433  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
434  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
435  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
436  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
437  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
438  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
439  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
440  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
441  DMA_FLAG_HTIF3_7)
442 
448 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
449 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
450  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
451  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
452  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
453  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
454  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
455  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
456  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
457  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
458  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
459  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
460  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
461  DMA_FLAG_TEIF3_7)
462 
468 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
469 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
470  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
471  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
472  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
473  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
474  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
475  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
481  DMA_FLAG_FEIF3_7)
482 
488 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
489 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
490  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
491  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
492  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
493  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
495  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
498  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
499  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
500  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
501  DMA_FLAG_DMEIF3_7)
502 
516 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
517 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
518  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
519  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
520 
534 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
535 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
536  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
537  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
538 
551 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
552 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
553 
566 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
567 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
568 
581 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
582  ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
583  ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
584 
602 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
603 
610 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
611 
612 
613 /* Include DMA HAL Extension module */
614 #include "stm32f7xx_hal_dma_ex.h"
615 
616 /* Exported functions --------------------------------------------------------*/
617 
627 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
628 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
637 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
638 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
639 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
640 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
641 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
642 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
643 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
644 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
645 
654 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
655 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
662 /* Private Constants -------------------------------------------------------------*/
671 /* Private macros ------------------------------------------------------------*/
676 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
677  ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
678  ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
679 
680 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
681 
682 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
683  ((STATE) == DMA_PINC_DISABLE))
684 
685 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
686  ((STATE) == DMA_MINC_DISABLE))
687 
688 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
689  ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
690  ((SIZE) == DMA_PDATAALIGN_WORD))
691 
692 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
693  ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
694  ((SIZE) == DMA_MDATAALIGN_WORD ))
695 
696 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
697  ((MODE) == DMA_CIRCULAR) || \
698  ((MODE) == DMA_PFCTRL))
699 
700 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
701  ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
702  ((PRIORITY) == DMA_PRIORITY_HIGH) || \
703  ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
704 
705 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
706  ((STATE) == DMA_FIFOMODE_ENABLE))
707 
708 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
709  ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
710  ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
711  ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
712 
713 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
714  ((BURST) == DMA_MBURST_INC4) || \
715  ((BURST) == DMA_MBURST_INC8) || \
716  ((BURST) == DMA_MBURST_INC16))
717 
718 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
719  ((BURST) == DMA_PBURST_INC4) || \
720  ((BURST) == DMA_PBURST_INC8) || \
721  ((BURST) == DMA_PBURST_INC16))
722 
726 /* Private functions ---------------------------------------------------------*/
743 #ifdef __cplusplus
744 }
745 #endif
746 
747 #endif /* __STM32F7xx_HAL_DMA_H */
748 
749 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
Definition: stm32f7xx_hal_dma.h:106
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Definition: stm32f7xx_hal_dma.h:130
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f407xx.h:346
__DMA_HandleTypeDef::XferHalfCpltCallback
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:153
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
__DMA_HandleTypeDef::StreamIndex
uint32_t StreamIndex
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:167
__DMA_HandleTypeDef::StreamBaseAddress
uint32_t StreamBaseAddress
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:165
__DMA_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:163
DMA_InitTypeDef
DMA Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:49
HAL_DMA_Abort_IT
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::XferM1CpltCallback
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:155
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
Definition: stm32f7xx_hal_dma.h:108
__DMA_HandleTypeDef::XferAbortCallback
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:161
__DMA_HandleTypeDef::Init
DMA_InitTypeDef Init
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:143
HAL_DMA_STATE_ABORT
@ HAL_DMA_STATE_ABORT
Definition: stm32f7xx_hal_dma.h:109
__DMA_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:145
HAL_DMA_STATE_TIMEOUT
@ HAL_DMA_STATE_TIMEOUT
Definition: stm32f7xx_hal_dma.h:107
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
__DMA_HandleTypeDef::State
__IO HAL_DMA_StateTypeDef State
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:147
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Definition: stm32f7xx_hal_dma.h:131
HAL_DMA_XFER_M1HALFCPLT_CB_ID
@ HAL_DMA_XFER_M1HALFCPLT_CB_ID
Definition: stm32f7xx_hal_dma.h:129
HAL_DMA_FULL_TRANSFER
@ HAL_DMA_FULL_TRANSFER
Definition: stm32f7xx_hal_dma.h:117
HAL_DMA_UnRegisterCallback
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
Definition: stm32f7xx_hal_dma.h:132
HAL_DMA_PollForTransfer
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
HAL_DMA_GetState
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::Instance
DMA_Stream_TypeDef * Instance
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:141
HAL_DMA_CallbackIDTypeDef
HAL_DMA_CallbackIDTypeDef
HAL DMA Error Code structure definition.
Definition: stm32f7xx_hal_dma.h:124
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_DMA_XFER_M1CPLT_CB_ID
@ HAL_DMA_XFER_M1CPLT_CB_ID
Definition: stm32f7xx_hal_dma.h:128
HAL_DMA_Abort
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_DMA_XFER_CPLT_CB_ID
@ HAL_DMA_XFER_CPLT_CB_ID
Definition: stm32f7xx_hal_dma.h:126
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
Definition: stm32f7xx_hal_dma.h:104
__DMA_HandleTypeDef::Parent
void * Parent
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:149
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:151
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_DMA_Init
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
HAL_DMA_HALF_TRANSFER
@ HAL_DMA_HALF_TRANSFER
Definition: stm32f7xx_hal_dma.h:118
HAL_DMA_DeInit
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
HAL_DMA_XFER_HALFCPLT_CB_ID
@ HAL_DMA_XFER_HALFCPLT_CB_ID
Definition: stm32f7xx_hal_dma.h:127
__DMA_HandleTypeDef::XferM1HalfCpltCallback
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:157
HAL_DMA_GetError
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
stm32f7xx_hal_dma_ex.h
Header file of DMA HAL extension module.
HAL_DMA_Start
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_DMA_StateTypeDef
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
Definition: stm32f7xx_hal_dma.h:102
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_LevelCompleteTypeDef
HAL DMA Error Code structure definition.
Definition: stm32f7xx_hal_dma.h:115
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745
HAL_DMA_IRQHandler
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:159
HAL_DMA_RegisterCallback
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition: stm32f7xx_hal_dma.h:105

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autogenerated on Fri Apr 1 2022 02:14:53