picovoice_driver: stm32f7xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_dma_ex.h"

Include dependency graph for stm32f7xx_hal_dma.h:

This graph shows which files directly or indirectly include this file:

Classes
struct	__DMA_HandleTypeDef
	DMA handle Structure definition. More...

struct	DMA_InitTypeDef
	DMA Configuration Structure definition. More...

Macros
#define	__HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
	Clear the DMA Stream pending flags. More...

#define	__HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
	Disable the specified DMA Stream. More...

#define	__HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
	Disable the specified DMA Stream interrupts. More...

#define	__HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= DMA_SxCR_EN)
	Enable the specified DMA Stream. More...

#define	__HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
	Enable the specified DMA Stream interrupts. More...

#define	__HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
	Returns the number of remaining data units in the current DMAy Streamx transfer. More...

#define	__HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
	Return the current DMA Stream direct mode error flag. More...

#define	__HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
	Return the current DMA Stream FIFO error flag. More...

#define	__HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
	Get the DMA Stream pending flags. More...

#define	__HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
	Return the current DMA Stream FIFO filled level. More...

#define	__HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
	Return the current DMA Stream half transfer complete flag. More...

#define	__HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
	Check whether the specified DMA Stream interrupt is enabled or not. More...

#define	__HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
	Return the current DMA Stream transfer complete flag. More...

#define	__HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
	Return the current DMA Stream transfer error flag. More...

#define	__HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
	Reset DMA handle state. More...

#define	__HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
	Writes the number of data units to be transferred on the DMA Stream. More...

#define	DMA_CIRCULAR DMA_SxCR_CIRC

#define	DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U

#define	DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1

#define	DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH

#define	DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0

#define	DMA_FIFOMODE_DISABLE 0x00000000U

#define	DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS

#define	DMA_FLAG_DMEIF0_4 0x00000004U

#define	DMA_FLAG_DMEIF1_5 0x00000100U

#define	DMA_FLAG_DMEIF2_6 0x00040000U

#define	DMA_FLAG_DMEIF3_7 0x01000000U

#define	DMA_FLAG_FEIF0_4 0x00000001U

#define	DMA_FLAG_FEIF1_5 0x00000040U

#define	DMA_FLAG_FEIF2_6 0x00010000U

#define	DMA_FLAG_FEIF3_7 0x00400000U

#define	DMA_FLAG_HTIF0_4 0x00000010U

#define	DMA_FLAG_HTIF1_5 0x00000400U

#define	DMA_FLAG_HTIF2_6 0x00100000U

#define	DMA_FLAG_HTIF3_7 0x04000000U

#define	DMA_FLAG_TCIF0_4 0x00000020U

#define	DMA_FLAG_TCIF1_5 0x00000800U

#define	DMA_FLAG_TCIF2_6 0x00200000U

#define	DMA_FLAG_TCIF3_7 0x08000000U

#define	DMA_FLAG_TEIF0_4 0x00000008U

#define	DMA_FLAG_TEIF1_5 0x00000200U

#define	DMA_FLAG_TEIF2_6 0x00080000U

#define	DMA_FLAG_TEIF3_7 0x02000000U

#define	DMA_IT_DME DMA_SxCR_DMEIE

#define	DMA_IT_FE 0x00000080U

#define	DMA_IT_HT DMA_SxCR_HTIE

#define	DMA_IT_TC DMA_SxCR_TCIE

#define	DMA_IT_TE DMA_SxCR_TEIE

#define	DMA_MBURST_INC16 DMA_SxCR_MBURST

#define	DMA_MBURST_INC4 DMA_SxCR_MBURST_0

#define	DMA_MBURST_INC8 DMA_SxCR_MBURST_1

#define	DMA_MBURST_SINGLE 0x00000000U

#define	DMA_MDATAALIGN_BYTE 0x00000000U

#define	DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0

#define	DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1

#define	DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1

#define	DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0

#define	DMA_MINC_DISABLE 0x00000000U

#define	DMA_MINC_ENABLE DMA_SxCR_MINC

#define	DMA_NORMAL 0x00000000U

#define	DMA_PBURST_INC16 DMA_SxCR_PBURST

#define	DMA_PBURST_INC4 DMA_SxCR_PBURST_0

#define	DMA_PBURST_INC8 DMA_SxCR_PBURST_1

#define	DMA_PBURST_SINGLE 0x00000000U

#define	DMA_PDATAALIGN_BYTE 0x00000000U

#define	DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0

#define	DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1

#define	DMA_PERIPH_TO_MEMORY 0x00000000U

#define	DMA_PFCTRL DMA_SxCR_PFCTRL

#define	DMA_PINC_DISABLE 0x00000000U

#define	DMA_PINC_ENABLE DMA_SxCR_PINC

#define	DMA_PRIORITY_HIGH DMA_SxCR_PL_1

#define	DMA_PRIORITY_LOW 0x00000000U

#define	DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0

#define	DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL

#define	HAL_DMA_ERROR_DME 0x00000004U

#define	HAL_DMA_ERROR_FE 0x00000002U

#define	HAL_DMA_ERROR_NO_XFER 0x00000080U

#define	HAL_DMA_ERROR_NONE 0x00000000U

#define	HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U

#define	HAL_DMA_ERROR_PARAM 0x00000040U

#define	HAL_DMA_ERROR_TE 0x00000001U

#define	HAL_DMA_ERROR_TIMEOUT 0x00000020U

#define	IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))

#define	IS_DMA_DIRECTION(DIRECTION)

#define	IS_DMA_FIFO_MODE_STATE(STATE)

#define	IS_DMA_FIFO_THRESHOLD(THRESHOLD)

#define	IS_DMA_MEMORY_BURST(BURST)

#define	IS_DMA_MEMORY_DATA_SIZE(SIZE)

#define	IS_DMA_MEMORY_INC_STATE(STATE)

#define	IS_DMA_MODE(MODE)

#define	IS_DMA_PERIPHERAL_BURST(BURST)

#define	IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)

#define	IS_DMA_PERIPHERAL_INC_STATE(STATE)

#define	IS_DMA_PRIORITY(PRIORITY)

Typedefs
typedef struct __DMA_HandleTypeDef	DMA_HandleTypeDef
	DMA handle Structure definition. More...

Enumerations
enum	HAL_DMA_CallbackIDTypeDef { HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U, HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U, HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U, HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U, HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U, HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U }
	HAL DMA Error Code structure definition. More...

enum	HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U, HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U, HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U, HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U, HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U, HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
	HAL DMA Error Code structure definition. More...

enum	HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U, HAL_DMA_STATE_ERROR = 0x04U, HAL_DMA_STATE_ABORT = 0x05U, HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U, HAL_DMA_STATE_ERROR = 0x04U, HAL_DMA_STATE_ABORT = 0x05U, HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U, HAL_DMA_STATE_ERROR = 0x04U, HAL_DMA_STATE_ABORT = 0x05U, HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U, HAL_DMA_STATE_ERROR = 0x04U, HAL_DMA_STATE_ABORT = 0x05U, HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_ERROR = 0x03U, HAL_DMA_STATE_ABORT = 0x04U, HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_ERROR = 0x03U, HAL_DMA_STATE_ABORT = 0x04U }
	HAL DMA State structures definition. More...

Functions
HAL_StatusTypeDef	HAL_DMA_Abort (DMA_HandleTypeDef *hdma)

HAL_StatusTypeDef	HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)

HAL_StatusTypeDef	HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)

uint32_t	HAL_DMA_GetError (DMA_HandleTypeDef *hdma)

HAL_DMA_StateTypeDef	HAL_DMA_GetState (DMA_HandleTypeDef *hdma)

HAL_StatusTypeDef	HAL_DMA_Init (DMA_HandleTypeDef *hdma)

void	HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)

HAL_StatusTypeDef	HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)

HAL_StatusTypeDef	HAL_DMA_RegisterCallback (DMA_HandleTypeDef hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(pCallback)(DMA_HandleTypeDef *_hdma))

HAL_StatusTypeDef	HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)

HAL_StatusTypeDef	HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)

HAL_StatusTypeDef	HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)

Detailed Description

Header file of DMA HAL module.

Author: MCD Application Team

Attention

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32f7xx_hal_dma.h.

Classes

Macros

Typedefs

Enumerations

Functions

Detailed Description

© Copyright (c) 2017 STMicroelectronics. All rights reserved.