stm32f30x_rcc.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F30x_RCC_H
31 #define __STM32F30x_RCC_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f30x.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
50 typedef struct
51 {
52  uint32_t SYSCLK_Frequency;
53  uint32_t HCLK_Frequency;
54  uint32_t PCLK1_Frequency;
55  uint32_t PCLK2_Frequency;
56  uint32_t ADC12CLK_Frequency;
57  uint32_t ADC34CLK_Frequency;
58  uint32_t I2C1CLK_Frequency;
59  uint32_t I2C2CLK_Frequency;
60  uint32_t I2C3CLK_Frequency;
61  uint32_t TIM1CLK_Frequency;
62  uint32_t HRTIM1CLK_Frequency;
63  uint32_t TIM8CLK_Frequency;
64  uint32_t USART1CLK_Frequency;
65  uint32_t USART2CLK_Frequency;
66  uint32_t USART3CLK_Frequency;
67  uint32_t UART4CLK_Frequency;
68  uint32_t UART5CLK_Frequency;
69  uint32_t TIM15CLK_Frequency;
70  uint32_t TIM16CLK_Frequency;
71  uint32_t TIM17CLK_Frequency;
72 }RCC_ClocksTypeDef;
73 
74 /* Exported constants --------------------------------------------------------*/
75 
84 #define RCC_HSE_OFF ((uint8_t)0x00)
85 #define RCC_HSE_ON ((uint8_t)0x01)
86 #define RCC_HSE_Bypass ((uint8_t)0x05)
87 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
88  ((HSE) == RCC_HSE_Bypass))
89 
98 #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
99 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
100 
101 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
102  ((SOURCE) == RCC_PLLSource_PREDIV1))
103 
111 #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
112 #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
113 #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
114 #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
115 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
116 #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
117 #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
118 #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
119 #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
120 #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
121 #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
122 #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
123 #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
124 #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
125 #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
126 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
127  ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
128  ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
129  ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
130  ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
131  ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
132  ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
133  ((MUL) == RCC_PLLMul_16))
134 
141 #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
142 #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
143 #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
144 #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
145 #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
146 #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
147 #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
148 #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
149 #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
150 #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
151 #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
152 #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
153 #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
154 #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
155 #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
156 #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
157 
158 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
159  ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
160  ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
161  ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
162  ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
163  ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
164  ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
165  ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
166 
174 #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
175 #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
176 #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
177 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
178  ((SOURCE) == RCC_SYSCLKSource_HSE) || \
179  ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
180 
188 #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
189 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
190 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
191 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
192 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
193 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
194 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
195 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
196 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
197 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
198  ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
199  ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
200  ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
201  ((HCLK) == RCC_SYSCLK_Div512))
202 
210 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
211 #define RCC_HCLK_Div2 ((uint32_t)0x00000400)
212 #define RCC_HCLK_Div4 ((uint32_t)0x00000500)
213 #define RCC_HCLK_Div8 ((uint32_t)0x00000600)
214 #define RCC_HCLK_Div16 ((uint32_t)0x00000700)
215 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
216  ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
217  ((PCLK) == RCC_HCLK_Div16))
218 
226 /* ADC1 & ADC2 */
227 #define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
228 #define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
229 #define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
230 #define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
231 #define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
232 #define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
233 #define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
234 #define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
235 #define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
236 #define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
237 #define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
238 #define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
239 #define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
240 
241 /* ADC3 & ADC4 */
242 #define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
243 #define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
244 #define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
245 #define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
246 #define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
247 #define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
248 #define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
249 #define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
250 #define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
251 #define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
252 #define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
253 #define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
254 #define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
255 
256 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
257  ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
258  ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
259  ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
260  ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
261  ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
262  ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
263  ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
264  ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
265  ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
266  ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
267  ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
268  ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
269 
278 #define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
279 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
280 
281 #define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
282 #define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
283 
284 #define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
285 #define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
286 
287 #define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
288 #define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
289 
290 #define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
291 #define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
292 
293 #define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
294  ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
295  ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
296  ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
297  ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
298 
307 #define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
308 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
309 
310 #define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
311 
320 #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
321 #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
322 
323 #define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
324 #define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
325 
326 #define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
327 #define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
328 
329 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
330  ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
331  ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
332 
341 #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
342 #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
343 #define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
344 #define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
345 
346 #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
347 #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
348 #define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
349 #define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
350 
351 #define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
352 #define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
353 #define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
354 #define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
355 
356 #define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
357 #define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
358 #define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
359 #define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
360 
361 #define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
362 #define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
363 #define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
364 #define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
365 
366 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
367  ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
368  ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
369  ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
370  ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
371  ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
372  ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
373  ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
374  ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
375  ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
376 
385 #define RCC_IT_LSIRDY ((uint8_t)0x01)
386 #define RCC_IT_LSERDY ((uint8_t)0x02)
387 #define RCC_IT_HSIRDY ((uint8_t)0x04)
388 #define RCC_IT_HSERDY ((uint8_t)0x08)
389 #define RCC_IT_PLLRDY ((uint8_t)0x10)
390 #define RCC_IT_CSS ((uint8_t)0x80)
391 
392 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
393 
394 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
395  ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
396  ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
397 
398 
399 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
400 
409 #define RCC_LSE_OFF ((uint32_t)0x00000000)
410 #define RCC_LSE_ON RCC_BDCR_LSEON
411 #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
412 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
413  ((LSE) == RCC_LSE_Bypass))
414 
422 #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
423 #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
424 #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
425 
426 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
427  ((SOURCE) == RCC_RTCCLKSource_LSI) || \
428  ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
429 
436 #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
437 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
438 
439 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
440 
445 #define RCC_LSEDrive_Low ((uint32_t)0x00000000)
446 #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
447 #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
448 #define RCC_LSEDrive_High RCC_BDCR_LSEDRV
449 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
450  ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
451 
459 #define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
460 #define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
461 #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
462 #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
463 #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
464 #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
465 #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
466 #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
467 #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
468 #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
469 #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
470 #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
471 #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
472 #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
473 
474 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
475 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
476 
485 #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
486 #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
487 #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
488 #define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
489 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
490 #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
491 #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
492 #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
493 #define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
494 
495 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
496 
504 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
505 #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
506 #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
507 #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
508 #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
509 #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
510 #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
511 #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
512 #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
513 #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
514 #define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
515 #define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
516 #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
517 #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
518 #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
519 #define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
520 #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
521 #define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
522 #define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
523 #define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
524 #define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
525 
526 
527 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
528 
536 #define RCC_MCOSource_NoClock ((uint8_t)0x00)
537 #define RCC_MCOSource_LSI ((uint8_t)0x02)
538 #define RCC_MCOSource_LSE ((uint8_t)0x03)
539 #define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
540 #define RCC_MCOSource_HSI ((uint8_t)0x05)
541 #define RCC_MCOSource_HSE ((uint8_t)0x06)
542 #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
543 
544 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
545  ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
546  ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
547  ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
548 
556 #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
557 #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
558 #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
559 #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
560 #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
561 #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
562 #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
563 #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
564 
565 #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
566  ((PRESCALER) == RCC_MCOPrescaler_2) || \
567  ((PRESCALER) == RCC_MCOPrescaler_4) || \
568  ((PRESCALER) == RCC_MCOPrescaler_8) || \
569  ((PRESCALER) == RCC_MCOPrescaler_16) || \
570  ((PRESCALER) == RCC_MCOPrescaler_32) || \
571  ((PRESCALER) == RCC_MCOPrescaler_64) || \
572  ((PRESCALER) == RCC_MCOPrescaler_128))
573 
581 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
582 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
583 
584 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
585  ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
586 
593 #define RCC_FLAG_HSIRDY ((uint8_t)0x01)
594 #define RCC_FLAG_HSERDY ((uint8_t)0x11)
595 #define RCC_FLAG_PLLRDY ((uint8_t)0x19)
596 #define RCC_FLAG_MCOF ((uint8_t)0x9C)
597 #define RCC_FLAG_LSERDY ((uint8_t)0x21)
598 #define RCC_FLAG_LSIRDY ((uint8_t)0x41)
599 #define RCC_FLAG_OBLRST ((uint8_t)0x59)
600 #define RCC_FLAG_PINRST ((uint8_t)0x5A)
601 #define RCC_FLAG_PORRST ((uint8_t)0x5B)
602 #define RCC_FLAG_SFTRST ((uint8_t)0x5C)
603 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
604 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
605 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
606 
607 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
608  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
609  ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
610  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
611  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
612  ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
613  ((FLAG) == RCC_FLAG_MCOF))
614 
615 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
616 
625 /* Exported macro ------------------------------------------------------------*/
626 /* Exported functions ------------------------------------------------------- */
627 
628 /* Function used to set the RCC clock configuration to the default reset state */
629 void RCC_DeInit(void);
630 
631 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
632 void RCC_HSEConfig(uint8_t RCC_HSE);
633 ErrorStatus RCC_WaitForHSEStartUp(void);
634 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
635 void RCC_HSICmd(FunctionalState NewState);
636 void RCC_LSEConfig(uint32_t RCC_LSE);
637 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
638 void RCC_LSICmd(FunctionalState NewState);
639 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
640 void RCC_PLLCmd(FunctionalState NewState);
641 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
642 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
643 #ifdef STM32F303xC
644  void RCC_MCOConfig(uint8_t RCC_MCOSource);
645 #else
646  void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
647 #endif /* STM32F303xC */
648 
649 /* System, AHB and APB busses clocks configuration functions ******************/
650 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
651 uint8_t RCC_GetSYSCLKSource(void);
652 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
653 void RCC_PCLK1Config(uint32_t RCC_HCLK);
654 void RCC_PCLK2Config(uint32_t RCC_HCLK);
655 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
656 
657 /* Peripheral clocks configuration functions **********************************/
658 void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
659 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
660 void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
661 void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
662 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
663 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
664 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
665 
666 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
667 void RCC_RTCCLKCmd(FunctionalState NewState);
668 void RCC_BackupResetCmd(FunctionalState NewState);
669 
670 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
671 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
672 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
673 
674 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
675 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
676 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
677 
678 /* Interrupts and flags management functions **********************************/
679 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
680 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
681 void RCC_ClearFlag(void);
682 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
683 void RCC_ClearITPendingBit(uint8_t RCC_IT);
684 
685 #ifdef __cplusplus
686 }
687 #endif
688 
689 #endif /* __STM32F30x_RCC_H */
690 
699 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_RTCCLKConfig
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1470
RCC_ClearITPendingBit
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC&#39;s interrupt pending bits.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2924
FlagStatus
FlagStatus
Definition: stm32f4xx.h:706
RCC_WaitForHSEStartUp
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:308
RCC_BackupResetCmd
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1519
RCC_ClocksTypeDef::HRTIM1CLK_Frequency
uint32_t HRTIM1CLK_Frequency
Definition: stm32f30x_rcc.h:62
FunctionalState
FunctionalState
Definition: stm32f4xx.h:708
RCC_ClocksTypeDef::USART3CLK_Frequency
uint32_t USART3CLK_Frequency
Definition: stm32f30x_rcc.h:66
RCC_USBCLKConfig
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
Configures the USB clock (USBCLK).
Definition: stm32f10x_rcc.c:729
RCC_HCLKConfig
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1203
RCC_AdjustHSICalibrationValue
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:339
RCC_RTCCLKCmd
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1502
RCC_LSICmd
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:440
RCC_ClockSecuritySystemCmd
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:879
RCC_HSICmd
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:375
RCC_APB2PeriphClockCmd
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2051
RCC_ITConfig
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2788
RCC_APB1PeriphResetCmd
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2204
RCC_APB2PeriphResetCmd
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2247
RCC_I2CCLKConfig
void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
Configures the I2C clock (I2CCLK).
Definition: stm32f30x_rcc.c:1268
RCC_PLLCmd
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the main PLL.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:563
RCC_PCLK1Config
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1234
RCC_ClocksTypeDef::I2C3CLK_Frequency
uint32_t I2C3CLK_Frequency
Definition: stm32f30x_rcc.h:60
RCC_ClocksTypeDef::TIM16CLK_Frequency
uint32_t TIM16CLK_Frequency
Definition: stm32f30x_rcc.h:70
RCC_ClocksTypeDef::TIM15CLK_Frequency
uint32_t TIM15CLK_Frequency
Definition: stm32f30x_rcc.h:69
RCC_ClearFlag
void RCC_ClearFlag(void)
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2870
RCC_HRTIM1CLKConfig
void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK)
Configures the HRTIM1 clock sources(HRTIM1CLK).
Definition: stm32f30x_rcc.c:1361
RCC_LSEConfig
void RCC_LSEConfig(uint32_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
Definition: stm32f30x_rcc.c:354
RCC_GetFlagStatus
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2825
RCC_SYSCLKConfig
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1149
RCC_ClocksTypeDef::USART2CLK_Frequency
uint32_t USART2CLK_Frequency
Definition: stm32f30x_rcc.h:65
RCC_ClocksTypeDef::UART4CLK_Frequency
uint32_t UART4CLK_Frequency
Definition: stm32f30x_rcc.h:67
ITStatus
enum FlagStatus ITStatus
RCC_GetClocksFreq
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1317
RCC_ClocksTypeDef::USART1CLK_Frequency
uint32_t USART1CLK_Frequency
Definition: stm32f30x_rcc.h:64
RCC_ClocksTypeDef::TIM17CLK_Frequency
uint32_t TIM17CLK_Frequency
Definition: stm32f30x_rcc.h:71
RCC_USARTCLKConfig
void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
Configures the USART clock (USARTCLK).
Definition: stm32f30x_rcc.c:1385
RCC_LSEDriveConfig
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
Configures the External Low Speed oscillator (LSE) drive capability.
Definition: stm32f30x_rcc.c:380
RCC_ClocksTypeDef::I2C2CLK_Frequency
uint32_t I2C2CLK_Frequency
Definition: stm32f30x_rcc.h:59
RCC_HSEConfig
void RCC_HSEConfig(uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:284
RCC_ADCCLKConfig
void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK)
Configures the ADC clock (ADCCLK).
Definition: stm32f10x_rcc.c:767
RCC_ClocksTypeDef::I2C1CLK_Frequency
uint32_t I2C1CLK_Frequency
Definition: stm32f30x_rcc.h:58
RCC_ClocksTypeDef::ADC34CLK_Frequency
uint32_t ADC34CLK_Frequency
Definition: stm32f30x_rcc.h:57
RCC_TIMCLKConfig
void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK)
Configures the TIMx clock sources(TIMCLK).
Definition: stm32f30x_rcc.c:1311
ErrorStatus
ErrorStatus
Definition: stm32f4xx.h:711
RCC_ClocksTypeDef::TIM1CLK_Frequency
uint32_t TIM1CLK_Frequency
Definition: stm32f30x_rcc.h:61
RCC_PREDIV1Config
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
Configures the PREDIV1 division factor.
Definition: stm32f30x_rcc.c:466
RCC_ClocksTypeDef::ADC12CLK_Frequency
uint32_t ADC12CLK_Frequency
Definition: stm32f30x_rcc.h:56
RCC_ClocksTypeDef::UART5CLK_Frequency
uint32_t UART5CLK_Frequency
Definition: stm32f30x_rcc.h:68
RCC_PLLConfig
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
Configures the PLL clock source and multiplication factor.
Definition: stm32f10x_rcc.c:379
RCC_MCOConfig
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
Selects the clock source to output on MCO pin (PA8) and the corresponding prescsaler.
Definition: stm32f30x_rcc.c:567
RCC_ClocksTypeDef
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.h:48
RCC_GetSYSCLKSource
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1178
RCC_DeInit
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:225
RCC_AHBPeriphClockCmd
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
Definition: stm32f10x_rcc.c:1065
RCC_APB1PeriphClockCmd
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2004
RCC_GetITStatus
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2890
RCC_I2SCLKConfig
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
Configures the I2S clock source (I2SCLK).
Definition: STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c:1065
RCC_PCLK2Config
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1265
RCC_ClocksTypeDef::TIM8CLK_Frequency
uint32_t TIM8CLK_Frequency
Definition: stm32f30x_rcc.h:63
RCC_AHBPeriphResetCmd
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
Forces or releases AHB peripheral reset.
Definition: stm32f30x_rcc.c:1660

rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Apr 15 2021 05:07:48