core_armv81mml.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_ARMV81MML_H_GENERIC
32 #define __CORE_ARMV81MML_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 #define __ARM_ARCH_8M_MAIN__ 1 // patching for now
66 /* CMSIS ARMV81MML definitions */
67 #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
68 #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
69 #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
70  __ARMv81MML_CMSIS_VERSION_SUB )
72 #define __CORTEX_M (81U)
77 #if defined ( __CC_ARM )
78  #if defined __TARGET_FPU_VFP
79  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
80  #define __FPU_USED 1U
81  #else
82  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83  #define __FPU_USED 0U
84  #endif
85  #else
86  #define __FPU_USED 0U
87  #endif
88 
89  #if defined(__ARM_FEATURE_DSP)
90  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
91  #define __DSP_USED 1U
92  #else
93  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
94  #define __DSP_USED 0U
95  #endif
96  #else
97  #define __DSP_USED 0U
98  #endif
99 
100 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
101  #if defined __ARM_FP
102  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103  #define __FPU_USED 1U
104  #else
105  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #define __FPU_USED 0U
107  #endif
108  #else
109  #define __FPU_USED 0U
110  #endif
111 
112  #if defined(__ARM_FEATURE_DSP)
113  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
114  #define __DSP_USED 1U
115  #else
116  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
117  #define __DSP_USED 0U
118  #endif
119  #else
120  #define __DSP_USED 0U
121  #endif
122 
123 #elif defined ( __GNUC__ )
124  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
125  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
126  #define __FPU_USED 1U
127  #else
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #define __FPU_USED 0U
130  #endif
131  #else
132  #define __FPU_USED 0U
133  #endif
134 
135  #if defined(__ARM_FEATURE_DSP)
136  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
137  #define __DSP_USED 1U
138  #else
139  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
140  #define __DSP_USED 0U
141  #endif
142  #else
143  #define __DSP_USED 0U
144  #endif
145 
146 #elif defined ( __ICCARM__ )
147  #if defined __ARMVFP__
148  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
149  #define __FPU_USED 1U
150  #else
151  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
152  #define __FPU_USED 0U
153  #endif
154  #else
155  #define __FPU_USED 0U
156  #endif
157 
158  #if defined(__ARM_FEATURE_DSP)
159  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
160  #define __DSP_USED 1U
161  #else
162  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
163  #define __DSP_USED 0U
164  #endif
165  #else
166  #define __DSP_USED 0U
167  #endif
168 
169 #elif defined ( __TI_ARM__ )
170  #if defined __TI_VFP_SUPPORT__
171  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
172  #define __FPU_USED 1U
173  #else
174  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
175  #define __FPU_USED 0U
176  #endif
177  #else
178  #define __FPU_USED 0U
179  #endif
180 
181 #elif defined ( __TASKING__ )
182  #if defined __FPU_VFP__
183  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
184  #define __FPU_USED 1U
185  #else
186  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
187  #define __FPU_USED 0U
188  #endif
189  #else
190  #define __FPU_USED 0U
191  #endif
192 
193 #elif defined ( __CSMC__ )
194  #if ( __CSMC__ & 0x400U)
195  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
196  #define __FPU_USED 1U
197  #else
198  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
199  #define __FPU_USED 0U
200  #endif
201  #else
202  #define __FPU_USED 0U
203  #endif
204 
205 #endif
206 
207 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
208 
209 
210 #ifdef __cplusplus
211 }
212 #endif
213 
214 #endif /* __CORE_ARMV81MML_H_GENERIC */
215 
216 #ifndef __CMSIS_GENERIC
217 
218 #ifndef __CORE_ARMV81MML_H_DEPENDANT
219 #define __CORE_ARMV81MML_H_DEPENDANT
220 
221 #ifdef __cplusplus
222  extern "C" {
223 #endif
224 
225 /* check device defines and use defaults */
226 #if defined __CHECK_DEVICE_DEFINES
227  #ifndef __ARMv81MML_REV
228  #define __ARMv81MML_REV 0x0000U
229  #warning "__ARMv81MML_REV not defined in device header file; using default!"
230  #endif
231 
232  #ifndef __FPU_PRESENT
233  #define __FPU_PRESENT 0U
234  #warning "__FPU_PRESENT not defined in device header file; using default!"
235  #endif
236 
237  #ifndef __MPU_PRESENT
238  #define __MPU_PRESENT 0U
239  #warning "__MPU_PRESENT not defined in device header file; using default!"
240  #endif
241 
242  #ifndef __SAUREGION_PRESENT
243  #define __SAUREGION_PRESENT 0U
244  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
245  #endif
246 
247  #ifndef __DSP_PRESENT
248  #define __DSP_PRESENT 0U
249  #warning "__DSP_PRESENT not defined in device header file; using default!"
250  #endif
251 
252  #ifndef __NVIC_PRIO_BITS
253  #define __NVIC_PRIO_BITS 3U
254  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
255  #endif
256 
257  #ifndef __Vendor_SysTickConfig
258  #define __Vendor_SysTickConfig 0U
259  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
260  #endif
261 #endif
262 
263 /* IO definitions (access restrictions to peripheral registers) */
271 #ifdef __cplusplus
272  #define __I volatile
273 #else
274  #define __I volatile const
275 #endif
276 #define __O volatile
277 #define __IO volatile
279 /* following defines should be used for structure members */
280 #define __IM volatile const
281 #define __OM volatile
282 #define __IOM volatile
284 
288 /*******************************************************************************
289  * Register Abstraction
290  Core Register contain:
291  - Core Register
292  - Core NVIC Register
293  - Core SCB Register
294  - Core SysTick Register
295  - Core Debug Register
296  - Core MPU Register
297  - Core SAU Register
298  - Core FPU Register
299  ******************************************************************************/
300 
315 typedef union
316 {
317  struct
318  {
319  uint32_t _reserved0:16;
320  uint32_t GE:4;
321  uint32_t _reserved1:7;
322  uint32_t Q:1;
323  uint32_t V:1;
324  uint32_t C:1;
325  uint32_t Z:1;
326  uint32_t N:1;
327  } b;
328  uint32_t w;
329 } APSR_Type;
330 
331 /* APSR Register Definitions */
332 #define APSR_N_Pos 31U
333 #define APSR_N_Msk (1UL << APSR_N_Pos)
335 #define APSR_Z_Pos 30U
336 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
338 #define APSR_C_Pos 29U
339 #define APSR_C_Msk (1UL << APSR_C_Pos)
341 #define APSR_V_Pos 28U
342 #define APSR_V_Msk (1UL << APSR_V_Pos)
344 #define APSR_Q_Pos 27U
345 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
347 #define APSR_GE_Pos 16U
348 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
354 typedef union
355 {
356  struct
357  {
358  uint32_t ISR:9;
359  uint32_t _reserved0:23;
360  } b;
361  uint32_t w;
362 } IPSR_Type;
363 
364 /* IPSR Register Definitions */
365 #define IPSR_ISR_Pos 0U
366 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
372 typedef union
373 {
374  struct
375  {
376  uint32_t ISR:9;
377  uint32_t _reserved0:7;
378  uint32_t GE:4;
379  uint32_t _reserved1:4;
380  uint32_t T:1;
381  uint32_t IT:2;
382  uint32_t Q:1;
383  uint32_t V:1;
384  uint32_t C:1;
385  uint32_t Z:1;
386  uint32_t N:1;
387  } b;
388  uint32_t w;
389 } xPSR_Type;
390 
391 /* xPSR Register Definitions */
392 #define xPSR_N_Pos 31U
393 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
395 #define xPSR_Z_Pos 30U
396 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
398 #define xPSR_C_Pos 29U
399 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
401 #define xPSR_V_Pos 28U
402 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
404 #define xPSR_Q_Pos 27U
405 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
407 #define xPSR_IT_Pos 25U
408 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
410 #define xPSR_T_Pos 24U
411 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
413 #define xPSR_GE_Pos 16U
414 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
416 #define xPSR_ISR_Pos 0U
417 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
423 typedef union
424 {
425  struct
426  {
427  uint32_t nPRIV:1;
428  uint32_t SPSEL:1;
429  uint32_t FPCA:1;
430  uint32_t SFPA:1;
431  uint32_t _reserved1:28;
432  } b;
433  uint32_t w;
434 } CONTROL_Type;
435 
436 /* CONTROL Register Definitions */
437 #define CONTROL_SFPA_Pos 3U
438 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
440 #define CONTROL_FPCA_Pos 2U
441 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
443 #define CONTROL_SPSEL_Pos 1U
444 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
446 #define CONTROL_nPRIV_Pos 0U
447 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
449 
462 typedef struct
463 {
464  __IOM uint32_t ISER[16U];
465  uint32_t RESERVED0[16U];
466  __IOM uint32_t ICER[16U];
467  uint32_t RSERVED1[16U];
468  __IOM uint32_t ISPR[16U];
469  uint32_t RESERVED2[16U];
470  __IOM uint32_t ICPR[16U];
471  uint32_t RESERVED3[16U];
472  __IOM uint32_t IABR[16U];
473  uint32_t RESERVED4[16U];
474  __IOM uint32_t ITNS[16U];
475  uint32_t RESERVED5[16U];
476  __IOM uint8_t IPR[496U];
477  uint32_t RESERVED6[580U];
478  __OM uint32_t STIR;
479 } NVIC_Type;
480 
481 /* Software Triggered Interrupt Register Definitions */
482 #define NVIC_STIR_INTID_Pos 0U
483 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
485 
498 typedef struct
499 {
500  __IM uint32_t CPUID;
501  __IOM uint32_t ICSR;
502  __IOM uint32_t VTOR;
503  __IOM uint32_t AIRCR;
504  __IOM uint32_t SCR;
505  __IOM uint32_t CCR;
506  __IOM uint8_t SHPR[12U];
507  __IOM uint32_t SHCSR;
508  __IOM uint32_t CFSR;
509  __IOM uint32_t HFSR;
510  __IOM uint32_t DFSR;
511  __IOM uint32_t MMFAR;
512  __IOM uint32_t BFAR;
513  __IOM uint32_t AFSR;
514  __IM uint32_t ID_PFR[2U];
515  __IM uint32_t ID_DFR;
516  __IM uint32_t ID_ADR;
517  __IM uint32_t ID_MMFR[4U];
518  __IM uint32_t ID_ISAR[6U];
519  __IM uint32_t CLIDR;
520  __IM uint32_t CTR;
521  __IM uint32_t CCSIDR;
522  __IOM uint32_t CSSELR;
523  __IOM uint32_t CPACR;
524  __IOM uint32_t NSACR;
525  uint32_t RESERVED3[92U];
526  __OM uint32_t STIR;
527  uint32_t RESERVED4[15U];
528  __IM uint32_t MVFR0;
529  __IM uint32_t MVFR1;
530  __IM uint32_t MVFR2;
531  uint32_t RESERVED5[1U];
532  __OM uint32_t ICIALLU;
533  uint32_t RESERVED6[1U];
534  __OM uint32_t ICIMVAU;
535  __OM uint32_t DCIMVAC;
536  __OM uint32_t DCISW;
537  __OM uint32_t DCCMVAU;
538  __OM uint32_t DCCMVAC;
539  __OM uint32_t DCCSW;
540  __OM uint32_t DCCIMVAC;
541  __OM uint32_t DCCISW;
542  uint32_t RESERVED7[6U];
543  __IOM uint32_t ITCMCR;
544  __IOM uint32_t DTCMCR;
545  __IOM uint32_t AHBPCR;
546  __IOM uint32_t CACR;
547  __IOM uint32_t AHBSCR;
548  uint32_t RESERVED8[1U];
549  __IOM uint32_t ABFSR;
550 } SCB_Type;
551 
552 /* SCB CPUID Register Definitions */
553 #define SCB_CPUID_IMPLEMENTER_Pos 24U
554 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
556 #define SCB_CPUID_VARIANT_Pos 20U
557 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
559 #define SCB_CPUID_ARCHITECTURE_Pos 16U
560 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
562 #define SCB_CPUID_PARTNO_Pos 4U
563 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
565 #define SCB_CPUID_REVISION_Pos 0U
566 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
568 /* SCB Interrupt Control State Register Definitions */
569 #define SCB_ICSR_PENDNMISET_Pos 31U
570 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
572 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
573 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
575 #define SCB_ICSR_PENDNMICLR_Pos 30U
576 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
578 #define SCB_ICSR_PENDSVSET_Pos 28U
579 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
581 #define SCB_ICSR_PENDSVCLR_Pos 27U
582 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
584 #define SCB_ICSR_PENDSTSET_Pos 26U
585 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
587 #define SCB_ICSR_PENDSTCLR_Pos 25U
588 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
590 #define SCB_ICSR_STTNS_Pos 24U
591 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
593 #define SCB_ICSR_ISRPREEMPT_Pos 23U
594 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
596 #define SCB_ICSR_ISRPENDING_Pos 22U
597 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
599 #define SCB_ICSR_VECTPENDING_Pos 12U
600 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
602 #define SCB_ICSR_RETTOBASE_Pos 11U
603 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
605 #define SCB_ICSR_VECTACTIVE_Pos 0U
606 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
608 /* SCB Vector Table Offset Register Definitions */
609 #define SCB_VTOR_TBLOFF_Pos 7U
610 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
612 /* SCB Application Interrupt and Reset Control Register Definitions */
613 #define SCB_AIRCR_VECTKEY_Pos 16U
614 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
616 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
617 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
619 #define SCB_AIRCR_ENDIANESS_Pos 15U
620 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
622 #define SCB_AIRCR_PRIS_Pos 14U
623 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
625 #define SCB_AIRCR_BFHFNMINS_Pos 13U
626 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
628 #define SCB_AIRCR_PRIGROUP_Pos 8U
629 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
631 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
632 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
634 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
635 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
637 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
638 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
640 /* SCB System Control Register Definitions */
641 #define SCB_SCR_SEVONPEND_Pos 4U
642 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
644 #define SCB_SCR_SLEEPDEEPS_Pos 3U
645 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
647 #define SCB_SCR_SLEEPDEEP_Pos 2U
648 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
650 #define SCB_SCR_SLEEPONEXIT_Pos 1U
651 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
653 /* SCB Configuration Control Register Definitions */
654 #define SCB_CCR_BP_Pos 18U
655 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
657 #define SCB_CCR_IC_Pos 17U
658 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
660 #define SCB_CCR_DC_Pos 16U
661 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
663 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
664 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
666 #define SCB_CCR_BFHFNMIGN_Pos 8U
667 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
669 #define SCB_CCR_DIV_0_TRP_Pos 4U
670 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
672 #define SCB_CCR_UNALIGN_TRP_Pos 3U
673 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
675 #define SCB_CCR_USERSETMPEND_Pos 1U
676 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
678 /* SCB System Handler Control and State Register Definitions */
679 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
680 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
682 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
683 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
685 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U
686 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
688 #define SCB_SHCSR_USGFAULTENA_Pos 18U
689 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
691 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
692 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
694 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
695 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
697 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
698 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
700 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
701 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
703 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
704 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
706 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
707 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
709 #define SCB_SHCSR_SYSTICKACT_Pos 11U
710 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
712 #define SCB_SHCSR_PENDSVACT_Pos 10U
713 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
715 #define SCB_SHCSR_MONITORACT_Pos 8U
716 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
718 #define SCB_SHCSR_SVCALLACT_Pos 7U
719 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
721 #define SCB_SHCSR_NMIACT_Pos 5U
722 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
724 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U
725 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
727 #define SCB_SHCSR_USGFAULTACT_Pos 3U
728 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
730 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
731 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
733 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
734 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
736 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
737 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
739 /* SCB Configurable Fault Status Register Definitions */
740 #define SCB_CFSR_USGFAULTSR_Pos 16U
741 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
743 #define SCB_CFSR_BUSFAULTSR_Pos 8U
744 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
746 #define SCB_CFSR_MEMFAULTSR_Pos 0U
747 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
749 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
750 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
751 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
753 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
754 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
756 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
757 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
759 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
760 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
762 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
763 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
765 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
766 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
768 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
769 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
770 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
772 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
773 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
775 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
776 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
778 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
779 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
781 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
782 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
784 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
785 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
787 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
788 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
790 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
791 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
792 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
794 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
795 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
797 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
798 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
800 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
801 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
803 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
804 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
806 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
807 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
809 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
810 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
812 /* SCB Hard Fault Status Register Definitions */
813 #define SCB_HFSR_DEBUGEVT_Pos 31U
814 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
816 #define SCB_HFSR_FORCED_Pos 30U
817 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
819 #define SCB_HFSR_VECTTBL_Pos 1U
820 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
822 /* SCB Debug Fault Status Register Definitions */
823 #define SCB_DFSR_EXTERNAL_Pos 4U
824 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
826 #define SCB_DFSR_VCATCH_Pos 3U
827 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
829 #define SCB_DFSR_DWTTRAP_Pos 2U
830 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
832 #define SCB_DFSR_BKPT_Pos 1U
833 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
835 #define SCB_DFSR_HALTED_Pos 0U
836 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
838 /* SCB Non-Secure Access Control Register Definitions */
839 #define SCB_NSACR_CP11_Pos 11U
840 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
842 #define SCB_NSACR_CP10_Pos 10U
843 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
845 #define SCB_NSACR_CPn_Pos 0U
846 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
848 /* SCB Cache Level ID Register Definitions */
849 #define SCB_CLIDR_LOUU_Pos 27U
850 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
852 #define SCB_CLIDR_LOC_Pos 24U
853 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
855 /* SCB Cache Type Register Definitions */
856 #define SCB_CTR_FORMAT_Pos 29U
857 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
859 #define SCB_CTR_CWG_Pos 24U
860 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
862 #define SCB_CTR_ERG_Pos 20U
863 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
865 #define SCB_CTR_DMINLINE_Pos 16U
866 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
868 #define SCB_CTR_IMINLINE_Pos 0U
869 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
871 /* SCB Cache Size ID Register Definitions */
872 #define SCB_CCSIDR_WT_Pos 31U
873 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
875 #define SCB_CCSIDR_WB_Pos 30U
876 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
878 #define SCB_CCSIDR_RA_Pos 29U
879 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
881 #define SCB_CCSIDR_WA_Pos 28U
882 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
884 #define SCB_CCSIDR_NUMSETS_Pos 13U
885 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
887 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
888 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
890 #define SCB_CCSIDR_LINESIZE_Pos 0U
891 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
893 /* SCB Cache Size Selection Register Definitions */
894 #define SCB_CSSELR_LEVEL_Pos 1U
895 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
897 #define SCB_CSSELR_IND_Pos 0U
898 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
900 /* SCB Software Triggered Interrupt Register Definitions */
901 #define SCB_STIR_INTID_Pos 0U
902 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
904 /* SCB D-Cache Invalidate by Set-way Register Definitions */
905 #define SCB_DCISW_WAY_Pos 30U
906 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
908 #define SCB_DCISW_SET_Pos 5U
909 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
911 /* SCB D-Cache Clean by Set-way Register Definitions */
912 #define SCB_DCCSW_WAY_Pos 30U
913 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
915 #define SCB_DCCSW_SET_Pos 5U
916 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
918 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
919 #define SCB_DCCISW_WAY_Pos 30U
920 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
922 #define SCB_DCCISW_SET_Pos 5U
923 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
925 /* Instruction Tightly-Coupled Memory Control Register Definitions */
926 #define SCB_ITCMCR_SZ_Pos 3U
927 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
929 #define SCB_ITCMCR_RETEN_Pos 2U
930 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
932 #define SCB_ITCMCR_RMW_Pos 1U
933 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
935 #define SCB_ITCMCR_EN_Pos 0U
936 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
938 /* Data Tightly-Coupled Memory Control Register Definitions */
939 #define SCB_DTCMCR_SZ_Pos 3U
940 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
942 #define SCB_DTCMCR_RETEN_Pos 2U
943 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
945 #define SCB_DTCMCR_RMW_Pos 1U
946 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
948 #define SCB_DTCMCR_EN_Pos 0U
949 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
951 /* AHBP Control Register Definitions */
952 #define SCB_AHBPCR_SZ_Pos 1U
953 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
955 #define SCB_AHBPCR_EN_Pos 0U
956 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
958 /* L1 Cache Control Register Definitions */
959 #define SCB_CACR_FORCEWT_Pos 2U
960 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
962 #define SCB_CACR_ECCEN_Pos 1U
963 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
965 #define SCB_CACR_SIWT_Pos 0U
966 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
968 /* AHBS Control Register Definitions */
969 #define SCB_AHBSCR_INITCOUNT_Pos 11U
970 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
972 #define SCB_AHBSCR_TPRI_Pos 2U
973 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
975 #define SCB_AHBSCR_CTL_Pos 0U
976 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
978 /* Auxiliary Bus Fault Status Register Definitions */
979 #define SCB_ABFSR_AXIMTYPE_Pos 8U
980 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
982 #define SCB_ABFSR_EPPB_Pos 4U
983 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
985 #define SCB_ABFSR_AXIM_Pos 3U
986 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
988 #define SCB_ABFSR_AHBP_Pos 2U
989 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
991 #define SCB_ABFSR_DTCM_Pos 1U
992 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
994 #define SCB_ABFSR_ITCM_Pos 0U
995 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
997 
1010 typedef struct
1011 {
1012  uint32_t RESERVED0[1U];
1013  __IM uint32_t ICTR;
1014  __IOM uint32_t ACTLR;
1015  __IOM uint32_t CPPWR;
1016 } SCnSCB_Type;
1017 
1018 /* Interrupt Controller Type Register Definitions */
1019 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
1020 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
1022 
1035 typedef struct
1036 {
1037  __IOM uint32_t CTRL;
1038  __IOM uint32_t LOAD;
1039  __IOM uint32_t VAL;
1040  __IM uint32_t CALIB;
1041 } SysTick_Type;
1042 
1043 /* SysTick Control / Status Register Definitions */
1044 #define SysTick_CTRL_COUNTFLAG_Pos 16U
1045 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1047 #define SysTick_CTRL_CLKSOURCE_Pos 2U
1048 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1050 #define SysTick_CTRL_TICKINT_Pos 1U
1051 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1053 #define SysTick_CTRL_ENABLE_Pos 0U
1054 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1056 /* SysTick Reload Register Definitions */
1057 #define SysTick_LOAD_RELOAD_Pos 0U
1058 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1060 /* SysTick Current Register Definitions */
1061 #define SysTick_VAL_CURRENT_Pos 0U
1062 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1064 /* SysTick Calibration Register Definitions */
1065 #define SysTick_CALIB_NOREF_Pos 31U
1066 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1068 #define SysTick_CALIB_SKEW_Pos 30U
1069 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1071 #define SysTick_CALIB_TENMS_Pos 0U
1072 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1074 
1087 typedef struct
1088 {
1089  __OM union
1090  {
1091  __OM uint8_t u8;
1092  __OM uint16_t u16;
1093  __OM uint32_t u32;
1094  } PORT [32U];
1095  uint32_t RESERVED0[864U];
1096  __IOM uint32_t TER;
1097  uint32_t RESERVED1[15U];
1098  __IOM uint32_t TPR;
1099  uint32_t RESERVED2[15U];
1100  __IOM uint32_t TCR;
1101  uint32_t RESERVED3[29U];
1102  __OM uint32_t IWR;
1103  __IM uint32_t IRR;
1104  __IOM uint32_t IMCR;
1105  uint32_t RESERVED4[43U];
1106  __OM uint32_t LAR;
1107  __IM uint32_t LSR;
1108  uint32_t RESERVED5[1U];
1109  __IM uint32_t DEVARCH;
1110  uint32_t RESERVED6[4U];
1111  __IM uint32_t PID4;
1112  __IM uint32_t PID5;
1113  __IM uint32_t PID6;
1114  __IM uint32_t PID7;
1115  __IM uint32_t PID0;
1116  __IM uint32_t PID1;
1117  __IM uint32_t PID2;
1118  __IM uint32_t PID3;
1119  __IM uint32_t CID0;
1120  __IM uint32_t CID1;
1121  __IM uint32_t CID2;
1122  __IM uint32_t CID3;
1123 } ITM_Type;
1124 
1125 /* ITM Stimulus Port Register Definitions */
1126 #define ITM_STIM_DISABLED_Pos 1U
1127 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1129 #define ITM_STIM_FIFOREADY_Pos 0U
1130 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1132 /* ITM Trace Privilege Register Definitions */
1133 #define ITM_TPR_PRIVMASK_Pos 0U
1134 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1136 /* ITM Trace Control Register Definitions */
1137 #define ITM_TCR_BUSY_Pos 23U
1138 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1140 #define ITM_TCR_TRACEBUSID_Pos 16U
1141 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1143 #define ITM_TCR_GTSFREQ_Pos 10U
1144 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1146 #define ITM_TCR_TSPRESCALE_Pos 8U
1147 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1149 #define ITM_TCR_STALLENA_Pos 5U
1150 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1152 #define ITM_TCR_SWOENA_Pos 4U
1153 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1155 #define ITM_TCR_DWTENA_Pos 3U
1156 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1158 #define ITM_TCR_SYNCENA_Pos 2U
1159 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1161 #define ITM_TCR_TSENA_Pos 1U
1162 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1164 #define ITM_TCR_ITMENA_Pos 0U
1165 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1167 /* ITM Integration Write Register Definitions */
1168 #define ITM_IWR_ATVALIDM_Pos 0U
1169 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
1171 /* ITM Integration Read Register Definitions */
1172 #define ITM_IRR_ATREADYM_Pos 0U
1173 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
1175 /* ITM Integration Mode Control Register Definitions */
1176 #define ITM_IMCR_INTEGRATION_Pos 0U
1177 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
1179 /* ITM Lock Status Register Definitions */
1180 #define ITM_LSR_ByteAcc_Pos 2U
1181 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1183 #define ITM_LSR_Access_Pos 1U
1184 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1186 #define ITM_LSR_Present_Pos 0U
1187 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1189  /* end of group CMSIS_ITM */
1190 
1191 
1202 typedef struct
1203 {
1204  __IOM uint32_t CTRL;
1205  __IOM uint32_t CYCCNT;
1206  __IOM uint32_t CPICNT;
1207  __IOM uint32_t EXCCNT;
1208  __IOM uint32_t SLEEPCNT;
1209  __IOM uint32_t LSUCNT;
1210  __IOM uint32_t FOLDCNT;
1211  __IM uint32_t PCSR;
1212  __IOM uint32_t COMP0;
1213  uint32_t RESERVED1[1U];
1214  __IOM uint32_t FUNCTION0;
1215  uint32_t RESERVED2[1U];
1216  __IOM uint32_t COMP1;
1217  uint32_t RESERVED3[1U];
1218  __IOM uint32_t FUNCTION1;
1219  uint32_t RESERVED4[1U];
1220  __IOM uint32_t COMP2;
1221  uint32_t RESERVED5[1U];
1222  __IOM uint32_t FUNCTION2;
1223  uint32_t RESERVED6[1U];
1224  __IOM uint32_t COMP3;
1225  uint32_t RESERVED7[1U];
1226  __IOM uint32_t FUNCTION3;
1227  uint32_t RESERVED8[1U];
1228  __IOM uint32_t COMP4;
1229  uint32_t RESERVED9[1U];
1230  __IOM uint32_t FUNCTION4;
1231  uint32_t RESERVED10[1U];
1232  __IOM uint32_t COMP5;
1233  uint32_t RESERVED11[1U];
1234  __IOM uint32_t FUNCTION5;
1235  uint32_t RESERVED12[1U];
1236  __IOM uint32_t COMP6;
1237  uint32_t RESERVED13[1U];
1238  __IOM uint32_t FUNCTION6;
1239  uint32_t RESERVED14[1U];
1240  __IOM uint32_t COMP7;
1241  uint32_t RESERVED15[1U];
1242  __IOM uint32_t FUNCTION7;
1243  uint32_t RESERVED16[1U];
1244  __IOM uint32_t COMP8;
1245  uint32_t RESERVED17[1U];
1246  __IOM uint32_t FUNCTION8;
1247  uint32_t RESERVED18[1U];
1248  __IOM uint32_t COMP9;
1249  uint32_t RESERVED19[1U];
1250  __IOM uint32_t FUNCTION9;
1251  uint32_t RESERVED20[1U];
1252  __IOM uint32_t COMP10;
1253  uint32_t RESERVED21[1U];
1254  __IOM uint32_t FUNCTION10;
1255  uint32_t RESERVED22[1U];
1256  __IOM uint32_t COMP11;
1257  uint32_t RESERVED23[1U];
1258  __IOM uint32_t FUNCTION11;
1259  uint32_t RESERVED24[1U];
1260  __IOM uint32_t COMP12;
1261  uint32_t RESERVED25[1U];
1262  __IOM uint32_t FUNCTION12;
1263  uint32_t RESERVED26[1U];
1264  __IOM uint32_t COMP13;
1265  uint32_t RESERVED27[1U];
1266  __IOM uint32_t FUNCTION13;
1267  uint32_t RESERVED28[1U];
1268  __IOM uint32_t COMP14;
1269  uint32_t RESERVED29[1U];
1270  __IOM uint32_t FUNCTION14;
1271  uint32_t RESERVED30[1U];
1272  __IOM uint32_t COMP15;
1273  uint32_t RESERVED31[1U];
1274  __IOM uint32_t FUNCTION15;
1275  uint32_t RESERVED32[934U];
1276  __IM uint32_t LSR;
1277  uint32_t RESERVED33[1U];
1278  __IM uint32_t DEVARCH;
1279 } DWT_Type;
1280 
1281 /* DWT Control Register Definitions */
1282 #define DWT_CTRL_NUMCOMP_Pos 28U
1283 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1285 #define DWT_CTRL_NOTRCPKT_Pos 27U
1286 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1288 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1289 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1291 #define DWT_CTRL_NOCYCCNT_Pos 25U
1292 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1294 #define DWT_CTRL_NOPRFCNT_Pos 24U
1295 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1297 #define DWT_CTRL_CYCDISS_Pos 23U
1298 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1300 #define DWT_CTRL_CYCEVTENA_Pos 22U
1301 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1303 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1304 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1306 #define DWT_CTRL_LSUEVTENA_Pos 20U
1307 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1309 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1310 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1312 #define DWT_CTRL_EXCEVTENA_Pos 18U
1313 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1315 #define DWT_CTRL_CPIEVTENA_Pos 17U
1316 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1318 #define DWT_CTRL_EXCTRCENA_Pos 16U
1319 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1321 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1322 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1324 #define DWT_CTRL_SYNCTAP_Pos 10U
1325 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1327 #define DWT_CTRL_CYCTAP_Pos 9U
1328 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1330 #define DWT_CTRL_POSTINIT_Pos 5U
1331 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1333 #define DWT_CTRL_POSTPRESET_Pos 1U
1334 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1336 #define DWT_CTRL_CYCCNTENA_Pos 0U
1337 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1339 /* DWT CPI Count Register Definitions */
1340 #define DWT_CPICNT_CPICNT_Pos 0U
1341 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1343 /* DWT Exception Overhead Count Register Definitions */
1344 #define DWT_EXCCNT_EXCCNT_Pos 0U
1345 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1347 /* DWT Sleep Count Register Definitions */
1348 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1349 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1351 /* DWT LSU Count Register Definitions */
1352 #define DWT_LSUCNT_LSUCNT_Pos 0U
1353 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1355 /* DWT Folded-instruction Count Register Definitions */
1356 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1357 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1359 /* DWT Comparator Function Register Definitions */
1360 #define DWT_FUNCTION_ID_Pos 27U
1361 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1363 #define DWT_FUNCTION_MATCHED_Pos 24U
1364 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1366 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1367 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1369 #define DWT_FUNCTION_ACTION_Pos 4U
1370 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1372 #define DWT_FUNCTION_MATCH_Pos 0U
1373 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
1375  /* end of group CMSIS_DWT */
1376 
1377 
1388 typedef struct
1389 {
1390  __IM uint32_t SSPSR;
1391  __IOM uint32_t CSPSR;
1392  uint32_t RESERVED0[2U];
1393  __IOM uint32_t ACPR;
1394  uint32_t RESERVED1[55U];
1395  __IOM uint32_t SPPR;
1396  uint32_t RESERVED2[131U];
1397  __IM uint32_t FFSR;
1398  __IOM uint32_t FFCR;
1399  __IM uint32_t FSCR;
1400  uint32_t RESERVED3[759U];
1401  __IM uint32_t TRIGGER;
1402  __IM uint32_t FIFO0;
1403  __IM uint32_t ITATBCTR2;
1404  uint32_t RESERVED4[1U];
1405  __IM uint32_t ITATBCTR0;
1406  __IM uint32_t FIFO1;
1407  __IOM uint32_t ITCTRL;
1408  uint32_t RESERVED5[39U];
1409  __IOM uint32_t CLAIMSET;
1410  __IOM uint32_t CLAIMCLR;
1411  uint32_t RESERVED7[8U];
1412  __IM uint32_t DEVID;
1413  __IM uint32_t DEVTYPE;
1414 } TPI_Type;
1415 
1416 /* TPI Asynchronous Clock Prescaler Register Definitions */
1417 #define TPI_ACPR_PRESCALER_Pos 0U
1418 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1420 /* TPI Selected Pin Protocol Register Definitions */
1421 #define TPI_SPPR_TXMODE_Pos 0U
1422 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1424 /* TPI Formatter and Flush Status Register Definitions */
1425 #define TPI_FFSR_FtNonStop_Pos 3U
1426 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1428 #define TPI_FFSR_TCPresent_Pos 2U
1429 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1431 #define TPI_FFSR_FtStopped_Pos 1U
1432 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1434 #define TPI_FFSR_FlInProg_Pos 0U
1435 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1437 /* TPI Formatter and Flush Control Register Definitions */
1438 #define TPI_FFCR_TrigIn_Pos 8U
1439 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1441 #define TPI_FFCR_EnFCont_Pos 1U
1442 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1444 /* TPI TRIGGER Register Definitions */
1445 #define TPI_TRIGGER_TRIGGER_Pos 0U
1446 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1448 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1449 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1450 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1452 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1453 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1455 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1456 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1458 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1459 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1461 #define TPI_FIFO0_ETM2_Pos 16U
1462 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1464 #define TPI_FIFO0_ETM1_Pos 8U
1465 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1467 #define TPI_FIFO0_ETM0_Pos 0U
1468 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1470 /* TPI ITATBCTR2 Register Definitions */
1471 #define TPI_ITATBCTR2_ATREADY_Pos 0U
1472 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)
1474 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1475 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1476 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1478 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1479 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1481 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1482 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1484 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1485 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1487 #define TPI_FIFO1_ITM2_Pos 16U
1488 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1490 #define TPI_FIFO1_ITM1_Pos 8U
1491 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1493 #define TPI_FIFO1_ITM0_Pos 0U
1494 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1496 /* TPI ITATBCTR0 Register Definitions */
1497 #define TPI_ITATBCTR0_ATREADY_Pos 0U
1498 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)
1500 /* TPI Integration Mode Control Register Definitions */
1501 #define TPI_ITCTRL_Mode_Pos 0U
1502 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)
1504 /* TPI DEVID Register Definitions */
1505 #define TPI_DEVID_NRZVALID_Pos 11U
1506 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1508 #define TPI_DEVID_MANCVALID_Pos 10U
1509 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1511 #define TPI_DEVID_PTINVALID_Pos 9U
1512 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1514 #define TPI_DEVID_MinBufSz_Pos 6U
1515 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1517 #define TPI_DEVID_AsynClkIn_Pos 5U
1518 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1520 #define TPI_DEVID_NrTraceInput_Pos 0U
1521 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1523 /* TPI DEVTYPE Register Definitions */
1524 #define TPI_DEVTYPE_MajorType_Pos 4U
1525 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1527 #define TPI_DEVTYPE_SubType_Pos 0U
1528 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1530  /* end of group CMSIS_TPI */
1531 
1532 
1533 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1534 
1544 typedef struct
1545 {
1546  __IM uint32_t TYPE;
1547  __IOM uint32_t CTRL;
1548  __IOM uint32_t RNR;
1549  __IOM uint32_t RBAR;
1550  __IOM uint32_t RLAR;
1551  __IOM uint32_t RBAR_A1;
1552  __IOM uint32_t RLAR_A1;
1553  __IOM uint32_t RBAR_A2;
1554  __IOM uint32_t RLAR_A2;
1555  __IOM uint32_t RBAR_A3;
1556  __IOM uint32_t RLAR_A3;
1557  uint32_t RESERVED0[1];
1558  union {
1559  __IOM uint32_t MAIR[2];
1560  struct {
1561  __IOM uint32_t MAIR0;
1562  __IOM uint32_t MAIR1;
1563  };
1564  };
1565 } MPU_Type;
1566 
1567 #define MPU_TYPE_RALIASES 4U
1568 
1569 /* MPU Type Register Definitions */
1570 #define MPU_TYPE_IREGION_Pos 16U
1571 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1573 #define MPU_TYPE_DREGION_Pos 8U
1574 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1576 #define MPU_TYPE_SEPARATE_Pos 0U
1577 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1579 /* MPU Control Register Definitions */
1580 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1581 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1583 #define MPU_CTRL_HFNMIENA_Pos 1U
1584 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1586 #define MPU_CTRL_ENABLE_Pos 0U
1587 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1589 /* MPU Region Number Register Definitions */
1590 #define MPU_RNR_REGION_Pos 0U
1591 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1593 /* MPU Region Base Address Register Definitions */
1594 #define MPU_RBAR_ADDR_Pos 5U
1595 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1597 #define MPU_RBAR_SH_Pos 3U
1598 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1600 #define MPU_RBAR_AP_Pos 1U
1601 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1603 #define MPU_RBAR_XN_Pos 0U
1604 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1606 /* MPU Region Limit Address Register Definitions */
1607 #define MPU_RLAR_LIMIT_Pos 5U
1608 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1610 #define MPU_RLAR_PXN_Pos 4U
1611 #define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos)
1613 #define MPU_RLAR_AttrIndx_Pos 1U
1614 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1616 #define MPU_RLAR_EN_Pos 0U
1617 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1619 /* MPU Memory Attribute Indirection Register 0 Definitions */
1620 #define MPU_MAIR0_Attr3_Pos 24U
1621 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1623 #define MPU_MAIR0_Attr2_Pos 16U
1624 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1626 #define MPU_MAIR0_Attr1_Pos 8U
1627 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1629 #define MPU_MAIR0_Attr0_Pos 0U
1630 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1632 /* MPU Memory Attribute Indirection Register 1 Definitions */
1633 #define MPU_MAIR1_Attr7_Pos 24U
1634 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1636 #define MPU_MAIR1_Attr6_Pos 16U
1637 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1639 #define MPU_MAIR1_Attr5_Pos 8U
1640 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1642 #define MPU_MAIR1_Attr4_Pos 0U
1643 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1645 
1646 #endif
1647 
1648 
1649 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1650 
1660 typedef struct
1661 {
1662  __IOM uint32_t CTRL;
1663  __IM uint32_t TYPE;
1664 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1665  __IOM uint32_t RNR;
1666  __IOM uint32_t RBAR;
1667  __IOM uint32_t RLAR;
1668 #else
1669  uint32_t RESERVED0[3];
1670 #endif
1671  __IOM uint32_t SFSR;
1672  __IOM uint32_t SFAR;
1673 } SAU_Type;
1674 
1675 /* SAU Control Register Definitions */
1676 #define SAU_CTRL_ALLNS_Pos 1U
1677 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1679 #define SAU_CTRL_ENABLE_Pos 0U
1680 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1682 /* SAU Type Register Definitions */
1683 #define SAU_TYPE_SREGION_Pos 0U
1684 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1686 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1687 /* SAU Region Number Register Definitions */
1688 #define SAU_RNR_REGION_Pos 0U
1689 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1691 /* SAU Region Base Address Register Definitions */
1692 #define SAU_RBAR_BADDR_Pos 5U
1693 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1695 /* SAU Region Limit Address Register Definitions */
1696 #define SAU_RLAR_LADDR_Pos 5U
1697 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1699 #define SAU_RLAR_NSC_Pos 1U
1700 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1702 #define SAU_RLAR_ENABLE_Pos 0U
1703 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1705 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1706 
1707 /* Secure Fault Status Register Definitions */
1708 #define SAU_SFSR_LSERR_Pos 7U
1709 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1711 #define SAU_SFSR_SFARVALID_Pos 6U
1712 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1714 #define SAU_SFSR_LSPERR_Pos 5U
1715 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1717 #define SAU_SFSR_INVTRAN_Pos 4U
1718 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1720 #define SAU_SFSR_AUVIOL_Pos 3U
1721 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1723 #define SAU_SFSR_INVER_Pos 2U
1724 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1726 #define SAU_SFSR_INVIS_Pos 1U
1727 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1729 #define SAU_SFSR_INVEP_Pos 0U
1730 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1732 
1733 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1734 
1735 
1746 typedef struct
1747 {
1748  uint32_t RESERVED0[1U];
1749  __IOM uint32_t FPCCR;
1750  __IOM uint32_t FPCAR;
1751  __IOM uint32_t FPDSCR;
1752  __IM uint32_t MVFR0;
1753  __IM uint32_t MVFR1;
1754 } FPU_Type;
1755 
1756 /* Floating-Point Context Control Register Definitions */
1757 #define FPU_FPCCR_ASPEN_Pos 31U
1758 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1760 #define FPU_FPCCR_LSPEN_Pos 30U
1761 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1763 #define FPU_FPCCR_LSPENS_Pos 29U
1764 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1766 #define FPU_FPCCR_CLRONRET_Pos 28U
1767 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1769 #define FPU_FPCCR_CLRONRETS_Pos 27U
1770 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1772 #define FPU_FPCCR_TS_Pos 26U
1773 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1775 #define FPU_FPCCR_UFRDY_Pos 10U
1776 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1778 #define FPU_FPCCR_SPLIMVIOL_Pos 9U
1779 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1781 #define FPU_FPCCR_MONRDY_Pos 8U
1782 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1784 #define FPU_FPCCR_SFRDY_Pos 7U
1785 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1787 #define FPU_FPCCR_BFRDY_Pos 6U
1788 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1790 #define FPU_FPCCR_MMRDY_Pos 5U
1791 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1793 #define FPU_FPCCR_HFRDY_Pos 4U
1794 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1796 #define FPU_FPCCR_THREAD_Pos 3U
1797 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1799 #define FPU_FPCCR_S_Pos 2U
1800 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1802 #define FPU_FPCCR_USER_Pos 1U
1803 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1805 #define FPU_FPCCR_LSPACT_Pos 0U
1806 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1808 /* Floating-Point Context Address Register Definitions */
1809 #define FPU_FPCAR_ADDRESS_Pos 3U
1810 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1812 /* Floating-Point Default Status Control Register Definitions */
1813 #define FPU_FPDSCR_AHP_Pos 26U
1814 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1816 #define FPU_FPDSCR_DN_Pos 25U
1817 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1819 #define FPU_FPDSCR_FZ_Pos 24U
1820 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1822 #define FPU_FPDSCR_RMode_Pos 22U
1823 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1825 /* Media and FP Feature Register 0 Definitions */
1826 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1827 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1829 #define FPU_MVFR0_Short_vectors_Pos 24U
1830 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1832 #define FPU_MVFR0_Square_root_Pos 20U
1833 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1835 #define FPU_MVFR0_Divide_Pos 16U
1836 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1838 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1839 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1841 #define FPU_MVFR0_Double_precision_Pos 8U
1842 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1844 #define FPU_MVFR0_Single_precision_Pos 4U
1845 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1847 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1848 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1850 /* Media and FP Feature Register 1 Definitions */
1851 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1852 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1854 #define FPU_MVFR1_FP_HPFP_Pos 24U
1855 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1857 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1858 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1860 #define FPU_MVFR1_FtZ_mode_Pos 0U
1861 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1863 
1876 typedef struct
1877 {
1878  __IOM uint32_t DHCSR;
1879  __OM uint32_t DCRSR;
1880  __IOM uint32_t DCRDR;
1881  __IOM uint32_t DEMCR;
1882  uint32_t RESERVED4[1U];
1883  __IOM uint32_t DAUTHCTRL;
1884  __IOM uint32_t DSCSR;
1885 } CoreDebug_Type;
1886 
1887 /* Debug Halting Control and Status Register Definitions */
1888 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1889 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1891 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1892 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1894 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1895 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1897 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1898 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1900 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1901 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1903 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1904 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1906 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1907 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1909 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1910 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1912 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1913 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1915 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1916 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1918 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1919 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1921 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1922 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1924 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1925 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1927 /* Debug Core Register Selector Register Definitions */
1928 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1929 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1931 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1932 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1934 /* Debug Exception and Monitor Control Register Definitions */
1935 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1936 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1938 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1939 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1941 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1942 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1944 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1945 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1947 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1948 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1950 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1951 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1953 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1954 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1956 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1957 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1959 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1960 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1962 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1963 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1965 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1966 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1968 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1969 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1971 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1972 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1974 /* Debug Authentication Control Register Definitions */
1975 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1976 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1978 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1979 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1981 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1982 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1984 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1985 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1987 /* Debug Security Control and Status Register Definitions */
1988 #define CoreDebug_DSCSR_CDS_Pos 16U
1989 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1991 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1992 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1994 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1995 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1997 
2013 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2014 
2021 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2022 
2033 /* Memory mapping of Core Hardware */
2034  #define SCS_BASE (0xE000E000UL)
2035  #define ITM_BASE (0xE0000000UL)
2036  #define DWT_BASE (0xE0001000UL)
2037  #define TPI_BASE (0xE0040000UL)
2038  #define CoreDebug_BASE (0xE000EDF0UL)
2039  #define SysTick_BASE (SCS_BASE + 0x0010UL)
2040  #define NVIC_BASE (SCS_BASE + 0x0100UL)
2041  #define SCB_BASE (SCS_BASE + 0x0D00UL)
2043  #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
2044  #define SCB ((SCB_Type *) SCB_BASE )
2045  #define SysTick ((SysTick_Type *) SysTick_BASE )
2046  #define NVIC ((NVIC_Type *) NVIC_BASE )
2047  #define ITM ((ITM_Type *) ITM_BASE )
2048  #define DWT ((DWT_Type *) DWT_BASE )
2049  #define TPI ((TPI_Type *) TPI_BASE )
2050  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
2052  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2053  #define MPU_BASE (SCS_BASE + 0x0D90UL)
2054  #define MPU ((MPU_Type *) MPU_BASE )
2055  #endif
2056 
2057  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2058  #define SAU_BASE (SCS_BASE + 0x0DD0UL)
2059  #define SAU ((SAU_Type *) SAU_BASE )
2060  #endif
2061 
2062  #define FPU_BASE (SCS_BASE + 0x0F30UL)
2063  #define FPU ((FPU_Type *) FPU_BASE )
2065 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2066  #define SCS_BASE_NS (0xE002E000UL)
2067  #define CoreDebug_BASE_NS (0xE002EDF0UL)
2068  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
2069  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
2070  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
2072  #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
2073  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
2074  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
2075  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
2076  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
2078  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2079  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
2080  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
2081  #endif
2082 
2083  #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
2084  #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
2086 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2087 
2091 /*******************************************************************************
2092  * Hardware Abstraction Layer
2093  Core Function Interface contains:
2094  - Core NVIC Functions
2095  - Core SysTick Functions
2096  - Core Debug Functions
2097  - Core Register Access Functions
2098  ******************************************************************************/
2105 /* ########################## NVIC functions #################################### */
2113 #ifdef CMSIS_NVIC_VIRTUAL
2114  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2115  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2116  #endif
2117  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2118 #else
2119  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2120  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2121  #define NVIC_EnableIRQ __NVIC_EnableIRQ
2122  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2123  #define NVIC_DisableIRQ __NVIC_DisableIRQ
2124  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2125  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2126  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2127  #define NVIC_GetActive __NVIC_GetActive
2128  #define NVIC_SetPriority __NVIC_SetPriority
2129  #define NVIC_GetPriority __NVIC_GetPriority
2130  #define NVIC_SystemReset __NVIC_SystemReset
2131 #endif /* CMSIS_NVIC_VIRTUAL */
2132 
2133 #ifdef CMSIS_VECTAB_VIRTUAL
2134  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2135  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2136  #endif
2137  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2138 #else
2139  #define NVIC_SetVector __NVIC_SetVector
2140  #define NVIC_GetVector __NVIC_GetVector
2141 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2142 
2143 #define NVIC_USER_IRQ_OFFSET 16
2144 
2145 
2146 
2156 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2157 {
2158  uint32_t reg_value;
2159  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2160 
2161  reg_value = SCB->AIRCR; /* read old register configuration */
2162  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2163  reg_value = (reg_value |
2164  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2165  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2166  SCB->AIRCR = reg_value;
2167 }
2168 
2169 
2175 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2176 {
2177  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2178 }
2179 
2180 
2187 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2188 {
2189  if ((int32_t)(IRQn) >= 0)
2190  {
2191  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2192  }
2193 }
2194 
2195 
2204 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2205 {
2206  if ((int32_t)(IRQn) >= 0)
2207  {
2208  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2209  }
2210  else
2211  {
2212  return(0U);
2213  }
2214 }
2215 
2216 
2223 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2224 {
2225  if ((int32_t)(IRQn) >= 0)
2226  {
2227  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2228  __DSB();
2229  __ISB();
2230  }
2231 }
2232 
2233 
2242 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2243 {
2244  if ((int32_t)(IRQn) >= 0)
2245  {
2246  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2247  }
2248  else
2249  {
2250  return(0U);
2251  }
2252 }
2253 
2254 
2261 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2262 {
2263  if ((int32_t)(IRQn) >= 0)
2264  {
2265  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2266  }
2267 }
2268 
2269 
2276 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2277 {
2278  if ((int32_t)(IRQn) >= 0)
2279  {
2280  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2281  }
2282 }
2283 
2284 
2293 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2294 {
2295  if ((int32_t)(IRQn) >= 0)
2296  {
2297  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2298  }
2299  else
2300  {
2301  return(0U);
2302  }
2303 }
2304 
2305 
2306 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2307 
2315 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2316 {
2317  if ((int32_t)(IRQn) >= 0)
2318  {
2319  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2320  }
2321  else
2322  {
2323  return(0U);
2324  }
2325 }
2326 
2327 
2336 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2337 {
2338  if ((int32_t)(IRQn) >= 0)
2339  {
2340  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2341  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2342  }
2343  else
2344  {
2345  return(0U);
2346  }
2347 }
2348 
2349 
2358 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2359 {
2360  if ((int32_t)(IRQn) >= 0)
2361  {
2362  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2363  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2364  }
2365  else
2366  {
2367  return(0U);
2368  }
2369 }
2370 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2371 
2372 
2382 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2383 {
2384  if ((int32_t)(IRQn) >= 0)
2385  {
2386  NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2387  }
2388  else
2389  {
2390  SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2391  }
2392 }
2393 
2394 
2404 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2405 {
2406 
2407  if ((int32_t)(IRQn) >= 0)
2408  {
2409  return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2410  }
2411  else
2412  {
2413  return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2414  }
2415 }
2416 
2417 
2429 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2430 {
2431  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2432  uint32_t PreemptPriorityBits;
2433  uint32_t SubPriorityBits;
2434 
2435  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2436  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2437 
2438  return (
2439  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2440  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2441  );
2442 }
2443 
2444 
2456 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2457 {
2458  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2459  uint32_t PreemptPriorityBits;
2460  uint32_t SubPriorityBits;
2461 
2462  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2463  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2464 
2465  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2466  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2467 }
2468 
2469 
2479 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2480 {
2481  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2482  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2483  __DSB();
2484 }
2485 
2486 
2495 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2496 {
2497  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2498  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2499 }
2500 
2501 
2506 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2507 {
2508  __DSB(); /* Ensure all outstanding memory accesses included
2509  buffered write are completed before reset */
2510  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2511  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2512  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2513  __DSB(); /* Ensure completion of memory access */
2514 
2515  for(;;) /* wait until reset */
2516  {
2517  __NOP();
2518  }
2519 }
2520 
2521 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2522 
2531 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2532 {
2533  uint32_t reg_value;
2534  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2535 
2536  reg_value = SCB_NS->AIRCR; /* read old register configuration */
2537  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2538  reg_value = (reg_value |
2539  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2540  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2541  SCB_NS->AIRCR = reg_value;
2542 }
2543 
2544 
2550 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2551 {
2552  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2553 }
2554 
2555 
2562 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2563 {
2564  if ((int32_t)(IRQn) >= 0)
2565  {
2566  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2567  }
2568 }
2569 
2570 
2579 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2580 {
2581  if ((int32_t)(IRQn) >= 0)
2582  {
2583  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2584  }
2585  else
2586  {
2587  return(0U);
2588  }
2589 }
2590 
2591 
2598 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2599 {
2600  if ((int32_t)(IRQn) >= 0)
2601  {
2602  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2603  }
2604 }
2605 
2606 
2615 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2616 {
2617  if ((int32_t)(IRQn) >= 0)
2618  {
2619  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2620  }
2621  else
2622  {
2623  return(0U);
2624  }
2625 }
2626 
2627 
2634 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2635 {
2636  if ((int32_t)(IRQn) >= 0)
2637  {
2638  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2639  }
2640 }
2641 
2642 
2649 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2650 {
2651  if ((int32_t)(IRQn) >= 0)
2652  {
2653  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2654  }
2655 }
2656 
2657 
2666 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2667 {
2668  if ((int32_t)(IRQn) >= 0)
2669  {
2670  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2671  }
2672  else
2673  {
2674  return(0U);
2675  }
2676 }
2677 
2678 
2688 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2689 {
2690  if ((int32_t)(IRQn) >= 0)
2691  {
2692  NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2693  }
2694  else
2695  {
2696  SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2697  }
2698 }
2699 
2700 
2709 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2710 {
2711 
2712  if ((int32_t)(IRQn) >= 0)
2713  {
2714  return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2715  }
2716  else
2717  {
2718  return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2719  }
2720 }
2721 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2722 
2725 /* ########################## MPU functions #################################### */
2726 
2727 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2728 
2729 #include "mpu_armv8.h"
2730 
2731 #endif
2732 
2733 /* ########################## FPU functions #################################### */
2749 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2750 {
2751  uint32_t mvfr0;
2752 
2753  mvfr0 = FPU->MVFR0;
2754  if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2755  {
2756  return 2U; /* Double + Single precision FPU */
2757  }
2758  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2759  {
2760  return 1U; /* Single precision FPU */
2761  }
2762  else
2763  {
2764  return 0U; /* No FPU */
2765  }
2766 }
2767 
2768 
2773 /* ########################## SAU functions #################################### */
2781 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2782 
2787 __STATIC_INLINE void TZ_SAU_Enable(void)
2788 {
2789  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2790 }
2791 
2792 
2793 
2798 __STATIC_INLINE void TZ_SAU_Disable(void)
2799 {
2800  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2801 }
2802 
2803 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2804 
2810 /* ################################## SysTick function ############################################ */
2818 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2819 
2831 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2832 {
2833  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2834  {
2835  return (1UL); /* Reload value impossible */
2836  }
2837 
2838  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2839  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2840  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2841  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2842  SysTick_CTRL_TICKINT_Msk |
2843  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2844  return (0UL); /* Function successful */
2845 }
2846 
2847 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2848 
2860 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2861 {
2862  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2863  {
2864  return (1UL); /* Reload value impossible */
2865  }
2866 
2867  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2868  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2869  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2870  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2871  SysTick_CTRL_TICKINT_Msk |
2872  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2873  return (0UL); /* Function successful */
2874 }
2875 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2876 
2877 #endif
2878 
2883 /* ##################################### Debug In/Output function ########################################### */
2891 extern volatile int32_t ITM_RxBuffer;
2892 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2903 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2904 {
2905  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2906  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2907  {
2908  while (ITM->PORT[0U].u32 == 0UL)
2909  {
2910  __NOP();
2911  }
2912  ITM->PORT[0U].u8 = (uint8_t)ch;
2913  }
2914  return (ch);
2915 }
2916 
2917 
2924 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2925 {
2926  int32_t ch = -1; /* no character available */
2927 
2928  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2929  {
2930  ch = ITM_RxBuffer;
2931  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2932  }
2933 
2934  return (ch);
2935 }
2936 
2937 
2944 __STATIC_INLINE int32_t ITM_CheckChar (void)
2945 {
2946 
2947  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2948  {
2949  return (0); /* no character available */
2950  }
2951  else
2952  {
2953  return (1); /* character available */
2954  }
2955 }
2956 
2962 #ifdef __cplusplus
2963 }
2964 #endif
2965 
2966 #endif /* __CORE_ARMV81MML_H_DEPENDANT */
2967 
2968 #endif /* __CMSIS_GENERIC */
xPSR_Type::@545::_reserved1
uint32_t _reserved1
Definition: core_armv81mml.h:379
SCB
#define SCB
Definition: core_armv81mml.h:2044
xPSR_Type::@545::Q
uint32_t Q
Definition: core_armv81mml.h:382
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2054
COMP2
#define COMP2
Definition: stm32h735xx.h:2592
CONTROL_Type::@546::SFPA
uint32_t SFPA
Definition: core_armv81mml.h:430
COMP1
#define COMP1
Definition: stm32h735xx.h:2591
__OM
#define __OM
Definition: core_armv81mml.h:281
xPSR_Type::@545::ISR
uint32_t ISR
Definition: core_armv81mml.h:376
IRQn
IRQn
Definition: MIMXRT1052.h:78
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2106
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv81mml.h:1048
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:331
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv81mml.h:635
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:944
CONTROL_Type::@546::nPRIV
uint32_t nPRIV
Definition: core_armv81mml.h:427
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: core_armv81mml.h:1842
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:274
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1031
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:933
IPSR_Type::@544::_reserved0
uint32_t _reserved0
Definition: core_armv81mml.h:359
xPSR_Type::@545::T
uint32_t T
Definition: core_armv81mml.h:380
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1052.h:91
__IM
#define __IM
Definition: core_armv81mml.h:280
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2079
ITM_Type::@547::u16
__OM uint16_t u16
Definition: core_armv81mml.h:1092
xPSR_Type::@545::V
uint32_t V
Definition: core_armv81mml.h:383
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2701
APSR_Type::@543::Q
uint32_t Q
Definition: core_armv81mml.h:322
__NOP
#define __NOP
No Operation.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:416
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2010
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1978
APSR_Type::@543::N
uint32_t N
Definition: core_armv81mml.h:326
xPSR_Type::@545::C
uint32_t C
Definition: core_armv81mml.h:384
APSR_Type::@543::Z
uint32_t Z
Definition: core_armv81mml.h:325
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:455
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_armv81mml.h:1165
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv81mml.h:1051
ITM
#define ITM
Definition: core_armv81mml.h:2047
APSR_Type::@543::GE
uint32_t GE
Definition: core_armv81mml.h:320
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1119
xPSR_Type::@545::_reserved0
uint32_t _reserved0
Definition: core_armv81mml.h:377
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1902
ITM_Type::@547::u32
__OM uint32_t u32
Definition: core_armv81mml.h:1093
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1993
__STATIC_INLINE
#define __STATIC_INLINE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:63
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
cmsis_version.h
CMSIS Core(M) Version definitions.
xPSR_Type::@545::GE
uint32_t GE
Definition: core_armv81mml.h:378
xPSR_Type::@545::N
uint32_t N
Definition: core_armv81mml.h:386
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv81mml.h:1058
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f407xx.h:66
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:386
APSR_Type::@543::V
uint32_t V
Definition: core_armv81mml.h:323
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2129
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv81mml.h:613
APSR_Type::@543::_reserved0
uint32_t _reserved0
Definition: core_armv81mml.h:319
APSR_Type::@543::_reserved1
uint32_t _reserved1
Definition: core_armv81mml.h:321
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1871
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1940
CONTROL_Type::@546::_reserved1
uint32_t _reserved1
Definition: core_armv81mml.h:431
NVIC
#define NVIC
Definition: core_armv81mml.h:2046
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2681
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2145
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_armv81mml.h:2892
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1639
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_armv81mml.h:628
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv81mml.h:2128
__IOM
#define __IOM
Definition: core_armv81mml.h:282
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1527
ITM_Type::@547::u8
__OM uint8_t u8
Definition: core_armv81mml.h:1091
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1269
IPSR_Type::@544::ISR
uint32_t ISR
Definition: core_armv81mml.h:358
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv81mml.h:1054
APSR_Type::@543::C
uint32_t C
Definition: core_armv81mml.h:324
__NO_RETURN
#define __NO_RETURN
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:69
COMP12
#define COMP12
Definition: stm32h735xx.h:2590
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:421
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1890
CONTROL_Type::@546::SPSEL
uint32_t SPSEL
Definition: core_armv81mml.h:428
SysTick
#define SysTick
Definition: core_armv81mml.h:2045
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv81mml.h:2143
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:921
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_armv81mml.h:629
cmsis_compiler.h
CMSIS compiler generic header file.
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2156
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2032
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2199
xPSR_Type::@545::Z
uint32_t Z
Definition: core_armv81mml.h:385
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1959
xPSR_Type::@545::IT
uint32_t IT
Definition: core_armv81mml.h:381
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1052.h:266
CONTROL_Type::@546::FPCA
uint32_t FPCA
Definition: core_armv81mml.h:429
FPU
#define FPU
Definition: core_armv81mml.h:2063
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:979
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:313
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1921
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: core_armv81mml.h:1845
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_armv81mml.h:614

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:13:47