stm32h735xx.h
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1 
34 #ifndef STM32H735xx_H
35 #define STM32H735xx_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
49 typedef enum
50 {
51 /****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52  NonMaskableInt_IRQn = -14,
53  HardFault_IRQn = -13,
54  MemoryManagement_IRQn = -12,
55  BusFault_IRQn = -11,
56  UsageFault_IRQn = -10,
57  SVCall_IRQn = -5,
58  DebugMonitor_IRQn = -4,
59  PendSV_IRQn = -2,
60  SysTick_IRQn = -1,
61 /****** STM32 specific Interrupt Numbers **********************************************************************/
62  WWDG_IRQn = 0,
63  PVD_AVD_IRQn = 1,
64  TAMP_STAMP_IRQn = 2,
65  RTC_WKUP_IRQn = 3,
66  FLASH_IRQn = 4,
67  RCC_IRQn = 5,
68  EXTI0_IRQn = 6,
69  EXTI1_IRQn = 7,
70  EXTI2_IRQn = 8,
71  EXTI3_IRQn = 9,
72  EXTI4_IRQn = 10,
73  DMA1_Stream0_IRQn = 11,
74  DMA1_Stream1_IRQn = 12,
75  DMA1_Stream2_IRQn = 13,
76  DMA1_Stream3_IRQn = 14,
77  DMA1_Stream4_IRQn = 15,
78  DMA1_Stream5_IRQn = 16,
79  DMA1_Stream6_IRQn = 17,
80  ADC_IRQn = 18,
81  FDCAN1_IT0_IRQn = 19,
82  FDCAN2_IT0_IRQn = 20,
83  FDCAN1_IT1_IRQn = 21,
84  FDCAN2_IT1_IRQn = 22,
85  EXTI9_5_IRQn = 23,
86  TIM1_BRK_IRQn = 24,
87  TIM1_UP_IRQn = 25,
88  TIM1_TRG_COM_IRQn = 26,
89  TIM1_CC_IRQn = 27,
90  TIM2_IRQn = 28,
91  TIM3_IRQn = 29,
92  TIM4_IRQn = 30,
93  I2C1_EV_IRQn = 31,
94  I2C1_ER_IRQn = 32,
95  I2C2_EV_IRQn = 33,
96  I2C2_ER_IRQn = 34,
97  SPI1_IRQn = 35,
98  SPI2_IRQn = 36,
99  USART1_IRQn = 37,
100  USART2_IRQn = 38,
101  USART3_IRQn = 39,
102  EXTI15_10_IRQn = 40,
103  RTC_Alarm_IRQn = 41,
104  TIM8_BRK_TIM12_IRQn = 43,
105  TIM8_UP_TIM13_IRQn = 44,
106  TIM8_TRG_COM_TIM14_IRQn = 45,
107  TIM8_CC_IRQn = 46,
108  DMA1_Stream7_IRQn = 47,
109  FMC_IRQn = 48,
110  SDMMC1_IRQn = 49,
111  TIM5_IRQn = 50,
112  SPI3_IRQn = 51,
113  UART4_IRQn = 52,
114  UART5_IRQn = 53,
115  TIM6_DAC_IRQn = 54,
116  TIM7_IRQn = 55,
117  DMA2_Stream0_IRQn = 56,
118  DMA2_Stream1_IRQn = 57,
119  DMA2_Stream2_IRQn = 58,
120  DMA2_Stream3_IRQn = 59,
121  DMA2_Stream4_IRQn = 60,
122  ETH_IRQn = 61,
123  ETH_WKUP_IRQn = 62,
124  FDCAN_CAL_IRQn = 63,
125  DMA2_Stream5_IRQn = 68,
126  DMA2_Stream6_IRQn = 69,
127  DMA2_Stream7_IRQn = 70,
128  USART6_IRQn = 71,
129  I2C3_EV_IRQn = 72,
130  I2C3_ER_IRQn = 73,
131  OTG_HS_EP1_OUT_IRQn = 74,
132  OTG_HS_EP1_IN_IRQn = 75,
133  OTG_HS_WKUP_IRQn = 76,
134  OTG_HS_IRQn = 77,
135  DCMI_PSSI_IRQn = 78,
136  CRYP_IRQn = 79,
137  HASH_RNG_IRQn = 80,
138  FPU_IRQn = 81,
139  UART7_IRQn = 82,
140  UART8_IRQn = 83,
141  SPI4_IRQn = 84,
142  SPI5_IRQn = 85,
143  SPI6_IRQn = 86,
144  SAI1_IRQn = 87,
145  LTDC_IRQn = 88,
146  LTDC_ER_IRQn = 89,
147  DMA2D_IRQn = 90,
148  OCTOSPI1_IRQn = 92,
149  LPTIM1_IRQn = 93,
150  CEC_IRQn = 94,
151  I2C4_EV_IRQn = 95,
152  I2C4_ER_IRQn = 96,
153  SPDIF_RX_IRQn = 97,
154  DMAMUX1_OVR_IRQn = 102,
155  DFSDM1_FLT0_IRQn = 110,
156  DFSDM1_FLT1_IRQn = 111,
157  DFSDM1_FLT2_IRQn = 112,
158  DFSDM1_FLT3_IRQn = 113,
159  SWPMI1_IRQn = 115,
160  TIM15_IRQn = 116,
161  TIM16_IRQn = 117,
162  TIM17_IRQn = 118,
163  MDIOS_WKUP_IRQn = 119,
164  MDIOS_IRQn = 120,
165  MDMA_IRQn = 122,
166  SDMMC2_IRQn = 124,
167  HSEM1_IRQn = 125,
168  ADC3_IRQn = 127,
169  DMAMUX2_OVR_IRQn = 128,
170  BDMA_Channel0_IRQn = 129,
171  BDMA_Channel1_IRQn = 130,
172  BDMA_Channel2_IRQn = 131,
173  BDMA_Channel3_IRQn = 132,
174  BDMA_Channel4_IRQn = 133,
175  BDMA_Channel5_IRQn = 134,
176  BDMA_Channel6_IRQn = 135,
177  BDMA_Channel7_IRQn = 136,
178  COMP_IRQn = 137 ,
179  LPTIM2_IRQn = 138,
180  LPTIM3_IRQn = 139,
181  LPTIM4_IRQn = 140,
182  LPTIM5_IRQn = 141,
183  LPUART1_IRQn = 142,
184  CRS_IRQn = 144,
185  ECC_IRQn = 145,
186  SAI4_IRQn = 146,
187  DTS_IRQn = 147,
188  WAKEUP_PIN_IRQn = 149,
189  OCTOSPI2_IRQn = 150,
190  OTFDEC1_IRQn = 151,
191  OTFDEC2_IRQn = 152,
192  FMAC_IRQn = 153,
193  CORDIC_IRQn = 154,
194  UART9_IRQn = 155,
195  USART10_IRQn = 156,
196  I2C5_EV_IRQn = 157,
197  I2C5_ER_IRQn = 158,
198  FDCAN3_IT0_IRQn = 159,
199  FDCAN3_IT1_IRQn = 160,
200  TIM23_IRQn = 161,
201  TIM24_IRQn = 162,
202 } IRQn_Type;
203 
212 #define SMPS
219 #define __CM7_REV 0x0100U
220 #define __MPU_PRESENT 1
221 #define __NVIC_PRIO_BITS 4
222 #define __Vendor_SysTickConfig 0
223 #define __FPU_PRESENT 1
224 #define __ICACHE_PRESENT 1
225 #define __DCACHE_PRESENT 1
226 #include "core_cm7.h"
235 #include "system_stm32h7xx.h"
236 #include <stdint.h>
237 
246 typedef struct
247 {
248  __IO uint32_t ISR;
249  __IO uint32_t IER;
250  __IO uint32_t CR;
251  __IO uint32_t CFGR;
252  __IO uint32_t CFGR2;
253  __IO uint32_t SMPR1;
254  __IO uint32_t SMPR2;
255  __IO uint32_t PCSEL_RES0;
256  __IO uint32_t LTR1_TR1;
257  __IO uint32_t HTR1_TR2;
258  __IO uint32_t RES1_TR3;
259  uint32_t RESERVED2;
260  __IO uint32_t SQR1;
261  __IO uint32_t SQR2;
262  __IO uint32_t SQR3;
263  __IO uint32_t SQR4;
264  __IO uint32_t DR;
265  uint32_t RESERVED3;
266  uint32_t RESERVED4;
267  __IO uint32_t JSQR;
268  uint32_t RESERVED5[4];
269  __IO uint32_t OFR1;
270  __IO uint32_t OFR2;
271  __IO uint32_t OFR3;
272  __IO uint32_t OFR4;
273  uint32_t RESERVED6[4];
274  __IO uint32_t JDR1;
275  __IO uint32_t JDR2;
276  __IO uint32_t JDR3;
277  __IO uint32_t JDR4;
278  uint32_t RESERVED7[4];
279  __IO uint32_t AWD2CR;
280  __IO uint32_t AWD3CR;
281  uint32_t RESERVED8;
282  uint32_t RESERVED9;
283  __IO uint32_t LTR2_DIFSEL;
284  __IO uint32_t HTR2_CALFACT;
285  __IO uint32_t LTR3_RES10;
286  __IO uint32_t HTR3_RES11;
287  __IO uint32_t DIFSEL_RES12;
288  __IO uint32_t CALFACT_RES13;
289  __IO uint32_t CALFACT2_RES14;
290 } ADC_TypeDef;
291 
292 
293 typedef struct
294 {
295 __IO uint32_t CSR;
296 uint32_t RESERVED;
297 __IO uint32_t CCR;
298 __IO uint32_t CDR;
299 __IO uint32_t CDR2;
301 } ADC_Common_TypeDef;
302 
303 
308 typedef struct
309 {
310  __IO uint32_t CSR;
311  __IO uint32_t CCR;
312 } VREFBUF_TypeDef;
313 
314 
319 typedef struct
320 {
321  __IO uint32_t CREL;
322  __IO uint32_t ENDN;
323  __IO uint32_t RESERVED1;
324  __IO uint32_t DBTP;
325  __IO uint32_t TEST;
326  __IO uint32_t RWD;
327  __IO uint32_t CCCR;
328  __IO uint32_t NBTP;
329  __IO uint32_t TSCC;
330  __IO uint32_t TSCV;
331  __IO uint32_t TOCC;
332  __IO uint32_t TOCV;
333  __IO uint32_t RESERVED2[4];
334  __IO uint32_t ECR;
335  __IO uint32_t PSR;
336  __IO uint32_t TDCR;
337  __IO uint32_t RESERVED3;
338  __IO uint32_t IR;
339  __IO uint32_t IE;
340  __IO uint32_t ILS;
341  __IO uint32_t ILE;
342  __IO uint32_t RESERVED4[8];
343  __IO uint32_t GFC;
344  __IO uint32_t SIDFC;
345  __IO uint32_t XIDFC;
346  __IO uint32_t RESERVED5;
347  __IO uint32_t XIDAM;
348  __IO uint32_t HPMS;
349  __IO uint32_t NDAT1;
350  __IO uint32_t NDAT2;
351  __IO uint32_t RXF0C;
352  __IO uint32_t RXF0S;
353  __IO uint32_t RXF0A;
354  __IO uint32_t RXBC;
355  __IO uint32_t RXF1C;
356  __IO uint32_t RXF1S;
357  __IO uint32_t RXF1A;
358  __IO uint32_t RXESC;
359  __IO uint32_t TXBC;
360  __IO uint32_t TXFQS;
361  __IO uint32_t TXESC;
362  __IO uint32_t TXBRP;
363  __IO uint32_t TXBAR;
364  __IO uint32_t TXBCR;
365  __IO uint32_t TXBTO;
366  __IO uint32_t TXBCF;
367  __IO uint32_t TXBTIE;
368  __IO uint32_t TXBCIE;
369  __IO uint32_t RESERVED6[2];
370  __IO uint32_t TXEFC;
371  __IO uint32_t TXEFS;
372  __IO uint32_t TXEFA;
373  __IO uint32_t RESERVED7;
374 } FDCAN_GlobalTypeDef;
375 
380 typedef struct
381 {
382  __IO uint32_t TTTMC;
383  __IO uint32_t TTRMC;
384  __IO uint32_t TTOCF;
385  __IO uint32_t TTMLM;
386  __IO uint32_t TURCF;
387  __IO uint32_t TTOCN;
388  __IO uint32_t TTGTP;
389  __IO uint32_t TTTMK;
390  __IO uint32_t TTIR;
391  __IO uint32_t TTIE;
392  __IO uint32_t TTILS;
393  __IO uint32_t TTOST;
394  __IO uint32_t TURNA;
395  __IO uint32_t TTLGT;
396  __IO uint32_t TTCTC;
397  __IO uint32_t TTCPT;
398  __IO uint32_t TTCSM;
399  __IO uint32_t RESERVED1[111];
400  __IO uint32_t TTTS;
401 } TTCAN_TypeDef;
402 
407 typedef struct
408 {
409  __IO uint32_t CREL;
410  __IO uint32_t CCFG;
411  __IO uint32_t CSTAT;
412  __IO uint32_t CWD;
413  __IO uint32_t IR;
414  __IO uint32_t IE;
415 } FDCAN_ClockCalibrationUnit_TypeDef;
416 
417 
422 typedef struct
423 {
424  __IO uint32_t CR;
425  __IO uint32_t CFGR;
426  __IO uint32_t TXDR;
427  __IO uint32_t RXDR;
428  __IO uint32_t ISR;
429  __IO uint32_t IER;
430 }CEC_TypeDef;
431 
435 typedef struct
436 {
437  __IO uint32_t CSR;
438  __IO uint32_t WDATA;
439  __IO uint32_t RDATA;
440 } CORDIC_TypeDef;
441 
446 typedef struct
447 {
448  __IO uint32_t DR;
449  __IO uint32_t IDR;
450  __IO uint32_t CR;
451  uint32_t RESERVED2;
452  __IO uint32_t INIT;
453  __IO uint32_t POL;
454 } CRC_TypeDef;
455 
456 
460 typedef struct
461 {
462 __IO uint32_t CR;
463 __IO uint32_t CFGR;
464 __IO uint32_t ISR;
465 __IO uint32_t ICR;
466 } CRS_TypeDef;
467 
468 
473 typedef struct
474 {
475  __IO uint32_t CR;
476  __IO uint32_t SWTRIGR;
477  __IO uint32_t DHR12R1;
478  __IO uint32_t DHR12L1;
479  __IO uint32_t DHR8R1;
480  __IO uint32_t DHR12R2;
481  __IO uint32_t DHR12L2;
482  __IO uint32_t DHR8R2;
483  __IO uint32_t DHR12RD;
484  __IO uint32_t DHR12LD;
485  __IO uint32_t DHR8RD;
486  __IO uint32_t DOR1;
487  __IO uint32_t DOR2;
488  __IO uint32_t SR;
489  __IO uint32_t CCR;
490  __IO uint32_t MCR;
491  __IO uint32_t SHSR1;
492  __IO uint32_t SHSR2;
493  __IO uint32_t SHHR;
494  __IO uint32_t SHRR;
495 } DAC_TypeDef;
496 
500 typedef struct
501 {
502  __IO uint32_t FLTCR1;
503  __IO uint32_t FLTCR2;
504  __IO uint32_t FLTISR;
505  __IO uint32_t FLTICR;
506  __IO uint32_t FLTJCHGR;
507  __IO uint32_t FLTFCR;
508  __IO uint32_t FLTJDATAR;
509  __IO uint32_t FLTRDATAR;
510  __IO uint32_t FLTAWHTR;
511  __IO uint32_t FLTAWLTR;
512  __IO uint32_t FLTAWSR;
513  __IO uint32_t FLTAWCFR;
514  __IO uint32_t FLTEXMAX;
515  __IO uint32_t FLTEXMIN;
516  __IO uint32_t FLTCNVTIMR;
517 } DFSDM_Filter_TypeDef;
518 
522 typedef struct
523 {
524  __IO uint32_t CHCFGR1;
525  __IO uint32_t CHCFGR2;
526  __IO uint32_t CHAWSCDR;
528  __IO uint32_t CHWDATAR;
529  __IO uint32_t CHDATINR;
530 } DFSDM_Channel_TypeDef;
531 
535 typedef struct
536 {
537  __IO uint32_t IDCODE;
538  __IO uint32_t CR;
539  uint32_t RESERVED4[11];
540  __IO uint32_t APB3FZ1;
541  uint32_t RESERVED5;
542  __IO uint32_t APB1LFZ1;
543  uint32_t RESERVED6;
544  __IO uint32_t APB1HFZ1;
545  uint32_t RESERVED7;
546  __IO uint32_t APB2FZ1;
547  uint32_t RESERVED8;
548  __IO uint32_t APB4FZ1;
549  __IO uint32_t RESERVED9[990];
550  __IO uint32_t PIDR4;
551  __IO uint32_t RESERVED10[3];
552  __IO uint32_t PIDR0;
553  __IO uint32_t PIDR1;
554  __IO uint32_t PIDR2;
555  __IO uint32_t PIDR3;
556  __IO uint32_t CIDR0;
557  __IO uint32_t CIDR1;
558  __IO uint32_t CIDR2;
559  __IO uint32_t CIDR3;
560 }DBGMCU_TypeDef;
565 typedef struct
566 {
567  __IO uint32_t CR;
568  __IO uint32_t SR;
569  __IO uint32_t RISR;
570  __IO uint32_t IER;
571  __IO uint32_t MISR;
572  __IO uint32_t ICR;
573  __IO uint32_t ESCR;
574  __IO uint32_t ESUR;
575  __IO uint32_t CWSTRTR;
576  __IO uint32_t CWSIZER;
577  __IO uint32_t DR;
578 } DCMI_TypeDef;
579 
584 typedef struct
585 {
586  __IO uint32_t CR;
587  __IO uint32_t SR;
588  __IO uint32_t RIS;
589  __IO uint32_t IER;
590  __IO uint32_t MIS;
591  __IO uint32_t ICR;
592  __IO uint32_t RESERVED1[4];
593  __IO uint32_t DR;
594  __IO uint32_t RESERVED2[241];
595  __IO uint32_t HWCFGR;
596  __IO uint32_t VERR;
597  __IO uint32_t IPIDR;
598  __IO uint32_t SIDR;
599 } PSSI_TypeDef;
600 
605 typedef struct
606 {
607  __IO uint32_t CR;
608  __IO uint32_t NDTR;
609  __IO uint32_t PAR;
610  __IO uint32_t M0AR;
611  __IO uint32_t M1AR;
612  __IO uint32_t FCR;
613 } DMA_Stream_TypeDef;
614 
615 typedef struct
616 {
617  __IO uint32_t LISR;
618  __IO uint32_t HISR;
619  __IO uint32_t LIFCR;
620  __IO uint32_t HIFCR;
621 } DMA_TypeDef;
622 
623 typedef struct
624 {
625  __IO uint32_t CCR;
626  __IO uint32_t CNDTR;
627  __IO uint32_t CPAR;
628  __IO uint32_t CM0AR;
629  __IO uint32_t CM1AR;
630 } BDMA_Channel_TypeDef;
631 
632 typedef struct
633 {
634  __IO uint32_t ISR;
635  __IO uint32_t IFCR;
636 } BDMA_TypeDef;
637 
638 typedef struct
639 {
640  __IO uint32_t CCR;
641 }DMAMUX_Channel_TypeDef;
642 
643 typedef struct
644 {
645  __IO uint32_t CSR;
646  __IO uint32_t CFR;
647 }DMAMUX_ChannelStatus_TypeDef;
648 
649 typedef struct
650 {
651  __IO uint32_t RGCR;
652 }DMAMUX_RequestGen_TypeDef;
653 
654 typedef struct
655 {
656  __IO uint32_t RGSR;
657  __IO uint32_t RGCFR;
658 }DMAMUX_RequestGenStatus_TypeDef;
659 
663 typedef struct
664 {
665  __IO uint32_t GISR0;
666 }MDMA_TypeDef;
667 
668 typedef struct
669 {
670  __IO uint32_t CISR;
671  __IO uint32_t CIFCR;
672  __IO uint32_t CESR;
673  __IO uint32_t CCR;
674  __IO uint32_t CTCR;
675  __IO uint32_t CBNDTR;
676  __IO uint32_t CSAR;
677  __IO uint32_t CDAR;
678  __IO uint32_t CBRUR;
679  __IO uint32_t CLAR;
680  __IO uint32_t CTBR;
681  uint32_t RESERVED0;
682  __IO uint32_t CMAR;
683  __IO uint32_t CMDR;
684 }MDMA_Channel_TypeDef;
685 
690 typedef struct
691 {
692  __IO uint32_t CR;
693  __IO uint32_t ISR;
694  __IO uint32_t IFCR;
695  __IO uint32_t FGMAR;
696  __IO uint32_t FGOR;
697  __IO uint32_t BGMAR;
698  __IO uint32_t BGOR;
699  __IO uint32_t FGPFCCR;
700  __IO uint32_t FGCOLR;
701  __IO uint32_t BGPFCCR;
702  __IO uint32_t BGCOLR;
703  __IO uint32_t FGCMAR;
704  __IO uint32_t BGCMAR;
705  __IO uint32_t OPFCCR;
706  __IO uint32_t OCOLR;
707  __IO uint32_t OMAR;
708  __IO uint32_t OOR;
709  __IO uint32_t NLR;
710  __IO uint32_t LWR;
711  __IO uint32_t AMTCR;
712  uint32_t RESERVED[236];
713  __IO uint32_t FGCLUT[256];
714  __IO uint32_t BGCLUT[256];
715 } DMA2D_TypeDef;
716 
717 
721 typedef struct
722 {
723  __IO uint32_t MACCR;
724  __IO uint32_t MACECR;
725  __IO uint32_t MACPFR;
726  __IO uint32_t MACWTR;
727  __IO uint32_t MACHT0R;
728  __IO uint32_t MACHT1R;
729  uint32_t RESERVED1[14];
730  __IO uint32_t MACVTR;
731  uint32_t RESERVED2;
732  __IO uint32_t MACVHTR;
733  uint32_t RESERVED3;
734  __IO uint32_t MACVIR;
735  __IO uint32_t MACIVIR;
736  uint32_t RESERVED4[2];
737  __IO uint32_t MACTFCR;
738  uint32_t RESERVED5[7];
739  __IO uint32_t MACRFCR;
740  uint32_t RESERVED6[7];
741  __IO uint32_t MACISR;
742  __IO uint32_t MACIER;
743  __IO uint32_t MACRXTXSR;
744  uint32_t RESERVED7;
745  __IO uint32_t MACPCSR;
746  __IO uint32_t MACRWKPFR;
747  uint32_t RESERVED8[2];
748  __IO uint32_t MACLCSR;
749  __IO uint32_t MACLTCR;
750  __IO uint32_t MACLETR;
751  __IO uint32_t MAC1USTCR;
752  uint32_t RESERVED9[12];
753  __IO uint32_t MACVR;
754  __IO uint32_t MACDR;
755  uint32_t RESERVED10;
756  __IO uint32_t MACHWF0R;
757  __IO uint32_t MACHWF1R;
758  __IO uint32_t MACHWF2R;
759  uint32_t RESERVED11[54];
760  __IO uint32_t MACMDIOAR;
761  __IO uint32_t MACMDIODR;
762  uint32_t RESERVED12[2];
763  __IO uint32_t MACARPAR;
764  uint32_t RESERVED13[59];
765  __IO uint32_t MACA0HR;
766  __IO uint32_t MACA0LR;
767  __IO uint32_t MACA1HR;
768  __IO uint32_t MACA1LR;
769  __IO uint32_t MACA2HR;
770  __IO uint32_t MACA2LR;
771  __IO uint32_t MACA3HR;
772  __IO uint32_t MACA3LR;
773  uint32_t RESERVED14[248];
774  __IO uint32_t MMCCR;
775  __IO uint32_t MMCRIR;
776  __IO uint32_t MMCTIR;
777  __IO uint32_t MMCRIMR;
778  __IO uint32_t MMCTIMR;
779  uint32_t RESERVED15[14];
780  __IO uint32_t MMCTSCGPR;
781  __IO uint32_t MMCTMCGPR;
782  uint32_t RESERVED16[5];
783  __IO uint32_t MMCTPCGR;
784  uint32_t RESERVED17[10];
785  __IO uint32_t MMCRCRCEPR;
786  __IO uint32_t MMCRAEPR;
787  uint32_t RESERVED18[10];
788  __IO uint32_t MMCRUPGR;
789  uint32_t RESERVED19[9];
790  __IO uint32_t MMCTLPIMSTR;
791  __IO uint32_t MMCTLPITCR;
792  __IO uint32_t MMCRLPIMSTR;
793  __IO uint32_t MMCRLPITCR;
794  uint32_t RESERVED20[65];
795  __IO uint32_t MACL3L4C0R;
796  __IO uint32_t MACL4A0R;
797  uint32_t RESERVED21[2];
798  __IO uint32_t MACL3A0R0R;
799  __IO uint32_t MACL3A1R0R;
800  __IO uint32_t MACL3A2R0R;
801  __IO uint32_t MACL3A3R0R;
802  uint32_t RESERVED22[4];
803  __IO uint32_t MACL3L4C1R;
804  __IO uint32_t MACL4A1R;
805  uint32_t RESERVED23[2];
806  __IO uint32_t MACL3A0R1R;
807  __IO uint32_t MACL3A1R1R;
808  __IO uint32_t MACL3A2R1R;
809  __IO uint32_t MACL3A3R1R;
810  uint32_t RESERVED24[108];
811  __IO uint32_t MACTSCR;
812  __IO uint32_t MACSSIR;
813  __IO uint32_t MACSTSR;
814  __IO uint32_t MACSTNR;
815  __IO uint32_t MACSTSUR;
816  __IO uint32_t MACSTNUR;
817  __IO uint32_t MACTSAR;
818  uint32_t RESERVED25;
819  __IO uint32_t MACTSSR;
820  uint32_t RESERVED26[3];
821  __IO uint32_t MACTTSSNR;
822  __IO uint32_t MACTTSSSR;
823  uint32_t RESERVED27[2];
824  __IO uint32_t MACACR;
825  uint32_t RESERVED28;
826  __IO uint32_t MACATSNR;
827  __IO uint32_t MACATSSR;
828  __IO uint32_t MACTSIACR;
829  __IO uint32_t MACTSEACR;
830  __IO uint32_t MACTSICNR;
831  __IO uint32_t MACTSECNR;
832  uint32_t RESERVED29[4];
833  __IO uint32_t MACPPSCR;
834  uint32_t RESERVED30[3];
835  __IO uint32_t MACPPSTTSR;
836  __IO uint32_t MACPPSTTNR;
837  __IO uint32_t MACPPSIR;
838  __IO uint32_t MACPPSWR;
839  uint32_t RESERVED31[12];
840  __IO uint32_t MACPOCR;
841  __IO uint32_t MACSPI0R;
842  __IO uint32_t MACSPI1R;
843  __IO uint32_t MACSPI2R;
844  __IO uint32_t MACLMIR;
845  uint32_t RESERVED32[11];
846  __IO uint32_t MTLOMR;
847  uint32_t RESERVED33[7];
848  __IO uint32_t MTLISR;
849  uint32_t RESERVED34[55];
850  __IO uint32_t MTLTQOMR;
851  __IO uint32_t MTLTQUR;
852  __IO uint32_t MTLTQDR;
853  uint32_t RESERVED35[8];
854  __IO uint32_t MTLQICSR;
855  __IO uint32_t MTLRQOMR;
856  __IO uint32_t MTLRQMPOCR;
857  __IO uint32_t MTLRQDR;
858  uint32_t RESERVED36[177];
859  __IO uint32_t DMAMR;
860  __IO uint32_t DMASBMR;
861  __IO uint32_t DMAISR;
862  __IO uint32_t DMADSR;
863  uint32_t RESERVED37[60];
864  __IO uint32_t DMACCR;
865  __IO uint32_t DMACTCR;
866  __IO uint32_t DMACRCR;
867  uint32_t RESERVED38[2];
868  __IO uint32_t DMACTDLAR;
869  uint32_t RESERVED39;
870  __IO uint32_t DMACRDLAR;
871  __IO uint32_t DMACTDTPR;
872  uint32_t RESERVED40;
873  __IO uint32_t DMACRDTPR;
874  __IO uint32_t DMACTDRLR;
875  __IO uint32_t DMACRDRLR;
876  __IO uint32_t DMACIER;
877  __IO uint32_t DMACRIWTR;
878 __IO uint32_t DMACSFCSR;
879  uint32_t RESERVED41;
880  __IO uint32_t DMACCATDR;
881  uint32_t RESERVED42;
882  __IO uint32_t DMACCARDR;
883  uint32_t RESERVED43;
884  __IO uint32_t DMACCATBR;
885  uint32_t RESERVED44;
886  __IO uint32_t DMACCARBR;
887  __IO uint32_t DMACSR;
888 uint32_t RESERVED45[2];
889 __IO uint32_t DMACMFCR;
890 }ETH_TypeDef;
895 typedef struct
896 {
897 __IO uint32_t RTSR1;
898 __IO uint32_t FTSR1;
899 __IO uint32_t SWIER1;
900 __IO uint32_t D3PMR1;
901 __IO uint32_t D3PCR1L;
902 __IO uint32_t D3PCR1H;
903 uint32_t RESERVED1[2];
904 __IO uint32_t RTSR2;
905 __IO uint32_t FTSR2;
906 __IO uint32_t SWIER2;
907 __IO uint32_t D3PMR2;
908 __IO uint32_t D3PCR2L;
909 __IO uint32_t D3PCR2H;
910 uint32_t RESERVED2[2];
911 __IO uint32_t RTSR3;
912 __IO uint32_t FTSR3;
913 __IO uint32_t SWIER3;
914 __IO uint32_t D3PMR3;
915 __IO uint32_t D3PCR3L;
916 __IO uint32_t D3PCR3H;
917 uint32_t RESERVED3[10];
918 __IO uint32_t IMR1;
919 __IO uint32_t EMR1;
920 __IO uint32_t PR1;
921 uint32_t RESERVED4;
922 __IO uint32_t IMR2;
923 __IO uint32_t EMR2;
924 __IO uint32_t PR2;
925 uint32_t RESERVED5;
926 __IO uint32_t IMR3;
927 __IO uint32_t EMR3;
928 __IO uint32_t PR3;
929 }EXTI_TypeDef;
930 
940 typedef struct
941 {
942 __IO uint32_t IMR1;
943 __IO uint32_t EMR1;
944 __IO uint32_t PR1;
945 uint32_t RESERVED1;
946 __IO uint32_t IMR2;
947 __IO uint32_t EMR2;
948 __IO uint32_t PR2;
949 uint32_t RESERVED2;
950 __IO uint32_t IMR3;
951 __IO uint32_t EMR3;
952 __IO uint32_t PR3;
953 }EXTI_Core_TypeDef;
954 
955 
960 typedef struct
961 {
962  __IO uint32_t ACR;
963  __IO uint32_t KEYR1;
964  __IO uint32_t OPTKEYR;
965  __IO uint32_t CR1;
966  __IO uint32_t SR1;
967  __IO uint32_t CCR1;
968  __IO uint32_t OPTCR;
969  __IO uint32_t OPTSR_CUR;
970  __IO uint32_t OPTSR_PRG;
971  __IO uint32_t OPTCCR;
972  __IO uint32_t PRAR_CUR1;
973  __IO uint32_t PRAR_PRG1;
974  __IO uint32_t SCAR_CUR1;
975  __IO uint32_t SCAR_PRG1;
976  __IO uint32_t WPSN_CUR1;
977  __IO uint32_t WPSN_PRG1;
978  __IO uint32_t BOOT_CUR;
979  __IO uint32_t BOOT_PRG;
980  uint32_t RESERVED0[2];
981  __IO uint32_t CRCCR1;
982  __IO uint32_t CRCSADD1;
983  __IO uint32_t CRCEADD1;
984  __IO uint32_t CRCDATA;
985  __IO uint32_t ECC_FA1;
986  uint32_t RESERVED[3];
987  __IO uint32_t OPTSR2_CUR;
988  __IO uint32_t OPTSR2_PRG;
989 } FLASH_TypeDef;
990 
994 typedef struct
995 {
996  __IO uint32_t X1BUFCFG;
997  __IO uint32_t X2BUFCFG;
998  __IO uint32_t YBUFCFG;
999  __IO uint32_t PARAM;
1000  __IO uint32_t CR;
1001  __IO uint32_t SR;
1002  __IO uint32_t WDATA;
1003  __IO uint32_t RDATA;
1004 } FMAC_TypeDef;
1005 
1010 typedef struct
1011 {
1012  __IO uint32_t BTCR[8];
1013 } FMC_Bank1_TypeDef;
1014 
1019 typedef struct
1020 {
1021  __IO uint32_t BWTR[7];
1022 } FMC_Bank1E_TypeDef;
1023 
1028 typedef struct
1029 {
1030  __IO uint32_t PCR2;
1031  __IO uint32_t SR2;
1032  __IO uint32_t PMEM2;
1033  __IO uint32_t PATT2;
1034  uint32_t RESERVED0;
1035  __IO uint32_t ECCR2;
1036 } FMC_Bank2_TypeDef;
1037 
1042 typedef struct
1043 {
1044  __IO uint32_t PCR;
1045  __IO uint32_t SR;
1046  __IO uint32_t PMEM;
1047  __IO uint32_t PATT;
1048  uint32_t RESERVED;
1049  __IO uint32_t ECCR;
1050 } FMC_Bank3_TypeDef;
1051 
1057 typedef struct
1058 {
1059  __IO uint32_t SDCR[2];
1060  __IO uint32_t SDTR[2];
1061  __IO uint32_t SDCMR;
1062  __IO uint32_t SDRTR;
1063  __IO uint32_t SDSR;
1064 } FMC_Bank5_6_TypeDef;
1065 
1070 typedef struct
1071 {
1072  __IO uint32_t MODER;
1073  __IO uint32_t OTYPER;
1074  __IO uint32_t OSPEEDR;
1075  __IO uint32_t PUPDR;
1076  __IO uint32_t IDR;
1077  __IO uint32_t ODR;
1078  __IO uint32_t BSRR;
1079  __IO uint32_t LCKR;
1080  __IO uint32_t AFR[2];
1081 } GPIO_TypeDef;
1082 
1087 typedef struct
1088 {
1089  __IO uint32_t CSR;
1090  __IO uint32_t OTR;
1091  __IO uint32_t HSOTR;
1092 } OPAMP_TypeDef;
1093 
1098 typedef struct
1099 {
1100  uint32_t RESERVED1;
1101  __IO uint32_t PMCR;
1102  __IO uint32_t EXTICR[4];
1103  __IO uint32_t CFGR;
1104  uint32_t RESERVED2;
1105  __IO uint32_t CCCSR;
1106  __IO uint32_t CCVR;
1107  __IO uint32_t CCCR;
1108  uint32_t RESERVED3;
1109  __IO uint32_t ADC2ALT;
1110  uint32_t RESERVED4[60];
1111  __IO uint32_t PKGR;
1112  uint32_t RESERVED5[118];
1113  __IO uint32_t UR0;
1114  __IO uint32_t UR1;
1115  __IO uint32_t UR2;
1116  __IO uint32_t UR3;
1117  __IO uint32_t UR4;
1118  __IO uint32_t UR5;
1119  __IO uint32_t UR6;
1120  __IO uint32_t UR7;
1121  uint32_t RESERVED6[3];
1122  __IO uint32_t UR11;
1123  __IO uint32_t UR12;
1124  __IO uint32_t UR13;
1125  __IO uint32_t UR14;
1126  __IO uint32_t UR15;
1127  __IO uint32_t UR16;
1128  __IO uint32_t UR17;
1129  __IO uint32_t UR18;
1131 } SYSCFG_TypeDef;
1132 
1137 typedef struct
1138 {
1139  __IO uint32_t CR1;
1140  __IO uint32_t CR2;
1141  __IO uint32_t OAR1;
1142  __IO uint32_t OAR2;
1143  __IO uint32_t TIMINGR;
1144  __IO uint32_t TIMEOUTR;
1145  __IO uint32_t ISR;
1146  __IO uint32_t ICR;
1147  __IO uint32_t PECR;
1148  __IO uint32_t RXDR;
1149  __IO uint32_t TXDR;
1150 } I2C_TypeDef;
1151 
1156 typedef struct
1157 {
1158  __IO uint32_t KR;
1159  __IO uint32_t PR;
1160  __IO uint32_t RLR;
1161  __IO uint32_t SR;
1162  __IO uint32_t WINR;
1163 } IWDG_TypeDef;
1164 
1165 
1170 typedef struct
1171 {
1172  uint32_t RESERVED0[2];
1173  __IO uint32_t SSCR;
1174  __IO uint32_t BPCR;
1175  __IO uint32_t AWCR;
1176  __IO uint32_t TWCR;
1177  __IO uint32_t GCR;
1178  uint32_t RESERVED1[2];
1179  __IO uint32_t SRCR;
1180  uint32_t RESERVED2[1];
1181  __IO uint32_t BCCR;
1182  uint32_t RESERVED3[1];
1183  __IO uint32_t IER;
1184  __IO uint32_t ISR;
1185  __IO uint32_t ICR;
1186  __IO uint32_t LIPCR;
1187  __IO uint32_t CPSR;
1188  __IO uint32_t CDSR;
1189 } LTDC_TypeDef;
1190 
1195 typedef struct
1196 {
1197  __IO uint32_t CR;
1198  __IO uint32_t WHPCR;
1199  __IO uint32_t WVPCR;
1200  __IO uint32_t CKCR;
1201  __IO uint32_t PFCR;
1202  __IO uint32_t CACR;
1203  __IO uint32_t DCCR;
1204  __IO uint32_t BFCR;
1205  uint32_t RESERVED0[2];
1206  __IO uint32_t CFBAR;
1207  __IO uint32_t CFBLR;
1208  __IO uint32_t CFBLNR;
1209  uint32_t RESERVED1[3];
1210  __IO uint32_t CLUTWR;
1212 } LTDC_Layer_TypeDef;
1213 
1218 typedef struct
1219 {
1220  __IO uint32_t CR1;
1221  __IO uint32_t CSR1;
1222  __IO uint32_t CR2;
1223  __IO uint32_t CR3;
1224  __IO uint32_t CPUCR;
1225  uint32_t RESERVED0;
1226  __IO uint32_t D3CR;
1227  uint32_t RESERVED1;
1228  __IO uint32_t WKUPCR;
1229  __IO uint32_t WKUPFR;
1230  __IO uint32_t WKUPEPR;
1231 } PWR_TypeDef;
1232 
1237 typedef struct
1238 {
1239  __IO uint32_t CR;
1240  __IO uint32_t HSICFGR;
1241  __IO uint32_t CRRCR;
1242  __IO uint32_t CSICFGR;
1243  __IO uint32_t CFGR;
1244  uint32_t RESERVED1;
1245  __IO uint32_t D1CFGR;
1246  __IO uint32_t D2CFGR;
1247  __IO uint32_t D3CFGR;
1248  uint32_t RESERVED2;
1249  __IO uint32_t PLLCKSELR;
1250  __IO uint32_t PLLCFGR;
1251  __IO uint32_t PLL1DIVR;
1252  __IO uint32_t PLL1FRACR;
1253  __IO uint32_t PLL2DIVR;
1254  __IO uint32_t PLL2FRACR;
1255  __IO uint32_t PLL3DIVR;
1256  __IO uint32_t PLL3FRACR;
1257  uint32_t RESERVED3;
1258  __IO uint32_t D1CCIPR;
1259  __IO uint32_t D2CCIP1R;
1260  __IO uint32_t D2CCIP2R;
1261  __IO uint32_t D3CCIPR;
1262  uint32_t RESERVED4;
1263  __IO uint32_t CIER;
1264  __IO uint32_t CIFR;
1265  __IO uint32_t CICR;
1266  uint32_t RESERVED5;
1267  __IO uint32_t BDCR;
1268  __IO uint32_t CSR;
1269  uint32_t RESERVED6;
1270  __IO uint32_t AHB3RSTR;
1271  __IO uint32_t AHB1RSTR;
1272  __IO uint32_t AHB2RSTR;
1273  __IO uint32_t AHB4RSTR;
1274  __IO uint32_t APB3RSTR;
1275  __IO uint32_t APB1LRSTR;
1276  __IO uint32_t APB1HRSTR;
1277  __IO uint32_t APB2RSTR;
1278  __IO uint32_t APB4RSTR;
1279  __IO uint32_t GCR;
1280  uint32_t RESERVED8;
1281  __IO uint32_t D3AMR;
1282  uint32_t RESERVED11[9];
1283  __IO uint32_t RSR;
1284  __IO uint32_t AHB3ENR;
1285  __IO uint32_t AHB1ENR;
1286  __IO uint32_t AHB2ENR;
1287  __IO uint32_t AHB4ENR;
1288  __IO uint32_t APB3ENR;
1289  __IO uint32_t APB1LENR;
1290  __IO uint32_t APB1HENR;
1291  __IO uint32_t APB2ENR;
1292  __IO uint32_t APB4ENR;
1293  uint32_t RESERVED12;
1294  __IO uint32_t AHB3LPENR;
1295  __IO uint32_t AHB1LPENR;
1296  __IO uint32_t AHB2LPENR;
1297  __IO uint32_t AHB4LPENR;
1298  __IO uint32_t APB3LPENR;
1299  __IO uint32_t APB1LLPENR;
1300  __IO uint32_t APB1HLPENR;
1301  __IO uint32_t APB2LPENR;
1302  __IO uint32_t APB4LPENR;
1303  uint32_t RESERVED13[4];
1305 } RCC_TypeDef;
1306 
1307 
1311 typedef struct
1312 {
1313  __IO uint32_t TR;
1314  __IO uint32_t DR;
1315  __IO uint32_t CR;
1316  __IO uint32_t ISR;
1317  __IO uint32_t PRER;
1318  __IO uint32_t WUTR;
1319  uint32_t RESERVED;
1320  __IO uint32_t ALRMAR;
1321  __IO uint32_t ALRMBR;
1322  __IO uint32_t WPR;
1323  __IO uint32_t SSR;
1324  __IO uint32_t SHIFTR;
1325  __IO uint32_t TSTR;
1326  __IO uint32_t TSDR;
1327  __IO uint32_t TSSSR;
1328  __IO uint32_t CALR;
1329  __IO uint32_t TAMPCR;
1330  __IO uint32_t ALRMASSR;
1331  __IO uint32_t ALRMBSSR;
1332  __IO uint32_t OR;
1333  __IO uint32_t BKP0R;
1334  __IO uint32_t BKP1R;
1335  __IO uint32_t BKP2R;
1336  __IO uint32_t BKP3R;
1337  __IO uint32_t BKP4R;
1338  __IO uint32_t BKP5R;
1339  __IO uint32_t BKP6R;
1340  __IO uint32_t BKP7R;
1341  __IO uint32_t BKP8R;
1342  __IO uint32_t BKP9R;
1343  __IO uint32_t BKP10R;
1344  __IO uint32_t BKP11R;
1345  __IO uint32_t BKP12R;
1346  __IO uint32_t BKP13R;
1347  __IO uint32_t BKP14R;
1348  __IO uint32_t BKP15R;
1349  __IO uint32_t BKP16R;
1350  __IO uint32_t BKP17R;
1351  __IO uint32_t BKP18R;
1352  __IO uint32_t BKP19R;
1353  __IO uint32_t BKP20R;
1354  __IO uint32_t BKP21R;
1355  __IO uint32_t BKP22R;
1356  __IO uint32_t BKP23R;
1357  __IO uint32_t BKP24R;
1358  __IO uint32_t BKP25R;
1359  __IO uint32_t BKP26R;
1360  __IO uint32_t BKP27R;
1361  __IO uint32_t BKP28R;
1362  __IO uint32_t BKP29R;
1363  __IO uint32_t BKP30R;
1364  __IO uint32_t BKP31R;
1365 } RTC_TypeDef;
1366 
1371 typedef struct
1372 {
1373  __IO uint32_t GCR;
1374  uint32_t RESERVED0[16];
1375  __IO uint32_t PDMCR;
1376  __IO uint32_t PDMDLY;
1377 } SAI_TypeDef;
1378 
1379 typedef struct
1380 {
1381  __IO uint32_t CR1;
1382  __IO uint32_t CR2;
1383  __IO uint32_t FRCR;
1384  __IO uint32_t SLOTR;
1385  __IO uint32_t IMR;
1386  __IO uint32_t SR;
1387  __IO uint32_t CLRFR;
1388  __IO uint32_t DR;
1389 } SAI_Block_TypeDef;
1390 
1395 typedef struct
1396 {
1397  __IO uint32_t CR;
1398  __IO uint32_t IMR;
1399  __IO uint32_t SR;
1400  __IO uint32_t IFCR;
1401  __IO uint32_t DR;
1402  __IO uint32_t CSR;
1403  __IO uint32_t DIR;
1404  uint32_t RESERVED2;
1405 } SPDIFRX_TypeDef;
1406 
1407 
1412 typedef struct
1413 {
1414  __IO uint32_t POWER;
1415  __IO uint32_t CLKCR;
1416  __IO uint32_t ARG;
1417  __IO uint32_t CMD;
1418  __I uint32_t RESPCMD;
1419  __I uint32_t RESP1;
1420  __I uint32_t RESP2;
1421  __I uint32_t RESP3;
1422  __I uint32_t RESP4;
1423  __IO uint32_t DTIMER;
1424  __IO uint32_t DLEN;
1425  __IO uint32_t DCTRL;
1426  __I uint32_t DCOUNT;
1427  __I uint32_t STA;
1428  __IO uint32_t ICR;
1429  __IO uint32_t MASK;
1430  __IO uint32_t ACKTIME;
1431  uint32_t RESERVED0[3];
1432  __IO uint32_t IDMACTRL;
1433  __IO uint32_t IDMABSIZE;
1434  __IO uint32_t IDMABASE0;
1435  __IO uint32_t IDMABASE1;
1436  uint32_t RESERVED1[8];
1437  __IO uint32_t FIFO;
1438  uint32_t RESERVED2[222];
1439  __IO uint32_t IPVR;
1440 } SDMMC_TypeDef;
1441 
1442 
1447 typedef struct
1448 {
1449  __IO uint32_t CR;
1450  __IO uint32_t CFGR;
1451 } DLYB_TypeDef;
1452 
1457 typedef struct
1458 {
1459  __IO uint32_t R[32];
1460  __IO uint32_t RLR[32];
1461  __IO uint32_t C1IER;
1462  __IO uint32_t C1ICR;
1463  __IO uint32_t C1ISR;
1464  __IO uint32_t C1MISR;
1465  uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1466  __IO uint32_t CR;
1467  __IO uint32_t KEYR;
1469 } HSEM_TypeDef;
1470 
1471 typedef struct
1472 {
1473  __IO uint32_t IER;
1474  __IO uint32_t ICR;
1475  __IO uint32_t ISR;
1476  __IO uint32_t MISR;
1477 } HSEM_Common_TypeDef;
1478 
1483 typedef struct
1484 {
1485  __IO uint32_t CR1;
1486  __IO uint32_t CR2;
1487  __IO uint32_t CFG1;
1488  __IO uint32_t CFG2;
1489  __IO uint32_t IER;
1490  __IO uint32_t SR;
1491  __IO uint32_t IFCR;
1492  uint32_t RESERVED0;
1493  __IO uint32_t TXDR;
1494  uint32_t RESERVED1[3];
1495  __IO uint32_t RXDR;
1496  uint32_t RESERVED2[3];
1497  __IO uint32_t CRCPOLY;
1498  __IO uint32_t TXCRC;
1499  __IO uint32_t RXCRC;
1500  __IO uint32_t UDRDR;
1501  __IO uint32_t I2SCFGR;
1503 } SPI_TypeDef;
1504 
1508 typedef struct
1509 {
1510  __IO uint32_t CFGR1;
1511  uint32_t RESERVED0;
1512  __IO uint32_t T0VALR1;
1513  uint32_t RESERVED1;
1514  __IO uint32_t RAMPVALR;
1515  __IO uint32_t ITR1;
1516  uint32_t RESERVED2;
1517  __IO uint32_t DR;
1518  __IO uint32_t SR;
1519  __IO uint32_t ITENR;
1520  __IO uint32_t ICIFR;
1521  __IO uint32_t OR;
1522 }
1523 DTS_TypeDef;
1524 
1529 typedef struct
1530 {
1531  __IO uint32_t CR1;
1532  __IO uint32_t CR2;
1533  __IO uint32_t SMCR;
1534  __IO uint32_t DIER;
1535  __IO uint32_t SR;
1536  __IO uint32_t EGR;
1537  __IO uint32_t CCMR1;
1538  __IO uint32_t CCMR2;
1539  __IO uint32_t CCER;
1540  __IO uint32_t CNT;
1541  __IO uint32_t PSC;
1542  __IO uint32_t ARR;
1543  __IO uint32_t RCR;
1544  __IO uint32_t CCR1;
1545  __IO uint32_t CCR2;
1546  __IO uint32_t CCR3;
1547  __IO uint32_t CCR4;
1548  __IO uint32_t BDTR;
1549  __IO uint32_t DCR;
1550  __IO uint32_t DMAR;
1551  uint32_t RESERVED1;
1552  __IO uint32_t CCMR3;
1553  __IO uint32_t CCR5;
1554  __IO uint32_t CCR6;
1555  __IO uint32_t AF1;
1556  __IO uint32_t AF2;
1557  __IO uint32_t TISEL;
1558 } TIM_TypeDef;
1559 
1563 typedef struct
1564 {
1565  __IO uint32_t ISR;
1566  __IO uint32_t ICR;
1567  __IO uint32_t IER;
1568  __IO uint32_t CFGR;
1569  __IO uint32_t CR;
1570  __IO uint32_t CMP;
1571  __IO uint32_t ARR;
1572  __IO uint32_t CNT;
1573  uint32_t RESERVED1;
1574  __IO uint32_t CFGR2;
1575 } LPTIM_TypeDef;
1576 
1580 typedef struct
1581 {
1582  __IO uint32_t SR;
1583  __IO uint32_t ICFR;
1584  __IO uint32_t OR;
1585 } COMPOPT_TypeDef;
1586 
1587 typedef struct
1588 {
1589  __IO uint32_t CFGR;
1590 } COMP_TypeDef;
1591 
1592 typedef struct
1593 {
1594  __IO uint32_t CFGR;
1595 } COMP_Common_TypeDef;
1600 typedef struct
1601 {
1602  __IO uint32_t CR1;
1603  __IO uint32_t CR2;
1604  __IO uint32_t CR3;
1605  __IO uint32_t BRR;
1606  __IO uint32_t GTPR;
1607  __IO uint32_t RTOR;
1608  __IO uint32_t RQR;
1609  __IO uint32_t ISR;
1610  __IO uint32_t ICR;
1611  __IO uint32_t RDR;
1612  __IO uint32_t TDR;
1613  __IO uint32_t PRESC;
1614 } USART_TypeDef;
1615 
1619 typedef struct
1620 {
1621  __IO uint32_t CR;
1622  __IO uint32_t BRR;
1623  uint32_t RESERVED1;
1624  __IO uint32_t ISR;
1625  __IO uint32_t ICR;
1626  __IO uint32_t IER;
1627  __IO uint32_t RFL;
1628  __IO uint32_t TDR;
1629  __IO uint32_t RDR;
1630  __IO uint32_t OR;
1631 } SWPMI_TypeDef;
1632 
1637 typedef struct
1638 {
1639  __IO uint32_t CR;
1640  __IO uint32_t CFR;
1641  __IO uint32_t SR;
1642 } WWDG_TypeDef;
1643 
1644 
1648 typedef struct
1649 {
1650  __IO uint32_t CR;
1651  __IO uint32_t SR;
1652  __IO uint32_t FAR;
1653  __IO uint32_t FDRL;
1654  __IO uint32_t FDRH;
1655  __IO uint32_t FECR;
1656 } RAMECC_MonitorTypeDef;
1657 
1658 typedef struct
1659 {
1660  __IO uint32_t IER;
1661 } RAMECC_TypeDef;
1671 typedef struct
1672 {
1673  __IO uint32_t CR;
1674  __IO uint32_t SR;
1675  __IO uint32_t DIN;
1676  __IO uint32_t DOUT;
1677  __IO uint32_t DMACR;
1678  __IO uint32_t IMSCR;
1679  __IO uint32_t RISR;
1680  __IO uint32_t MISR;
1681  __IO uint32_t K0LR;
1682  __IO uint32_t K0RR;
1683  __IO uint32_t K1LR;
1684  __IO uint32_t K1RR;
1685  __IO uint32_t K2LR;
1686  __IO uint32_t K2RR;
1687  __IO uint32_t K3LR;
1688  __IO uint32_t K3RR;
1689  __IO uint32_t IV0LR;
1690  __IO uint32_t IV0RR;
1691  __IO uint32_t IV1LR;
1692  __IO uint32_t IV1RR;
1693  __IO uint32_t CSGCMCCM0R;
1694  __IO uint32_t CSGCMCCM1R;
1695  __IO uint32_t CSGCMCCM2R;
1696  __IO uint32_t CSGCMCCM3R;
1697  __IO uint32_t CSGCMCCM4R;
1698  __IO uint32_t CSGCMCCM5R;
1699  __IO uint32_t CSGCMCCM6R;
1700  __IO uint32_t CSGCMCCM7R;
1701  __IO uint32_t CSGCM0R;
1702  __IO uint32_t CSGCM1R;
1703  __IO uint32_t CSGCM2R;
1704  __IO uint32_t CSGCM3R;
1705  __IO uint32_t CSGCM4R;
1706  __IO uint32_t CSGCM5R;
1707  __IO uint32_t CSGCM6R;
1708  __IO uint32_t CSGCM7R;
1709 } CRYP_TypeDef;
1710 
1715 typedef struct
1716 {
1717  __IO uint32_t CR;
1718  __IO uint32_t DIN;
1719  __IO uint32_t STR;
1720  __IO uint32_t HR[5];
1721  __IO uint32_t IMR;
1722  __IO uint32_t SR;
1723  uint32_t RESERVED[52];
1724  __IO uint32_t CSR[54];
1725 } HASH_TypeDef;
1726 
1731 typedef struct
1732 {
1733  __IO uint32_t HR[8];
1734 } HASH_DIGEST_TypeDef;
1735 
1736 
1741 typedef struct
1742 {
1743  __IO uint32_t CR;
1744  __IO uint32_t SR;
1745  __IO uint32_t DR;
1746  uint32_t RESERVED;
1747  __IO uint32_t HTCR;
1748 } RNG_TypeDef;
1749 
1754 typedef struct
1755 {
1756  __IO uint32_t CR;
1757  __IO uint32_t WRFR;
1758  __IO uint32_t CWRFR;
1759  __IO uint32_t RDFR;
1760  __IO uint32_t CRDFR;
1761  __IO uint32_t SR;
1762  __IO uint32_t CLRFR;
1763  uint32_t RESERVED[57];
1764  __IO uint32_t DINR0;
1765  __IO uint32_t DINR1;
1766  __IO uint32_t DINR2;
1767  __IO uint32_t DINR3;
1768  __IO uint32_t DINR4;
1769  __IO uint32_t DINR5;
1770  __IO uint32_t DINR6;
1771  __IO uint32_t DINR7;
1772  __IO uint32_t DINR8;
1773  __IO uint32_t DINR9;
1774  __IO uint32_t DINR10;
1775  __IO uint32_t DINR11;
1776  __IO uint32_t DINR12;
1777  __IO uint32_t DINR13;
1778  __IO uint32_t DINR14;
1779  __IO uint32_t DINR15;
1780  __IO uint32_t DINR16;
1781  __IO uint32_t DINR17;
1782  __IO uint32_t DINR18;
1783  __IO uint32_t DINR19;
1784  __IO uint32_t DINR20;
1785  __IO uint32_t DINR21;
1786  __IO uint32_t DINR22;
1787  __IO uint32_t DINR23;
1788  __IO uint32_t DINR24;
1789  __IO uint32_t DINR25;
1790  __IO uint32_t DINR26;
1791  __IO uint32_t DINR27;
1792  __IO uint32_t DINR28;
1793  __IO uint32_t DINR29;
1794  __IO uint32_t DINR30;
1795  __IO uint32_t DINR31;
1796  __IO uint32_t DOUTR0;
1797  __IO uint32_t DOUTR1;
1798  __IO uint32_t DOUTR2;
1799  __IO uint32_t DOUTR3;
1800  __IO uint32_t DOUTR4;
1801  __IO uint32_t DOUTR5;
1802  __IO uint32_t DOUTR6;
1803  __IO uint32_t DOUTR7;
1804  __IO uint32_t DOUTR8;
1805  __IO uint32_t DOUTR9;
1806  __IO uint32_t DOUTR10;
1807  __IO uint32_t DOUTR11;
1808  __IO uint32_t DOUTR12;
1809  __IO uint32_t DOUTR13;
1810  __IO uint32_t DOUTR14;
1811  __IO uint32_t DOUTR15;
1812  __IO uint32_t DOUTR16;
1813  __IO uint32_t DOUTR17;
1814  __IO uint32_t DOUTR18;
1815  __IO uint32_t DOUTR19;
1816  __IO uint32_t DOUTR20;
1817  __IO uint32_t DOUTR21;
1818  __IO uint32_t DOUTR22;
1819  __IO uint32_t DOUTR23;
1820  __IO uint32_t DOUTR24;
1821  __IO uint32_t DOUTR25;
1822  __IO uint32_t DOUTR26;
1823  __IO uint32_t DOUTR27;
1824  __IO uint32_t DOUTR28;
1825  __IO uint32_t DOUTR29;
1826  __IO uint32_t DOUTR30;
1827  __IO uint32_t DOUTR31;
1828 } MDIOS_TypeDef;
1829 
1830 
1834 typedef struct
1835 {
1836  __IO uint32_t GOTGCTL;
1837  __IO uint32_t GOTGINT;
1838  __IO uint32_t GAHBCFG;
1839  __IO uint32_t GUSBCFG;
1840  __IO uint32_t GRSTCTL;
1841  __IO uint32_t GINTSTS;
1842  __IO uint32_t GINTMSK;
1843  __IO uint32_t GRXSTSR;
1844  __IO uint32_t GRXSTSP;
1845  __IO uint32_t GRXFSIZ;
1846  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1847  __IO uint32_t HNPTXSTS;
1848  uint32_t Reserved30[2];
1849  __IO uint32_t GCCFG;
1850  __IO uint32_t CID;
1851  __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1852  __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1853  __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1854  __IO uint32_t GHWCFG3;
1855  uint32_t Reserved6;
1856  __IO uint32_t GLPMCFG;
1857  __IO uint32_t GPWRDN;
1858  __IO uint32_t GDFIFOCFG;
1859  __IO uint32_t GADPCTL;
1860  uint32_t Reserved43[39];
1861  __IO uint32_t HPTXFSIZ;
1862  __IO uint32_t DIEPTXF[0x0F];
1863 } USB_OTG_GlobalTypeDef;
1864 
1865 
1869 typedef struct
1870 {
1871  __IO uint32_t DCFG;
1872  __IO uint32_t DCTL;
1873  __IO uint32_t DSTS;
1874  uint32_t Reserved0C;
1875  __IO uint32_t DIEPMSK;
1876  __IO uint32_t DOEPMSK;
1877  __IO uint32_t DAINT;
1878  __IO uint32_t DAINTMSK;
1879  uint32_t Reserved20;
1880  uint32_t Reserved9;
1881  __IO uint32_t DVBUSDIS;
1882  __IO uint32_t DVBUSPULSE;
1883  __IO uint32_t DTHRCTL;
1884  __IO uint32_t DIEPEMPMSK;
1885  __IO uint32_t DEACHINT;
1886  __IO uint32_t DEACHMSK;
1887  uint32_t Reserved40;
1888  __IO uint32_t DINEP1MSK;
1889  uint32_t Reserved44[15];
1890  __IO uint32_t DOUTEP1MSK;
1891 } USB_OTG_DeviceTypeDef;
1892 
1893 
1897 typedef struct
1898 {
1899  __IO uint32_t DIEPCTL;
1900  uint32_t Reserved04;
1901  __IO uint32_t DIEPINT;
1902  uint32_t Reserved0C;
1903  __IO uint32_t DIEPTSIZ;
1904  __IO uint32_t DIEPDMA;
1905  __IO uint32_t DTXFSTS;
1906  uint32_t Reserved18;
1907 } USB_OTG_INEndpointTypeDef;
1908 
1909 
1913 typedef struct
1914 {
1915  __IO uint32_t DOEPCTL;
1916  uint32_t Reserved04;
1917  __IO uint32_t DOEPINT;
1918  uint32_t Reserved0C;
1919  __IO uint32_t DOEPTSIZ;
1920  __IO uint32_t DOEPDMA;
1921  uint32_t Reserved18[2];
1922 } USB_OTG_OUTEndpointTypeDef;
1923 
1924 
1928 typedef struct
1929 {
1930  __IO uint32_t HCFG;
1931  __IO uint32_t HFIR;
1932  __IO uint32_t HFNUM;
1933  uint32_t Reserved40C;
1934  __IO uint32_t HPTXSTS;
1935  __IO uint32_t HAINT;
1936  __IO uint32_t HAINTMSK;
1937 } USB_OTG_HostTypeDef;
1938 
1942 typedef struct
1943 {
1944  __IO uint32_t HCCHAR;
1945  __IO uint32_t HCSPLT;
1946  __IO uint32_t HCINT;
1947  __IO uint32_t HCINTMSK;
1948  __IO uint32_t HCTSIZ;
1949  __IO uint32_t HCDMA;
1950  uint32_t Reserved[2];
1951 } USB_OTG_HostChannelTypeDef;
1960 typedef struct
1961 {
1962  __IO uint32_t CR;
1963  uint32_t RESERVED;
1964  __IO uint32_t DCR1;
1965  __IO uint32_t DCR2;
1966  __IO uint32_t DCR3;
1967  __IO uint32_t DCR4;
1968  uint32_t RESERVED1[2];
1969  __IO uint32_t SR;
1970  __IO uint32_t FCR;
1971  uint32_t RESERVED2[6];
1972  __IO uint32_t DLR;
1973  uint32_t RESERVED3;
1974  __IO uint32_t AR;
1975  uint32_t RESERVED4;
1976  __IO uint32_t DR;
1977  uint32_t RESERVED5[11];
1978  __IO uint32_t PSMKR;
1979  uint32_t RESERVED6;
1980  __IO uint32_t PSMAR;
1981  uint32_t RESERVED7;
1982  __IO uint32_t PIR;
1983  uint32_t RESERVED8[27];
1984  __IO uint32_t CCR;
1985  uint32_t RESERVED9;
1986  __IO uint32_t TCR;
1987  uint32_t RESERVED10;
1988  __IO uint32_t IR;
1989  uint32_t RESERVED11[3];
1990  __IO uint32_t ABR;
1991  uint32_t RESERVED12[3];
1992  __IO uint32_t LPTR;
1993  uint32_t RESERVED13[3];
1994  __IO uint32_t WPCCR;
1995  uint32_t RESERVED14;
1996  __IO uint32_t WPTCR;
1997  uint32_t RESERVED15;
1998  __IO uint32_t WPIR;
1999  uint32_t RESERVED16[3];
2000  __IO uint32_t WPABR;
2001  uint32_t RESERVED17[7];
2002  __IO uint32_t WCCR;
2003  uint32_t RESERVED18;
2004  __IO uint32_t WTCR;
2005  uint32_t RESERVED19;
2006  __IO uint32_t WIR;
2007  uint32_t RESERVED20[3];
2008  __IO uint32_t WABR;
2009  uint32_t RESERVED21[23];
2010  __IO uint32_t HLCR;
2011  uint32_t RESERVED22[122];
2012  __IO uint32_t HWCFGR;
2013  __IO uint32_t VER;
2014  __IO uint32_t ID;
2015  __IO uint32_t MID;
2016 } OCTOSPI_TypeDef;
2017 
2025 typedef struct
2026 {
2027  __IO uint32_t CR;
2028  __IO uint32_t PCR[3];
2029 } OCTOSPIM_TypeDef;
2030 
2038 typedef struct
2039 {
2040  __IO uint32_t REG_CONFIGR;
2041  __IO uint32_t REG_START_ADDR;
2042  __IO uint32_t REG_END_ADDR;
2043  __IO uint32_t REG_NONCER0;
2044  __IO uint32_t REG_NONCER1;
2045  __IO uint32_t REG_KEYR0;
2046  __IO uint32_t REG_KEYR1;
2047  __IO uint32_t REG_KEYR2;
2048  __IO uint32_t REG_KEYR3;
2049 } OTFDEC_Region_TypeDef;
2050 
2051 typedef struct
2052 {
2053  __IO uint32_t CR;
2054  uint32_t RESERVED1[191];
2055  __IO uint32_t ISR;
2056  __IO uint32_t ICR;
2057  __IO uint32_t IER;
2058  uint32_t RESERVED2[56];
2059  __IO uint32_t HWCFGR2;
2060  __IO uint32_t HWCFGR1;
2061  __IO uint32_t VERR;
2062  __IO uint32_t IPIDR;
2063  __IO uint32_t SIDR;
2064 } OTFDEC_TypeDef;
2073 typedef struct
2074 {
2075  uint32_t RESERVED0[2036];
2076  __IO uint32_t AXI_PERIPH_ID_4;
2077  uint32_t AXI_PERIPH_ID_5;
2078  uint32_t AXI_PERIPH_ID_6;
2079  uint32_t AXI_PERIPH_ID_7;
2080  __IO uint32_t AXI_PERIPH_ID_0;
2081  __IO uint32_t AXI_PERIPH_ID_1;
2082  __IO uint32_t AXI_PERIPH_ID_2;
2083  __IO uint32_t AXI_PERIPH_ID_3;
2084  __IO uint32_t AXI_COMP_ID_0;
2085  __IO uint32_t AXI_COMP_ID_1;
2086  __IO uint32_t AXI_COMP_ID_2;
2087  __IO uint32_t AXI_COMP_ID_3;
2088  uint32_t RESERVED1[2];
2089  __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;
2090  uint32_t RESERVED2[6];
2091  __IO uint32_t AXI_TARG1_FN_MOD2;
2092  uint32_t RESERVED3;
2093  __IO uint32_t AXI_TARG1_FN_MOD_LB;
2094  uint32_t RESERVED4[54];
2095  __IO uint32_t AXI_TARG1_FN_MOD;
2096  uint32_t RESERVED5[959];
2097  __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;
2098  uint32_t RESERVED6[6];
2099  __IO uint32_t AXI_TARG2_FN_MOD2;
2100  uint32_t RESERVED7;
2101  __IO uint32_t AXI_TARG2_FN_MOD_LB;
2102  uint32_t RESERVED8[54];
2103  __IO uint32_t AXI_TARG2_FN_MOD;
2104  uint32_t RESERVED9[959];
2105  __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;
2106  uint32_t RESERVED10[1023];
2107  __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;
2108  uint32_t RESERVED11[1023];
2109  __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;
2110  uint32_t RESERVED12[1023];
2111  __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;
2112  uint32_t RESERVED13[1023];
2113  __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;
2114  uint32_t RESERVED14[6];
2115  __IO uint32_t AXI_TARG7_FN_MOD2;
2116  uint32_t RESERVED15;
2117  __IO uint32_t AXI_TARG7_FN_MOD_LB;
2118  uint32_t RESERVED16[54];
2119  __IO uint32_t AXI_TARG7_FN_MOD;
2120  uint32_t RESERVED17[959];
2121  __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM;
2122  uint32_t RESERVED117[6];
2123  __IO uint32_t AXI_TARG8_FN_MOD2;
2124  uint32_t RESERVED118[56];
2125  __IO uint32_t AXI_TARG8_FN_MOD;
2126  uint32_t RESERVED119[58310];
2127  __IO uint32_t AXI_INI1_FN_MOD2;
2128  __IO uint32_t AXI_INI1_FN_MOD_AHB;
2129  uint32_t RESERVED18[53];
2130  __IO uint32_t AXI_INI1_READ_QOS;
2131  __IO uint32_t AXI_INI1_WRITE_QOS;
2132  __IO uint32_t AXI_INI1_FN_MOD;
2133  uint32_t RESERVED19[1021];
2134  __IO uint32_t AXI_INI2_READ_QOS;
2135  __IO uint32_t AXI_INI2_WRITE_QOS;
2136  __IO uint32_t AXI_INI2_FN_MOD;
2137  uint32_t RESERVED20[966];
2138  __IO uint32_t AXI_INI3_FN_MOD2;
2139  __IO uint32_t AXI_INI3_FN_MOD_AHB;
2140  uint32_t RESERVED21[53];
2141  __IO uint32_t AXI_INI3_READ_QOS;
2142  __IO uint32_t AXI_INI3_WRITE_QOS;
2143  __IO uint32_t AXI_INI3_FN_MOD;
2144  uint32_t RESERVED22[1021];
2145  __IO uint32_t AXI_INI4_READ_QOS;
2146  __IO uint32_t AXI_INI4_WRITE_QOS;
2147  __IO uint32_t AXI_INI4_FN_MOD;
2148  uint32_t RESERVED23[1021];
2149  __IO uint32_t AXI_INI5_READ_QOS;
2150  __IO uint32_t AXI_INI5_WRITE_QOS;
2151  __IO uint32_t AXI_INI5_FN_MOD;
2152  uint32_t RESERVED24[1021];
2153  __IO uint32_t AXI_INI6_READ_QOS;
2154  __IO uint32_t AXI_INI6_WRITE_QOS;
2155  __IO uint32_t AXI_INI6_FN_MOD;
2157 } GPV_TypeDef;
2158 
2162 #define D1_ITCMRAM_BASE (0x00000000UL)
2163 #define D1_ITCMICP_BASE (0x00100000UL)
2164 #define D1_DTCMRAM_BASE (0x20000000UL)
2165 #define D1_AXIFLASH_BASE (0x08000000UL)
2166 #define D1_AXIICP_BASE (0x1FF00000UL)
2167 #define D1_AXISRAM1_BASE (0x24000000UL)
2168 #define D1_AXISRAM2_BASE (0x24020000UL)
2169 #define D1_AXISRAM_BASE D1_AXISRAM1_BASE
2171 #define D2_AHBSRAM1_BASE (0x30000000UL)
2172 #define D2_AHBSRAM2_BASE (0x30004000UL)
2173 #define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE
2175 #define D3_BKPSRAM_BASE (0x38800000UL)
2176 #define D3_SRAM_BASE (0x38000000UL)
2178 #define PERIPH_BASE (0x40000000UL)
2179 #define OCTOSPI1_BASE (0x90000000UL)
2180 #define OCTOSPI2_BASE (0x70000000UL)
2182 #define FLASH_BANK1_BASE (0x08000000UL)
2183 #define FLASH_END (0x080FFFFFUL)
2186 /* Legacy define */
2187 #define FLASH_BASE FLASH_BANK1_BASE
2188 
2190 #define UID_BASE (0x1FF1E800UL)
2191 #define FLASHSIZE_BASE (0x1FF1E880UL)
2195 #define D2_APB1PERIPH_BASE PERIPH_BASE
2196 #define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2197 #define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2198 #define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2199 
2200 #define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2201 #define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2202 
2203 #define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2204 #define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2205 
2207 #define APB1PERIPH_BASE PERIPH_BASE
2208 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2209 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2210 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2211 
2212 
2215 #define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2216 #define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2217 #define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2218 #define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2219 #define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2220 #define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2221 #define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2222 #define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2223 #define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2224 #define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL)
2225 #define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL)
2226 #define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL)
2227 
2228 #define OTFDEC1_BASE (D1_AHB1PERIPH_BASE + 0xB800UL)
2229 #define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL)
2230 #define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL)
2231 #define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL)
2232 #define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL)
2233 #define OTFDEC2_BASE (D1_AHB1PERIPH_BASE + 0xBC00UL)
2234 #define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL)
2235 #define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL)
2236 #define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL)
2237 #define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL)
2238 
2241 #define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2242 #define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2243 #define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2244 #define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2245 #define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2246 #define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2247 #define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2248 #define ETH_MAC_BASE (ETH_BASE)
2249 
2251 #define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2252 #define USB_OTG_GLOBAL_BASE (0x000UL)
2253 #define USB_OTG_DEVICE_BASE (0x800UL)
2254 #define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2255 #define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2256 #define USB_OTG_EP_REG_SIZE (0x20UL)
2257 #define USB_OTG_HOST_BASE (0x400UL)
2258 #define USB_OTG_HOST_PORT_BASE (0x440UL)
2259 #define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2260 #define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2261 #define USB_OTG_PCGCCTL_BASE (0xE00UL)
2262 #define USB_OTG_FIFO_BASE (0x1000UL)
2263 #define USB_OTG_FIFO_SIZE (0x1000UL)
2264 
2267 #define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2268 #define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL)
2269 #define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL)
2270 #define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL)
2271 #define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL)
2272 #define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2273 #define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2274 #define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2275 #define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2276 #define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL)
2277 #define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL)
2278 
2280 #define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2281 #define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2282 #define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2283 #define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2284 #define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2285 #define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2286 #define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2287 #define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2288 #define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2289 #define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2290 #define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2291 #define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2292 #define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2293 #define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2294 #define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2295 #define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2296 #define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2297 #define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2298 #define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2299 
2301 #define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2302 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2303 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2304 #define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2305 
2307 #define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2308 #define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2309 #define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2310 #define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2311 #define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2312 #define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2313 #define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2314 #define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2315 #define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2316 #define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2317 
2318 
2319 #define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2320 #define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2321 #define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2322 #define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2323 #define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2324 #define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2325 #define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2326 #define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2327 #define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2328 #define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2329 #define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL)
2330 #define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2331 #define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2332 #define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2333 #define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2334 #define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2335 #define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2336 #define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2337 #define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2338 #define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2339 #define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2340 #define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2341 #define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2342 #define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2343 #define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2344 #define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL)
2345 #define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL)
2346 #define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL)
2347 
2350 #define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2351 #define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2352 #define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2353 #define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2354 #define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL)
2355 #define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL)
2356 #define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2357 #define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2358 #define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2359 #define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2360 #define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2361 #define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2362 #define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2363 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2364 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2365 #define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL)
2366 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2367 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2368 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2369 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2370 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2371 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2372 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2373 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2374 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2375 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2376 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2377 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2378 
2379 
2381 #define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2382 #define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2383 #define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2384 #define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2385 #define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2386 #define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2387 #define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2388 #define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2389 #define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2390 #define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2391 #define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2392 #define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2393 #define COMP1_BASE (COMP12_BASE + 0x0CUL)
2394 #define COMP2_BASE (COMP12_BASE + 0x10UL)
2395 #define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2396 #define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2397 #define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2398 
2399 
2400 #define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2401 #define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2402 #define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2403 
2404 #define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL)
2405 
2406 
2407 
2408 #define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2409 #define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2410 #define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2411 #define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2412 #define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2413 #define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2414 #define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2415 #define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2416 
2417 #define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2418 #define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2419 #define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2420 #define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2421 #define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2422 #define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2423 #define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2424 #define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2425 
2426 #define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2427 #define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2428 #define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2429 #define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2430 #define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2431 #define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2432 #define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2433 #define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2434 
2435 #define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2436 #define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2437 
2438 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2439 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2440 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2441 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2442 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2443 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2444 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2445 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2446 
2447 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2448 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2449 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2450 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2451 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2452 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2453 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2454 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2455 
2456 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2457 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2458 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2459 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2460 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2461 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2462 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2463 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2464 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2465 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2466 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2467 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2468 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2469 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2470 #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2471 #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2472 
2473 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2474 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2475 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2476 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2477 #define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2478 #define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2479 #define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2480 #define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2481 
2482 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2483 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2484 
2486 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2487 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2488 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2489 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2490 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2491 
2492 /* Debug MCU registers base address */
2493 #define DBGMCU_BASE (0x5C001000UL)
2494 
2495 #define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2496 #define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2497 #define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2498 #define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2499 #define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2500 #define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2501 #define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2502 #define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2503 #define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2504 #define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2505 #define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2506 #define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2507 #define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2508 #define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2509 #define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2510 #define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2511 
2512 #define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2513 #define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2514 #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2515 #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2516 #define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2517 #define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL)
2518 
2519 #define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2520 #define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2521 #define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2522 
2523 #define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2524 #define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2525 
2526 
2527 
2528 #define GPV_BASE (PERIPH_BASE + 0x11000000UL)
2537 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2538 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2539 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2540 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2541 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2542 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2543 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2544 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2545 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2546 #define RTC ((RTC_TypeDef *) RTC_BASE)
2547 #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2548 
2549 
2550 #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2551 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2552 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2553 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2554 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2555 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2556 #define USART2 ((USART_TypeDef *) USART2_BASE)
2557 #define USART3 ((USART_TypeDef *) USART3_BASE)
2558 #define USART6 ((USART_TypeDef *) USART6_BASE)
2559 #define USART10 ((USART_TypeDef *) USART10_BASE)
2560 #define UART7 ((USART_TypeDef *) UART7_BASE)
2561 #define UART8 ((USART_TypeDef *) UART8_BASE)
2562 #define UART9 ((USART_TypeDef *) UART9_BASE)
2563 #define CRS ((CRS_TypeDef *) CRS_BASE)
2564 #define UART4 ((USART_TypeDef *) UART4_BASE)
2565 #define UART5 ((USART_TypeDef *) UART5_BASE)
2566 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2567 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2568 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2569 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2570 #define I2C5 ((I2C_TypeDef *) I2C5_BASE)
2571 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2572 #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2573 #define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2574 #define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
2575 #define TIM23 ((TIM_TypeDef *) TIM23_BASE)
2576 #define TIM24 ((TIM_TypeDef *) TIM24_BASE)
2577 #define CEC ((CEC_TypeDef *) CEC_BASE)
2578 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2579 #define PWR ((PWR_TypeDef *) PWR_BASE)
2580 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2581 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2582 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2583 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2584 #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2585 #define DTS ((DTS_TypeDef *) DTS_BASE)
2586 #define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2587 #define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2588 
2589 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2590 #define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2591 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2592 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2593 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2594 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2595 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2596 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2597 
2598 
2599 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2600 #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2601 #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2602 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2603 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2604 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2605 #define USART1 ((USART_TypeDef *) USART1_BASE)
2606 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2607 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2608 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2609 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2610 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2611 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2612 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2613 #define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2614 #define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2615 #define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2616 
2617 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2618 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2619 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2620 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2621 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2622 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2623 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2624 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2625 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2626 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2627 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2628 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2629 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2630 #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2631 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2632 #define PSSI ((PSSI_TypeDef *) PSSI_BASE)
2633 #define RCC ((RCC_TypeDef *) RCC_BASE)
2634 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2635 #define CRC ((CRC_TypeDef *) CRC_BASE)
2636 
2637 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2638 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2639 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2640 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2641 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2642 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2643 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2644 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2645 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2646 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2647 
2648 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2649 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2650 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2651 #define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2652 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2653 
2654 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
2655 #define HASH ((HASH_TypeDef *) HASH_BASE)
2656 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2657 #define RNG ((RNG_TypeDef *) RNG_BASE)
2658 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2659 #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2660 #define FMAC ((FMAC_TypeDef *) FMAC_BASE)
2661 #define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
2662 
2663 #define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2664 #define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2665 #define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2666 #define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2667 #define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2668 #define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2669 #define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2670 #define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2671 #define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2672 
2673 #define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2674 #define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2675 #define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2676 #define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2677 #define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2678 #define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2679 #define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)
2680 
2681 #define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2682 #define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2683 #define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2684 #define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2685 
2686 #define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2687 #define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2688 #define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2689 
2690 #define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2691 #define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2692 #define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2693 #define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2694 #define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2695 #define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2696 #define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2697 #define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2698 #define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2699 
2700 
2701 #define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2702 #define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2703 #define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2704 #define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2705 #define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2706 #define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2707 #define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2708 #define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2709 
2710 #define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2711 #define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2712 
2713 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2714 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2715 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2716 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2717 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2718 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2719 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2720 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2721 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2722 
2723 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2724 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2725 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2726 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2727 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2728 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2729 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2730 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2731 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2732 
2733 
2734 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2735 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2736 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2737 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2738 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2739 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2740 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2741 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2742 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2743 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2744 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2745 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2746 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2747 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2748 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2749 #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2750 #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2751 
2752 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2753 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2754 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2755 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2756 #define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2757 #define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2758 #define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2759 #define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2760 
2761 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2762 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2763 
2764 
2765 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2766 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2767 #define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2768 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2769 #define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2770 
2771 #define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
2772 #define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
2773 #define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
2774 #define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
2775 #define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
2776 
2777 #define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)
2778 #define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)
2779 #define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)
2780 #define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)
2781 #define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)
2782 
2783 #define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)
2784 #define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)
2785 #define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)
2786 #define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)
2787 #define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)
2788 
2789 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2790 #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2791 
2792 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2793 
2794 #define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2795 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2796 
2797 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2798 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2799 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2800 
2801 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2802 
2803 #define ETH ((ETH_TypeDef *)ETH_BASE)
2804 #define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2805 #define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2806 #define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2807 #define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2808 #define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2809 #define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2810 #define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2811 #define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2812 #define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2813 #define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2814 #define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2815 #define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2816 #define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2817 #define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2818 #define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2819 #define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2820 #define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2821 
2822 
2823 #define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2824 
2825 /* Legacy defines */
2826 #define USB_OTG_HS USB1_OTG_HS
2827 #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2828 
2829 #define GPV ((GPV_TypeDef *) GPV_BASE)
2830 
2843 /******************************************************************************/
2844 /* Peripheral Registers_Bits_Definition */
2845 /******************************************************************************/
2846 
2847 /******************************************************************************/
2848 /* */
2849 /* Analog to Digital Converter */
2850 /* */
2851 /******************************************************************************/
2852 /******************************* ADC VERSION ********************************/
2853 #define ADC_VER_V5_V90
2854 /******************** Bit definition for ADC_ISR register ********************/
2855 #define ADC_ISR_ADRDY_Pos (0U)
2856 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
2857 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
2858 #define ADC_ISR_EOSMP_Pos (1U)
2859 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
2860 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
2861 #define ADC_ISR_EOC_Pos (2U)
2862 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
2863 #define ADC_ISR_EOC ADC_ISR_EOC_Msk
2864 #define ADC_ISR_EOS_Pos (3U)
2865 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
2866 #define ADC_ISR_EOS ADC_ISR_EOS_Msk
2867 #define ADC_ISR_OVR_Pos (4U)
2868 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
2869 #define ADC_ISR_OVR ADC_ISR_OVR_Msk
2870 #define ADC_ISR_JEOC_Pos (5U)
2871 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
2872 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
2873 #define ADC_ISR_JEOS_Pos (6U)
2874 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
2875 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
2876 #define ADC_ISR_AWD1_Pos (7U)
2877 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
2878 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
2879 #define ADC_ISR_AWD2_Pos (8U)
2880 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
2881 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
2882 #define ADC_ISR_AWD3_Pos (9U)
2883 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
2884 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
2885 #define ADC_ISR_JQOVF_Pos (10U)
2886 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
2887 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
2889 /******************** Bit definition for ADC_IER register ********************/
2890 #define ADC_IER_ADRDYIE_Pos (0U)
2891 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
2892 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
2893 #define ADC_IER_EOSMPIE_Pos (1U)
2894 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
2895 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
2896 #define ADC_IER_EOCIE_Pos (2U)
2897 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
2898 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
2899 #define ADC_IER_EOSIE_Pos (3U)
2900 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
2901 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
2902 #define ADC_IER_OVRIE_Pos (4U)
2903 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
2904 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
2905 #define ADC_IER_JEOCIE_Pos (5U)
2906 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
2907 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
2908 #define ADC_IER_JEOSIE_Pos (6U)
2909 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
2910 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
2911 #define ADC_IER_AWD1IE_Pos (7U)
2912 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
2913 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
2914 #define ADC_IER_AWD2IE_Pos (8U)
2915 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
2916 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
2917 #define ADC_IER_AWD3IE_Pos (9U)
2918 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
2919 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
2920 #define ADC_IER_JQOVFIE_Pos (10U)
2921 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
2922 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
2924 /******************** Bit definition for ADC_CR register ********************/
2925 #define ADC_CR_ADEN_Pos (0U)
2926 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
2927 #define ADC_CR_ADEN ADC_CR_ADEN_Msk
2928 #define ADC_CR_ADDIS_Pos (1U)
2929 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
2930 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
2931 #define ADC_CR_ADSTART_Pos (2U)
2932 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
2933 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
2934 #define ADC_CR_JADSTART_Pos (3U)
2935 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
2936 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
2937 #define ADC_CR_ADSTP_Pos (4U)
2938 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
2939 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
2940 #define ADC_CR_JADSTP_Pos (5U)
2941 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
2942 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
2943 #define ADC_CR_BOOST_Pos (8U)
2944 #define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos)
2945 #define ADC_CR_BOOST ADC_CR_BOOST_Msk
2946 #define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos)
2947 #define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos)
2948 #define ADC_CR_ADCALLIN_Pos (16U)
2949 #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos)
2950 #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk
2951 #define ADC_CR_LINCALRDYW1_Pos (22U)
2952 #define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos)
2953 #define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk
2954 #define ADC_CR_LINCALRDYW2_Pos (23U)
2955 #define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos)
2956 #define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk
2957 #define ADC_CR_LINCALRDYW3_Pos (24U)
2958 #define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos)
2959 #define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk
2960 #define ADC_CR_LINCALRDYW4_Pos (25U)
2961 #define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos)
2962 #define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk
2963 #define ADC_CR_LINCALRDYW5_Pos (26U)
2964 #define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos)
2965 #define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk
2966 #define ADC_CR_LINCALRDYW6_Pos (27U)
2967 #define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos)
2968 #define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk
2969 #define ADC_CR_ADVREGEN_Pos (28U)
2970 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
2971 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
2972 #define ADC_CR_DEEPPWD_Pos (29U)
2973 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
2974 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
2975 #define ADC_CR_ADCALDIF_Pos (30U)
2976 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
2977 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
2978 #define ADC_CR_ADCAL_Pos (31U)
2979 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
2980 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
2982 /******************** Bit definition for ADC_CFGR register ********************/
2983 #define ADC_CFGR_DMNGT_Pos (0U)
2984 #define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos)
2985 #define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk
2986 #define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos)
2987 #define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos)
2989 #define ADC_CFGR_RES_Pos (2U)
2990 #define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos)
2991 #define ADC_CFGR_RES ADC_CFGR_RES_Msk
2992 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
2993 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
2994 #define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos)
2996 #define ADC_CFGR_EXTSEL_Pos (5U)
2997 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)
2998 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
2999 #define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos)
3000 #define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos)
3001 #define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos)
3002 #define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos)
3003 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)
3005 #define ADC_CFGR_EXTEN_Pos (10U)
3006 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
3007 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
3008 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
3009 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
3011 #define ADC_CFGR_OVRMOD_Pos (12U)
3012 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
3013 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
3014 #define ADC_CFGR_CONT_Pos (13U)
3015 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
3016 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
3017 #define ADC_CFGR_AUTDLY_Pos (14U)
3018 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
3019 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
3021 #define ADC_CFGR_DISCEN_Pos (16U)
3022 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
3023 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
3025 #define ADC_CFGR_DISCNUM_Pos (17U)
3026 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
3027 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
3028 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
3029 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
3030 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
3032 #define ADC_CFGR_JDISCEN_Pos (20U)
3033 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
3034 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
3035 #define ADC_CFGR_JQM_Pos (21U)
3036 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
3037 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
3038 #define ADC_CFGR_AWD1SGL_Pos (22U)
3039 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
3040 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
3041 #define ADC_CFGR_AWD1EN_Pos (23U)
3042 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
3043 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
3044 #define ADC_CFGR_JAWD1EN_Pos (24U)
3045 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
3046 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
3047 #define ADC_CFGR_JAUTO_Pos (25U)
3048 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
3049 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
3051 #define ADC_CFGR_AWD1CH_Pos (26U)
3052 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
3053 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
3054 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
3055 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
3056 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
3057 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
3058 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
3060 #define ADC_CFGR_JQDIS_Pos (31U)
3061 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
3062 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
3064 #define ADC3_CFGR_DMAEN_Pos (0U)
3065 #define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos)
3066 #define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk
3067 #define ADC3_CFGR_DMACFG_Pos (1U)
3068 #define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos)
3069 #define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk
3071 #define ADC3_CFGR_RES_Pos (3U)
3072 #define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos)
3073 #define ADC3_CFGR_RES ADC3_CFGR_RES_Msk
3074 #define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos)
3075 #define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos)
3077 #define ADC3_CFGR_ALIGN_Pos (15U)
3078 #define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos)
3079 #define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk
3080 /******************** Bit definition for ADC_CFGR2 register ********************/
3081 #define ADC_CFGR2_ROVSE_Pos (0U)
3082 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
3083 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
3084 #define ADC_CFGR2_JOVSE_Pos (1U)
3085 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
3086 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
3088 #define ADC_CFGR2_OVSS_Pos (5U)
3089 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
3090 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
3091 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
3092 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
3093 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
3094 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
3096 #define ADC_CFGR2_TROVS_Pos (9U)
3097 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
3098 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
3099 #define ADC_CFGR2_ROVSM_Pos (10U)
3100 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
3101 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
3103 #define ADC_CFGR2_RSHIFT1_Pos (11U)
3104 #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos)
3105 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk
3106 #define ADC_CFGR2_RSHIFT2_Pos (12U)
3107 #define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos)
3108 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk
3109 #define ADC_CFGR2_RSHIFT3_Pos (13U)
3110 #define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos)
3111 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk
3112 #define ADC_CFGR2_RSHIFT4_Pos (14U)
3113 #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos)
3114 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk
3116 #define ADC_CFGR2_OVSR_Pos (16U)
3117 #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos)
3118 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
3119 #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos)
3120 #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos)
3121 #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos)
3122 #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos)
3123 #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos)
3124 #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos)
3125 #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos)
3126 #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos)
3127 #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos)
3128 #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos)
3130 #define ADC_CFGR2_LSHIFT_Pos (28U)
3131 #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos)
3132 #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk
3133 #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos)
3134 #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos)
3135 #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos)
3136 #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos)
3138 #define ADC3_CFGR2_OVSR_Pos (2U)
3139 #define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos)
3140 #define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk
3141 #define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos)
3142 #define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos)
3143 #define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos)
3145 #define ADC3_CFGR2_SWTRIG_Pos (25U)
3146 #define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos)
3147 #define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk
3148 #define ADC3_CFGR2_BULB_Pos (26U)
3149 #define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos)
3150 #define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk
3151 #define ADC3_CFGR2_SMPTRIG_Pos (27U)
3152 #define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos)
3153 #define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk
3154 /******************** Bit definition for ADC_SMPR1 register ********************/
3155 #define ADC_SMPR1_SMP0_Pos (0U)
3156 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
3157 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
3158 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
3159 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
3160 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
3162 #define ADC_SMPR1_SMP1_Pos (3U)
3163 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
3164 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
3165 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
3166 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
3167 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
3169 #define ADC_SMPR1_SMP2_Pos (6U)
3170 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
3171 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
3172 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
3173 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
3174 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
3176 #define ADC_SMPR1_SMP3_Pos (9U)
3177 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
3178 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
3179 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
3180 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
3181 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
3183 #define ADC_SMPR1_SMP4_Pos (12U)
3184 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
3185 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
3186 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
3187 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
3188 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
3190 #define ADC_SMPR1_SMP5_Pos (15U)
3191 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
3192 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
3193 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
3194 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
3195 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
3197 #define ADC_SMPR1_SMP6_Pos (18U)
3198 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
3199 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
3200 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
3201 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
3202 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
3204 #define ADC_SMPR1_SMP7_Pos (21U)
3205 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
3206 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
3207 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
3208 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
3209 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
3211 #define ADC_SMPR1_SMP8_Pos (24U)
3212 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
3213 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
3214 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
3215 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
3216 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
3218 #define ADC_SMPR1_SMP9_Pos (27U)
3219 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
3220 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
3221 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
3222 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
3223 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
3225 /******************** Bit definition for ADC_SMPR2 register ********************/
3226 #define ADC_SMPR2_SMP10_Pos (0U)
3227 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
3228 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
3229 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
3230 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
3231 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
3233 #define ADC_SMPR2_SMP11_Pos (3U)
3234 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
3235 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
3236 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
3237 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
3238 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
3240 #define ADC_SMPR2_SMP12_Pos (6U)
3241 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
3242 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
3243 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
3244 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
3245 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
3247 #define ADC_SMPR2_SMP13_Pos (9U)
3248 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
3249 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
3250 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
3251 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
3252 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
3254 #define ADC_SMPR2_SMP14_Pos (12U)
3255 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
3256 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
3257 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
3258 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
3259 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
3261 #define ADC_SMPR2_SMP15_Pos (15U)
3262 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
3263 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
3264 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
3265 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
3266 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
3268 #define ADC_SMPR2_SMP16_Pos (18U)
3269 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
3270 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
3271 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
3272 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
3273 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
3275 #define ADC_SMPR2_SMP17_Pos (21U)
3276 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
3277 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
3278 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
3279 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
3280 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
3282 #define ADC_SMPR2_SMP18_Pos (24U)
3283 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
3284 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
3285 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
3286 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
3287 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
3289 #define ADC_SMPR2_SMP19_Pos (27U)
3290 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos)
3291 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk
3292 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos)
3293 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos)
3294 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos)
3296 /******************** Bit definition for ADC_PCSEL register ********************/
3297 #define ADC_PCSEL_PCSEL_Pos (0U)
3298 #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)
3299 #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk
3300 #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos)
3301 #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos)
3302 #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos)
3303 #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos)
3304 #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos)
3305 #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos)
3306 #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos)
3307 #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos)
3308 #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos)
3309 #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos)
3310 #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos)
3311 #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos)
3312 #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos)
3313 #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos)
3314 #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos)
3315 #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos)
3316 #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos)
3317 #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos)
3318 #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos)
3319 #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos)
3321 /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3322 #define ADC_LTR_LT_Pos (0U)
3323 #define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos)
3324 #define ADC_LTR_LT ADC_LTR_LT_Msk
3326 /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3327 #define ADC_HTR_HT_Pos (0U)
3328 #define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos)
3329 #define ADC_HTR_HT ADC_HTR_HT_Msk
3331 /******************** Bit definition for ADC3_TR1 register *******************/
3332 #define ADC3_TR1_LT1_Pos (0U)
3333 #define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos)
3334 #define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk
3336 #define ADC3_TR1_AWDFILT_Pos (12U)
3337 #define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos)
3338 #define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk
3339 #define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos)
3340 #define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos)
3341 #define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos)
3343 #define ADC3_TR1_HT1_Pos (16U)
3344 #define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos)
3345 #define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk
3347 /******************** Bit definition for ADC3_TR2 register *******************/
3348 #define ADC3_TR2_LT2_Pos (0U)
3349 #define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos)
3350 #define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk
3352 #define ADC3_TR2_HT2_Pos (16U)
3353 #define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos)
3354 #define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk
3356 /******************** Bit definition for ADC3_TR3 register *******************/
3357 #define ADC3_TR3_LT3_Pos (0U)
3358 #define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos)
3359 #define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk
3361 #define ADC3_TR3_HT3_Pos (16U)
3362 #define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos)
3363 #define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk
3365 /******************** Bit definition for ADC_SQR1 register ********************/
3366 #define ADC_SQR1_L_Pos (0U)
3367 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
3368 #define ADC_SQR1_L ADC_SQR1_L_Msk
3369 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
3370 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
3371 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
3372 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
3374 #define ADC_SQR1_SQ1_Pos (6U)
3375 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
3376 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
3377 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
3378 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
3379 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
3380 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
3381 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
3383 #define ADC_SQR1_SQ2_Pos (12U)
3384 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
3385 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
3386 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
3387 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
3388 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
3389 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
3390 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
3392 #define ADC_SQR1_SQ3_Pos (18U)
3393 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
3394 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
3395 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
3396 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
3397 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
3398 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
3399 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
3401 #define ADC_SQR1_SQ4_Pos (24U)
3402 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
3403 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
3404 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
3405 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
3406 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
3407 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
3408 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
3410 /******************** Bit definition for ADC_SQR2 register ********************/
3411 #define ADC_SQR2_SQ5_Pos (0U)
3412 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
3413 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
3414 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
3415 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
3416 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
3417 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
3418 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
3420 #define ADC_SQR2_SQ6_Pos (6U)
3421 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
3422 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
3423 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
3424 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
3425 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
3426 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
3427 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
3429 #define ADC_SQR2_SQ7_Pos (12U)
3430 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
3431 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
3432 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
3433 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
3434 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
3435 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
3436 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
3438 #define ADC_SQR2_SQ8_Pos (18U)
3439 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
3440 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
3441 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
3442 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
3443 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
3444 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
3445 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
3447 #define ADC_SQR2_SQ9_Pos (24U)
3448 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
3449 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
3450 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
3451 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
3452 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
3453 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
3454 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
3456 /******************** Bit definition for ADC_SQR3 register ********************/
3457 #define ADC_SQR3_SQ10_Pos (0U)
3458 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
3459 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
3460 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
3461 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
3462 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
3463 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
3464 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
3466 #define ADC_SQR3_SQ11_Pos (6U)
3467 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
3468 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
3469 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
3470 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
3471 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
3472 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
3473 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
3475 #define ADC_SQR3_SQ12_Pos (12U)
3476 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
3477 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
3478 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
3479 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
3480 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
3481 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
3482 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
3484 #define ADC_SQR3_SQ13_Pos (18U)
3485 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
3486 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
3487 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
3488 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
3489 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
3490 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
3491 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
3493 #define ADC_SQR3_SQ14_Pos (24U)
3494 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
3495 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
3496 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
3497 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
3498 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
3499 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
3500 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
3502 /******************** Bit definition for ADC_SQR4 register ********************/
3503 #define ADC_SQR4_SQ15_Pos (0U)
3504 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
3505 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
3506 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
3507 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
3508 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
3509 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
3510 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
3512 #define ADC_SQR4_SQ16_Pos (6U)
3513 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
3514 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
3515 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
3516 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
3517 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
3518 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
3519 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
3520 /******************** Bit definition for ADC_DR register ********************/
3521 #define ADC_DR_RDATA_Pos (0U)
3522 #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)
3523 #define ADC_DR_RDATA ADC_DR_RDATA_Msk
3525 /******************** Bit definition for ADC_JSQR register ********************/
3526 #define ADC_JSQR_JL_Pos (0U)
3527 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
3528 #define ADC_JSQR_JL ADC_JSQR_JL_Msk
3529 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
3530 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
3532 #define ADC_JSQR_JEXTSEL_Pos (2U)
3533 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)
3534 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
3535 #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos)
3536 #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos)
3537 #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos)
3538 #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos)
3539 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)
3541 #define ADC_JSQR_JEXTEN_Pos (7U)
3542 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
3543 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
3544 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
3545 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
3547 #define ADC_JSQR_JSQ1_Pos (9U)
3548 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
3549 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
3550 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
3551 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
3552 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
3553 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
3554 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
3556 #define ADC_JSQR_JSQ2_Pos (15U)
3557 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
3558 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
3559 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
3560 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
3561 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
3562 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
3563 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
3565 #define ADC_JSQR_JSQ3_Pos (21U)
3566 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
3567 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
3568 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
3569 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
3570 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
3571 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
3572 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
3574 #define ADC_JSQR_JSQ4_Pos (27U)
3575 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
3576 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
3577 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
3578 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
3579 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
3580 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
3581 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
3583 /******************** Bit definition for ADC_OFR1 register ********************/
3584 #define ADC_OFR1_OFFSET1_Pos (0U)
3585 #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos)
3586 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
3587 #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos)
3588 #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos)
3589 #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos)
3590 #define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos)
3591 #define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos)
3592 #define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos)
3593 #define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos)
3594 #define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos)
3595 #define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos)
3596 #define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos)
3597 #define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos)
3598 #define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos)
3599 #define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos)
3600 #define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos)
3601 #define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos)
3602 #define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos)
3603 #define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos)
3604 #define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos)
3605 #define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos)
3606 #define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos)
3607 #define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos)
3608 #define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos)
3609 #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos)
3610 #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos)
3611 #define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos)
3612 #define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos)
3614 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
3615 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
3616 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
3617 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
3618 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
3619 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
3620 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
3621 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
3623 #define ADC_OFR1_SSATE_Pos (31U)
3624 #define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos)
3625 #define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk
3627 #define ADC3_OFR1_OFFSET1_Pos (0U)
3628 #define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos)
3629 #define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk
3631 #define ADC3_OFR1_OFFSETPOS_Pos (24U)
3632 #define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos)
3633 #define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk
3634 #define ADC3_OFR1_SATEN_Pos (25U)
3635 #define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos)
3636 #define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk
3638 #define ADC3_OFR1_OFFSET1_EN_Pos (31U)
3639 #define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos)
3640 #define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk
3642 /******************** Bit definition for ADC_OFR2 register ********************/
3643 #define ADC_OFR2_OFFSET2_Pos (0U)
3644 #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos)
3645 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
3646 #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos)
3647 #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos)
3648 #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos)
3649 #define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos)
3650 #define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos)
3651 #define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos)
3652 #define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos)
3653 #define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos)
3654 #define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos)
3655 #define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos)
3656 #define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos)
3657 #define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos)
3658 #define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos)
3659 #define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos)
3660 #define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos)
3661 #define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos)
3662 #define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos)
3663 #define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos)
3664 #define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos)
3665 #define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos)
3666 #define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos)
3667 #define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos)
3668 #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos)
3669 #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos)
3670 #define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos)
3671 #define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos)
3673 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
3674 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
3675 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
3676 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
3677 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
3678 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
3679 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
3680 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
3682 #define ADC_OFR2_SSATE_Pos (31U)
3683 #define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos)
3684 #define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk
3686 #define ADC3_OFR2_OFFSET2_Pos (0U)
3687 #define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos)
3688 #define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk
3690 #define ADC3_OFR2_OFFSETPOS_Pos (24U)
3691 #define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos)
3692 #define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk
3693 #define ADC3_OFR2_SATEN_Pos (25U)
3694 #define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos)
3695 #define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk
3697 #define ADC3_OFR2_OFFSET2_EN_Pos (31U)
3698 #define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos)
3699 #define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk
3701 /******************** Bit definition for ADC_OFR3 register ********************/
3702 #define ADC_OFR3_OFFSET3_Pos (0U)
3703 #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos)
3704 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
3705 #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos)
3706 #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos)
3707 #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos)
3708 #define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos)
3709 #define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos)
3710 #define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos)
3711 #define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos)
3712 #define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos)
3713 #define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos)
3714 #define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos)
3715 #define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos)
3716 #define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos)
3717 #define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos)
3718 #define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos)
3719 #define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos)
3720 #define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos)
3721 #define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos)
3722 #define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos)
3723 #define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos)
3724 #define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos)
3725 #define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos)
3726 #define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos)
3727 #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos)
3728 #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos)
3729 #define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos)
3730 #define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos)
3732 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
3733 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
3734 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
3735 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
3736 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
3737 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
3738 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
3739 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
3741 #define ADC_OFR3_SSATE_Pos (31U)
3742 #define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos)
3743 #define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk
3745 #define ADC3_OFR3_OFFSET3_Pos (0U)
3746 #define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos)
3747 #define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk
3749 #define ADC3_OFR3_OFFSETPOS_Pos (24U)
3750 #define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos)
3751 #define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk
3752 #define ADC3_OFR3_SATEN_Pos (25U)
3753 #define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos)
3754 #define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk
3756 #define ADC3_OFR3_OFFSET3_EN_Pos (31U)
3757 #define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos)
3758 #define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk
3760 /******************** Bit definition for ADC_OFR4 register ********************/
3761 #define ADC_OFR4_OFFSET4_Pos (0U)
3762 #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos)
3763 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
3764 #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos)
3765 #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos)
3766 #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos)
3767 #define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos)
3768 #define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos)
3769 #define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos)
3770 #define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos)
3771 #define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos)
3772 #define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos)
3773 #define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos)
3774 #define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos)
3775 #define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos)
3776 #define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos)
3777 #define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos)
3778 #define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos)
3779 #define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos)
3780 #define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos)
3781 #define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos)
3782 #define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos)
3783 #define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos)
3784 #define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos)
3785 #define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos)
3786 #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos)
3787 #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos)
3788 #define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos)
3789 #define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos)
3791 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
3792 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
3793 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
3794 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
3795 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
3796 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
3797 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
3798 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
3800 #define ADC_OFR4_SSATE_Pos (31U)
3801 #define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos)
3802 #define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk
3804 #define ADC3_OFR4_OFFSET4_Pos (0U)
3805 #define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos)
3806 #define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk
3808 #define ADC3_OFR4_OFFSETPOS_Pos (24U)
3809 #define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos)
3810 #define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk
3811 #define ADC3_OFR4_SATEN_Pos (25U)
3812 #define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos)
3813 #define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk
3815 #define ADC3_OFR4_OFFSET4_EN_Pos (31U)
3816 #define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos)
3817 #define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk
3819 /******************** Bit definition for ADC_JDR1 register ********************/
3820 #define ADC_JDR1_JDATA_Pos (0U)
3821 #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)
3822 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
3823 #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos)
3824 #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos)
3825 #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos)
3826 #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos)
3827 #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos)
3828 #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos)
3829 #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos)
3830 #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos)
3831 #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos)
3832 #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos)
3833 #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos)
3834 #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos)
3835 #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos)
3836 #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos)
3837 #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos)
3838 #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos)
3839 #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos)
3840 #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos)
3841 #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos)
3842 #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos)
3843 #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos)
3844 #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos)
3845 #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos)
3846 #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos)
3847 #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos)
3848 #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos)
3849 #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos)
3850 #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos)
3851 #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos)
3852 #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos)
3853 #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos)
3854 #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos)
3856 /******************** Bit definition for ADC_JDR2 register ********************/
3857 #define ADC_JDR2_JDATA_Pos (0U)
3858 #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)
3859 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
3860 #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos)
3861 #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos)
3862 #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos)
3863 #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos)
3864 #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos)
3865 #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos)
3866 #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos)
3867 #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos)
3868 #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos)
3869 #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos)
3870 #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos)
3871 #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos)
3872 #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos)
3873 #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos)
3874 #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos)
3875 #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos)
3876 #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos)
3877 #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos)
3878 #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos)
3879 #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos)
3880 #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos)
3881 #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos)
3882 #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos)
3883 #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos)
3884 #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos)
3885 #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos)
3886 #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos)
3887 #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos)
3888 #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos)
3889 #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos)
3890 #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos)
3891 #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos)
3893 /******************** Bit definition for ADC_JDR3 register ********************/
3894 #define ADC_JDR3_JDATA_Pos (0U)
3895 #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)
3896 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
3897 #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos)
3898 #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos)
3899 #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos)
3900 #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos)
3901 #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos)
3902 #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos)
3903 #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos)
3904 #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos)
3905 #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos)
3906 #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos)
3907 #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos)
3908 #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos)
3909 #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos)
3910 #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos)
3911 #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos)
3912 #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos)
3913 #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos)
3914 #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos)
3915 #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos)
3916 #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos)
3917 #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos)
3918 #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos)
3919 #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos)
3920 #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos)
3921 #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos)
3922 #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos)
3923 #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos)
3924 #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos)
3925 #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos)
3926 #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos)
3927 #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos)
3928 #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos)
3930 /******************** Bit definition for ADC_JDR4 register ********************/
3931 #define ADC_JDR4_JDATA_Pos (0U)
3932 #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)
3933 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
3934 #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos)
3935 #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos)
3936 #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos)
3937 #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos)
3938 #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos)
3939 #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos)
3940 #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos)
3941 #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos)
3942 #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos)
3943 #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos)
3944 #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos)
3945 #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos)
3946 #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos)
3947 #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos)
3948 #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos)
3949 #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos)
3950 #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos)
3951 #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos)
3952 #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos)
3953 #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos)
3954 #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos)
3955 #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos)
3956 #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos)
3957 #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos)
3958 #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos)
3959 #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos)
3960 #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos)
3961 #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos)
3962 #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos)
3963 #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos)
3964 #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos)
3965 #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos)
3967 /******************** Bit definition for ADC_AWD2CR register ********************/
3968 #define ADC_AWD2CR_AWD2CH_Pos (0U)
3969 #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)
3970 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
3971 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
3972 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
3973 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
3974 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
3975 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
3976 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
3977 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
3978 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
3979 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
3980 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
3981 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
3982 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
3983 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
3984 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
3985 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
3986 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
3987 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
3988 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
3989 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
3990 #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)
3992 /******************** Bit definition for ADC_AWD3CR register ********************/
3993 #define ADC_AWD3CR_AWD3CH_Pos (0U)
3994 #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)
3995 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
3996 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
3997 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
3998 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
3999 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
4000 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
4001 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
4002 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
4003 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
4004 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
4005 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
4006 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
4007 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
4008 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
4009 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
4010 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
4011 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
4012 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
4013 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
4014 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
4015 #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)
4017 /******************** Bit definition for ADC_DIFSEL register ********************/
4018 #define ADC_DIFSEL_DIFSEL_Pos (0U)
4019 #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)
4020 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
4021 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
4022 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
4023 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
4024 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
4025 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
4026 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
4027 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
4028 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
4029 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
4030 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
4031 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
4032 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
4033 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
4034 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
4035 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
4036 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
4037 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
4038 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
4039 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
4040 #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)
4042 /******************** Bit definition for ADC_CALFACT register ********************/
4043 #define ADC_CALFACT_CALFACT_S_Pos (0U)
4044 #define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos)
4045 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
4046 #define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos)
4047 #define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos)
4048 #define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos)
4049 #define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos)
4050 #define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos)
4051 #define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos)
4052 #define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos)
4053 #define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos)
4054 #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos)
4055 #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos)
4056 #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos)
4057 #define ADC_CALFACT_CALFACT_D_Pos (16U)
4058 #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos)
4059 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
4060 #define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos)
4061 #define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos)
4062 #define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos)
4063 #define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos)
4064 #define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos)
4065 #define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos)
4066 #define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos)
4067 #define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos)
4068 #define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos)
4069 #define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos)
4070 #define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos)
4072 /******************** Bit definition for ADC_CALFACT2 register ********************/
4073 #define ADC_CALFACT2_LINCALFACT_Pos (0U)
4074 #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos)
4075 #define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk
4076 #define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos)
4077 #define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos)
4078 #define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos)
4079 #define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos)
4080 #define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos)
4081 #define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos)
4082 #define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos)
4083 #define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos)
4084 #define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos)
4085 #define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos)
4086 #define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos)
4087 #define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos)
4088 #define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos)
4089 #define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos)
4090 #define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos)
4091 #define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos)
4092 #define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos)
4093 #define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos)
4094 #define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos)
4095 #define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos)
4096 #define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos)
4097 #define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos)
4098 #define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos)
4099 #define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos)
4100 #define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4101 #define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4102 #define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4103 #define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4104 #define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4105 #define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4107 /************************* ADC Common registers *****************************/
4108 /******************** Bit definition for ADC_CSR register ********************/
4109 #define ADC_CSR_ADRDY_MST_Pos (0U)
4110 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
4111 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
4112 #define ADC_CSR_EOSMP_MST_Pos (1U)
4113 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
4114 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
4115 #define ADC_CSR_EOC_MST_Pos (2U)
4116 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
4117 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
4118 #define ADC_CSR_EOS_MST_Pos (3U)
4119 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
4120 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
4121 #define ADC_CSR_OVR_MST_Pos (4U)
4122 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
4123 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
4124 #define ADC_CSR_JEOC_MST_Pos (5U)
4125 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
4126 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
4127 #define ADC_CSR_JEOS_MST_Pos (6U)
4128 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
4129 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
4130 #define ADC_CSR_AWD1_MST_Pos (7U)
4131 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
4132 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
4133 #define ADC_CSR_AWD2_MST_Pos (8U)
4134 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
4135 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
4136 #define ADC_CSR_AWD3_MST_Pos (9U)
4137 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
4138 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
4139 #define ADC_CSR_JQOVF_MST_Pos (10U)
4140 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
4141 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
4142 #define ADC_CSR_ADRDY_SLV_Pos (16U)
4143 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
4144 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
4145 #define ADC_CSR_EOSMP_SLV_Pos (17U)
4146 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
4147 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
4148 #define ADC_CSR_EOC_SLV_Pos (18U)
4149 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
4150 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
4151 #define ADC_CSR_EOS_SLV_Pos (19U)
4152 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
4153 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
4154 #define ADC_CSR_OVR_SLV_Pos (20U)
4155 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
4156 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
4157 #define ADC_CSR_JEOC_SLV_Pos (21U)
4158 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
4159 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
4160 #define ADC_CSR_JEOS_SLV_Pos (22U)
4161 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
4162 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
4163 #define ADC_CSR_AWD1_SLV_Pos (23U)
4164 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
4165 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
4166 #define ADC_CSR_AWD2_SLV_Pos (24U)
4167 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
4168 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
4169 #define ADC_CSR_AWD3_SLV_Pos (25U)
4170 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
4171 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
4172 #define ADC_CSR_JQOVF_SLV_Pos (26U)
4173 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
4174 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
4176 /******************** Bit definition for ADC_CCR register ********************/
4177 #define ADC_CCR_DUAL_Pos (0U)
4178 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
4179 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
4180 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
4181 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
4182 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
4183 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
4184 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
4186 #define ADC_CCR_DELAY_Pos (8U)
4187 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
4188 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
4189 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
4190 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
4191 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
4192 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
4195 #define ADC_CCR_DAMDF_Pos (14U)
4196 #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos)
4197 #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk
4198 #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos)
4199 #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos)
4201 #define ADC_CCR_CKMODE_Pos (16U)
4202 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
4203 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
4204 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
4205 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
4207 #define ADC_CCR_PRESC_Pos (18U)
4208 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
4209 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
4210 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
4211 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
4212 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
4213 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
4215 #define ADC_CCR_VREFEN_Pos (22U)
4216 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
4217 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
4218 #define ADC_CCR_TSEN_Pos (23U)
4219 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
4220 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
4221 #define ADC_CCR_VBATEN_Pos (24U)
4222 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
4223 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
4225 /******************** Bit definition for ADC_CDR register *******************/
4226 #define ADC_CDR_RDATA_MST_Pos (0U)
4227 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
4228 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
4230 #define ADC_CDR_RDATA_SLV_Pos (16U)
4231 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
4232 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
4234 /******************** Bit definition for ADC_CDR2 register ******************/
4235 #define ADC_CDR2_RDATA_ALT_Pos (0U)
4236 #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos)
4237 #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk
4240 /******************************************************************************/
4241 /* */
4242 /* VREFBUF */
4243 /* */
4244 /******************************************************************************/
4245 /******************* Bit definition for VREFBUF_CSR register ****************/
4246 #define VREFBUF_CSR_ENVR_Pos (0U)
4247 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
4248 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
4249 #define VREFBUF_CSR_HIZ_Pos (1U)
4250 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
4251 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
4252 #define VREFBUF_CSR_VRR_Pos (3U)
4253 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
4254 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
4255 #define VREFBUF_CSR_VRS_Pos (4U)
4256 #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos)
4257 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
4259 #define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000)
4260 #define VREFBUF_CSR_VRS_OUT2_Pos (4U)
4261 #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)
4262 #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk
4263 #define VREFBUF_CSR_VRS_OUT3_Pos (5U)
4264 #define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)
4265 #define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk
4266 #define VREFBUF_CSR_VRS_OUT4_Pos (4U)
4267 #define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)
4268 #define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk
4270 /******************* Bit definition for VREFBUF_CCR register ****************/
4271 #define VREFBUF_CCR_TRIM_Pos (0U)
4272 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
4273 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
4275 /******************************************************************************/
4276 /* */
4277 /* Flexible Datarate Controller Area Network */
4278 /* */
4279 /******************************************************************************/
4281 /***************** Bit definition for FDCAN_CREL register *******************/
4282 #define FDCAN_CREL_DAY_Pos (0U)
4283 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)
4284 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk
4285 #define FDCAN_CREL_MON_Pos (8U)
4286 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)
4287 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk
4288 #define FDCAN_CREL_YEAR_Pos (16U)
4289 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)
4290 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk
4291 #define FDCAN_CREL_SUBSTEP_Pos (20U)
4292 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)
4293 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk
4294 #define FDCAN_CREL_STEP_Pos (24U)
4295 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)
4296 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk
4297 #define FDCAN_CREL_REL_Pos (28U)
4298 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)
4299 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk
4301 /***************** Bit definition for FDCAN_ENDN register *******************/
4302 #define FDCAN_ENDN_ETV_Pos (0U)
4303 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)
4304 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk
4306 /***************** Bit definition for FDCAN_DBTP register *******************/
4307 #define FDCAN_DBTP_DSJW_Pos (0U)
4308 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)
4309 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk
4310 #define FDCAN_DBTP_DTSEG2_Pos (4U)
4311 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)
4312 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk
4313 #define FDCAN_DBTP_DTSEG1_Pos (8U)
4314 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)
4315 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk
4316 #define FDCAN_DBTP_DBRP_Pos (16U)
4317 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)
4318 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk
4319 #define FDCAN_DBTP_TDC_Pos (23U)
4320 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)
4321 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk
4323 /***************** Bit definition for FDCAN_TEST register *******************/
4324 #define FDCAN_TEST_LBCK_Pos (4U)
4325 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)
4326 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk
4327 #define FDCAN_TEST_TX_Pos (5U)
4328 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)
4329 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk
4330 #define FDCAN_TEST_RX_Pos (7U)
4331 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)
4332 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk
4334 /***************** Bit definition for FDCAN_RWD register ********************/
4335 #define FDCAN_RWD_WDC_Pos (0U)
4336 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)
4337 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk
4338 #define FDCAN_RWD_WDV_Pos (8U)
4339 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)
4340 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk
4342 /***************** Bit definition for FDCAN_CCCR register ********************/
4343 #define FDCAN_CCCR_INIT_Pos (0U)
4344 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)
4345 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk
4346 #define FDCAN_CCCR_CCE_Pos (1U)
4347 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)
4348 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk
4349 #define FDCAN_CCCR_ASM_Pos (2U)
4350 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)
4351 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk
4352 #define FDCAN_CCCR_CSA_Pos (3U)
4353 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)
4354 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk
4355 #define FDCAN_CCCR_CSR_Pos (4U)
4356 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)
4357 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk
4358 #define FDCAN_CCCR_MON_Pos (5U)
4359 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)
4360 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk
4361 #define FDCAN_CCCR_DAR_Pos (6U)
4362 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)
4363 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk
4364 #define FDCAN_CCCR_TEST_Pos (7U)
4365 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)
4366 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk
4367 #define FDCAN_CCCR_FDOE_Pos (8U)
4368 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)
4369 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk
4370 #define FDCAN_CCCR_BRSE_Pos (9U)
4371 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)
4372 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk
4373 #define FDCAN_CCCR_PXHD_Pos (12U)
4374 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)
4375 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk
4376 #define FDCAN_CCCR_EFBI_Pos (13U)
4377 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)
4378 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk
4379 #define FDCAN_CCCR_TXP_Pos (14U)
4380 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)
4381 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk
4382 #define FDCAN_CCCR_NISO_Pos (15U)
4383 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)
4384 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk
4386 /***************** Bit definition for FDCAN_NBTP register ********************/
4387 #define FDCAN_NBTP_NTSEG2_Pos (0U)
4388 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)
4389 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk
4390 #define FDCAN_NBTP_NTSEG1_Pos (8U)
4391 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)
4392 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk
4393 #define FDCAN_NBTP_NBRP_Pos (16U)
4394 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)
4395 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk
4396 #define FDCAN_NBTP_NSJW_Pos (25U)
4397 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)
4398 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk
4400 /***************** Bit definition for FDCAN_TSCC register ********************/
4401 #define FDCAN_TSCC_TSS_Pos (0U)
4402 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)
4403 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk
4404 #define FDCAN_TSCC_TCP_Pos (16U)
4405 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)
4406 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk
4408 /***************** Bit definition for FDCAN_TSCV register ********************/
4409 #define FDCAN_TSCV_TSC_Pos (0U)
4410 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)
4411 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk
4413 /***************** Bit definition for FDCAN_TOCC register ********************/
4414 #define FDCAN_TOCC_ETOC_Pos (0U)
4415 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)
4416 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk
4417 #define FDCAN_TOCC_TOS_Pos (1U)
4418 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)
4419 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk
4420 #define FDCAN_TOCC_TOP_Pos (16U)
4421 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)
4422 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk
4424 /***************** Bit definition for FDCAN_TOCV register ********************/
4425 #define FDCAN_TOCV_TOC_Pos (0U)
4426 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)
4427 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk
4429 /***************** Bit definition for FDCAN_ECR register *********************/
4430 #define FDCAN_ECR_TEC_Pos (0U)
4431 #define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)
4432 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk
4433 #define FDCAN_ECR_REC_Pos (8U)
4434 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)
4435 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk
4436 #define FDCAN_ECR_RP_Pos (15U)
4437 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)
4438 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk
4439 #define FDCAN_ECR_CEL_Pos (16U)
4440 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)
4441 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk
4443 /***************** Bit definition for FDCAN_PSR register *********************/
4444 #define FDCAN_PSR_LEC_Pos (0U)
4445 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)
4446 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk
4447 #define FDCAN_PSR_ACT_Pos (3U)
4448 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)
4449 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk
4450 #define FDCAN_PSR_EP_Pos (5U)
4451 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)
4452 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk
4453 #define FDCAN_PSR_EW_Pos (6U)
4454 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)
4455 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk
4456 #define FDCAN_PSR_BO_Pos (7U)
4457 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)
4458 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk
4459 #define FDCAN_PSR_DLEC_Pos (8U)
4460 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)
4461 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk
4462 #define FDCAN_PSR_RESI_Pos (11U)
4463 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)
4464 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk
4465 #define FDCAN_PSR_RBRS_Pos (12U)
4466 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)
4467 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk
4468 #define FDCAN_PSR_REDL_Pos (13U)
4469 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)
4470 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk
4471 #define FDCAN_PSR_PXE_Pos (14U)
4472 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)
4473 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk
4474 #define FDCAN_PSR_TDCV_Pos (16U)
4475 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)
4476 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk
4478 /***************** Bit definition for FDCAN_TDCR register ********************/
4479 #define FDCAN_TDCR_TDCF_Pos (0U)
4480 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)
4481 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk
4482 #define FDCAN_TDCR_TDCO_Pos (8U)
4483 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)
4484 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk
4486 /***************** Bit definition for FDCAN_IR register **********************/
4487 #define FDCAN_IR_RF0N_Pos (0U)
4488 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)
4489 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk
4490 #define FDCAN_IR_RF0W_Pos (1U)
4491 #define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos)
4492 #define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk
4493 #define FDCAN_IR_RF0F_Pos (2U)
4494 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)
4495 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk
4496 #define FDCAN_IR_RF0L_Pos (3U)
4497 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)
4498 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk
4499 #define FDCAN_IR_RF1N_Pos (4U)
4500 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)
4501 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk
4502 #define FDCAN_IR_RF1W_Pos (5U)
4503 #define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos)
4504 #define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk
4505 #define FDCAN_IR_RF1F_Pos (6U)
4506 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)
4507 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk
4508 #define FDCAN_IR_RF1L_Pos (7U)
4509 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)
4510 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk
4511 #define FDCAN_IR_HPM_Pos (8U)
4512 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)
4513 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk
4514 #define FDCAN_IR_TC_Pos (9U)
4515 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)
4516 #define FDCAN_IR_TC FDCAN_IR_TC_Msk
4517 #define FDCAN_IR_TCF_Pos (10U)
4518 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)
4519 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk
4520 #define FDCAN_IR_TFE_Pos (11U)
4521 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)
4522 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk
4523 #define FDCAN_IR_TEFN_Pos (12U)
4524 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)
4525 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk
4526 #define FDCAN_IR_TEFW_Pos (13U)
4527 #define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos)
4528 #define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk
4529 #define FDCAN_IR_TEFF_Pos (14U)
4530 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)
4531 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk
4532 #define FDCAN_IR_TEFL_Pos (15U)
4533 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)
4534 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk
4535 #define FDCAN_IR_TSW_Pos (16U)
4536 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)
4537 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk
4538 #define FDCAN_IR_MRAF_Pos (17U)
4539 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)
4540 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk
4541 #define FDCAN_IR_TOO_Pos (18U)
4542 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)
4543 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk
4544 #define FDCAN_IR_DRX_Pos (19U)
4545 #define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos)
4546 #define FDCAN_IR_DRX FDCAN_IR_DRX_Msk
4547 #define FDCAN_IR_ELO_Pos (22U)
4548 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)
4549 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk
4550 #define FDCAN_IR_EP_Pos (23U)
4551 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)
4552 #define FDCAN_IR_EP FDCAN_IR_EP_Msk
4553 #define FDCAN_IR_EW_Pos (24U)
4554 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)
4555 #define FDCAN_IR_EW FDCAN_IR_EW_Msk
4556 #define FDCAN_IR_BO_Pos (25U)
4557 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)
4558 #define FDCAN_IR_BO FDCAN_IR_BO_Msk
4559 #define FDCAN_IR_WDI_Pos (26U)
4560 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)
4561 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk
4562 #define FDCAN_IR_PEA_Pos (27U)
4563 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)
4564 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk
4565 #define FDCAN_IR_PED_Pos (28U)
4566 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)
4567 #define FDCAN_IR_PED FDCAN_IR_PED_Msk
4568 #define FDCAN_IR_ARA_Pos (29U)
4569 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)
4570 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk
4572 /***************** Bit definition for FDCAN_IE register **********************/
4573 #define FDCAN_IE_RF0NE_Pos (0U)
4574 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)
4575 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk
4576 #define FDCAN_IE_RF0WE_Pos (1U)
4577 #define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos)
4578 #define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk
4579 #define FDCAN_IE_RF0FE_Pos (2U)
4580 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)
4581 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk
4582 #define FDCAN_IE_RF0LE_Pos (3U)
4583 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)
4584 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk
4585 #define FDCAN_IE_RF1NE_Pos (4U)
4586 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)
4587 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk
4588 #define FDCAN_IE_RF1WE_Pos (5U)
4589 #define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos)
4590 #define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk
4591 #define FDCAN_IE_RF1FE_Pos (6U)
4592 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)
4593 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk
4594 #define FDCAN_IE_RF1LE_Pos (7U)
4595 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)
4596 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk
4597 #define FDCAN_IE_HPME_Pos (8U)
4598 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)
4599 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk
4600 #define FDCAN_IE_TCE_Pos (9U)
4601 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)
4602 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk
4603 #define FDCAN_IE_TCFE_Pos (10U)
4604 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)
4605 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk
4606 #define FDCAN_IE_TFEE_Pos (11U)
4607 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)
4608 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk
4609 #define FDCAN_IE_TEFNE_Pos (12U)
4610 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)
4611 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk
4612 #define FDCAN_IE_TEFWE_Pos (13U)
4613 #define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos)
4614 #define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk
4615 #define FDCAN_IE_TEFFE_Pos (14U)
4616 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)
4617 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk
4618 #define FDCAN_IE_TEFLE_Pos (15U)
4619 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)
4620 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk
4621 #define FDCAN_IE_TSWE_Pos (16U)
4622 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)
4623 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk
4624 #define FDCAN_IE_MRAFE_Pos (17U)
4625 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)
4626 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk
4627 #define FDCAN_IE_TOOE_Pos (18U)
4628 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)
4629 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk
4630 #define FDCAN_IE_DRXE_Pos (19U)
4631 #define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos)
4632 #define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk
4633 #define FDCAN_IE_BECE_Pos (20U)
4634 #define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos)
4635 #define FDCAN_IE_BECE FDCAN_IE_BECE_Msk
4636 #define FDCAN_IE_BEUE_Pos (21U)
4637 #define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos)
4638 #define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk
4639 #define FDCAN_IE_ELOE_Pos (22U)
4640 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)
4641 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk
4642 #define FDCAN_IE_EPE_Pos (23U)
4643 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)
4644 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk
4645 #define FDCAN_IE_EWE_Pos (24U)
4646 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)
4647 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk
4648 #define FDCAN_IE_BOE_Pos (25U)
4649 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)
4650 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk
4651 #define FDCAN_IE_WDIE_Pos (26U)
4652 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)
4653 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk
4654 #define FDCAN_IE_PEAE_Pos (27U)
4655 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)
4656 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk
4657 #define FDCAN_IE_PEDE_Pos (28U)
4658 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)
4659 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk
4660 #define FDCAN_IE_ARAE_Pos (29U)
4661 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)
4662 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk
4664 /***************** Bit definition for FDCAN_ILS register **********************/
4665 #define FDCAN_ILS_RF0NL_Pos (0U)
4666 #define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos)
4667 #define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk
4668 #define FDCAN_ILS_RF0WL_Pos (1U)
4669 #define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos)
4670 #define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk
4671 #define FDCAN_ILS_RF0FL_Pos (2U)
4672 #define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos)
4673 #define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk
4674 #define FDCAN_ILS_RF0LL_Pos (3U)
4675 #define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos)
4676 #define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk
4677 #define FDCAN_ILS_RF1NL_Pos (4U)
4678 #define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos)
4679 #define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk
4680 #define FDCAN_ILS_RF1WL_Pos (5U)
4681 #define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos)
4682 #define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk
4683 #define FDCAN_ILS_RF1FL_Pos (6U)
4684 #define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos)
4685 #define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk
4686 #define FDCAN_ILS_RF1LL_Pos (7U)
4687 #define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos)
4688 #define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk
4689 #define FDCAN_ILS_HPML_Pos (8U)
4690 #define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos)
4691 #define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk
4692 #define FDCAN_ILS_TCL_Pos (9U)
4693 #define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos)
4694 #define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk
4695 #define FDCAN_ILS_TCFL_Pos (10U)
4696 #define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos)
4697 #define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk
4698 #define FDCAN_ILS_TFEL_Pos (11U)
4699 #define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos)
4700 #define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk
4701 #define FDCAN_ILS_TEFNL_Pos (12U)
4702 #define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos)
4703 #define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk
4704 #define FDCAN_ILS_TEFWL_Pos (13U)
4705 #define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos)
4706 #define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk
4707 #define FDCAN_ILS_TEFFL_Pos (14U)
4708 #define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos)
4709 #define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk
4710 #define FDCAN_ILS_TEFLL_Pos (15U)
4711 #define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos)
4712 #define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk
4713 #define FDCAN_ILS_TSWL_Pos (16U)
4714 #define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos)
4715 #define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk
4716 #define FDCAN_ILS_MRAFE_Pos (17U)
4717 #define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos)
4718 #define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk
4719 #define FDCAN_ILS_TOOE_Pos (18U)
4720 #define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos)
4721 #define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk
4722 #define FDCAN_ILS_DRXE_Pos (19U)
4723 #define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos)
4724 #define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk
4725 #define FDCAN_ILS_BECE_Pos (20U)
4726 #define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos)
4727 #define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk
4728 #define FDCAN_ILS_BEUE_Pos (21U)
4729 #define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos)
4730 #define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk
4731 #define FDCAN_ILS_ELOE_Pos (22U)
4732 #define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos)
4733 #define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk
4734 #define FDCAN_ILS_EPE_Pos (23U)
4735 #define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos)
4736 #define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk
4737 #define FDCAN_ILS_EWE_Pos (24U)
4738 #define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos)
4739 #define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk
4740 #define FDCAN_ILS_BOE_Pos (25U)
4741 #define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos)
4742 #define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk
4743 #define FDCAN_ILS_WDIE_Pos (26U)
4744 #define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos)
4745 #define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk
4746 #define FDCAN_ILS_PEAE_Pos (27U)
4747 #define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos)
4748 #define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk
4749 #define FDCAN_ILS_PEDE_Pos (28U)
4750 #define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos)
4751 #define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk
4752 #define FDCAN_ILS_ARAE_Pos (29U)
4753 #define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos)
4754 #define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk
4756 /***************** Bit definition for FDCAN_ILE register **********************/
4757 #define FDCAN_ILE_EINT0_Pos (0U)
4758 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)
4759 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk
4760 #define FDCAN_ILE_EINT1_Pos (1U)
4761 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)
4762 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk
4764 /***************** Bit definition for FDCAN_GFC register **********************/
4765 #define FDCAN_GFC_RRFE_Pos (0U)
4766 #define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos)
4767 #define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk
4768 #define FDCAN_GFC_RRFS_Pos (1U)
4769 #define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos)
4770 #define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk
4771 #define FDCAN_GFC_ANFE_Pos (2U)
4772 #define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos)
4773 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk
4774 #define FDCAN_GFC_ANFS_Pos (4U)
4775 #define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos)
4776 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk
4778 /***************** Bit definition for FDCAN_SIDFC register ********************/
4779 #define FDCAN_SIDFC_FLSSA_Pos (2U)
4780 #define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)
4781 #define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk
4782 #define FDCAN_SIDFC_LSS_Pos (16U)
4783 #define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos)
4784 #define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk
4786 /***************** Bit definition for FDCAN_XIDFC register ********************/
4787 #define FDCAN_XIDFC_FLESA_Pos (2U)
4788 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)
4789 #define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk
4790 #define FDCAN_XIDFC_LSE_Pos (16U)
4791 #define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos)
4792 #define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk
4794 /***************** Bit definition for FDCAN_XIDAM register ********************/
4795 #define FDCAN_XIDAM_EIDM_Pos (0U)
4796 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)
4797 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk
4799 /***************** Bit definition for FDCAN_HPMS register *********************/
4800 #define FDCAN_HPMS_BIDX_Pos (0U)
4801 #define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos)
4802 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk
4803 #define FDCAN_HPMS_MSI_Pos (6U)
4804 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)
4805 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk
4806 #define FDCAN_HPMS_FIDX_Pos (8U)
4807 #define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos)
4808 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk
4809 #define FDCAN_HPMS_FLST_Pos (15U)
4810 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)
4811 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk
4813 /***************** Bit definition for FDCAN_NDAT1 register ********************/
4814 #define FDCAN_NDAT1_ND0_Pos (0U)
4815 #define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos)
4816 #define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk
4817 #define FDCAN_NDAT1_ND1_Pos (1U)
4818 #define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos)
4819 #define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk
4820 #define FDCAN_NDAT1_ND2_Pos (2U)
4821 #define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos)
4822 #define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk
4823 #define FDCAN_NDAT1_ND3_Pos (3U)
4824 #define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos)
4825 #define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk
4826 #define FDCAN_NDAT1_ND4_Pos (4U)
4827 #define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos)
4828 #define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk
4829 #define FDCAN_NDAT1_ND5_Pos (5U)
4830 #define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos)
4831 #define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk
4832 #define FDCAN_NDAT1_ND6_Pos (6U)
4833 #define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos)
4834 #define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk
4835 #define FDCAN_NDAT1_ND7_Pos (7U)
4836 #define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos)
4837 #define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk
4838 #define FDCAN_NDAT1_ND8_Pos (8U)
4839 #define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos)
4840 #define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk
4841 #define FDCAN_NDAT1_ND9_Pos (9U)
4842 #define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos)
4843 #define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk
4844 #define FDCAN_NDAT1_ND10_Pos (10U)
4845 #define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos)
4846 #define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk
4847 #define FDCAN_NDAT1_ND11_Pos (11U)
4848 #define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos)
4849 #define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk
4850 #define FDCAN_NDAT1_ND12_Pos (12U)
4851 #define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos)
4852 #define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk
4853 #define FDCAN_NDAT1_ND13_Pos (13U)
4854 #define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos)
4855 #define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk
4856 #define FDCAN_NDAT1_ND14_Pos (14U)
4857 #define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos)
4858 #define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk
4859 #define FDCAN_NDAT1_ND15_Pos (15U)
4860 #define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos)
4861 #define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk
4862 #define FDCAN_NDAT1_ND16_Pos (16U)
4863 #define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos)
4864 #define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk
4865 #define FDCAN_NDAT1_ND17_Pos (17U)
4866 #define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos)
4867 #define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk
4868 #define FDCAN_NDAT1_ND18_Pos (18U)
4869 #define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos)
4870 #define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk
4871 #define FDCAN_NDAT1_ND19_Pos (19U)
4872 #define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos)
4873 #define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk
4874 #define FDCAN_NDAT1_ND20_Pos (20U)
4875 #define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos)
4876 #define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk
4877 #define FDCAN_NDAT1_ND21_Pos (21U)
4878 #define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos)
4879 #define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk
4880 #define FDCAN_NDAT1_ND22_Pos (22U)
4881 #define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos)
4882 #define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk
4883 #define FDCAN_NDAT1_ND23_Pos (23U)
4884 #define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos)
4885 #define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk
4886 #define FDCAN_NDAT1_ND24_Pos (24U)
4887 #define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos)
4888 #define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk
4889 #define FDCAN_NDAT1_ND25_Pos (25U)
4890 #define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos)
4891 #define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk
4892 #define FDCAN_NDAT1_ND26_Pos (26U)
4893 #define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos)
4894 #define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk
4895 #define FDCAN_NDAT1_ND27_Pos (27U)
4896 #define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos)
4897 #define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk
4898 #define FDCAN_NDAT1_ND28_Pos (28U)
4899 #define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos)
4900 #define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk
4901 #define FDCAN_NDAT1_ND29_Pos (29U)
4902 #define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos)
4903 #define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk
4904 #define FDCAN_NDAT1_ND30_Pos (30U)
4905 #define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos)
4906 #define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk
4907 #define FDCAN_NDAT1_ND31_Pos (31U)
4908 #define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos)
4909 #define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk
4911 /***************** Bit definition for FDCAN_NDAT2 register ********************/
4912 #define FDCAN_NDAT2_ND32_Pos (0U)
4913 #define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos)
4914 #define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk
4915 #define FDCAN_NDAT2_ND33_Pos (1U)
4916 #define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos)
4917 #define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk
4918 #define FDCAN_NDAT2_ND34_Pos (2U)
4919 #define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos)
4920 #define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk
4921 #define FDCAN_NDAT2_ND35_Pos (3U)
4922 #define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos)
4923 #define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk
4924 #define FDCAN_NDAT2_ND36_Pos (4U)
4925 #define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos)
4926 #define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk
4927 #define FDCAN_NDAT2_ND37_Pos (5U)
4928 #define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos)
4929 #define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk
4930 #define FDCAN_NDAT2_ND38_Pos (6U)
4931 #define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos)
4932 #define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk
4933 #define FDCAN_NDAT2_ND39_Pos (7U)
4934 #define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos)
4935 #define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk
4936 #define FDCAN_NDAT2_ND40_Pos (8U)
4937 #define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos)
4938 #define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk
4939 #define FDCAN_NDAT2_ND41_Pos (9U)
4940 #define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos)
4941 #define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk
4942 #define FDCAN_NDAT2_ND42_Pos (10U)
4943 #define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos)
4944 #define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk
4945 #define FDCAN_NDAT2_ND43_Pos (11U)
4946 #define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos)
4947 #define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk
4948 #define FDCAN_NDAT2_ND44_Pos (12U)
4949 #define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos)
4950 #define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk
4951 #define FDCAN_NDAT2_ND45_Pos (13U)
4952 #define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos)
4953 #define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk
4954 #define FDCAN_NDAT2_ND46_Pos (14U)
4955 #define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos)
4956 #define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk
4957 #define FDCAN_NDAT2_ND47_Pos (15U)
4958 #define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos)
4959 #define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk
4960 #define FDCAN_NDAT2_ND48_Pos (16U)
4961 #define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos)
4962 #define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk
4963 #define FDCAN_NDAT2_ND49_Pos (17U)
4964 #define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos)
4965 #define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk
4966 #define FDCAN_NDAT2_ND50_Pos (18U)
4967 #define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos)
4968 #define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk
4969 #define FDCAN_NDAT2_ND51_Pos (19U)
4970 #define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos)
4971 #define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk
4972 #define FDCAN_NDAT2_ND52_Pos (20U)
4973 #define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos)
4974 #define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk
4975 #define FDCAN_NDAT2_ND53_Pos (21U)
4976 #define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos)
4977 #define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk
4978 #define FDCAN_NDAT2_ND54_Pos (22U)
4979 #define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos)
4980 #define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk
4981 #define FDCAN_NDAT2_ND55_Pos (23U)
4982 #define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos)
4983 #define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk
4984 #define FDCAN_NDAT2_ND56_Pos (24U)
4985 #define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos)
4986 #define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk
4987 #define FDCAN_NDAT2_ND57_Pos (25U)
4988 #define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos)
4989 #define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk
4990 #define FDCAN_NDAT2_ND58_Pos (26U)
4991 #define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos)
4992 #define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk
4993 #define FDCAN_NDAT2_ND59_Pos (27U)
4994 #define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos)
4995 #define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk
4996 #define FDCAN_NDAT2_ND60_Pos (28U)
4997 #define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos)
4998 #define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk
4999 #define FDCAN_NDAT2_ND61_Pos (29U)
5000 #define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos)
5001 #define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk
5002 #define FDCAN_NDAT2_ND62_Pos (30U)
5003 #define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos)
5004 #define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk
5005 #define FDCAN_NDAT2_ND63_Pos (31U)
5006 #define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos)
5007 #define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk
5009 /***************** Bit definition for FDCAN_RXF0C register ********************/
5010 #define FDCAN_RXF0C_F0SA_Pos (2U)
5011 #define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)
5012 #define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk
5013 #define FDCAN_RXF0C_F0S_Pos (16U)
5014 #define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos)
5015 #define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk
5016 #define FDCAN_RXF0C_F0WM_Pos (24U)
5017 #define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos)
5018 #define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk
5019 #define FDCAN_RXF0C_F0OM_Pos (31U)
5020 #define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos)
5021 #define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk
5023 /***************** Bit definition for FDCAN_RXF0S register ********************/
5024 #define FDCAN_RXF0S_F0FL_Pos (0U)
5025 #define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos)
5026 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk
5027 #define FDCAN_RXF0S_F0GI_Pos (8U)
5028 #define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos)
5029 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk
5030 #define FDCAN_RXF0S_F0PI_Pos (16U)
5031 #define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos)
5032 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk
5033 #define FDCAN_RXF0S_F0F_Pos (24U)
5034 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)
5035 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk
5036 #define FDCAN_RXF0S_RF0L_Pos (25U)
5037 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)
5038 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk
5040 /***************** Bit definition for FDCAN_RXF0A register ********************/
5041 #define FDCAN_RXF0A_F0AI_Pos (0U)
5042 #define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos)
5043 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk
5045 /***************** Bit definition for FDCAN_RXBC register ********************/
5046 #define FDCAN_RXBC_RBSA_Pos (2U)
5047 #define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)
5048 #define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk
5050 /***************** Bit definition for FDCAN_RXF1C register ********************/
5051 #define FDCAN_RXF1C_F1SA_Pos (2U)
5052 #define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)
5053 #define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk
5054 #define FDCAN_RXF1C_F1S_Pos (16U)
5055 #define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos)
5056 #define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk
5057 #define FDCAN_RXF1C_F1WM_Pos (24U)
5058 #define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos)
5059 #define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk
5060 #define FDCAN_RXF1C_F1OM_Pos (31U)
5061 #define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos)
5062 #define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk
5064 /***************** Bit definition for FDCAN_RXF1S register ********************/
5065 #define FDCAN_RXF1S_F1FL_Pos (0U)
5066 #define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos)
5067 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk
5068 #define FDCAN_RXF1S_F1GI_Pos (8U)
5069 #define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos)
5070 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk
5071 #define FDCAN_RXF1S_F1PI_Pos (16U)
5072 #define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos)
5073 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk
5074 #define FDCAN_RXF1S_F1F_Pos (24U)
5075 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)
5076 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk
5077 #define FDCAN_RXF1S_RF1L_Pos (25U)
5078 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)
5079 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk
5081 /***************** Bit definition for FDCAN_RXF1A register ********************/
5082 #define FDCAN_RXF1A_F1AI_Pos (0U)
5083 #define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos)
5084 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk
5086 /***************** Bit definition for FDCAN_RXESC register ********************/
5087 #define FDCAN_RXESC_F0DS_Pos (0U)
5088 #define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos)
5089 #define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk
5090 #define FDCAN_RXESC_F1DS_Pos (4U)
5091 #define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos)
5092 #define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk
5093 #define FDCAN_RXESC_RBDS_Pos (8U)
5094 #define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos)
5095 #define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk
5097 /***************** Bit definition for FDCAN_TXBC register *********************/
5098 #define FDCAN_TXBC_TBSA_Pos (2U)
5099 #define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)
5100 #define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk
5101 #define FDCAN_TXBC_NDTB_Pos (16U)
5102 #define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos)
5103 #define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk
5104 #define FDCAN_TXBC_TFQS_Pos (24U)
5105 #define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos)
5106 #define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk
5107 #define FDCAN_TXBC_TFQM_Pos (30U)
5108 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)
5109 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk
5111 /***************** Bit definition for FDCAN_TXFQS register *********************/
5112 #define FDCAN_TXFQS_TFFL_Pos (0U)
5113 #define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos)
5114 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk
5115 #define FDCAN_TXFQS_TFGI_Pos (8U)
5116 #define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos)
5117 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk
5118 #define FDCAN_TXFQS_TFQPI_Pos (16U)
5119 #define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)
5120 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk
5121 #define FDCAN_TXFQS_TFQF_Pos (21U)
5122 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)
5123 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk
5125 /***************** Bit definition for FDCAN_TXESC register *********************/
5126 #define FDCAN_TXESC_TBDS_Pos (0U)
5127 #define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos)
5128 #define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk
5130 /***************** Bit definition for FDCAN_TXBRP register *********************/
5131 #define FDCAN_TXBRP_TRP_Pos (0U)
5132 #define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)
5133 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk
5135 /***************** Bit definition for FDCAN_TXBAR register *********************/
5136 #define FDCAN_TXBAR_AR_Pos (0U)
5137 #define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)
5138 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk
5140 /***************** Bit definition for FDCAN_TXBCR register *********************/
5141 #define FDCAN_TXBCR_CR_Pos (0U)
5142 #define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)
5143 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk
5145 /***************** Bit definition for FDCAN_TXBTO register *********************/
5146 #define FDCAN_TXBTO_TO_Pos (0U)
5147 #define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)
5148 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk
5150 /***************** Bit definition for FDCAN_TXBCF register *********************/
5151 #define FDCAN_TXBCF_CF_Pos (0U)
5152 #define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)
5153 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk
5155 /***************** Bit definition for FDCAN_TXBTIE register ********************/
5156 #define FDCAN_TXBTIE_TIE_Pos (0U)
5157 #define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)
5158 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk
5160 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
5161 #define FDCAN_TXBCIE_CFIE_Pos (0U)
5162 #define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)
5163 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk
5165 /***************** Bit definition for FDCAN_TXEFC register *********************/
5166 #define FDCAN_TXEFC_EFSA_Pos (2U)
5167 #define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)
5168 #define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk
5169 #define FDCAN_TXEFC_EFS_Pos (16U)
5170 #define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos)
5171 #define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk
5172 #define FDCAN_TXEFC_EFWM_Pos (24U)
5173 #define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos)
5174 #define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk
5176 /***************** Bit definition for FDCAN_TXEFS register *********************/
5177 #define FDCAN_TXEFS_EFFL_Pos (0U)
5178 #define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos)
5179 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk
5180 #define FDCAN_TXEFS_EFGI_Pos (8U)
5181 #define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos)
5182 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk
5183 #define FDCAN_TXEFS_EFPI_Pos (16U)
5184 #define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos)
5185 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk
5186 #define FDCAN_TXEFS_EFF_Pos (24U)
5187 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)
5188 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk
5189 #define FDCAN_TXEFS_TEFL_Pos (25U)
5190 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)
5191 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk
5193 /***************** Bit definition for FDCAN_TXEFA register *********************/
5194 #define FDCAN_TXEFA_EFAI_Pos (0U)
5195 #define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos)
5196 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk
5198 /***************** Bit definition for FDCAN_TTTMC register *********************/
5199 #define FDCAN_TTTMC_TMSA_Pos (2U)
5200 #define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)
5201 #define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk
5202 #define FDCAN_TTTMC_TME_Pos (16U)
5203 #define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos)
5204 #define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk
5206 /***************** Bit definition for FDCAN_TTRMC register *********************/
5207 #define FDCAN_TTRMC_RID_Pos (0U)
5208 #define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)
5209 #define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk
5210 #define FDCAN_TTRMC_XTD_Pos (30U)
5211 #define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos)
5212 #define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk
5213 #define FDCAN_TTRMC_RMPS_Pos (31U)
5214 #define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos)
5215 #define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk
5217 /***************** Bit definition for FDCAN_TTOCF register *********************/
5218 #define FDCAN_TTOCF_OM_Pos (0U)
5219 #define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos)
5220 #define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk
5221 #define FDCAN_TTOCF_GEN_Pos (3U)
5222 #define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos)
5223 #define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk
5224 #define FDCAN_TTOCF_TM_Pos (4U)
5225 #define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos)
5226 #define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk
5227 #define FDCAN_TTOCF_LDSDL_Pos (5U)
5228 #define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos)
5229 #define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk
5230 #define FDCAN_TTOCF_IRTO_Pos (8U)
5231 #define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos)
5232 #define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk
5233 #define FDCAN_TTOCF_EECS_Pos (15U)
5234 #define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos)
5235 #define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk
5236 #define FDCAN_TTOCF_AWL_Pos (16U)
5237 #define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos)
5238 #define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk
5239 #define FDCAN_TTOCF_EGTF_Pos (24U)
5240 #define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos)
5241 #define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk
5242 #define FDCAN_TTOCF_ECC_Pos (25U)
5243 #define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos)
5244 #define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk
5245 #define FDCAN_TTOCF_EVTP_Pos (26U)
5246 #define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos)
5247 #define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk
5249 /***************** Bit definition for FDCAN_TTMLM register *********************/
5250 #define FDCAN_TTMLM_CCM_Pos (0U)
5251 #define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos)
5252 #define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk
5253 #define FDCAN_TTMLM_CSS_Pos (6U)
5254 #define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos)
5255 #define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk
5256 #define FDCAN_TTMLM_TXEW_Pos (8U)
5257 #define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos)
5258 #define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk
5259 #define FDCAN_TTMLM_ENTT_Pos (16U)
5260 #define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)
5261 #define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk
5263 /***************** Bit definition for FDCAN_TURCF register *********************/
5264 #define FDCAN_TURCF_NCL_Pos (0U)
5265 #define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos)
5266 #define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk
5267 #define FDCAN_TURCF_DC_Pos (16U)
5268 #define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos)
5269 #define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk
5270 #define FDCAN_TURCF_ELT_Pos (31U)
5271 #define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos)
5272 #define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk
5274 /***************** Bit definition for FDCAN_TTOCN register ********************/
5275 #define FDCAN_TTOCN_SGT_Pos (0U)
5276 #define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos)
5277 #define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk
5278 #define FDCAN_TTOCN_ECS_Pos (1U)
5279 #define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos)
5280 #define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk
5281 #define FDCAN_TTOCN_SWP_Pos (2U)
5282 #define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos)
5283 #define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk
5284 #define FDCAN_TTOCN_SWS_Pos (3U)
5285 #define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos)
5286 #define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk
5287 #define FDCAN_TTOCN_RTIE_Pos (5U)
5288 #define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos)
5289 #define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk
5290 #define FDCAN_TTOCN_TMC_Pos (6U)
5291 #define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos)
5292 #define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk
5293 #define FDCAN_TTOCN_TTIE_Pos (8U)
5294 #define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos)
5295 #define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk
5296 #define FDCAN_TTOCN_GCS_Pos (9U)
5297 #define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos)
5298 #define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk
5299 #define FDCAN_TTOCN_FGP_Pos (10U)
5300 #define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos)
5301 #define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk
5302 #define FDCAN_TTOCN_TMG_Pos (11U)
5303 #define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos)
5304 #define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk
5305 #define FDCAN_TTOCN_NIG_Pos (12U)
5306 #define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos)
5307 #define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk
5308 #define FDCAN_TTOCN_ESCN_Pos (13U)
5309 #define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos)
5310 #define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk
5311 #define FDCAN_TTOCN_LCKC_Pos (15U)
5312 #define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos)
5313 #define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk
5315 /***************** Bit definition for FDCAN_TTGTP register ********************/
5316 #define FDCAN_TTGTP_TP_Pos (0U)
5317 #define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos)
5318 #define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk
5319 #define FDCAN_TTGTP_CTP_Pos (16U)
5320 #define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)
5321 #define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk
5323 /***************** Bit definition for FDCAN_TTTMK register ********************/
5324 #define FDCAN_TTTMK_TM_Pos (0U)
5325 #define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos)
5326 #define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk
5327 #define FDCAN_TTTMK_TICC_Pos (16U)
5328 #define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos)
5329 #define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk
5330 #define FDCAN_TTTMK_LCKM_Pos (31U)
5331 #define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos)
5332 #define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk
5334 /***************** Bit definition for FDCAN_TTIR register ********************/
5335 #define FDCAN_TTIR_SBC_Pos (0U)
5336 #define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos)
5337 #define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk
5338 #define FDCAN_TTIR_SMC_Pos (1U)
5339 #define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos)
5340 #define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk
5341 #define FDCAN_TTIR_CSM_Pos (2U)
5342 #define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos)
5343 #define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk
5344 #define FDCAN_TTIR_SOG_Pos (3U)
5345 #define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos)
5346 #define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk
5347 #define FDCAN_TTIR_RTMI_Pos (4U)
5348 #define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos)
5349 #define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk
5350 #define FDCAN_TTIR_TTMI_Pos (5U)
5351 #define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos)
5352 #define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk
5353 #define FDCAN_TTIR_SWE_Pos (6U)
5354 #define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos)
5355 #define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk
5356 #define FDCAN_TTIR_GTW_Pos (7U)
5357 #define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos)
5358 #define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk
5359 #define FDCAN_TTIR_GTD_Pos (8U)
5360 #define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos)
5361 #define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk
5362 #define FDCAN_TTIR_GTE_Pos (9U)
5363 #define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos)
5364 #define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk
5365 #define FDCAN_TTIR_TXU_Pos (10U)
5366 #define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos)
5367 #define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk
5368 #define FDCAN_TTIR_TXO_Pos (11U)
5369 #define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos)
5370 #define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk
5371 #define FDCAN_TTIR_SE1_Pos (12U)
5372 #define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos)
5373 #define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk
5374 #define FDCAN_TTIR_SE2_Pos (13U)
5375 #define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos)
5376 #define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk
5377 #define FDCAN_TTIR_ELC_Pos (14U)
5378 #define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos)
5379 #define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk
5380 #define FDCAN_TTIR_IWT_Pos (15U)
5381 #define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos)
5382 #define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk
5383 #define FDCAN_TTIR_WT_Pos (16U)
5384 #define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos)
5385 #define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk
5386 #define FDCAN_TTIR_AW_Pos (17U)
5387 #define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos)
5388 #define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk
5389 #define FDCAN_TTIR_CER_Pos (18U)
5390 #define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos)
5391 #define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk
5393 /***************** Bit definition for FDCAN_TTIE register ********************/
5394 #define FDCAN_TTIE_SBCE_Pos (0U)
5395 #define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos)
5396 #define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk
5397 #define FDCAN_TTIE_SMCE_Pos (1U)
5398 #define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos)
5399 #define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk
5400 #define FDCAN_TTIE_CSME_Pos (2U)
5401 #define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos)
5402 #define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk
5403 #define FDCAN_TTIE_SOGE_Pos (3U)
5404 #define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos)
5405 #define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk
5406 #define FDCAN_TTIE_RTMIE_Pos (4U)
5407 #define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos)
5408 #define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk
5409 #define FDCAN_TTIE_TTMIE_Pos (5U)
5410 #define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos)
5411 #define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk
5412 #define FDCAN_TTIE_SWEE_Pos (6U)
5413 #define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos)
5414 #define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk
5415 #define FDCAN_TTIE_GTWE_Pos (7U)
5416 #define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos)
5417 #define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk
5418 #define FDCAN_TTIE_GTDE_Pos (8U)
5419 #define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos)
5420 #define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk
5421 #define FDCAN_TTIE_GTEE_Pos (9U)
5422 #define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos)
5423 #define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk
5424 #define FDCAN_TTIE_TXUE_Pos (10U)
5425 #define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos)
5426 #define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk
5427 #define FDCAN_TTIE_TXOE_Pos (11U)
5428 #define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos)
5429 #define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk
5430 #define FDCAN_TTIE_SE1E_Pos (12U)
5431 #define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos)
5432 #define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk
5433 #define FDCAN_TTIE_SE2E_Pos (13U)
5434 #define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos)
5435 #define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk
5436 #define FDCAN_TTIE_ELCE_Pos (14U)
5437 #define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos)
5438 #define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk
5439 #define FDCAN_TTIE_IWTE_Pos (15U)
5440 #define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos)
5441 #define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk
5442 #define FDCAN_TTIE_WTE_Pos (16U)
5443 #define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos)
5444 #define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk
5445 #define FDCAN_TTIE_AWE_Pos (17U)
5446 #define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos)
5447 #define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk
5448 #define FDCAN_TTIE_CERE_Pos (18U)
5449 #define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos)
5450 #define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk
5452 /***************** Bit definition for FDCAN_TTILS register ********************/
5453 #define FDCAN_TTILS_SBCS_Pos (0U)
5454 #define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos)
5455 #define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk
5456 #define FDCAN_TTILS_SMCS_Pos (1U)
5457 #define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos)
5458 #define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk
5459 #define FDCAN_TTILS_CSMS_Pos (2U)
5460 #define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos)
5461 #define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk
5462 #define FDCAN_TTILS_SOGS_Pos (3U)
5463 #define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos)
5464 #define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk
5465 #define FDCAN_TTILS_RTMIS_Pos (4U)
5466 #define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos)
5467 #define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk
5468 #define FDCAN_TTILS_TTMIS_Pos (5U)
5469 #define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos)
5470 #define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk
5471 #define FDCAN_TTILS_SWES_Pos (6U)
5472 #define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos)
5473 #define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk
5474 #define FDCAN_TTILS_GTWS_Pos (7U)
5475 #define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos)
5476 #define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk
5477 #define FDCAN_TTILS_GTDS_Pos (8U)
5478 #define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos)
5479 #define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk
5480 #define FDCAN_TTILS_GTES_Pos (9U)
5481 #define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos)
5482 #define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk
5483 #define FDCAN_TTILS_TXUS_Pos (10U)
5484 #define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos)
5485 #define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk
5486 #define FDCAN_TTILS_TXOS_Pos (11U)
5487 #define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos)
5488 #define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk
5489 #define FDCAN_TTILS_SE1S_Pos (12U)
5490 #define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos)
5491 #define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk
5492 #define FDCAN_TTILS_SE2S_Pos (13U)
5493 #define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos)
5494 #define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk
5495 #define FDCAN_TTILS_ELCS_Pos (14U)
5496 #define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos)
5497 #define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk
5498 #define FDCAN_TTILS_IWTS_Pos (15U)
5499 #define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos)
5500 #define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk
5501 #define FDCAN_TTILS_WTS_Pos (16U)
5502 #define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos)
5503 #define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk
5504 #define FDCAN_TTILS_AWS_Pos (17U)
5505 #define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos)
5506 #define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk
5507 #define FDCAN_TTILS_CERS_Pos (18U)
5508 #define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos)
5509 #define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk
5511 /***************** Bit definition for FDCAN_TTOST register ********************/
5512 #define FDCAN_TTOST_EL_Pos (0U)
5513 #define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos)
5514 #define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk
5515 #define FDCAN_TTOST_MS_Pos (2U)
5516 #define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos)
5517 #define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk
5518 #define FDCAN_TTOST_SYS_Pos (4U)
5519 #define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos)
5520 #define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk
5521 #define FDCAN_TTOST_QGTP_Pos (6U)
5522 #define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos)
5523 #define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk
5524 #define FDCAN_TTOST_QCS_Pos (7U)
5525 #define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos)
5526 #define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk
5527 #define FDCAN_TTOST_RTO_Pos (8U)
5528 #define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos)
5529 #define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk
5530 #define FDCAN_TTOST_WGTD_Pos (22U)
5531 #define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos)
5532 #define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk
5533 #define FDCAN_TTOST_GFI_Pos (23U)
5534 #define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos)
5535 #define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk
5536 #define FDCAN_TTOST_TMP_Pos (24U)
5537 #define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos)
5538 #define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk
5539 #define FDCAN_TTOST_GSI_Pos (27U)
5540 #define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos)
5541 #define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk
5542 #define FDCAN_TTOST_WFE_Pos (28U)
5543 #define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos)
5544 #define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk
5545 #define FDCAN_TTOST_AWE_Pos (29U)
5546 #define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos)
5547 #define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk
5548 #define FDCAN_TTOST_WECS_Pos (30U)
5549 #define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos)
5550 #define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk
5551 #define FDCAN_TTOST_SPL_Pos (31U)
5552 #define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos)
5553 #define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk
5555 /***************** Bit definition for FDCAN_TURNA register ********************/
5556 #define FDCAN_TURNA_NAV_Pos (0U)
5557 #define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)
5558 #define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk
5560 /***************** Bit definition for FDCAN_TTLGT register ********************/
5561 #define FDCAN_TTLGT_LT_Pos (0U)
5562 #define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos)
5563 #define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk
5564 #define FDCAN_TTLGT_GT_Pos (16U)
5565 #define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos)
5566 #define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk
5568 /***************** Bit definition for FDCAN_TTCTC register ********************/
5569 #define FDCAN_TTCTC_CT_Pos (0U)
5570 #define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos)
5571 #define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk
5572 #define FDCAN_TTCTC_CC_Pos (16U)
5573 #define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos)
5574 #define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk
5576 /***************** Bit definition for FDCAN_TTCPT register ********************/
5577 #define FDCAN_TTCPT_CCV_Pos (0U)
5578 #define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos)
5579 #define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk
5580 #define FDCAN_TTCPT_SWV_Pos (16U)
5581 #define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)
5582 #define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk
5584 /***************** Bit definition for FDCAN_TTCSM register ********************/
5585 #define FDCAN_TTCSM_CSM_Pos (0U)
5586 #define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)
5587 #define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk
5589 /***************** Bit definition for FDCAN_TTTS register *********************/
5590 #define FDCAN_TTTS_SWTSEL_Pos (0U)
5591 #define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos)
5592 #define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk
5593 #define FDCAN_TTTS_EVTSEL_Pos (4U)
5594 #define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos)
5595 #define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk
5597 /********************************************************************************/
5598 /* */
5599 /* FDCANCCU (Clock Calibration unit) */
5600 /* */
5601 /********************************************************************************/
5602 
5603 /***************** Bit definition for FDCANCCU_CREL register ******************/
5604 #define FDCANCCU_CREL_DAY_Pos (0U)
5605 #define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos)
5606 #define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk
5607 #define FDCANCCU_CREL_MON_Pos (8U)
5608 #define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos)
5609 #define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk
5610 #define FDCANCCU_CREL_YEAR_Pos (16U)
5611 #define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos)
5612 #define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk
5613 #define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5614 #define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)
5615 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk
5616 #define FDCANCCU_CREL_STEP_Pos (24U)
5617 #define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos)
5618 #define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk
5619 #define FDCANCCU_CREL_REL_Pos (28U)
5620 #define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos)
5621 #define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk
5623 /***************** Bit definition for FDCANCCU_CCFG register ******************/
5624 #define FDCANCCU_CCFG_TQBT_Pos (0U)
5625 #define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)
5626 #define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk
5627 #define FDCANCCU_CCFG_BCC_Pos (6U)
5628 #define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos)
5629 #define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk
5630 #define FDCANCCU_CCFG_CFL_Pos (7U)
5631 #define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos)
5632 #define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk
5633 #define FDCANCCU_CCFG_OCPM_Pos (8U)
5634 #define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)
5635 #define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk
5636 #define FDCANCCU_CCFG_CDIV_Pos (16U)
5637 #define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos)
5638 #define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk
5639 #define FDCANCCU_CCFG_SWR_Pos (31U)
5640 #define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos)
5641 #define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk
5643 /***************** Bit definition for FDCANCCU_CSTAT register *****************/
5644 #define FDCANCCU_CSTAT_OCPC_Pos (0U)
5645 #define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)
5646 #define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk
5647 #define FDCANCCU_CSTAT_TQC_Pos (18U)
5648 #define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)
5649 #define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk
5650 #define FDCANCCU_CSTAT_CALS_Pos (30U)
5651 #define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos)
5652 #define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk
5654 /****************** Bit definition for FDCANCCU_CWD register ******************/
5655 #define FDCANCCU_CWD_WDC_Pos (0U)
5656 #define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)
5657 #define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk
5658 #define FDCANCCU_CWD_WDV_Pos (16U)
5659 #define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)
5660 #define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk
5662 /****************** Bit definition for FDCANCCU_IR register *******************/
5663 #define FDCANCCU_IR_CWE_Pos (0U)
5664 #define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos)
5665 #define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk
5666 #define FDCANCCU_IR_CSC_Pos (1U)
5667 #define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos)
5668 #define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk
5670 /****************** Bit definition for FDCANCCU_IE register *******************/
5671 #define FDCANCCU_IE_CWEE_Pos (0U)
5672 #define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos)
5673 #define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk
5674 #define FDCANCCU_IE_CSCE_Pos (1U)
5675 #define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos)
5676 #define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk
5678 /******************************************************************************/
5679 /* */
5680 /* HDMI-CEC (CEC) */
5681 /* */
5682 /******************************************************************************/
5683 
5684 /******************* Bit definition for CEC_CR register *********************/
5685 #define CEC_CR_CECEN_Pos (0U)
5686 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5687 #define CEC_CR_CECEN CEC_CR_CECEN_Msk
5688 #define CEC_CR_TXSOM_Pos (1U)
5689 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5690 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5691 #define CEC_CR_TXEOM_Pos (2U)
5692 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5693 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5695 /******************* Bit definition for CEC_CFGR register *******************/
5696 #define CEC_CFGR_SFT_Pos (0U)
5697 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5698 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5699 #define CEC_CFGR_RXTOL_Pos (3U)
5700 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5701 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5702 #define CEC_CFGR_BRESTP_Pos (4U)
5703 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5704 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5705 #define CEC_CFGR_BREGEN_Pos (5U)
5706 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5707 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5708 #define CEC_CFGR_LBPEGEN_Pos (6U)
5709 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5710 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5711 #define CEC_CFGR_SFTOPT_Pos (8U)
5712 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5713 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5714 #define CEC_CFGR_BRDNOGEN_Pos (7U)
5715 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5716 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5717 #define CEC_CFGR_OAR_Pos (16U)
5718 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5719 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5720 #define CEC_CFGR_LSTN_Pos (31U)
5721 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5722 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5724 /******************* Bit definition for CEC_TXDR register *******************/
5725 #define CEC_TXDR_TXD_Pos (0U)
5726 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5727 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5729 /******************* Bit definition for CEC_RXDR register *******************/
5730 #define CEC_RXDR_RXD_Pos (0U)
5731 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos)
5732 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5734 /******************* Bit definition for CEC_ISR register ********************/
5735 #define CEC_ISR_RXBR_Pos (0U)
5736 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5737 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5738 #define CEC_ISR_RXEND_Pos (1U)
5739 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5740 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5741 #define CEC_ISR_RXOVR_Pos (2U)
5742 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5743 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5744 #define CEC_ISR_BRE_Pos (3U)
5745 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5746 #define CEC_ISR_BRE CEC_ISR_BRE_Msk
5747 #define CEC_ISR_SBPE_Pos (4U)
5748 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5749 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5750 #define CEC_ISR_LBPE_Pos (5U)
5751 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5752 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5753 #define CEC_ISR_RXACKE_Pos (6U)
5754 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5755 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5756 #define CEC_ISR_ARBLST_Pos (7U)
5757 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5758 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5759 #define CEC_ISR_TXBR_Pos (8U)
5760 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5761 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5762 #define CEC_ISR_TXEND_Pos (9U)
5763 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5764 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5765 #define CEC_ISR_TXUDR_Pos (10U)
5766 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5767 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5768 #define CEC_ISR_TXERR_Pos (11U)
5769 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5770 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5771 #define CEC_ISR_TXACKE_Pos (12U)
5772 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5773 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5775 /******************* Bit definition for CEC_IER register ********************/
5776 #define CEC_IER_RXBRIE_Pos (0U)
5777 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5778 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5779 #define CEC_IER_RXENDIE_Pos (1U)
5780 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5781 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5782 #define CEC_IER_RXOVRIE_Pos (2U)
5783 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5784 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5785 #define CEC_IER_BREIE_Pos (3U)
5786 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5787 #define CEC_IER_BREIE CEC_IER_BREIE_Msk
5788 #define CEC_IER_SBPEIE_Pos (4U)
5789 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5790 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5791 #define CEC_IER_LBPEIE_Pos (5U)
5792 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5793 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5794 #define CEC_IER_RXACKEIE_Pos (6U)
5795 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5796 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5797 #define CEC_IER_ARBLSTIE_Pos (7U)
5798 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5799 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5800 #define CEC_IER_TXBRIE_Pos (8U)
5801 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5802 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5803 #define CEC_IER_TXENDIE_Pos (9U)
5804 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5805 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5806 #define CEC_IER_TXUDRIE_Pos (10U)
5807 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5808 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5809 #define CEC_IER_TXERRIE_Pos (11U)
5810 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5811 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5812 #define CEC_IER_TXACKEIE_Pos (12U)
5813 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5814 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5816 /******************************************************************************/
5817 /* */
5818 /* CORDIC calculation unit */
5819 /* */
5820 /******************************************************************************/
5821 /******************* Bit definition for CORDIC_CSR register *****************/
5822 #define CORDIC_CSR_FUNC_Pos (0U)
5823 #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos)
5824 #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk
5825 #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos)
5826 #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos)
5827 #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos)
5828 #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos)
5829 #define CORDIC_CSR_PRECISION_Pos (4U)
5830 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)
5831 #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk
5832 #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos)
5833 #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos)
5834 #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos)
5835 #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos)
5836 #define CORDIC_CSR_SCALE_Pos (8U)
5837 #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos)
5838 #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk
5839 #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos)
5840 #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos)
5841 #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos)
5842 #define CORDIC_CSR_IEN_Pos (16U)
5843 #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos)
5844 #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk
5845 #define CORDIC_CSR_DMAREN_Pos (17U)
5846 #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos)
5847 #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk
5848 #define CORDIC_CSR_DMAWEN_Pos (18U)
5849 #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos)
5850 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk
5851 #define CORDIC_CSR_NRES_Pos (19U)
5852 #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos)
5853 #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk
5854 #define CORDIC_CSR_NARGS_Pos (20U)
5855 #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos)
5856 #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk
5857 #define CORDIC_CSR_RESSIZE_Pos (21U)
5858 #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos)
5859 #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk
5860 #define CORDIC_CSR_ARGSIZE_Pos (22U)
5861 #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos)
5862 #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk
5863 #define CORDIC_CSR_RRDY_Pos (31U)
5864 #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos)
5865 #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk
5867 /******************* Bit definition for CORDIC_WDATA register ***************/
5868 #define CORDIC_WDATA_ARG_Pos (0U)
5869 #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)
5870 #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk
5872 /******************* Bit definition for CORDIC_RDATA register ***************/
5873 #define CORDIC_RDATA_RES_Pos (0U)
5874 #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)
5875 #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk
5877 /******************************************************************************/
5878 /* */
5879 /* CRC calculation unit */
5880 /* */
5881 /******************************************************************************/
5882 /******************* Bit definition for CRC_DR register *********************/
5883 #define CRC_DR_DR_Pos (0U)
5884 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5885 #define CRC_DR_DR CRC_DR_DR_Msk
5887 /******************* Bit definition for CRC_IDR register ********************/
5888 #define CRC_IDR_IDR_Pos (0U)
5889 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)
5890 #define CRC_IDR_IDR CRC_IDR_IDR_Msk
5892 /******************** Bit definition for CRC_CR register ********************/
5893 #define CRC_CR_RESET_Pos (0U)
5894 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5895 #define CRC_CR_RESET CRC_CR_RESET_Msk
5896 #define CRC_CR_POLYSIZE_Pos (3U)
5897 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5898 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5899 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5900 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5901 #define CRC_CR_REV_IN_Pos (5U)
5902 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5903 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5904 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5905 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5906 #define CRC_CR_REV_OUT_Pos (7U)
5907 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5908 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5910 /******************* Bit definition for CRC_INIT register *******************/
5911 #define CRC_INIT_INIT_Pos (0U)
5912 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5913 #define CRC_INIT_INIT CRC_INIT_INIT_Msk
5915 /******************* Bit definition for CRC_POL register ********************/
5916 #define CRC_POL_POL_Pos (0U)
5917 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5918 #define CRC_POL_POL CRC_POL_POL_Msk
5920 /******************************************************************************/
5921 /* */
5922 /* CRS Clock Recovery System */
5923 /******************************************************************************/
5924 
5925 /******************* Bit definition for CRS_CR register *********************/
5926 #define CRS_CR_SYNCOKIE_Pos (0U)
5927 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
5928 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
5929 #define CRS_CR_SYNCWARNIE_Pos (1U)
5930 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
5931 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
5932 #define CRS_CR_ERRIE_Pos (2U)
5933 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
5934 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
5935 #define CRS_CR_ESYNCIE_Pos (3U)
5936 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
5937 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
5938 #define CRS_CR_CEN_Pos (5U)
5939 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
5940 #define CRS_CR_CEN CRS_CR_CEN_Msk
5941 #define CRS_CR_AUTOTRIMEN_Pos (6U)
5942 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
5943 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
5944 #define CRS_CR_SWSYNC_Pos (7U)
5945 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
5946 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
5947 #define CRS_CR_TRIM_Pos (8U)
5948 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos)
5949 #define CRS_CR_TRIM CRS_CR_TRIM_Msk
5951 /******************* Bit definition for CRS_CFGR register *********************/
5952 #define CRS_CFGR_RELOAD_Pos (0U)
5953 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
5954 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
5955 #define CRS_CFGR_FELIM_Pos (16U)
5956 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
5957 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
5959 #define CRS_CFGR_SYNCDIV_Pos (24U)
5960 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
5961 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
5962 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
5963 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
5964 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
5966 #define CRS_CFGR_SYNCSRC_Pos (28U)
5967 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
5968 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
5969 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
5970 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
5972 #define CRS_CFGR_SYNCPOL_Pos (31U)
5973 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
5974 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
5976 /******************* Bit definition for CRS_ISR register *********************/
5977 #define CRS_ISR_SYNCOKF_Pos (0U)
5978 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
5979 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
5980 #define CRS_ISR_SYNCWARNF_Pos (1U)
5981 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
5982 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
5983 #define CRS_ISR_ERRF_Pos (2U)
5984 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
5985 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
5986 #define CRS_ISR_ESYNCF_Pos (3U)
5987 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
5988 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
5989 #define CRS_ISR_SYNCERR_Pos (8U)
5990 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
5991 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
5992 #define CRS_ISR_SYNCMISS_Pos (9U)
5993 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
5994 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
5995 #define CRS_ISR_TRIMOVF_Pos (10U)
5996 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
5997 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
5998 #define CRS_ISR_FEDIR_Pos (15U)
5999 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
6000 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
6001 #define CRS_ISR_FECAP_Pos (16U)
6002 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
6003 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
6005 /******************* Bit definition for CRS_ICR register *********************/
6006 #define CRS_ICR_SYNCOKC_Pos (0U)
6007 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
6008 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
6009 #define CRS_ICR_SYNCWARNC_Pos (1U)
6010 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
6011 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
6012 #define CRS_ICR_ERRC_Pos (2U)
6013 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
6014 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
6015 #define CRS_ICR_ESYNCC_Pos (3U)
6016 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
6017 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
6019 /******************************************************************************/
6020 /* */
6021 /* Crypto Processor */
6022 /* */
6023 /******************************************************************************/
6024 /******************************** CRYP VER **********************************/
6025 #define CRYP_VER_2_2
6026 /******************* Bits definition for CRYP_CR register ********************/
6027 #define CRYP_CR_ALGODIR_Pos (2U)
6028 #define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos)
6029 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
6030 
6031 #define CRYP_CR_ALGOMODE_Pos (3U)
6032 #define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos)
6033 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
6034 #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos)
6035 #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos)
6036 #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos)
6037 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
6038 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
6039 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos)
6040 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
6041 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
6042 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos)
6043 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
6044 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
6045 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos)
6046 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
6047 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
6048 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)
6049 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
6050 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
6051 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)
6052 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
6053 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
6054 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)
6055 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
6056 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
6057 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)
6058 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
6059 #define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
6060 #define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)
6061 #define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
6062 #define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
6063 #define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos)
6064 #define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
6065 
6066 #define CRYP_CR_DATATYPE_Pos (6U)
6067 #define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos)
6068 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
6069 #define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos)
6070 #define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos)
6071 #define CRYP_CR_KEYSIZE_Pos (8U)
6072 #define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos)
6073 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
6074 #define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos)
6075 #define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos)
6076 #define CRYP_CR_FFLUSH_Pos (14U)
6077 #define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos)
6078 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
6079 #define CRYP_CR_CRYPEN_Pos (15U)
6080 #define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos)
6081 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
6082 
6083 #define CRYP_CR_GCM_CCMPH_Pos (16U)
6084 #define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos)
6085 #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
6086 #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos)
6087 #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos)
6088 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
6089 #define CRYP_CR_NPBLB_Pos (20U)
6090 #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos)
6091 #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
6092 
6093 /****************** Bits definition for CRYP_SR register *********************/
6094 #define CRYP_SR_IFEM_Pos (0U)
6095 #define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos)
6096 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
6097 #define CRYP_SR_IFNF_Pos (1U)
6098 #define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos)
6099 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
6100 #define CRYP_SR_OFNE_Pos (2U)
6101 #define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos)
6102 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
6103 #define CRYP_SR_OFFU_Pos (3U)
6104 #define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos)
6105 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
6106 #define CRYP_SR_BUSY_Pos (4U)
6107 #define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos)
6108 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
6109 /****************** Bits definition for CRYP_DMACR register ******************/
6110 #define CRYP_DMACR_DIEN_Pos (0U)
6111 #define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos)
6112 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
6113 #define CRYP_DMACR_DOEN_Pos (1U)
6114 #define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos)
6115 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
6116 /***************** Bits definition for CRYP_IMSCR register ******************/
6117 #define CRYP_IMSCR_INIM_Pos (0U)
6118 #define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos)
6119 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
6120 #define CRYP_IMSCR_OUTIM_Pos (1U)
6121 #define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos)
6122 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
6123 /****************** Bits definition for CRYP_RISR register *******************/
6124 #define CRYP_RISR_INRIS_Pos (0U)
6125 #define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos)
6126 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
6127 #define CRYP_RISR_OUTRIS_Pos (1U)
6128 #define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos)
6129 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
6130 /****************** Bits definition for CRYP_MISR register *******************/
6131 #define CRYP_MISR_INMIS_Pos (0U)
6132 #define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos)
6133 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
6134 #define CRYP_MISR_OUTMIS_Pos (1U)
6135 #define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos)
6136 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
6137 
6138 /******************************************************************************/
6139 /* */
6140 /* Digital to Analog Converter */
6141 /* */
6142 /******************************************************************************/
6143 /******************** Bit definition for DAC_CR register ********************/
6144 #define DAC_CR_EN1_Pos (0U)
6145 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
6146 #define DAC_CR_EN1 DAC_CR_EN1_Msk
6147 #define DAC_CR_TEN1_Pos (1U)
6148 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
6149 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk
6151 #define DAC_CR_TSEL1_Pos (2U)
6152 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)
6153 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
6154 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
6155 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
6156 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
6157 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)
6160 #define DAC_CR_WAVE1_Pos (6U)
6161 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
6162 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
6163 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
6164 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
6166 #define DAC_CR_MAMP1_Pos (8U)
6167 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
6168 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
6169 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
6170 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
6171 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
6172 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
6174 #define DAC_CR_DMAEN1_Pos (12U)
6175 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
6176 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
6177 #define DAC_CR_DMAUDRIE1_Pos (13U)
6178 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
6179 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
6180 #define DAC_CR_CEN1_Pos (14U)
6181 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
6182 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk
6184 #define DAC_CR_EN2_Pos (16U)
6185 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
6186 #define DAC_CR_EN2 DAC_CR_EN2_Msk
6187 #define DAC_CR_TEN2_Pos (17U)
6188 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
6189 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk
6191 #define DAC_CR_TSEL2_Pos (18U)
6192 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)
6193 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
6194 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
6195 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
6196 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
6197 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)
6200 #define DAC_CR_WAVE2_Pos (22U)
6201 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
6202 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
6203 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
6204 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
6206 #define DAC_CR_MAMP2_Pos (24U)
6207 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
6208 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
6209 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
6210 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
6211 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
6212 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
6214 #define DAC_CR_DMAEN2_Pos (28U)
6215 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
6216 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
6217 #define DAC_CR_DMAUDRIE2_Pos (29U)
6218 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
6219 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
6220 #define DAC_CR_CEN2_Pos (30U)
6221 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
6222 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk
6224 /***************** Bit definition for DAC_SWTRIGR register ******************/
6225 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6226 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
6227 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
6228 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6229 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
6230 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
6232 /***************** Bit definition for DAC_DHR12R1 register ******************/
6233 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
6234 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
6235 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
6237 /***************** Bit definition for DAC_DHR12L1 register ******************/
6238 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
6239 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
6240 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
6242 /****************** Bit definition for DAC_DHR8R1 register ******************/
6243 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
6244 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
6245 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
6247 /***************** Bit definition for DAC_DHR12R2 register ******************/
6248 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
6249 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
6250 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
6252 /***************** Bit definition for DAC_DHR12L2 register ******************/
6253 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
6254 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
6255 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
6257 /****************** Bit definition for DAC_DHR8R2 register ******************/
6258 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
6259 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
6260 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
6262 /***************** Bit definition for DAC_DHR12RD register ******************/
6263 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
6264 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6265 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6266 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
6267 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6268 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6270 /***************** Bit definition for DAC_DHR12LD register ******************/
6271 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
6272 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6273 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6274 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
6275 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6276 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6278 /****************** Bit definition for DAC_DHR8RD register ******************/
6279 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
6280 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6281 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6282 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
6283 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6284 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6286 /******************* Bit definition for DAC_DOR1 register *******************/
6287 #define DAC_DOR1_DACC1DOR_Pos (0U)
6288 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6289 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6291 /******************* Bit definition for DAC_DOR2 register *******************/
6292 #define DAC_DOR2_DACC2DOR_Pos (0U)
6293 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6294 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6296 /******************** Bit definition for DAC_SR register ********************/
6297 #define DAC_SR_DMAUDR1_Pos (13U)
6298 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6299 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6300 #define DAC_SR_CAL_FLAG1_Pos (14U)
6301 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
6302 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
6303 #define DAC_SR_BWST1_Pos (15U)
6304 #define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos)
6305 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk
6307 #define DAC_SR_DMAUDR2_Pos (29U)
6308 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6309 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6310 #define DAC_SR_CAL_FLAG2_Pos (30U)
6311 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
6312 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
6313 #define DAC_SR_BWST2_Pos (31U)
6314 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
6315 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk
6317 /******************* Bit definition for DAC_CCR register ********************/
6318 #define DAC_CCR_OTRIM1_Pos (0U)
6319 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
6320 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
6321 #define DAC_CCR_OTRIM2_Pos (16U)
6322 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
6323 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
6325 /******************* Bit definition for DAC_MCR register *******************/
6326 #define DAC_MCR_MODE1_Pos (0U)
6327 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6328 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6329 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6330 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6331 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6333 #define DAC_MCR_MODE2_Pos (16U)
6334 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6335 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6336 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6337 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6338 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6340 /****************** Bit definition for DAC_SHSR1 register ******************/
6341 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
6342 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6343 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6345 /****************** Bit definition for DAC_SHSR2 register ******************/
6346 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
6347 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6348 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6350 /****************** Bit definition for DAC_SHHR register ******************/
6351 #define DAC_SHHR_THOLD1_Pos (0U)
6352 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6353 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6354 #define DAC_SHHR_THOLD2_Pos (16U)
6355 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6356 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6358 /****************** Bit definition for DAC_SHRR register ******************/
6359 #define DAC_SHRR_TREFRESH1_Pos (0U)
6360 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6361 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6362 #define DAC_SHRR_TREFRESH2_Pos (16U)
6363 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6364 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6366 /******************************************************************************/
6367 /* */
6368 /* DCMI */
6369 /* */
6370 /******************************************************************************/
6371 /******************** Bits definition for DCMI_CR register ******************/
6372 #define DCMI_CR_CAPTURE_Pos (0U)
6373 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6374 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6375 #define DCMI_CR_CM_Pos (1U)
6376 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6377 #define DCMI_CR_CM DCMI_CR_CM_Msk
6378 #define DCMI_CR_CROP_Pos (2U)
6379 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6380 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
6381 #define DCMI_CR_JPEG_Pos (3U)
6382 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6383 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6384 #define DCMI_CR_ESS_Pos (4U)
6385 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6386 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
6387 #define DCMI_CR_PCKPOL_Pos (5U)
6388 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6389 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6390 #define DCMI_CR_HSPOL_Pos (6U)
6391 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6392 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6393 #define DCMI_CR_VSPOL_Pos (7U)
6394 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6395 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6396 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
6397 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
6398 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
6399 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
6400 #define DCMI_CR_CRE_Pos (12U)
6401 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
6402 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
6403 #define DCMI_CR_ENABLE_Pos (14U)
6404 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6405 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6406 #define DCMI_CR_BSM_Pos (16U)
6407 #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
6408 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
6409 #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
6410 #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
6411 #define DCMI_CR_OEBS_Pos (18U)
6412 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6413 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6414 #define DCMI_CR_LSM_Pos (19U)
6415 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6416 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
6417 #define DCMI_CR_OELS_Pos (20U)
6418 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6419 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
6420 
6421 /******************** Bits definition for DCMI_SR register ******************/
6422 #define DCMI_SR_HSYNC_Pos (0U)
6423 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6424 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6425 #define DCMI_SR_VSYNC_Pos (1U)
6426 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6427 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6428 #define DCMI_SR_FNE_Pos (2U)
6429 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6430 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
6431 
6432 /******************** Bits definition for DCMI_RIS register ****************/
6433 #define DCMI_RIS_FRAME_RIS_Pos (0U)
6434 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6435 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6436 #define DCMI_RIS_OVR_RIS_Pos (1U)
6437 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6438 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6439 #define DCMI_RIS_ERR_RIS_Pos (2U)
6440 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6441 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6442 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
6443 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6444 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6445 #define DCMI_RIS_LINE_RIS_Pos (4U)
6446 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6447 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6448 
6449 /******************** Bits definition for DCMI_IER register *****************/
6450 #define DCMI_IER_FRAME_IE_Pos (0U)
6451 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6452 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6453 #define DCMI_IER_OVR_IE_Pos (1U)
6454 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6455 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6456 #define DCMI_IER_ERR_IE_Pos (2U)
6457 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6458 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6459 #define DCMI_IER_VSYNC_IE_Pos (3U)
6460 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6461 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6462 #define DCMI_IER_LINE_IE_Pos (4U)
6463 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6464 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6465 
6466 
6467 /******************** Bits definition for DCMI_MIS register *****************/
6468 #define DCMI_MIS_FRAME_MIS_Pos (0U)
6469 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6470 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6471 #define DCMI_MIS_OVR_MIS_Pos (1U)
6472 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6473 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6474 #define DCMI_MIS_ERR_MIS_Pos (2U)
6475 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6476 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6477 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
6478 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6479 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6480 #define DCMI_MIS_LINE_MIS_Pos (4U)
6481 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6482 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6483 
6484 
6485 /******************** Bits definition for DCMI_ICR register *****************/
6486 #define DCMI_ICR_FRAME_ISC_Pos (0U)
6487 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6488 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6489 #define DCMI_ICR_OVR_ISC_Pos (1U)
6490 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6491 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6492 #define DCMI_ICR_ERR_ISC_Pos (2U)
6493 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6494 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6495 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
6496 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6497 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6498 #define DCMI_ICR_LINE_ISC_Pos (4U)
6499 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6500 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6501 
6502 
6503 /******************** Bits definition for DCMI_ESCR register ******************/
6504 #define DCMI_ESCR_FSC_Pos (0U)
6505 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6506 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6507 #define DCMI_ESCR_LSC_Pos (8U)
6508 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6509 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6510 #define DCMI_ESCR_LEC_Pos (16U)
6511 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6512 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6513 #define DCMI_ESCR_FEC_Pos (24U)
6514 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6515 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6516 
6517 /******************** Bits definition for DCMI_ESUR register ******************/
6518 #define DCMI_ESUR_FSU_Pos (0U)
6519 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6520 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6521 #define DCMI_ESUR_LSU_Pos (8U)
6522 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6523 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6524 #define DCMI_ESUR_LEU_Pos (16U)
6525 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6526 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6527 #define DCMI_ESUR_FEU_Pos (24U)
6528 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6529 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6530 
6531 /******************** Bits definition for DCMI_CWSTRT register ******************/
6532 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6533 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6534 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6535 #define DCMI_CWSTRT_VST_Pos (16U)
6536 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6537 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6538 
6539 /******************** Bits definition for DCMI_CWSIZE register ******************/
6540 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
6541 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6542 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6543 #define DCMI_CWSIZE_VLINE_Pos (16U)
6544 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6545 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6546 
6547 /******************** Bits definition for DCMI_DR register ******************/
6548 #define DCMI_DR_BYTE0_Pos (0U)
6549 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6550 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6551 #define DCMI_DR_BYTE1_Pos (8U)
6552 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6553 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6554 #define DCMI_DR_BYTE2_Pos (16U)
6555 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6556 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6557 #define DCMI_DR_BYTE3_Pos (24U)
6558 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6559 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6560 
6561 /******************************************************************************/
6562 /* */
6563 /* Digital Filter for Sigma Delta Modulators */
6564 /* */
6565 /******************************************************************************/
6566 
6567 /**************** DFSDM channel configuration registers ********************/
6568 
6569 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6570 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6571 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6572 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6573 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6574 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6575 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6576 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6577 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6578 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6579 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6580 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6581 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6582 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6583 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6584 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6585 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6586 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6587 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6588 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6589 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6590 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6591 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6592 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
6593 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6594 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6595 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6596 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6597 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6598 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6599 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6600 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6601 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6602 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6603 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6604 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6605 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6606 #define DFSDM_CHCFGR1_SITP_Pos (0U)
6607 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6608 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6609 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6610 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6612 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6613 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6614 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6615 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6616 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6617 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6618 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6620 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6621 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6622 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6623 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6624 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6625 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6626 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6627 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6628 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6629 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6630 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6631 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6632 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6633 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6634 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6636 /**************** Bit definition for DFSDM_CHWDATR register *******************/
6637 #define DFSDM_CHWDATR_WDATA_Pos (0U)
6638 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6639 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6641 /**************** Bit definition for DFSDM_CHDATINR register *****************/
6642 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
6643 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6644 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6645 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
6646 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6647 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6649 /************************ DFSDM module registers ****************************/
6650 
6651 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
6652 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6653 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6654 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6655 #define DFSDM_FLTCR1_FAST_Pos (29U)
6656 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6657 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6658 #define DFSDM_FLTCR1_RCH_Pos (24U)
6659 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6660 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6661 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6662 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6663 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6664 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6665 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6666 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6667 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6668 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6669 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6670 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6671 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6672 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6673 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6674 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6675 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6676 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6677 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6678 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6679 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)
6680 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6681 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6682 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6683 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6684 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6685 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6687 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6688 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6689 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6690 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6691 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6692 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6693 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6694 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6695 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6696 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6697 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6698 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6699 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6700 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6701 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6703 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
6704 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6705 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6706 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6707 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6708 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6709 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6710 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6711 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6712 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6713 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6714 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6715 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6716 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6717 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6718 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6719 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6720 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6721 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6722 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6723 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6724 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6725 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6726 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6727 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6728 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6729 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6730 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6732 /******************** Bit definition for DFSDM_FLTISR register *******************/
6733 #define DFSDM_FLTISR_SCDF_Pos (24U)
6734 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6735 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6736 #define DFSDM_FLTISR_CKABF_Pos (16U)
6737 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6738 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6739 #define DFSDM_FLTISR_RCIP_Pos (14U)
6740 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6741 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6742 #define DFSDM_FLTISR_JCIP_Pos (13U)
6743 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6744 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6745 #define DFSDM_FLTISR_AWDF_Pos (4U)
6746 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6747 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6748 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6749 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6750 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6751 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6752 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6753 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6754 #define DFSDM_FLTISR_REOCF_Pos (1U)
6755 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6756 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6757 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6758 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6759 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6761 /******************** Bit definition for DFSDM_FLTICR register *******************/
6762 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6763 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6764 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6765 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6766 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6767 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6768 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6769 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6770 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6771 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6772 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6773 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6775 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6776 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6777 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6778 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6780 /******************** Bit definition for DFSDM_FLTFCR register *******************/
6781 #define DFSDM_FLTFCR_FORD_Pos (29U)
6782 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6783 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6784 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6785 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6786 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6787 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6788 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6789 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6790 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6791 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6792 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6794 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6795 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6796 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6797 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6798 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6799 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6800 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6802 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6803 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6804 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6805 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6806 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6807 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6808 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6809 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6810 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6811 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6813 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6814 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6815 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6816 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6817 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6818 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6819 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6821 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6822 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6823 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6824 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6825 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6826 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6827 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6829 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
6830 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6831 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6832 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6833 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6834 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6835 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6837 /****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6838 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6839 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6840 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6841 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6842 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6843 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6845 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6846 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6847 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6848 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6849 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6850 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6851 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6853 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6854 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6855 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6856 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6857 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6858 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6859 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6861 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6862 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6863 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6864 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6866 /******************************************************************************/
6867 /* */
6868 /* BDMA Controller */
6869 /* */
6870 /******************************************************************************/
6871 
6872 /******************* Bit definition for BDMA_ISR register ********************/
6873 #define BDMA_ISR_GIF0_Pos (0U)
6874 #define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos)
6875 #define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk
6876 #define BDMA_ISR_TCIF0_Pos (1U)
6877 #define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos)
6878 #define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk
6879 #define BDMA_ISR_HTIF0_Pos (2U)
6880 #define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos)
6881 #define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk
6882 #define BDMA_ISR_TEIF0_Pos (3U)
6883 #define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos)
6884 #define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk
6885 #define BDMA_ISR_GIF1_Pos (4U)
6886 #define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos)
6887 #define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk
6888 #define BDMA_ISR_TCIF1_Pos (5U)
6889 #define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos)
6890 #define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk
6891 #define BDMA_ISR_HTIF1_Pos (6U)
6892 #define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos)
6893 #define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk
6894 #define BDMA_ISR_TEIF1_Pos (7U)
6895 #define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos)
6896 #define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk
6897 #define BDMA_ISR_GIF2_Pos (8U)
6898 #define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos)
6899 #define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk
6900 #define BDMA_ISR_TCIF2_Pos (9U)
6901 #define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos)
6902 #define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk
6903 #define BDMA_ISR_HTIF2_Pos (10U)
6904 #define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos)
6905 #define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk
6906 #define BDMA_ISR_TEIF2_Pos (11U)
6907 #define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos)
6908 #define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk
6909 #define BDMA_ISR_GIF3_Pos (12U)
6910 #define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos)
6911 #define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk
6912 #define BDMA_ISR_TCIF3_Pos (13U)
6913 #define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos)
6914 #define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk
6915 #define BDMA_ISR_HTIF3_Pos (14U)
6916 #define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos)
6917 #define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk
6918 #define BDMA_ISR_TEIF3_Pos (15U)
6919 #define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos)
6920 #define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk
6921 #define BDMA_ISR_GIF4_Pos (16U)
6922 #define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos)
6923 #define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk
6924 #define BDMA_ISR_TCIF4_Pos (17U)
6925 #define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos)
6926 #define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk
6927 #define BDMA_ISR_HTIF4_Pos (18U)
6928 #define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos)
6929 #define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk
6930 #define BDMA_ISR_TEIF4_Pos (19U)
6931 #define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos)
6932 #define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk
6933 #define BDMA_ISR_GIF5_Pos (20U)
6934 #define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos)
6935 #define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk
6936 #define BDMA_ISR_TCIF5_Pos (21U)
6937 #define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos)
6938 #define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk
6939 #define BDMA_ISR_HTIF5_Pos (22U)
6940 #define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos)
6941 #define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk
6942 #define BDMA_ISR_TEIF5_Pos (23U)
6943 #define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos)
6944 #define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk
6945 #define BDMA_ISR_GIF6_Pos (24U)
6946 #define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos)
6947 #define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk
6948 #define BDMA_ISR_TCIF6_Pos (25U)
6949 #define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos)
6950 #define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk
6951 #define BDMA_ISR_HTIF6_Pos (26U)
6952 #define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos)
6953 #define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk
6954 #define BDMA_ISR_TEIF6_Pos (27U)
6955 #define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos)
6956 #define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk
6957 #define BDMA_ISR_GIF7_Pos (28U)
6958 #define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos)
6959 #define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk
6960 #define BDMA_ISR_TCIF7_Pos (29U)
6961 #define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos)
6962 #define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk
6963 #define BDMA_ISR_HTIF7_Pos (30U)
6964 #define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos)
6965 #define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk
6966 #define BDMA_ISR_TEIF7_Pos (31U)
6967 #define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos)
6968 #define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk
6970 /******************* Bit definition for BDMA_IFCR register *******************/
6971 #define BDMA_IFCR_CGIF0_Pos (0U)
6972 #define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos)
6973 #define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk
6974 #define BDMA_IFCR_CTCIF0_Pos (1U)
6975 #define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos)
6976 #define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk
6977 #define BDMA_IFCR_CHTIF0_Pos (2U)
6978 #define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos)
6979 #define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk
6980 #define BDMA_IFCR_CTEIF0_Pos (3U)
6981 #define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos)
6982 #define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk
6983 #define BDMA_IFCR_CGIF1_Pos (4U)
6984 #define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos)
6985 #define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk
6986 #define BDMA_IFCR_CTCIF1_Pos (5U)
6987 #define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos)
6988 #define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk
6989 #define BDMA_IFCR_CHTIF1_Pos (6U)
6990 #define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos)
6991 #define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk
6992 #define BDMA_IFCR_CTEIF1_Pos (7U)
6993 #define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos)
6994 #define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk
6995 #define BDMA_IFCR_CGIF2_Pos (8U)
6996 #define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos)
6997 #define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk
6998 #define BDMA_IFCR_CTCIF2_Pos (9U)
6999 #define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos)
7000 #define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk
7001 #define BDMA_IFCR_CHTIF2_Pos (10U)
7002 #define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos)
7003 #define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk
7004 #define BDMA_IFCR_CTEIF2_Pos (11U)
7005 #define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos)
7006 #define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk
7007 #define BDMA_IFCR_CGIF3_Pos (12U)
7008 #define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos)
7009 #define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk
7010 #define BDMA_IFCR_CTCIF3_Pos (13U)
7011 #define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos)
7012 #define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk
7013 #define BDMA_IFCR_CHTIF3_Pos (14U)
7014 #define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos)
7015 #define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk
7016 #define BDMA_IFCR_CTEIF3_Pos (15U)
7017 #define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos)
7018 #define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk
7019 #define BDMA_IFCR_CGIF4_Pos (16U)
7020 #define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos)
7021 #define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk
7022 #define BDMA_IFCR_CTCIF4_Pos (17U)
7023 #define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos)
7024 #define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk
7025 #define BDMA_IFCR_CHTIF4_Pos (18U)
7026 #define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos)
7027 #define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk
7028 #define BDMA_IFCR_CTEIF4_Pos (19U)
7029 #define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos)
7030 #define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk
7031 #define BDMA_IFCR_CGIF5_Pos (20U)
7032 #define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos)
7033 #define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk
7034 #define BDMA_IFCR_CTCIF5_Pos (21U)
7035 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos)
7036 #define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk
7037 #define BDMA_IFCR_CHTIF5_Pos (22U)
7038 #define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos)
7039 #define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk
7040 #define BDMA_IFCR_CTEIF5_Pos (23U)
7041 #define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos)
7042 #define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk
7043 #define BDMA_IFCR_CGIF6_Pos (24U)
7044 #define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos)
7045 #define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk
7046 #define BDMA_IFCR_CTCIF6_Pos (25U)
7047 #define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos)
7048 #define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk
7049 #define BDMA_IFCR_CHTIF6_Pos (26U)
7050 #define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos)
7051 #define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk
7052 #define BDMA_IFCR_CTEIF6_Pos (27U)
7053 #define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos)
7054 #define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk
7055 #define BDMA_IFCR_CGIF7_Pos (28U)
7056 #define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos)
7057 #define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk
7058 #define BDMA_IFCR_CTCIF7_Pos (29U)
7059 #define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos)
7060 #define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk
7061 #define BDMA_IFCR_CHTIF7_Pos (30U)
7062 #define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos)
7063 #define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk
7064 #define BDMA_IFCR_CTEIF7_Pos (31U)
7065 #define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos)
7066 #define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk
7068 /******************* Bit definition for BDMA_CCR register ********************/
7069 #define BDMA_CCR_EN_Pos (0U)
7070 #define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos)
7071 #define BDMA_CCR_EN BDMA_CCR_EN_Msk
7072 #define BDMA_CCR_TCIE_Pos (1U)
7073 #define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos)
7074 #define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk
7075 #define BDMA_CCR_HTIE_Pos (2U)
7076 #define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos)
7077 #define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk
7078 #define BDMA_CCR_TEIE_Pos (3U)
7079 #define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos)
7080 #define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk
7081 #define BDMA_CCR_DIR_Pos (4U)
7082 #define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos)
7083 #define BDMA_CCR_DIR BDMA_CCR_DIR_Msk
7084 #define BDMA_CCR_CIRC_Pos (5U)
7085 #define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos)
7086 #define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk
7087 #define BDMA_CCR_PINC_Pos (6U)
7088 #define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos)
7089 #define BDMA_CCR_PINC BDMA_CCR_PINC_Msk
7090 #define BDMA_CCR_MINC_Pos (7U)
7091 #define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos)
7092 #define BDMA_CCR_MINC BDMA_CCR_MINC_Msk
7094 #define BDMA_CCR_PSIZE_Pos (8U)
7095 #define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos)
7096 #define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk
7097 #define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos)
7098 #define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos)
7100 #define BDMA_CCR_MSIZE_Pos (10U)
7101 #define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos)
7102 #define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk
7103 #define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos)
7104 #define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos)
7106 #define BDMA_CCR_PL_Pos (12U)
7107 #define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos)
7108 #define BDMA_CCR_PL BDMA_CCR_PL_Msk
7109 #define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos)
7110 #define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos)
7112 #define BDMA_CCR_MEM2MEM_Pos (14U)
7113 #define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos)
7114 #define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk
7115 #define BDMA_CCR_DBM_Pos (15U)
7116 #define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos)
7117 #define BDMA_CCR_DBM BDMA_CCR_DBM_Msk
7118 #define BDMA_CCR_CT_Pos (16U)
7119 #define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos)
7120 #define BDMA_CCR_CT BDMA_CCR_CT_Msk
7122 /****************** Bit definition for BDMA_CNDTR register *******************/
7123 #define BDMA_CNDTR_NDT_Pos (0U)
7124 #define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos)
7125 #define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk
7127 /****************** Bit definition for BDMA_CPAR register ********************/
7128 #define BDMA_CPAR_PA_Pos (0U)
7129 #define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)
7130 #define BDMA_CPAR_PA BDMA_CPAR_PA_Msk
7132 /****************** Bit definition for BDMA_CM0AR register ********************/
7133 #define BDMA_CM0AR_MA_Pos (0U)
7134 #define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)
7135 #define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk
7137 /****************** Bit definition for BDMA_CM1AR register ********************/
7138 #define BDMA_CM1AR_MA_Pos (0U)
7139 #define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)
7140 #define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk
7142 /******************************************************************************/
7143 /* */
7144 /* Ethernet MAC Registers bits definitions */
7145 /* */
7146 /******************************************************************************/
7147 /* Bit definition for Ethernet MAC Configuration Register register */
7148 #define ETH_MACCR_ARP_Pos (31U)
7149 #define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos)
7150 #define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
7151 #define ETH_MACCR_SARC_Pos (28U)
7152 #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos)
7153 #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
7154 #define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
7155 #define ETH_MACCR_SARC_INSADDR0_Pos (29U)
7156 #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos)
7157 #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
7158 #define ETH_MACCR_SARC_INSADDR1_Pos (29U)
7159 #define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos)
7160 #define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
7161 #define ETH_MACCR_SARC_REPADDR0_Pos (28U)
7162 #define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos)
7163 #define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
7164 #define ETH_MACCR_SARC_REPADDR1_Pos (28U)
7165 #define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos)
7166 #define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
7167 #define ETH_MACCR_IPC_Pos (27U)
7168 #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos)
7169 #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
7170 #define ETH_MACCR_IPG_Pos (24U)
7171 #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos)
7172 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
7173 #define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
7174 #define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
7175 #define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
7176 #define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
7177 #define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
7178 #define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
7179 #define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
7180 #define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
7181 #define ETH_MACCR_GPSLCE_Pos (23U)
7182 #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos)
7183 #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
7184 #define ETH_MACCR_S2KP_Pos (22U)
7185 #define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos)
7186 #define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
7187 #define ETH_MACCR_CST_Pos (21U)
7188 #define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos)
7189 #define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
7190 #define ETH_MACCR_ACS_Pos (20U)
7191 #define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos)
7192 #define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
7193 #define ETH_MACCR_WD_Pos (19U)
7194 #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
7195 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
7196 #define ETH_MACCR_JD_Pos (17U)
7197 #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
7198 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
7199 #define ETH_MACCR_JE_Pos (16U)
7200 #define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos)
7201 #define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
7202 #define ETH_MACCR_FES_Pos (14U)
7203 #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
7204 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
7205 #define ETH_MACCR_DM_Pos (13U)
7206 #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
7207 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
7208 #define ETH_MACCR_LM_Pos (12U)
7209 #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
7210 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
7211 #define ETH_MACCR_ECRSFD_Pos (11U)
7212 #define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos)
7213 #define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
7214 #define ETH_MACCR_DO_Pos (10U)
7215 #define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos)
7216 #define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
7217 #define ETH_MACCR_DCRS_Pos (9U)
7218 #define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos)
7219 #define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
7220 #define ETH_MACCR_DR_Pos (8U)
7221 #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos)
7222 #define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
7223 #define ETH_MACCR_BL_Pos (5U)
7224 #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
7225 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
7226 #define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos)
7227 #define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos)
7228 #define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos)
7229 #define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos)
7230 #define ETH_MACCR_DC_Pos (4U)
7231 #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
7232 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
7233 #define ETH_MACCR_PRELEN_Pos (2U)
7234 #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos)
7235 #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
7236 #define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos)
7237 #define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos)
7238 #define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos)
7239 #define ETH_MACCR_TE_Pos (1U)
7240 #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
7241 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
7242 #define ETH_MACCR_RE_Pos (0U)
7243 #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
7244 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
7245 
7246 /* Bit definition for Ethernet MAC Extended Configuration Register register */
7247 #define ETH_MACECR_EIPG_Pos (25U)
7248 #define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos)
7249 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
7250 #define ETH_MACECR_EIPGEN_Pos (24U)
7251 #define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos)
7252 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
7253 #define ETH_MACECR_USP_Pos (18U)
7254 #define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos)
7255 #define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
7256 #define ETH_MACECR_SPEN_Pos (17U)
7257 #define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos)
7258 #define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
7259 #define ETH_MACECR_DCRCC_Pos (16U)
7260 #define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos)
7261 #define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
7262 #define ETH_MACECR_GPSL_Pos (0U)
7263 #define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos)
7264 #define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
7265 
7266 /* Bit definition for Ethernet MAC Packet Filter Register */
7267 #define ETH_MACPFR_RA_Pos (31U)
7268 #define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos)
7269 #define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
7270 #define ETH_MACPFR_DNTU_Pos (21U)
7271 #define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos)
7272 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
7273 #define ETH_MACPFR_IPFE_Pos (20U)
7274 #define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos)
7275 #define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
7276 #define ETH_MACPFR_VTFE_Pos (16U)
7277 #define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos)
7278 #define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
7279 #define ETH_MACPFR_HPF_Pos (10U)
7280 #define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos)
7281 #define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
7282 #define ETH_MACPFR_SAF_Pos (9U)
7283 #define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos)
7284 #define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
7285 #define ETH_MACPFR_SAIF_Pos (8U)
7286 #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos)
7287 #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
7288 #define ETH_MACPFR_PCF_Pos (6U)
7289 #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos)
7290 #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
7291 #define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
7292 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
7293 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos)
7294 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
7295 #define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
7296 #define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos)
7297 #define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
7298 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
7299 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos)
7300 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
7301 #define ETH_MACPFR_DBF_Pos (5U)
7302 #define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos)
7303 #define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
7304 #define ETH_MACPFR_PM_Pos (4U)
7305 #define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos)
7306 #define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
7307 #define ETH_MACPFR_DAIF_Pos (3U)
7308 #define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos)
7309 #define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
7310 #define ETH_MACPFR_HMC_Pos (2U)
7311 #define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos)
7312 #define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
7313 #define ETH_MACPFR_HUC_Pos (1U)
7314 #define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos)
7315 #define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
7316 #define ETH_MACPFR_PR_Pos (0U)
7317 #define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos)
7318 #define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
7319 
7320 /* Bit definition for Ethernet MAC Watchdog Timeout Register */
7321 #define ETH_MACWTR_PWE_Pos (8U)
7322 #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos)
7323 #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
7324 #define ETH_MACWTR_WTO_Pos (0U)
7325 #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos)
7326 #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
7327 #define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
7328 #define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
7329 #define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
7330 #define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
7331 #define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
7332 #define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
7333 #define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
7334 #define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
7335 #define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
7336 #define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
7337 #define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
7338 #define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
7339 #define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
7340 #define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
7341 #define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
7342 
7343 /* Bit definition for Ethernet MAC Hash Table High Register */
7344 #define ETH_MACHTHR_HTH_Pos (0U)
7345 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
7346 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
7347 
7348 /* Bit definition for Ethernet MAC Hash Table Low Register */
7349 #define ETH_MACHTLR_HTL_Pos (0U)
7350 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
7351 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
7352 
7353 /* Bit definition for Ethernet MAC VLAN Tag Register */
7354 #define ETH_MACVTR_EIVLRXS_Pos (31U)
7355 #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos)
7356 #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
7357 #define ETH_MACVTR_EIVLS_Pos (28U)
7358 #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos)
7359 #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
7360 #define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
7361 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
7362 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos)
7363 #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7364 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
7365 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos)
7366 #define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7367 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
7368 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos)
7369 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
7370 #define ETH_MACVTR_ERIVLT_Pos (27U)
7371 #define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos)
7372 #define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
7373 #define ETH_MACVTR_EDVLP_Pos (26U)
7374 #define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos)
7375 #define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
7376 #define ETH_MACVTR_VTHM_Pos (25U)
7377 #define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos)
7378 #define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
7379 #define ETH_MACVTR_EVLRXS_Pos (24U)
7380 #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos)
7381 #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
7382 #define ETH_MACVTR_EVLS_Pos (21U)
7383 #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos)
7384 #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
7385 #define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
7386 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
7387 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos)
7388 #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7389 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
7390 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos)
7391 #define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7392 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
7393 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos)
7394 #define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
7395 #define ETH_MACVTR_DOVLTC_Pos (20U)
7396 #define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos)
7397 #define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
7398 #define ETH_MACVTR_ERSVLM_Pos (19U)
7399 #define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos)
7400 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
7401 #define ETH_MACVTR_ESVL_Pos (18U)
7402 #define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos)
7403 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7404 #define ETH_MACVTR_VTIM_Pos (17U)
7405 #define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos)
7406 #define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
7407 #define ETH_MACVTR_ETV_Pos (16U)
7408 #define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos)
7409 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
7410 #define ETH_MACVTR_VL_Pos (0U)
7411 #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos)
7412 #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
7413 #define ETH_MACVTR_VL_UP_Pos (13U)
7414 #define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos)
7415 #define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
7416 #define ETH_MACVTR_VL_CFIDEI_Pos (12U)
7417 #define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos)
7418 #define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7419 #define ETH_MACVTR_VL_VID_Pos (0U)
7420 #define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos)
7421 #define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
7422 
7423 /* Bit definition for Ethernet MAC VLAN Hash Table Register */
7424 #define ETH_MACVHTR_VLHT_Pos (0U)
7425 #define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos)
7426 #define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
7427 
7428 /* Bit definition for Ethernet MAC VLAN Incl Register */
7429 #define ETH_MACVIR_VLTI_Pos (20U)
7430 #define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos)
7431 #define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
7432 #define ETH_MACVIR_CSVL_Pos (19U)
7433 #define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos)
7434 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7435 #define ETH_MACVIR_VLP_Pos (18U)
7436 #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos)
7437 #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
7438 #define ETH_MACVIR_VLC_Pos (16U)
7439 #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos)
7440 #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7441 #define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
7442 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
7443 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos)
7444 #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7445 #define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
7446 #define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos)
7447 #define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7448 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
7449 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos)
7450 #define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7451 #define ETH_MACVIR_VLT_Pos (0U)
7452 #define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos)
7453 #define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7454 #define ETH_MACVIR_VLT_UP_Pos (13U)
7455 #define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos)
7456 #define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
7457 #define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
7458 #define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos)
7459 #define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7460 #define ETH_MACVIR_VLT_VID_Pos (0U)
7461 #define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos)
7462 #define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7463 
7464 /* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
7465 #define ETH_MACIVIR_VLTI_Pos (20U)
7466 #define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos)
7467 #define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
7468 #define ETH_MACIVIR_CSVL_Pos (19U)
7469 #define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos)
7470 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7471 #define ETH_MACIVIR_VLP_Pos (18U)
7472 #define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos)
7473 #define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
7474 #define ETH_MACIVIR_VLC_Pos (16U)
7475 #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos)
7476 #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7477 #define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
7478 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
7479 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos)
7480 #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7481 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
7482 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos)
7483 #define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7484 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
7485 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos)
7486 #define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7487 #define ETH_MACIVIR_VLT_Pos (0U)
7488 #define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos)
7489 #define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7490 #define ETH_MACIVIR_VLT_UP_Pos (13U)
7491 #define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos)
7492 #define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
7493 #define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
7494 #define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos)
7495 #define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7496 #define ETH_MACIVIR_VLT_VID_Pos (0U)
7497 #define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos)
7498 #define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7499 
7500 /* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
7501 #define ETH_MACTFCR_PT_Pos (16U)
7502 #define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos)
7503 #define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
7504 #define ETH_MACTFCR_DZPQ_Pos (7U)
7505 #define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos)
7506 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
7507 #define ETH_MACTFCR_PLT_Pos (4U)
7508 #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos)
7509 #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
7510 #define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7511 #define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
7512 #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos)
7513 #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
7514 #define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
7515 #define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos)
7516 #define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
7517 #define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
7518 #define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos)
7519 #define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
7520 #define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
7521 #define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos)
7522 #define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
7523 #define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
7524 #define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos)
7525 #define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
7526 #define ETH_MACTFCR_TFE_Pos (1U)
7527 #define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos)
7528 #define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
7529 #define ETH_MACTFCR_FCB_Pos (0U)
7530 #define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos)
7531 #define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
7532 
7533 /* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
7534 #define ETH_MACRFCR_UP_Pos (1U)
7535 #define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos)
7536 #define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
7537 #define ETH_MACRFCR_RFE_Pos (0U)
7538 #define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos)
7539 #define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
7540 
7541 /* Bit definition for Ethernet MAC Interrupt Status Register */
7542 #define ETH_MACISR_RXSTSIS_Pos (14U)
7543 #define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos)
7544 #define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
7545 #define ETH_MACISR_TXSTSIS_Pos (13U)
7546 #define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos)
7547 #define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
7548 #define ETH_MACISR_TSIS_Pos (12U)
7549 #define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos)
7550 #define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
7551 #define ETH_MACISR_MMCTXIS_Pos (10U)
7552 #define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos)
7553 #define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
7554 #define ETH_MACISR_MMCRXIS_Pos (9U)
7555 #define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos)
7556 #define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
7557 #define ETH_MACISR_MMCIS_Pos (8U)
7558 #define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos)
7559 #define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
7560 #define ETH_MACISR_LPIIS_Pos (5U)
7561 #define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos)
7562 #define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
7563 #define ETH_MACISR_PMTIS_Pos (4U)
7564 #define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos)
7565 #define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
7566 #define ETH_MACISR_PHYIS_Pos (3U)
7567 #define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos)
7568 #define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
7569 
7570 /* Bit definition for Ethernet MAC Interrupt Enable Register */
7571 #define ETH_MACIER_RXSTSIE_Pos (14U)
7572 #define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos)
7573 #define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
7574 #define ETH_MACIER_TXSTSIE_Pos (13U)
7575 #define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos)
7576 #define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
7577 #define ETH_MACIER_TSIE_Pos (12U)
7578 #define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos)
7579 #define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
7580 #define ETH_MACIER_LPIIE_Pos (5U)
7581 #define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos)
7582 #define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
7583 #define ETH_MACIER_PMTIE_Pos (4U)
7584 #define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos)
7585 #define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
7586 #define ETH_MACIER_PHYIE_Pos (3U)
7587 #define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos)
7588 #define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
7589 
7590 /* Bit definition for Ethernet MAC Rx Tx Status Register */
7591 #define ETH_MACRXTXSR_RWT_Pos (8U)
7592 #define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos)
7593 #define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
7594 #define ETH_MACRXTXSR_EXCOL_Pos (5U)
7595 #define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos)
7596 #define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
7597 #define ETH_MACRXTXSR_LCOL_Pos (4U)
7598 #define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos)
7599 #define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
7600 #define ETH_MACRXTXSR_EXDEF_Pos (3U)
7601 #define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos)
7602 #define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
7603 #define ETH_MACRXTXSR_LCARR_Pos (2U)
7604 #define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos)
7605 #define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
7606 #define ETH_MACRXTXSR_NCARR_Pos (1U)
7607 #define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos)
7608 #define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
7609 #define ETH_MACRXTXSR_TJT_Pos (0U)
7610 #define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos)
7611 #define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
7612 
7613 /* Bit definition for Ethernet MAC PMT Control Status Register */
7614 #define ETH_MACPCSR_RWKFILTRST_Pos (31U)
7615 #define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos)
7616 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7617 #define ETH_MACPCSR_RWKPTR_Pos (24U)
7618 #define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos)
7619 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7620 #define ETH_MACPCSR_RWKPFE_Pos (10U)
7621 #define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos)
7622 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7623 #define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7624 #define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos)
7625 #define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7626 #define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7627 #define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos)
7628 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7629 #define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7630 #define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos)
7631 #define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7632 #define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7633 #define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos)
7634 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7635 #define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7636 #define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos)
7637 #define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7638 #define ETH_MACPCSR_PWRDWN_Pos (0U)
7639 #define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos)
7640 #define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7641 
7642 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7643 #define ETH_MACRWUPFR_D_Pos (0U)
7644 #define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos)
7645 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7646 
7647 /* Bit definition for Ethernet MAC LPI Control Status Register */
7648 #define ETH_MACLCSR_LPITCSE_Pos (21U)
7649 #define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos)
7650 #define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7651 #define ETH_MACLCSR_LPITE_Pos (20U)
7652 #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos)
7653 #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7654 #define ETH_MACLCSR_LPITXA_Pos (19U)
7655 #define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos)
7656 #define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7657 #define ETH_MACLCSR_PLS_Pos (17U)
7658 #define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos)
7659 #define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7660 #define ETH_MACLCSR_LPIEN_Pos (16U)
7661 #define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos)
7662 #define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7663 #define ETH_MACLCSR_RLPIST_Pos (9U)
7664 #define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos)
7665 #define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7666 #define ETH_MACLCSR_TLPIST_Pos (8U)
7667 #define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos)
7668 #define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7669 #define ETH_MACLCSR_RLPIEX_Pos (3U)
7670 #define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos)
7671 #define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7672 #define ETH_MACLCSR_RLPIEN_Pos (2U)
7673 #define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos)
7674 #define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7675 #define ETH_MACLCSR_TLPIEX_Pos (1U)
7676 #define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos)
7677 #define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7678 #define ETH_MACLCSR_TLPIEN_Pos (0U)
7679 #define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos)
7680 #define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7681 
7682 /* Bit definition for Ethernet MAC LPI Timers Control Register */
7683 #define ETH_MACLTCR_LST_Pos (16U)
7684 #define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos)
7685 #define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7686 #define ETH_MACLTCR_TWT_Pos (0U)
7687 #define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos)
7688 #define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7689 
7690 /* Bit definition for Ethernet MAC LPI Entry Timer Register */
7691 #define ETH_MACLETR_LPIET_Pos (0U)
7692 #define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos)
7693 #define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7694 
7695 /* Bit definition for Ethernet MAC 1US Tic Counter Register */
7696 #define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7697 #define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos)
7698 #define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7699 
7700 /* Bit definition for Ethernet MAC Version Register */
7701 #define ETH_MACVR_USERVER_Pos (8U)
7702 #define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos)
7703 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7704 #define ETH_MACVR_SNPSVER_Pos (0U)
7705 #define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos)
7706 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7707 
7708 /* Bit definition for Ethernet MAC Debug Register */
7709 #define ETH_MACDR_TFCSTS_Pos (17U)
7710 #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos)
7711 #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7712 #define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
7713 #define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7714 #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos)
7715 #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7716 #define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7717 #define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos)
7718 #define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7719 #define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7720 #define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos)
7721 #define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7722 #define ETH_MACDR_TPESTS_Pos (16U)
7723 #define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos)
7724 #define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7725 #define ETH_MACDR_RFCFCSTS_Pos (1U)
7726 #define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos)
7727 #define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7728 #define ETH_MACDR_RPESTS_Pos (0U)
7729 #define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos)
7730 #define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7731 
7732 /* Bit definition for Ethernet MAC HW Feature0 Register */
7733 #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7734 #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos)
7735 #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7736 #define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
7737 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7738 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos)
7739 #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7740 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7741 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos)
7742 #define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7743 #define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7744 #define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos)
7745 #define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7746 #define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7747 #define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos)
7748 #define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7749 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7750 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos)
7751 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7752 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7753 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos)
7754 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7755 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7756 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos)
7757 #define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7758 #define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7759 #define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos)
7760 #define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7761 #define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7762 #define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos)
7763 #define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7764 #define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7765 #define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos)
7766 #define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7767 #define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7768 #define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos)
7769 #define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7770 #define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7771 #define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos)
7772 #define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7773 #define ETH_MACHWF0R_EEESEL_Pos (13U)
7774 #define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos)
7775 #define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7776 #define ETH_MACHWF0R_TSSEL_Pos (12U)
7777 #define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos)
7778 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7779 #define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7780 #define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos)
7781 #define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7782 #define ETH_MACHWF0R_MMCSEL_Pos (8U)
7783 #define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos)
7784 #define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7785 #define ETH_MACHWF0R_MGKSEL_Pos (7U)
7786 #define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos)
7787 #define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7788 #define ETH_MACHWF0R_RWKSEL_Pos (6U)
7789 #define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos)
7790 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7791 #define ETH_MACHWF0R_SMASEL_Pos (5U)
7792 #define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos)
7793 #define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7794 #define ETH_MACHWF0R_VLHASH_Pos (4U)
7795 #define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos)
7796 #define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7797 #define ETH_MACHWF0R_PCSSEL_Pos (3U)
7798 #define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos)
7799 #define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7800 #define ETH_MACHWF0R_HDSEL_Pos (2U)
7801 #define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos)
7802 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7803 #define ETH_MACHWF0R_GMIISEL_Pos (1U)
7804 #define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos)
7805 #define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7806 #define ETH_MACHWF0R_MIISEL_Pos (0U)
7807 #define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos)
7808 #define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7809 
7810 /* Bit definition for Ethernet MAC HW Feature1 Register */
7811 #define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7812 #define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos)
7813 #define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7814 #define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7815 #define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos)
7816 #define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7817 #define ETH_MACHWF1R_AVSEL_Pos (20U)
7818 #define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos)
7819 #define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7820 #define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7821 #define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos)
7822 #define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7823 #define ETH_MACHWF1R_TSOEN_Pos (18U)
7824 #define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos)
7825 #define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7826 #define ETH_MACHWF1R_SPHEN_Pos (17U)
7827 #define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos)
7828 #define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7829 #define ETH_MACHWF1R_DCBEN_Pos (16U)
7830 #define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos)
7831 #define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7832 #define ETH_MACHWF1R_ADDR64_Pos (14U)
7833 #define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos)
7834 #define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7835 #define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos)
7836 #define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos)
7837 #define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos)
7838 #define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7839 #define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos)
7840 #define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7841 #define ETH_MACHWF1R_PTOEN_Pos (12U)
7842 #define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos)
7843 #define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7844 #define ETH_MACHWF1R_OSTEN_Pos (11U)
7845 #define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos)
7846 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7847 #define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7848 #define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos)
7849 #define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7850 #define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7851 #define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos)
7852 #define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7853 
7854 /* Bit definition for Ethernet MAC HW Feature2 Register */
7855 #define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
7856 #define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos)
7857 #define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
7858 #define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
7859 #define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos)
7860 #define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
7861 #define ETH_MACHWF2R_TXCHCNT_Pos (18U)
7862 #define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos)
7863 #define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
7864 #define ETH_MACHWF2R_RXCHCNT_Pos (13U)
7865 #define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos)
7866 #define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
7867 #define ETH_MACHWF2R_TXQCNT_Pos (6U)
7868 #define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos)
7869 #define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
7870 #define ETH_MACHWF2R_RXQCNT_Pos (0U)
7871 #define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos)
7872 #define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
7873 
7874 /* Bit definition for Ethernet MAC MDIO Address Register */
7875 #define ETH_MACMDIOAR_PSE_Pos (27U)
7876 #define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos)
7877 #define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
7878 #define ETH_MACMDIOAR_BTB_Pos (26U)
7879 #define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos)
7880 #define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
7881 #define ETH_MACMDIOAR_PA_Pos (21U)
7882 #define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos)
7883 #define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
7884 #define ETH_MACMDIOAR_RDA_Pos (16U)
7885 #define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos)
7886 #define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
7887 #define ETH_MACMDIOAR_NTC_Pos (12U)
7888 #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos)
7889 #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
7890 #define ETH_MACMDIOAR_CR_Pos (8U)
7891 #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos)
7892 #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
7893 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
7894 #define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
7895 #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos)
7896 #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
7897 #define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
7898 #define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos)
7899 #define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
7900 #define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
7901 #define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos)
7902 #define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
7903 #define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
7904 #define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos)
7905 #define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
7906 #define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
7907 #define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos)
7908 #define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
7909 #define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
7910 #define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos)
7911 #define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
7912 #define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
7913 #define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos)
7914 #define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
7915 #define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
7916 #define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos)
7917 #define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
7918 #define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
7919 #define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos)
7920 #define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
7921 #define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
7922 #define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos)
7923 #define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
7924 #define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
7925 #define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos)
7926 #define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
7927 #define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
7928 #define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos)
7929 #define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
7930 #define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
7931 #define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos)
7932 #define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
7933 #define ETH_MACMDIOAR_SKAP_Pos (4U)
7934 #define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos)
7935 #define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
7936 #define ETH_MACMDIOAR_MOC_Pos (2U)
7937 #define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos)
7938 #define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
7939 #define ETH_MACMDIOAR_MOC_WR_Pos (2U)
7940 #define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos)
7941 #define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
7942 #define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
7943 #define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos)
7944 #define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
7945 #define ETH_MACMDIOAR_MOC_RD_Pos (2U)
7946 #define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos)
7947 #define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
7948 #define ETH_MACMDIOAR_C45E_Pos (1U)
7949 #define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos)
7950 #define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
7951 #define ETH_MACMDIOAR_MB_Pos (0U)
7952 #define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos)
7953 #define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
7954 
7955 /* Bit definition for Ethernet MAC MDIO Data Register */
7956 #define ETH_MACMDIODR_RA_Pos (16U)
7957 #define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos)
7958 #define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
7959 #define ETH_MACMDIODR_MD_Pos (0U)
7960 #define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos)
7961 #define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
7962 
7963 /* Bit definition for Ethernet ARP Address Register */
7964 #define ETH_MACARPAR_ARPPA_Pos (0U)
7965 #define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos)
7966 #define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
7967 
7968 /* Bit definition for Ethernet MAC Address 0 High Register */
7969 #define ETH_MACA0HR_AE_Pos (31U)
7970 #define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos)
7971 #define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
7972 #define ETH_MACA0HR_ADDRHI_Pos (0U)
7973 #define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos)
7974 #define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
7975 
7976 /* Bit definition for Ethernet MAC Address 0 Low Register */
7977 #define ETH_MACA0LR_ADDRLO_Pos (0U)
7978 #define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos)
7979 #define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
7980 
7981 /* Bit definition for Ethernet MAC Address 1 High Register */
7982 #define ETH_MACA1HR_AE_Pos (31U)
7983 #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
7984 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
7985 #define ETH_MACA1HR_SA_Pos (30U)
7986 #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
7987 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
7988 #define ETH_MACA1HR_MBC_Pos (24U)
7989 #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
7990 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
7991 #define ETH_MACA1HR_ADDRHI_Pos (0U)
7992 #define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos)
7993 #define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
7994 
7995 /* Bit definition for Ethernet MAC Address 1 Low Register */
7996 #define ETH_MACA1LR_ADDRLO_Pos (0U)
7997 #define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos)
7998 #define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
7999 
8000 /* Bit definition for Ethernet MAC Address 2 High Register */
8001 #define ETH_MACA2HR_AE_Pos (31U)
8002 #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
8003 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
8004 #define ETH_MACA2HR_SA_Pos (30U)
8005 #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
8006 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
8007 #define ETH_MACA2HR_MBC_Pos (24U)
8008 #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
8009 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
8010 #define ETH_MACA2HR_ADDRHI_Pos (0U)
8011 #define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos)
8012 #define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
8013 
8014 /* Bit definition for Ethernet MAC Address 2 Low Register */
8015 #define ETH_MACA2LR_ADDRLO_Pos (0U)
8016 #define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos)
8017 #define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
8018 
8019 /* Bit definition for Ethernet MAC Address 3 High Register */
8020 #define ETH_MACA3HR_AE_Pos (31U)
8021 #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
8022 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
8023 #define ETH_MACA3HR_SA_Pos (30U)
8024 #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
8025 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
8026 #define ETH_MACA3HR_MBC_Pos (24U)
8027 #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
8028 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
8029 #define ETH_MACA3HR_ADDRHI_Pos (0U)
8030 #define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos)
8031 #define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
8032 
8033 /* Bit definition for Ethernet MAC Address 3 Low Register */
8034 #define ETH_MACA3LR_ADDRLO_Pos (0U)
8035 #define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos)
8036 #define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
8037 
8038 /* Bit definition for Ethernet MAC Address High Register */
8039 #define ETH_MACAHR_AE_Pos (31U)
8040 #define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos)
8041 #define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
8042 #define ETH_MACAHR_SA_Pos (30U)
8043 #define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos)
8044 #define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
8045 #define ETH_MACAHR_MBC_Pos (24U)
8046 #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos)
8047 #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8048 #define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8049 #define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8050 #define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8051 #define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8052 #define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8053 #define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
8054 #define ETH_MACAHR_MACAH_Pos (0U)
8055 #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos)
8056 #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
8057 
8058 /* Bit definition for Ethernet MAC Address Low Register */
8059 #define ETH_MACALR_MACAL_Pos (0U)
8060 #define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos)
8061 #define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
8062 
8063 /* Bit definition for Ethernet MMC Control Register */
8064 #define ETH_MMCCR_UCDBC_Pos (8U)
8065 #define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos)
8066 #define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
8067 #define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
8068 #define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos)
8069 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
8070 #define ETH_MMCCR_CNTPRST_Pos (4U)
8071 #define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos)
8072 #define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
8073 #define ETH_MMCCR_CNTFREEZ_Pos (3U)
8074 #define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos)
8075 #define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
8076 #define ETH_MMCCR_RSTONRD_Pos (2U)
8077 #define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos)
8078 #define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
8079 #define ETH_MMCCR_CNTSTOPRO_Pos (1U)
8080 #define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos)
8081 #define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
8082 #define ETH_MMCCR_CNTRST_Pos (0U)
8083 #define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos)
8084 #define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
8085 
8086 /* Bit definition for Ethernet MMC Rx Interrupt Register */
8087 #define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
8088 #define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos)
8089 #define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
8090 #define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
8091 #define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos)
8092 #define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
8093 #define ETH_MMCRIR_RXUCGPIS_Pos (17U)
8094 #define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos)
8095 #define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
8096 #define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
8097 #define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos)
8098 #define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
8099 #define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
8100 #define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos)
8101 #define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
8102 
8103 /* Bit definition for Ethernet MMC Tx Interrupt Register */
8104 #define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
8105 #define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos)
8106 #define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
8107 #define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
8108 #define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos)
8109 #define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
8110 #define ETH_MMCTIR_TXGPKTIS_Pos (21U)
8111 #define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos)
8112 #define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
8113 #define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
8114 #define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos)
8115 #define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
8116 #define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
8117 #define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos)
8118 #define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
8119 
8120 /* Bit definition for Ethernet MMC Rx interrupt Mask register */
8121 #define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
8122 #define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos)
8123 #define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
8124 #define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
8125 #define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos)
8126 #define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
8127 #define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
8128 #define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos)
8129 #define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
8130 #define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
8131 #define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos)
8132 #define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
8133 #define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
8134 #define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos)
8135 #define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
8136 
8137 /* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
8138 #define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
8139 #define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos)
8140 #define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
8141 #define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
8142 #define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos)
8143 #define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
8144 #define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
8145 #define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos)
8146 #define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
8147 #define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
8148 #define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos)
8149 #define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
8150 #define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
8151 #define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos)
8152 #define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
8153 
8154 /* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
8155 #define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
8156 #define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos)
8157 #define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
8158 
8159 /* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
8160 #define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
8161 #define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos)
8162 #define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
8163 
8164 /* Bit definition for Ethernet MMC Tx Packet Count Good Register */
8165 #define ETH_MMCTPCGR_TXPKTG_Pos (0U)
8166 #define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos)
8167 #define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
8168 
8169 /* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
8170 #define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
8171 #define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos)
8172 #define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
8173 
8174 /* Bit definition for Ethernet MMC Rx alignment error packets register */
8175 #define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
8176 #define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos)
8177 #define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
8178 
8179 /* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
8180 #define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
8181 #define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos)
8182 #define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
8183 
8184 /* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
8185 #define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
8186 #define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos)
8187 #define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
8188 
8189 /* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
8190 #define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
8191 #define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos)
8192 #define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
8193 
8194 /* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
8195 #define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
8196 #define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos)
8197 #define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
8198 
8199 /* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
8200 #define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
8201 #define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos)
8202 #define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
8203 
8204 /* Bit definition for Ethernet MAC L3 L4 Control Register */
8205 #define ETH_MACL3L4CR_L4DPIM_Pos (21U)
8206 #define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos)
8207 #define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
8208 #define ETH_MACL3L4CR_L4DPM_Pos (20U)
8209 #define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos)
8210 #define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
8211 #define ETH_MACL3L4CR_L4SPIM_Pos (19U)
8212 #define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos)
8213 #define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
8214 #define ETH_MACL3L4CR_L4SPM_Pos (18U)
8215 #define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos)
8216 #define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
8217 #define ETH_MACL3L4CR_L4PEN_Pos (16U)
8218 #define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos)
8219 #define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
8220 #define ETH_MACL3L4CR_L3HDBM_Pos (11U)
8221 #define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos)
8222 #define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
8223 #define ETH_MACL3L4CR_L3HSBM_Pos (6U)
8224 #define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos)
8225 #define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
8226 #define ETH_MACL3L4CR_L3DAIM_Pos (5U)
8227 #define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos)
8228 #define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
8229 #define ETH_MACL3L4CR_L3DAM_Pos (4U)
8230 #define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos)
8231 #define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
8232 #define ETH_MACL3L4CR_L3SAIM_Pos (3U)
8233 #define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos)
8234 #define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
8235 #define ETH_MACL3L4CR_L3SAM_Pos (2U)
8236 #define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos)
8237 #define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
8238 #define ETH_MACL3L4CR_L3PEN_Pos (0U)
8239 #define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos)
8240 #define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
8241 
8242 /* Bit definition for Ethernet MAC L4 Address Register */
8243 #define ETH_MACL4AR_L4DP_Pos (16U)
8244 #define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos)
8245 #define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
8246 #define ETH_MACL4AR_L4SP_Pos (0U)
8247 #define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos)
8248 #define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
8249 
8250 /* Bit definition for Ethernet MAC L3 Address0 Register */
8251 #define ETH_MACL3A0R_L3A0_Pos (0U)
8252 #define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos)
8253 #define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
8254 
8255 /* Bit definition for Ethernet MAC L4 Address1 Register */
8256 #define ETH_MACL3A1R_L3A1_Pos (0U)
8257 #define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos)
8258 #define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
8259 
8260 /* Bit definition for Ethernet MAC L4 Address2 Register */
8261 #define ETH_MACL3A2R_L3A2_Pos (0U)
8262 #define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos)
8263 #define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
8264 
8265 /* Bit definition for Ethernet MAC L4 Address3 Register */
8266 #define ETH_MACL3A3R_L3A3_Pos (0U)
8267 #define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos)
8268 #define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
8269 
8270 /* Bit definition for Ethernet MAC Timestamp Control Register */
8271 #define ETH_MACTSCR_TXTSSTSM_Pos (24U)
8272 #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos)
8273 #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
8274 #define ETH_MACTSCR_CSC_Pos (19U)
8275 #define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos)
8276 #define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
8277 #define ETH_MACTSCR_TSENMACADDR_Pos (18U)
8278 #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos)
8279 #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
8280 #define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
8281 #define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos)
8282 #define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
8283 #define ETH_MACTSCR_TSMSTRENA_Pos (15U)
8284 #define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos)
8285 #define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
8286 #define ETH_MACTSCR_TSEVNTENA_Pos (14U)
8287 #define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos)
8288 #define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
8289 #define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
8290 #define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos)
8291 #define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
8292 #define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
8293 #define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos)
8294 #define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
8295 #define ETH_MACTSCR_TSIPENA_Pos (11U)
8296 #define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos)
8297 #define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
8298 #define ETH_MACTSCR_TSVER2ENA_Pos (10U)
8299 #define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos)
8300 #define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
8301 #define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
8302 #define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos)
8303 #define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
8304 #define ETH_MACTSCR_TSENALL_Pos (8U)
8305 #define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos)
8306 #define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
8307 #define ETH_MACTSCR_TSADDREG_Pos (5U)
8308 #define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos)
8309 #define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
8310 #define ETH_MACTSCR_TSUPDT_Pos (3U)
8311 #define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos)
8312 #define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
8313 #define ETH_MACTSCR_TSINIT_Pos (2U)
8314 #define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos)
8315 #define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
8316 #define ETH_MACTSCR_TSCFUPDT_Pos (1U)
8317 #define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos)
8318 #define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
8319 #define ETH_MACTSCR_TSENA_Pos (0U)
8320 #define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos)
8321 #define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
8322 
8323 /* Bit definition for Ethernet MAC Sub-second Increment Register */
8324 #define ETH_MACMACSSIR_SSINC_Pos (16U)
8325 #define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos)
8326 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
8327 #define ETH_MACMACSSIR_SNSINC_Pos (8U)
8328 #define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos)
8329 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
8330 
8331 /* Bit definition for Ethernet MAC System Time Seconds Register */
8332 #define ETH_MACSTSR_TSS_Pos (0U)
8333 #define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos)
8334 #define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
8335 
8336 /* Bit definition for Ethernet MAC System Time Nanoseconds Register */
8337 #define ETH_MACSTNR_TSSS_Pos (0U)
8338 #define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos)
8339 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
8340 
8341 /* Bit definition for Ethernet MAC System Time Seconds Update Register */
8342 #define ETH_MACSTSUR_TSS_Pos (0U)
8343 #define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos)
8344 #define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
8345 
8346 /* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
8347 #define ETH_MACSTNUR_ADDSUB_Pos (31U)
8348 #define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos)
8349 #define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
8350 #define ETH_MACSTNUR_TSSS_Pos (0U)
8351 #define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos)
8352 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
8353 
8354 /* Bit definition for Ethernet MAC Timestamp Addend Register */
8355 #define ETH_MACTSAR_TSAR_Pos (0U)
8356 #define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos)
8357 #define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
8358 
8359 /* Bit definition for Ethernet MAC Timestamp Status Register */
8360 #define ETH_MACTSSR_ATSNS_Pos (25U)
8361 #define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos)
8362 #define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
8363 #define ETH_MACTSSR_ATSSTM_Pos (24U)
8364 #define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos)
8365 #define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
8366 #define ETH_MACTSSR_ATSSTN_Pos (16U)
8367 #define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos)
8368 #define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
8369 #define ETH_MACTSSR_TXTSSIS_Pos (15U)
8370 #define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos)
8371 #define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
8372 #define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
8373 #define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos)
8374 #define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
8375 #define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
8376 #define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos)
8377 #define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
8378 #define ETH_MACTSSR_TSTARGT0_Pos (1U)
8379 #define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos)
8380 #define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
8381 #define ETH_MACTSSR_TSSOVF_Pos (0U)
8382 #define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos)
8383 #define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
8384 
8385 /* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
8386 #define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
8387 #define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos)
8388 #define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
8389 #define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
8390 #define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos)
8391 #define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
8392 
8393 /* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
8394 #define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
8395 #define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos)
8396 #define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
8397 
8398 /* Bit definition for Ethernet MAC Auxiliary Control Register*/
8399 #define ETH_MACACR_ATSEN3_Pos (7U)
8400 #define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos)
8401 #define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
8402 #define ETH_MACACR_ATSEN2_Pos (6U)
8403 #define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos)
8404 #define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
8405 #define ETH_MACACR_ATSEN1_Pos (5U)
8406 #define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos)
8407 #define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
8408 #define ETH_MACACR_ATSEN0_Pos (4U)
8409 #define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos)
8410 #define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
8411 #define ETH_MACACR_ATSFC_Pos (0U)
8412 #define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos)
8413 #define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
8414 
8415 /* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
8416 #define ETH_MACATSNR_AUXTSLO_Pos (0U)
8417 #define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos)
8418 #define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
8419 
8420 /* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
8421 #define ETH_MACATSSR_AUXTSHI_Pos (0U)
8422 #define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos)
8423 #define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
8424 
8425 /* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
8426 #define ETH_MACTSIACR_OSTIAC_Pos (0U)
8427 #define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos)
8428 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
8429 
8430 /* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
8431 #define ETH_MACTSEACR_OSTEAC_Pos (0U)
8432 #define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos)
8433 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
8434 
8435 /* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
8436 #define ETH_MACTSICNR_TSIC_Pos (0U)
8437 #define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos)
8438 #define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
8439 
8440 /* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
8441 #define ETH_MACTSECNR_TSEC_Pos (0U)
8442 #define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos)
8443 #define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
8444 
8445 /* Bit definition for Ethernet MAC PPS Control Register */
8446 #define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
8447 #define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos)
8448 #define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
8449 #define ETH_MACPPSCR_PPSEN0_Pos (4U)
8450 #define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos)
8451 #define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
8452 #define ETH_MACPPSCR_PPSCTRL_Pos (0U)
8453 #define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos)
8454 #define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
8455 
8456 /* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
8457 #define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
8458 #define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos)
8459 #define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
8460 
8461 /* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
8462 #define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
8463 #define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos)
8464 #define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
8465 #define ETH_MACPPSTTNR_TTSL0_Pos (0U)
8466 #define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos)
8467 #define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
8468 
8469 /* Bit definition for Ethernet MAC PPS Interval Register */
8470 #define ETH_MACPPSIR_PPSINT0_Pos (0U)
8471 #define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos)
8472 #define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
8473 
8474 /* Bit definition for Ethernet MAC PPS Width Register */
8475 #define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
8476 #define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos)
8477 #define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
8478 
8479 /* Bit definition for Ethernet MAC PTP Offload Control Register */
8480 #define ETH_MACPOCR_DN_Pos (8U)
8481 #define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos)
8482 #define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
8483 #define ETH_MACPOCR_DRRDIS_Pos (6U)
8484 #define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos)
8485 #define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
8486 #define ETH_MACPOCR_APDREQTRIG_Pos (5U)
8487 #define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos)
8488 #define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
8489 #define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
8490 #define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos)
8491 #define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
8492 #define ETH_MACPOCR_APDREQEN_Pos (2U)
8493 #define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos)
8494 #define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
8495 #define ETH_MACPOCR_ASYNCEN_Pos (1U)
8496 #define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos)
8497 #define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
8498 #define ETH_MACPOCR_PTOEN_Pos (0U)
8499 #define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos)
8500 #define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
8501 
8502 /* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
8503 #define ETH_MACSPI0R_SPI0_Pos (0U)
8504 #define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos)
8505 #define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
8506 
8507 /* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
8508 #define ETH_MACSPI1R_SPI1_Pos (0U)
8509 #define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos)
8510 #define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
8511 
8512 /* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
8513 #define ETH_MACSPI2R_SPI2_Pos (0U)
8514 #define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos)
8515 #define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
8516 
8517 /* Bit definition for Ethernet MAC Log Message Interval Register */
8518 #define ETH_MACLMIR_LMPDRI_Pos (24U)
8519 #define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos)
8520 #define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
8521 #define ETH_MACLMIR_DRSYNCR_Pos (8U)
8522 #define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos)
8523 #define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
8524 #define ETH_MACLMIR_LSI_Pos (0U)
8525 #define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos)
8526 #define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
8527 
8528 /* Bit definition for Ethernet MTL Operation Mode Register */
8529 #define ETH_MTLOMR_CNTCLR_Pos (9U)
8530 #define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos)
8531 #define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
8532 #define ETH_MTLOMR_CNTPRST_Pos (8U)
8533 #define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos)
8534 #define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
8535 #define ETH_MTLOMR_DTXSTS_Pos (1U)
8536 #define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos)
8537 #define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
8538 
8539 /* Bit definition for Ethernet MTL Interrupt Status Register */
8540 #define ETH_MTLISR_MACIS_Pos (16U)
8541 #define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos)
8542 #define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
8543 #define ETH_MTLISR_QIS_Pos (0U)
8544 #define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos)
8545 #define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
8546 
8547 /* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
8548 #define ETH_MTLTQOMR_TTC_Pos (4U)
8549 #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos)
8550 #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
8551 #define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
8552 #define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
8553 #define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
8554 #define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
8555 #define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
8556 #define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
8557 #define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
8558 #define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
8559 #define ETH_MTLTQOMR_TSF_Pos (1U)
8560 #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos)
8561 #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
8562 #define ETH_MTLTQOMR_FTQ_Pos (0U)
8563 #define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos)
8564 #define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
8565 
8566 /* Bit definition for Ethernet MTL Tx Queue Underflow Register */
8567 #define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
8568 #define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos)
8569 #define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
8570 #define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
8571 #define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos)
8572 #define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
8573 
8574 /* Bit definition for Ethernet MTL Tx Queue Debug Register */
8575 #define ETH_MTLTQDR_STXSTSF_Pos (20U)
8576 #define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos)
8577 #define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
8578 #define ETH_MTLTQDR_PTXQ_Pos (16U)
8579 #define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos)
8580 #define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
8581 #define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
8582 #define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos)
8583 #define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
8584 #define ETH_MTLTQDR_TXQSTS_Pos (4U)
8585 #define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos)
8586 #define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
8587 #define ETH_MTLTQDR_TWCSTS_Pos (3U)
8588 #define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos)
8589 #define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
8590 #define ETH_MTLTQDR_TRCSTS_Pos (1U)
8591 #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos)
8592 #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
8593 #define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
8594 #define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
8595 #define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
8596 #define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
8597 #define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
8598 #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos)
8599 #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
8600 
8601 /* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
8602 #define ETH_MTLQICSR_RXOIE_Pos (24U)
8603 #define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos)
8604 #define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
8605 #define ETH_MTLQICSR_RXOVFIS_Pos (16U)
8606 #define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos)
8607 #define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
8608 #define ETH_MTLQICSR_TXUIE_Pos (8U)
8609 #define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos)
8610 #define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
8611 #define ETH_MTLQICSR_TXUNFIS_Pos (0U)
8612 #define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos)
8613 #define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
8614 
8615 /* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
8616 #define ETH_MTLRQOMR_RQS_Pos (20U)
8617 #define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos)
8618 #define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
8619 #define ETH_MTLRQOMR_RFD_Pos (14U)
8620 #define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos)
8621 #define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
8622 #define ETH_MTLRQOMR_RFA_Pos (8U)
8623 #define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos)
8624 #define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8625 #define ETH_MTLRQOMR_EHFC_Pos (7U)
8626 #define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos)
8627 #define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
8628 #define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
8629 #define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos)
8630 #define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
8631 #define ETH_MTLRQOMR_RSF_Pos (5U)
8632 #define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos)
8633 #define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
8634 #define ETH_MTLRQOMR_FEP_Pos (4U)
8635 #define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos)
8636 #define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
8637 #define ETH_MTLRQOMR_FUP_Pos (3U)
8638 #define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos)
8639 #define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
8640 #define ETH_MTLRQOMR_RTC_Pos (0U)
8641 #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos)
8642 #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
8643 #define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
8644 #define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
8645 #define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
8646 #define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
8647 
8648 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
8649 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
8650 #define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos)
8651 #define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
8652 #define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
8653 #define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos)
8654 #define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
8655 #define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
8656 #define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos)
8657 #define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
8658 #define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
8659 #define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos)
8660 #define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
8661 
8662 /* Bit definition for Ethernet MTL Rx Queue Debug Register */
8663 #define ETH_MTLRQDR_PRXQ_Pos (16U)
8664 #define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos)
8665 #define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
8666 #define ETH_MTLRQDR_RXQSTS_Pos (4U)
8667 #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos)
8668 #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8669 #define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
8670 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
8671 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos)
8672 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
8673 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
8674 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos)
8675 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
8676 #define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
8677 #define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos)
8678 #define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
8679 #define ETH_MTLRQDR_RRCSTS_Pos (1U)
8680 #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos)
8681 #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
8682 #define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
8683 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
8684 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos)
8685 #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
8686 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
8687 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos)
8688 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
8689 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
8690 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos)
8691 #define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
8692 #define ETH_MTLRQDR_RWCSTS_Pos (0U)
8693 #define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos)
8694 #define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
8695 
8696 /* Bit definition for Ethernet MTL Rx Queue Control Register */
8697 #define ETH_MTLRQCR_RQPA_Pos (3U)
8698 #define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos)
8699 #define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
8700 #define ETH_MTLRQCR_RQW_Pos (0U)
8701 #define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos)
8702 #define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
8703 
8704 /* Bit definition for Ethernet DMA Mode Register */
8705 #define ETH_DMAMR_INTM_Pos (16U)
8706 #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos)
8707 #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
8708 #define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos)
8709 #define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos)
8710 #define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos)
8711 #define ETH_DMAMR_PR_Pos (12U)
8712 #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos)
8713 #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
8714 #define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
8715 #define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
8716 #define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
8717 #define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
8718 #define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
8719 #define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
8720 #define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
8721 #define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
8722 #define ETH_DMAMR_TXPR_Pos (11U)
8723 #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos)
8724 #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
8725 #define ETH_DMAMR_DA_Pos (1U)
8726 #define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos)
8727 #define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
8728 #define ETH_DMAMR_SWR_Pos (0U)
8729 #define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos)
8730 #define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
8731 
8732 /* Bit definition for Ethernet DMA SysBus Mode Register */
8733 #define ETH_DMASBMR_RB_Pos (15U)
8734 #define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos)
8735 #define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
8736 #define ETH_DMASBMR_MB_Pos (14U)
8737 #define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos)
8738 #define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
8739 #define ETH_DMASBMR_AAL_Pos (12U)
8740 #define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos)
8741 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
8742 #define ETH_DMASBMR_FB_Pos (0U)
8743 #define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos)
8744 #define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
8745 
8746 /* Bit definition for Ethernet DMA Interrupt Status Register */
8747 #define ETH_DMAISR_MACIS_Pos (17U)
8748 #define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos)
8749 #define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
8750 #define ETH_DMAISR_MTLIS_Pos (16U)
8751 #define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos)
8752 #define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
8753 #define ETH_DMAISR_DMACIS_Pos (0U)
8754 #define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos)
8755 #define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
8756 
8757 /* Bit definition for Ethernet DMA Debug Status Register */
8758 #define ETH_DMADSR_TPS_Pos (12U)
8759 #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos)
8760 #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
8761 #define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
8762 #define ETH_DMADSR_TPS_FETCHING_Pos (12U)
8763 #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos)
8764 #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
8765 #define ETH_DMADSR_TPS_WAITING_Pos (13U)
8766 #define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos)
8767 #define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
8768 #define ETH_DMADSR_TPS_READING_Pos (12U)
8769 #define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos)
8770 #define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
8771 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
8772 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos)
8773 #define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8774 #define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
8775 #define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos)
8776 #define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
8777 #define ETH_DMADSR_TPS_CLOSING_Pos (12U)
8778 #define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos)
8779 #define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
8780 #define ETH_DMADSR_RPS_Pos (8U)
8781 #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos)
8782 #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
8783 #define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
8784 #define ETH_DMADSR_RPS_FETCHING_Pos (12U)
8785 #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos)
8786 #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
8787 #define ETH_DMADSR_RPS_WAITING_Pos (12U)
8788 #define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos)
8789 #define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
8790 #define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
8791 #define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos)
8792 #define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
8793 #define ETH_DMADSR_RPS_CLOSING_Pos (12U)
8794 #define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos)
8795 #define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
8796 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
8797 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos)
8798 #define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8799 #define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
8800 #define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos)
8801 #define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
8802 
8803 /* Bit definition for Ethernet DMA Channel Control Register */
8804 #define ETH_DMACCR_DSL_Pos (18U)
8805 #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos)
8806 #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
8807 #define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
8808 #define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
8809 #define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
8810 #define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
8811 #define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
8812 #define ETH_DMACCR_MSS_Pos (0U)
8813 #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos)
8814 #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
8815 
8816 /* Bit definition for Ethernet DMA Channel Tx Control Register */
8817 #define ETH_DMACTCR_TPBL_Pos (16U)
8818 #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos)
8819 #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
8820 #define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
8821 #define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
8822 #define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
8823 #define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
8824 #define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
8825 #define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
8826 #define ETH_DMACTCR_TSE_Pos (12U)
8827 #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos)
8828 #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
8829 #define ETH_DMACTCR_OSP_Pos (4U)
8830 #define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos)
8831 #define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
8832 #define ETH_DMACTCR_ST_Pos (0U)
8833 #define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos)
8834 #define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
8835 
8836 /* Bit definition for Ethernet DMA Channel Rx Control Register */
8837 #define ETH_DMACRCR_RPF_Pos (31U)
8838 #define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos)
8839 #define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
8840 #define ETH_DMACRCR_RPBL_Pos (16U)
8841 #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos)
8842 #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
8843 #define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
8844 #define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
8845 #define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
8846 #define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
8847 #define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
8848 #define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
8849 #define ETH_DMACRCR_RBSZ_Pos (1U)
8850 #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos)
8851 #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
8852 #define ETH_DMACRCR_SR_Pos (0U)
8853 #define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos)
8854 #define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
8855 
8856 /* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
8857 #define ETH_DMACTDLAR_TDESLA_Pos (2U)
8858 #define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos)
8859 #define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
8860 
8861 /* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
8862 #define ETH_DMACRDLAR_RDESLA_Pos (2U)
8863 #define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos)
8864 #define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
8865 
8866 /* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
8867 #define ETH_DMACTDTPR_TDT_Pos (2U)
8868 #define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos)
8869 #define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
8870 
8871 /* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
8872 #define ETH_DMACRDTPR_RDT_Pos (2U)
8873 #define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos)
8874 #define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
8875 
8876 /* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
8877 #define ETH_DMACTDRLR_TDRL_Pos (0U)
8878 #define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos)
8879 #define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
8880 
8881 /* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
8882 #define ETH_DMACRDRLR_RDRL_Pos (0U)
8883 #define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos)
8884 #define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
8885 
8886 /* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
8887 #define ETH_DMACIER_NIE_Pos (15U)
8888 #define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos)
8889 #define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
8890 #define ETH_DMACIER_AIE_Pos (14U)
8891 #define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos)
8892 #define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
8893 #define ETH_DMACIER_CDEE_Pos (13U)
8894 #define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos)
8895 #define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
8896 #define ETH_DMACIER_FBEE_Pos (12U)
8897 #define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos)
8898 #define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
8899 #define ETH_DMACIER_ERIE_Pos (11U)
8900 #define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos)
8901 #define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
8902 #define ETH_DMACIER_ETIE_Pos (10U)
8903 #define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos)
8904 #define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
8905 #define ETH_DMACIER_RWTE_Pos (9U)
8906 #define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos)
8907 #define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
8908 #define ETH_DMACIER_RSE_Pos (8U)
8909 #define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos)
8910 #define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
8911 #define ETH_DMACIER_RBUE_Pos (7U)
8912 #define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos)
8913 #define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
8914 #define ETH_DMACIER_RIE_Pos (6U)
8915 #define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos)
8916 #define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
8917 #define ETH_DMACIER_TBUE_Pos (2U)
8918 #define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos)
8919 #define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
8920 #define ETH_DMACIER_TXSE_Pos (1U)
8921 #define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos)
8922 #define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
8923 #define ETH_DMACIER_TIE_Pos (0U)
8924 #define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos)
8925 #define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
8926 
8927 /* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
8928 #define ETH_DMACRIWTR_RWT_Pos (0U)
8929 #define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos)
8930 #define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
8931 
8932 /* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
8933 #define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
8934 #define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos)
8935 #define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
8936 
8937 /* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
8938 #define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
8939 #define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos)
8940 #define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
8941 
8942 /* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
8943 #define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
8944 #define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos)
8945 #define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
8946 
8947 /* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
8948 #define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
8949 #define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos)
8950 #define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
8951 
8952 /* Bit definition for Ethernet DMA Channel Status Register */
8953 #define ETH_DMACSR_REB_Pos (19U)
8954 #define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos)
8955 #define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
8956 #define ETH_DMACSR_TEB_Pos (16U)
8957 #define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos)
8958 #define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
8959 #define ETH_DMACSR_NIS_Pos (15U)
8960 #define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos)
8961 #define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
8962 #define ETH_DMACSR_AIS_Pos (14U)
8963 #define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos)
8964 #define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
8965 #define ETH_DMACSR_CDE_Pos (13U)
8966 #define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos)
8967 #define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
8968 #define ETH_DMACSR_FBE_Pos (12U)
8969 #define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos)
8970 #define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
8971 #define ETH_DMACSR_ERI_Pos (11U)
8972 #define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos)
8973 #define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
8974 #define ETH_DMACSR_ETI_Pos (10U)
8975 #define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos)
8976 #define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
8977 #define ETH_DMACSR_RWT_Pos (9U)
8978 #define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos)
8979 #define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
8980 #define ETH_DMACSR_RPS_Pos (8U)
8981 #define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos)
8982 #define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
8983 #define ETH_DMACSR_RBU_Pos (7U)
8984 #define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos)
8985 #define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
8986 #define ETH_DMACSR_RI_Pos (6U)
8987 #define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos)
8988 #define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
8989 #define ETH_DMACSR_TBU_Pos (2U)
8990 #define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos)
8991 #define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
8992 #define ETH_DMACSR_TPS_Pos (1U)
8993 #define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos)
8994 #define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
8995 #define ETH_DMACSR_TI_Pos (0U)
8996 #define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos)
8997 #define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
8998 
8999 /* Bit definition for Ethernet DMA Channel missed frame count register */
9000 #define ETH_DMACMFCR_MFCO_Pos (15U)
9001 #define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos)
9002 #define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
9003 #define ETH_DMACMFCR_MFC_Pos (0U)
9004 #define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos)
9005 #define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
9006 
9007 /******************************************************************************/
9008 /* */
9009 /* DMA Controller */
9010 /* */
9011 /******************************************************************************/
9012 /******************** Bits definition for DMA_SxCR register *****************/
9013 #define DMA_SxCR_MBURST_Pos (23U)
9014 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
9015 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
9016 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
9017 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
9018 #define DMA_SxCR_PBURST_Pos (21U)
9019 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
9020 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
9021 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
9022 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
9023 #define DMA_SxCR_TRBUFF_Pos (20U)
9024 #define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos)
9025 #define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk
9026 #define DMA_SxCR_CT_Pos (19U)
9027 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
9028 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
9029 #define DMA_SxCR_DBM_Pos (18U)
9030 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
9031 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
9032 #define DMA_SxCR_PL_Pos (16U)
9033 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
9034 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
9035 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
9036 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
9037 #define DMA_SxCR_PINCOS_Pos (15U)
9038 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
9039 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
9040 #define DMA_SxCR_MSIZE_Pos (13U)
9041 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
9042 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
9043 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
9044 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
9045 #define DMA_SxCR_PSIZE_Pos (11U)
9046 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
9047 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
9048 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
9049 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
9050 #define DMA_SxCR_MINC_Pos (10U)
9051 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
9052 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
9053 #define DMA_SxCR_PINC_Pos (9U)
9054 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
9055 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
9056 #define DMA_SxCR_CIRC_Pos (8U)
9057 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
9058 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
9059 #define DMA_SxCR_DIR_Pos (6U)
9060 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
9061 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
9062 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
9063 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
9064 #define DMA_SxCR_PFCTRL_Pos (5U)
9065 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
9066 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
9067 #define DMA_SxCR_TCIE_Pos (4U)
9068 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
9069 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
9070 #define DMA_SxCR_HTIE_Pos (3U)
9071 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
9072 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
9073 #define DMA_SxCR_TEIE_Pos (2U)
9074 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
9075 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
9076 #define DMA_SxCR_DMEIE_Pos (1U)
9077 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
9078 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
9079 #define DMA_SxCR_EN_Pos (0U)
9080 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
9081 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
9083 /******************** Bits definition for DMA_SxCNDTR register **************/
9084 #define DMA_SxNDT_Pos (0U)
9085 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
9086 #define DMA_SxNDT DMA_SxNDT_Msk
9087 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
9088 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
9089 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
9090 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
9091 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
9092 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
9093 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
9094 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
9095 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
9096 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
9097 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
9098 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
9099 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
9100 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
9101 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
9102 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
9104 /******************** Bits definition for DMA_SxFCR register ****************/
9105 #define DMA_SxFCR_FEIE_Pos (7U)
9106 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
9107 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
9108 #define DMA_SxFCR_FS_Pos (3U)
9109 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
9110 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
9111 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
9112 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
9113 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
9114 #define DMA_SxFCR_DMDIS_Pos (2U)
9115 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
9116 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
9117 #define DMA_SxFCR_FTH_Pos (0U)
9118 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
9119 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
9120 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
9121 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
9123 /******************** Bits definition for DMA_LISR register *****************/
9124 #define DMA_LISR_TCIF3_Pos (27U)
9125 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
9126 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
9127 #define DMA_LISR_HTIF3_Pos (26U)
9128 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
9129 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
9130 #define DMA_LISR_TEIF3_Pos (25U)
9131 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
9132 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
9133 #define DMA_LISR_DMEIF3_Pos (24U)
9134 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
9135 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
9136 #define DMA_LISR_FEIF3_Pos (22U)
9137 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
9138 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
9139 #define DMA_LISR_TCIF2_Pos (21U)
9140 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
9141 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
9142 #define DMA_LISR_HTIF2_Pos (20U)
9143 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
9144 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
9145 #define DMA_LISR_TEIF2_Pos (19U)
9146 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
9147 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
9148 #define DMA_LISR_DMEIF2_Pos (18U)
9149 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
9150 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
9151 #define DMA_LISR_FEIF2_Pos (16U)
9152 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
9153 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
9154 #define DMA_LISR_TCIF1_Pos (11U)
9155 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
9156 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
9157 #define DMA_LISR_HTIF1_Pos (10U)
9158 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
9159 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
9160 #define DMA_LISR_TEIF1_Pos (9U)
9161 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
9162 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
9163 #define DMA_LISR_DMEIF1_Pos (8U)
9164 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
9165 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
9166 #define DMA_LISR_FEIF1_Pos (6U)
9167 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
9168 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
9169 #define DMA_LISR_TCIF0_Pos (5U)
9170 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
9171 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
9172 #define DMA_LISR_HTIF0_Pos (4U)
9173 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
9174 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
9175 #define DMA_LISR_TEIF0_Pos (3U)
9176 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
9177 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
9178 #define DMA_LISR_DMEIF0_Pos (2U)
9179 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
9180 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
9181 #define DMA_LISR_FEIF0_Pos (0U)
9182 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
9183 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
9185 /******************** Bits definition for DMA_HISR register *****************/
9186 #define DMA_HISR_TCIF7_Pos (27U)
9187 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
9188 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
9189 #define DMA_HISR_HTIF7_Pos (26U)
9190 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
9191 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
9192 #define DMA_HISR_TEIF7_Pos (25U)
9193 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
9194 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
9195 #define DMA_HISR_DMEIF7_Pos (24U)
9196 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
9197 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
9198 #define DMA_HISR_FEIF7_Pos (22U)
9199 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
9200 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
9201 #define DMA_HISR_TCIF6_Pos (21U)
9202 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
9203 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
9204 #define DMA_HISR_HTIF6_Pos (20U)
9205 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
9206 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
9207 #define DMA_HISR_TEIF6_Pos (19U)
9208 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
9209 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
9210 #define DMA_HISR_DMEIF6_Pos (18U)
9211 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
9212 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
9213 #define DMA_HISR_FEIF6_Pos (16U)
9214 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
9215 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
9216 #define DMA_HISR_TCIF5_Pos (11U)
9217 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
9218 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
9219 #define DMA_HISR_HTIF5_Pos (10U)
9220 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
9221 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
9222 #define DMA_HISR_TEIF5_Pos (9U)
9223 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
9224 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
9225 #define DMA_HISR_DMEIF5_Pos (8U)
9226 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
9227 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
9228 #define DMA_HISR_FEIF5_Pos (6U)
9229 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
9230 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
9231 #define DMA_HISR_TCIF4_Pos (5U)
9232 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
9233 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
9234 #define DMA_HISR_HTIF4_Pos (4U)
9235 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
9236 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
9237 #define DMA_HISR_TEIF4_Pos (3U)
9238 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
9239 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
9240 #define DMA_HISR_DMEIF4_Pos (2U)
9241 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
9242 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
9243 #define DMA_HISR_FEIF4_Pos (0U)
9244 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
9245 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
9247 /******************** Bits definition for DMA_LIFCR register ****************/
9248 #define DMA_LIFCR_CTCIF3_Pos (27U)
9249 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
9250 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
9251 #define DMA_LIFCR_CHTIF3_Pos (26U)
9252 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
9253 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
9254 #define DMA_LIFCR_CTEIF3_Pos (25U)
9255 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
9256 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
9257 #define DMA_LIFCR_CDMEIF3_Pos (24U)
9258 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
9259 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
9260 #define DMA_LIFCR_CFEIF3_Pos (22U)
9261 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
9262 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
9263 #define DMA_LIFCR_CTCIF2_Pos (21U)
9264 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
9265 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
9266 #define DMA_LIFCR_CHTIF2_Pos (20U)
9267 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
9268 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
9269 #define DMA_LIFCR_CTEIF2_Pos (19U)
9270 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
9271 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
9272 #define DMA_LIFCR_CDMEIF2_Pos (18U)
9273 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
9274 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
9275 #define DMA_LIFCR_CFEIF2_Pos (16U)
9276 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
9277 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
9278 #define DMA_LIFCR_CTCIF1_Pos (11U)
9279 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
9280 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
9281 #define DMA_LIFCR_CHTIF1_Pos (10U)
9282 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
9283 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
9284 #define DMA_LIFCR_CTEIF1_Pos (9U)
9285 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
9286 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
9287 #define DMA_LIFCR_CDMEIF1_Pos (8U)
9288 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
9289 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
9290 #define DMA_LIFCR_CFEIF1_Pos (6U)
9291 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
9292 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
9293 #define DMA_LIFCR_CTCIF0_Pos (5U)
9294 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
9295 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
9296 #define DMA_LIFCR_CHTIF0_Pos (4U)
9297 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
9298 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
9299 #define DMA_LIFCR_CTEIF0_Pos (3U)
9300 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
9301 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
9302 #define DMA_LIFCR_CDMEIF0_Pos (2U)
9303 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
9304 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
9305 #define DMA_LIFCR_CFEIF0_Pos (0U)
9306 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
9307 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
9309 /******************** Bits definition for DMA_HIFCR register ****************/
9310 #define DMA_HIFCR_CTCIF7_Pos (27U)
9311 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
9312 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
9313 #define DMA_HIFCR_CHTIF7_Pos (26U)
9314 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
9315 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
9316 #define DMA_HIFCR_CTEIF7_Pos (25U)
9317 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
9318 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
9319 #define DMA_HIFCR_CDMEIF7_Pos (24U)
9320 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
9321 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
9322 #define DMA_HIFCR_CFEIF7_Pos (22U)
9323 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
9324 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
9325 #define DMA_HIFCR_CTCIF6_Pos (21U)
9326 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
9327 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
9328 #define DMA_HIFCR_CHTIF6_Pos (20U)
9329 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
9330 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
9331 #define DMA_HIFCR_CTEIF6_Pos (19U)
9332 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
9333 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
9334 #define DMA_HIFCR_CDMEIF6_Pos (18U)
9335 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
9336 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
9337 #define DMA_HIFCR_CFEIF6_Pos (16U)
9338 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
9339 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
9340 #define DMA_HIFCR_CTCIF5_Pos (11U)
9341 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
9342 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
9343 #define DMA_HIFCR_CHTIF5_Pos (10U)
9344 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
9345 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
9346 #define DMA_HIFCR_CTEIF5_Pos (9U)
9347 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
9348 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
9349 #define DMA_HIFCR_CDMEIF5_Pos (8U)
9350 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
9351 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
9352 #define DMA_HIFCR_CFEIF5_Pos (6U)
9353 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
9354 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
9355 #define DMA_HIFCR_CTCIF4_Pos (5U)
9356 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
9357 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
9358 #define DMA_HIFCR_CHTIF4_Pos (4U)
9359 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
9360 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
9361 #define DMA_HIFCR_CTEIF4_Pos (3U)
9362 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
9363 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
9364 #define DMA_HIFCR_CDMEIF4_Pos (2U)
9365 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
9366 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
9367 #define DMA_HIFCR_CFEIF4_Pos (0U)
9368 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
9369 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
9371 /****************** Bit definition for DMA_SxPAR register ********************/
9372 #define DMA_SxPAR_PA_Pos (0U)
9373 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
9374 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
9376 /****************** Bit definition for DMA_SxM0AR register ********************/
9377 #define DMA_SxM0AR_M0A_Pos (0U)
9378 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
9379 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
9381 /****************** Bit definition for DMA_SxM1AR register ********************/
9382 #define DMA_SxM1AR_M1A_Pos (0U)
9383 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
9384 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
9386 /******************************************************************************/
9387 /* */
9388 /* DMAMUX Controller */
9389 /* */
9390 /******************************************************************************/
9391 /******************** Bits definition for DMAMUX_CxCR register **************/
9392 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
9393 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9394 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
9395 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9396 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9397 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9398 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9399 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9400 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9401 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9402 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9403 #define DMAMUX_CxCR_SOIE_Pos (8U)
9404 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)
9405 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
9406 #define DMAMUX_CxCR_EGE_Pos (9U)
9407 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)
9408 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
9409 #define DMAMUX_CxCR_SE_Pos (16U)
9410 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)
9411 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
9412 #define DMAMUX_CxCR_SPOL_Pos (17U)
9413 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)
9414 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
9415 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)
9416 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)
9417 #define DMAMUX_CxCR_NBREQ_Pos (19U)
9418 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)
9419 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
9420 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)
9421 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)
9422 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)
9423 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)
9424 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)
9425 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
9426 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)
9427 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
9428 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)
9429 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)
9430 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)
9431 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)
9432 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)
9434 /******************** Bits definition for DMAMUX_CSR register **************/
9435 #define DMAMUX_CSR_SOF0_Pos (0U)
9436 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)
9437 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
9438 #define DMAMUX_CSR_SOF1_Pos (1U)
9439 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)
9440 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
9441 #define DMAMUX_CSR_SOF2_Pos (2U)
9442 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)
9443 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
9444 #define DMAMUX_CSR_SOF3_Pos (3U)
9445 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)
9446 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
9447 #define DMAMUX_CSR_SOF4_Pos (4U)
9448 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)
9449 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
9450 #define DMAMUX_CSR_SOF5_Pos (5U)
9451 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)
9452 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
9453 #define DMAMUX_CSR_SOF6_Pos (6U)
9454 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)
9455 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
9456 #define DMAMUX_CSR_SOF7_Pos (7U)
9457 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)
9458 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
9459 #define DMAMUX_CSR_SOF8_Pos (8U)
9460 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)
9461 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
9462 #define DMAMUX_CSR_SOF9_Pos (9U)
9463 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)
9464 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
9465 #define DMAMUX_CSR_SOF10_Pos (10U)
9466 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)
9467 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
9468 #define DMAMUX_CSR_SOF11_Pos (11U)
9469 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)
9470 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
9471 #define DMAMUX_CSR_SOF12_Pos (12U)
9472 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)
9473 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
9474 #define DMAMUX_CSR_SOF13_Pos (13U)
9475 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)
9476 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
9477 #define DMAMUX_CSR_SOF14_Pos (14U)
9478 #define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)
9479 #define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
9480 #define DMAMUX_CSR_SOF15_Pos (15U)
9481 #define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)
9482 #define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
9484 /******************** Bits definition for DMAMUX_CFR register **************/
9485 #define DMAMUX_CFR_CSOF0_Pos (0U)
9486 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)
9487 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
9488 #define DMAMUX_CFR_CSOF1_Pos (1U)
9489 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)
9490 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
9491 #define DMAMUX_CFR_CSOF2_Pos (2U)
9492 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)
9493 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
9494 #define DMAMUX_CFR_CSOF3_Pos (3U)
9495 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)
9496 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
9497 #define DMAMUX_CFR_CSOF4_Pos (4U)
9498 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)
9499 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
9500 #define DMAMUX_CFR_CSOF5_Pos (5U)
9501 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)
9502 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
9503 #define DMAMUX_CFR_CSOF6_Pos (6U)
9504 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)
9505 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
9506 #define DMAMUX_CFR_CSOF7_Pos (7U)
9507 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)
9508 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
9509 #define DMAMUX_CFR_CSOF8_Pos (8U)
9510 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)
9511 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
9512 #define DMAMUX_CFR_CSOF9_Pos (9U)
9513 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)
9514 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
9515 #define DMAMUX_CFR_CSOF10_Pos (10U)
9516 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)
9517 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
9518 #define DMAMUX_CFR_CSOF11_Pos (11U)
9519 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)
9520 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
9521 #define DMAMUX_CFR_CSOF12_Pos (12U)
9522 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)
9523 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
9524 #define DMAMUX_CFR_CSOF13_Pos (13U)
9525 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)
9526 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
9527 #define DMAMUX_CFR_CSOF14_Pos (14U)
9528 #define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)
9529 #define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
9530 #define DMAMUX_CFR_CSOF15_Pos (15U)
9531 #define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)
9532 #define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
9534 /******************** Bits definition for DMAMUX_RGxCR register ************/
9535 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
9536 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)
9537 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
9538 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)
9539 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)
9540 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)
9541 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)
9542 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)
9543 #define DMAMUX_RGxCR_OIE_Pos (8U)
9544 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)
9545 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
9546 #define DMAMUX_RGxCR_GE_Pos (16U)
9547 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)
9548 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
9549 #define DMAMUX_RGxCR_GPOL_Pos (17U)
9550 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)
9551 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
9552 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)
9553 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)
9554 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
9555 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)
9556 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
9557 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)
9558 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)
9559 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)
9560 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)
9561 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)
9563 /******************** Bits definition for DMAMUX_RGSR register **************/
9564 #define DMAMUX_RGSR_OF0_Pos (0U)
9565 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)
9566 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
9567 #define DMAMUX_RGSR_OF1_Pos (1U)
9568 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)
9569 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
9570 #define DMAMUX_RGSR_OF2_Pos (2U)
9571 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)
9572 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
9573 #define DMAMUX_RGSR_OF3_Pos (3U)
9574 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)
9575 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
9576 #define DMAMUX_RGSR_OF4_Pos (4U)
9577 #define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos)
9578 #define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk
9579 #define DMAMUX_RGSR_OF5_Pos (5U)
9580 #define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos)
9581 #define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk
9582 #define DMAMUX_RGSR_OF6_Pos (6U)
9583 #define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos)
9584 #define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk
9585 #define DMAMUX_RGSR_OF7_Pos (7U)
9586 #define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos)
9587 #define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk
9589 /******************** Bits definition for DMAMUX_RGCFR register **************/
9590 #define DMAMUX_RGCFR_COF0_Pos (0U)
9591 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)
9592 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
9593 #define DMAMUX_RGCFR_COF1_Pos (1U)
9594 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)
9595 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
9596 #define DMAMUX_RGCFR_COF2_Pos (2U)
9597 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)
9598 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
9599 #define DMAMUX_RGCFR_COF3_Pos (3U)
9600 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)
9601 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
9602 #define DMAMUX_RGCFR_COF4_Pos (4U)
9603 #define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos)
9604 #define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk
9605 #define DMAMUX_RGCFR_COF5_Pos (5U)
9606 #define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos)
9607 #define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk
9608 #define DMAMUX_RGCFR_COF6_Pos (6U)
9609 #define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos)
9610 #define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk
9611 #define DMAMUX_RGCFR_COF7_Pos (7U)
9612 #define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos)
9613 #define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk
9615 /******************************************************************************/
9616 /* */
9617 /* AHB Master DMA2D Controller (DMA2D) */
9618 /* */
9619 /******************************************************************************/
9620 
9621 /******************** Bit definition for DMA2D_CR register ******************/
9622 
9623 #define DMA2D_CR_START_Pos (0U)
9624 #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
9625 #define DMA2D_CR_START DMA2D_CR_START_Msk
9626 #define DMA2D_CR_SUSP_Pos (1U)
9627 #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
9628 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
9629 #define DMA2D_CR_ABORT_Pos (2U)
9630 #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
9631 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
9632 #define DMA2D_CR_LOM_Pos (6U)
9633 #define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos)
9634 #define DMA2D_CR_LOM DMA2D_CR_LOM_Msk
9635 #define DMA2D_CR_TEIE_Pos (8U)
9636 #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
9637 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
9638 #define DMA2D_CR_TCIE_Pos (9U)
9639 #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
9640 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
9641 #define DMA2D_CR_TWIE_Pos (10U)
9642 #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
9643 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
9644 #define DMA2D_CR_CAEIE_Pos (11U)
9645 #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
9646 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
9647 #define DMA2D_CR_CTCIE_Pos (12U)
9648 #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
9649 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
9650 #define DMA2D_CR_CEIE_Pos (13U)
9651 #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
9652 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
9653 #define DMA2D_CR_MODE_Pos (16U)
9654 #define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos)
9655 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
9656 #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
9657 #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
9658 #define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos)
9660 /******************** Bit definition for DMA2D_ISR register *****************/
9661 
9662 #define DMA2D_ISR_TEIF_Pos (0U)
9663 #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
9664 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
9665 #define DMA2D_ISR_TCIF_Pos (1U)
9666 #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
9667 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
9668 #define DMA2D_ISR_TWIF_Pos (2U)
9669 #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
9670 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
9671 #define DMA2D_ISR_CAEIF_Pos (3U)
9672 #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
9673 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
9674 #define DMA2D_ISR_CTCIF_Pos (4U)
9675 #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
9676 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
9677 #define DMA2D_ISR_CEIF_Pos (5U)
9678 #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
9679 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
9681 /******************** Bit definition for DMA2D_IFCR register ****************/
9682 
9683 #define DMA2D_IFCR_CTEIF_Pos (0U)
9684 #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
9685 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
9686 #define DMA2D_IFCR_CTCIF_Pos (1U)
9687 #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
9688 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
9689 #define DMA2D_IFCR_CTWIF_Pos (2U)
9690 #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
9691 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
9692 #define DMA2D_IFCR_CAECIF_Pos (3U)
9693 #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
9694 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
9695 #define DMA2D_IFCR_CCTCIF_Pos (4U)
9696 #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
9697 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
9698 #define DMA2D_IFCR_CCEIF_Pos (5U)
9699 #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
9700 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
9702 /******************** Bit definition for DMA2D_FGMAR register ***************/
9703 
9704 #define DMA2D_FGMAR_MA_Pos (0U)
9705 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
9706 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
9708 /******************** Bit definition for DMA2D_FGOR register ****************/
9709 
9710 #define DMA2D_FGOR_LO_Pos (0U)
9711 #define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos)
9712 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
9714 /******************** Bit definition for DMA2D_BGMAR register ***************/
9715 
9716 #define DMA2D_BGMAR_MA_Pos (0U)
9717 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
9718 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
9720 /******************** Bit definition for DMA2D_BGOR register ****************/
9721 
9722 #define DMA2D_BGOR_LO_Pos (0U)
9723 #define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos)
9724 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
9726 /******************** Bit definition for DMA2D_FGPFCCR register *************/
9727 
9728 #define DMA2D_FGPFCCR_CM_Pos (0U)
9729 #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
9730 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
9731 #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
9732 #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
9733 #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
9734 #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
9735 #define DMA2D_FGPFCCR_CCM_Pos (4U)
9736 #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
9737 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
9738 #define DMA2D_FGPFCCR_START_Pos (5U)
9739 #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
9740 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
9741 #define DMA2D_FGPFCCR_CS_Pos (8U)
9742 #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
9743 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
9744 #define DMA2D_FGPFCCR_AM_Pos (16U)
9745 #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
9746 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
9747 #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
9748 #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
9749 #define DMA2D_FGPFCCR_CSS_Pos (18U)
9750 #define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos)
9751 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
9752 #define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos)
9753 #define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos)
9754 #define DMA2D_FGPFCCR_AI_Pos (20U)
9755 #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos)
9756 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk
9757 #define DMA2D_FGPFCCR_RBS_Pos (21U)
9758 #define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
9759 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk
9760 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
9761 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
9762 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
9764 /******************** Bit definition for DMA2D_FGCOLR register **************/
9765 
9766 #define DMA2D_FGCOLR_BLUE_Pos (0U)
9767 #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
9768 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
9769 #define DMA2D_FGCOLR_GREEN_Pos (8U)
9770 #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
9771 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
9772 #define DMA2D_FGCOLR_RED_Pos (16U)
9773 #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
9774 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
9776 /******************** Bit definition for DMA2D_BGPFCCR register *************/
9777 
9778 #define DMA2D_BGPFCCR_CM_Pos (0U)
9779 #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
9780 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
9781 #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
9782 #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
9783 #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
9784 #define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos)
9785 #define DMA2D_BGPFCCR_CCM_Pos (4U)
9786 #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
9787 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
9788 #define DMA2D_BGPFCCR_START_Pos (5U)
9789 #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
9790 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
9791 #define DMA2D_BGPFCCR_CS_Pos (8U)
9792 #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
9793 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
9794 #define DMA2D_BGPFCCR_AM_Pos (16U)
9795 #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
9796 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
9797 #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
9798 #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
9799 #define DMA2D_BGPFCCR_AI_Pos (20U)
9800 #define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos)
9801 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk
9802 #define DMA2D_BGPFCCR_RBS_Pos (21U)
9803 #define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
9804 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk
9805 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
9806 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
9807 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
9809 /******************** Bit definition for DMA2D_BGCOLR register **************/
9810 
9811 #define DMA2D_BGCOLR_BLUE_Pos (0U)
9812 #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
9813 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
9814 #define DMA2D_BGCOLR_GREEN_Pos (8U)
9815 #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
9816 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
9817 #define DMA2D_BGCOLR_RED_Pos (16U)
9818 #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
9819 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
9821 /******************** Bit definition for DMA2D_FGCMAR register **************/
9822 
9823 #define DMA2D_FGCMAR_MA_Pos (0U)
9824 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
9825 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
9827 /******************** Bit definition for DMA2D_BGCMAR register **************/
9828 
9829 #define DMA2D_BGCMAR_MA_Pos (0U)
9830 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
9831 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
9833 /******************** Bit definition for DMA2D_OPFCCR register **************/
9834 
9835 #define DMA2D_OPFCCR_CM_Pos (0U)
9836 #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
9837 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
9838 #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
9839 #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
9840 #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
9841 #define DMA2D_OPFCCR_SB_Pos (8U)
9842 #define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos)
9843 #define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk
9844 #define DMA2D_OPFCCR_AI_Pos (20U)
9845 #define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos)
9846 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk
9847 #define DMA2D_OPFCCR_RBS_Pos (21U)
9848 #define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos)
9849 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk
9851 /******************** Bit definition for DMA2D_OCOLR register ***************/
9852 
9855 #define DMA2D_OCOLR_BLUE_1_Pos (0U)
9856 #define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
9857 #define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk
9858 #define DMA2D_OCOLR_GREEN_1_Pos (8U)
9859 #define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
9860 #define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk
9861 #define DMA2D_OCOLR_RED_1_Pos (16U)
9862 #define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
9863 #define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk
9864 #define DMA2D_OCOLR_ALPHA_1_Pos (24U)
9865 #define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
9866 #define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk
9869 #define DMA2D_OCOLR_BLUE_2_Pos (0U)
9870 #define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
9871 #define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk
9872 #define DMA2D_OCOLR_GREEN_2_Pos (5U)
9873 #define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
9874 #define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk
9875 #define DMA2D_OCOLR_RED_2_Pos (11U)
9876 #define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
9877 #define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk
9880 #define DMA2D_OCOLR_BLUE_3_Pos (0U)
9881 #define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
9882 #define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk
9883 #define DMA2D_OCOLR_GREEN_3_Pos (5U)
9884 #define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
9885 #define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk
9886 #define DMA2D_OCOLR_RED_3_Pos (10U)
9887 #define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
9888 #define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk
9889 #define DMA2D_OCOLR_ALPHA_3_Pos (15U)
9890 #define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
9891 #define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk
9894 #define DMA2D_OCOLR_BLUE_4_Pos (0U)
9895 #define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
9896 #define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk
9897 #define DMA2D_OCOLR_GREEN_4_Pos (4U)
9898 #define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
9899 #define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk
9900 #define DMA2D_OCOLR_RED_4_Pos (8U)
9901 #define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
9902 #define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk
9903 #define DMA2D_OCOLR_ALPHA_4_Pos (12U)
9904 #define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
9905 #define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk
9907 /******************** Bit definition for DMA2D_OMAR register ****************/
9908 
9909 #define DMA2D_OMAR_MA_Pos (0U)
9910 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
9911 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
9913 /******************** Bit definition for DMA2D_OOR register *****************/
9914 
9915 #define DMA2D_OOR_LO_Pos (0U)
9916 #define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos)
9917 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
9919 /******************** Bit definition for DMA2D_NLR register *****************/
9920 
9921 #define DMA2D_NLR_NL_Pos (0U)
9922 #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
9923 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
9924 #define DMA2D_NLR_PL_Pos (16U)
9925 #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
9926 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
9928 /******************** Bit definition for DMA2D_LWR register *****************/
9929 
9930 #define DMA2D_LWR_LW_Pos (0U)
9931 #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
9932 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
9934 /******************** Bit definition for DMA2D_AMTCR register ***************/
9935 
9936 #define DMA2D_AMTCR_EN_Pos (0U)
9937 #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
9938 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
9939 #define DMA2D_AMTCR_DT_Pos (8U)
9940 #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
9941 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
9944 /******************** Bit definition for DMA2D_FGCLUT register **************/
9945 
9946 /******************** Bit definition for DMA2D_BGCLUT register **************/
9947 
9948 
9949 /******************************************************************************/
9950 /* */
9951 /* External Interrupt/Event Controller */
9952 /* */
9953 /******************************************************************************/
9954 /****************** Bit definition for EXTI_RTSR1 register *******************/
9955 #define EXTI_RTSR1_TR_Pos (0U)
9956 #define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)
9957 #define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk
9958 #define EXTI_RTSR1_TR0_Pos (0U)
9959 #define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos)
9960 #define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk
9961 #define EXTI_RTSR1_TR1_Pos (1U)
9962 #define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos)
9963 #define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk
9964 #define EXTI_RTSR1_TR2_Pos (2U)
9965 #define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos)
9966 #define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk
9967 #define EXTI_RTSR1_TR3_Pos (3U)
9968 #define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos)
9969 #define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk
9970 #define EXTI_RTSR1_TR4_Pos (4U)
9971 #define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos)
9972 #define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk
9973 #define EXTI_RTSR1_TR5_Pos (5U)
9974 #define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos)
9975 #define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk
9976 #define EXTI_RTSR1_TR6_Pos (6U)
9977 #define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos)
9978 #define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk
9979 #define EXTI_RTSR1_TR7_Pos (7U)
9980 #define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos)
9981 #define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk
9982 #define EXTI_RTSR1_TR8_Pos (8U)
9983 #define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos)
9984 #define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk
9985 #define EXTI_RTSR1_TR9_Pos (9U)
9986 #define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos)
9987 #define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk
9988 #define EXTI_RTSR1_TR10_Pos (10U)
9989 #define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos)
9990 #define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk
9991 #define EXTI_RTSR1_TR11_Pos (11U)
9992 #define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos)
9993 #define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk
9994 #define EXTI_RTSR1_TR12_Pos (12U)
9995 #define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos)
9996 #define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk
9997 #define EXTI_RTSR1_TR13_Pos (13U)
9998 #define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos)
9999 #define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk
10000 #define EXTI_RTSR1_TR14_Pos (14U)
10001 #define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos)
10002 #define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk
10003 #define EXTI_RTSR1_TR15_Pos (15U)
10004 #define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos)
10005 #define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk
10006 #define EXTI_RTSR1_TR16_Pos (16U)
10007 #define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos)
10008 #define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk
10009 #define EXTI_RTSR1_TR17_Pos (17U)
10010 #define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos)
10011 #define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk
10012 #define EXTI_RTSR1_TR18_Pos (18U)
10013 #define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos)
10014 #define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk
10015 #define EXTI_RTSR1_TR19_Pos (19U)
10016 #define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos)
10017 #define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk
10018 #define EXTI_RTSR1_TR20_Pos (20U)
10019 #define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos)
10020 #define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk
10021 #define EXTI_RTSR1_TR21_Pos (21U)
10022 #define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos)
10023 #define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk
10025 /****************** Bit definition for EXTI_FTSR1 register *******************/
10026 #define EXTI_FTSR1_TR_Pos (0U)
10027 #define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)
10028 #define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk
10029 #define EXTI_FTSR1_TR0_Pos (0U)
10030 #define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos)
10031 #define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk
10032 #define EXTI_FTSR1_TR1_Pos (1U)
10033 #define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos)
10034 #define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk
10035 #define EXTI_FTSR1_TR2_Pos (2U)
10036 #define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos)
10037 #define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk
10038 #define EXTI_FTSR1_TR3_Pos (3U)
10039 #define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos)
10040 #define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk
10041 #define EXTI_FTSR1_TR4_Pos (4U)
10042 #define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos)
10043 #define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk
10044 #define EXTI_FTSR1_TR5_Pos (5U)
10045 #define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos)
10046 #define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk
10047 #define EXTI_FTSR1_TR6_Pos (6U)
10048 #define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos)
10049 #define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk
10050 #define EXTI_FTSR1_TR7_Pos (7U)
10051 #define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos)
10052 #define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk
10053 #define EXTI_FTSR1_TR8_Pos (8U)
10054 #define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos)
10055 #define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk
10056 #define EXTI_FTSR1_TR9_Pos (9U)
10057 #define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos)
10058 #define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk
10059 #define EXTI_FTSR1_TR10_Pos (10U)
10060 #define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos)
10061 #define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk
10062 #define EXTI_FTSR1_TR11_Pos (11U)
10063 #define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos)
10064 #define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk
10065 #define EXTI_FTSR1_TR12_Pos (12U)
10066 #define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos)
10067 #define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk
10068 #define EXTI_FTSR1_TR13_Pos (13U)
10069 #define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos)
10070 #define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk
10071 #define EXTI_FTSR1_TR14_Pos (14U)
10072 #define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos)
10073 #define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk
10074 #define EXTI_FTSR1_TR15_Pos (15U)
10075 #define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos)
10076 #define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk
10077 #define EXTI_FTSR1_TR16_Pos (16U)
10078 #define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos)
10079 #define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk
10080 #define EXTI_FTSR1_TR17_Pos (17U)
10081 #define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos)
10082 #define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk
10083 #define EXTI_FTSR1_TR18_Pos (18U)
10084 #define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos)
10085 #define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk
10086 #define EXTI_FTSR1_TR19_Pos (19U)
10087 #define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos)
10088 #define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk
10089 #define EXTI_FTSR1_TR20_Pos (20U)
10090 #define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos)
10091 #define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk
10092 #define EXTI_FTSR1_TR21_Pos (21U)
10093 #define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos)
10094 #define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk
10096 /****************** Bit definition for EXTI_SWIER1 register ******************/
10097 #define EXTI_SWIER1_SWIER0_Pos (0U)
10098 #define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos)
10099 #define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk
10100 #define EXTI_SWIER1_SWIER1_Pos (1U)
10101 #define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos)
10102 #define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk
10103 #define EXTI_SWIER1_SWIER2_Pos (2U)
10104 #define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos)
10105 #define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk
10106 #define EXTI_SWIER1_SWIER3_Pos (3U)
10107 #define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos)
10108 #define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk
10109 #define EXTI_SWIER1_SWIER4_Pos (4U)
10110 #define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos)
10111 #define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk
10112 #define EXTI_SWIER1_SWIER5_Pos (5U)
10113 #define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos)
10114 #define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk
10115 #define EXTI_SWIER1_SWIER6_Pos (6U)
10116 #define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos)
10117 #define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk
10118 #define EXTI_SWIER1_SWIER7_Pos (7U)
10119 #define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos)
10120 #define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk
10121 #define EXTI_SWIER1_SWIER8_Pos (8U)
10122 #define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos)
10123 #define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk
10124 #define EXTI_SWIER1_SWIER9_Pos (9U)
10125 #define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos)
10126 #define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk
10127 #define EXTI_SWIER1_SWIER10_Pos (10U)
10128 #define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos)
10129 #define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk
10130 #define EXTI_SWIER1_SWIER11_Pos (11U)
10131 #define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos)
10132 #define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk
10133 #define EXTI_SWIER1_SWIER12_Pos (12U)
10134 #define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos)
10135 #define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk
10136 #define EXTI_SWIER1_SWIER13_Pos (13U)
10137 #define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos)
10138 #define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk
10139 #define EXTI_SWIER1_SWIER14_Pos (14U)
10140 #define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos)
10141 #define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk
10142 #define EXTI_SWIER1_SWIER15_Pos (15U)
10143 #define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos)
10144 #define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk
10145 #define EXTI_SWIER1_SWIER16_Pos (16U)
10146 #define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos)
10147 #define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk
10148 #define EXTI_SWIER1_SWIER17_Pos (17U)
10149 #define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos)
10150 #define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk
10151 #define EXTI_SWIER1_SWIER18_Pos (18U)
10152 #define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos)
10153 #define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk
10154 #define EXTI_SWIER1_SWIER19_Pos (19U)
10155 #define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos)
10156 #define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk
10157 #define EXTI_SWIER1_SWIER20_Pos (20U)
10158 #define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos)
10159 #define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk
10160 #define EXTI_SWIER1_SWIER21_Pos (21U)
10161 #define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos)
10162 #define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk
10164 /****************** Bit definition for EXTI_D3PMR1 register ******************/
10165 #define EXTI_D3PMR1_MR0_Pos (0U)
10166 #define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos)
10167 #define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk
10168 #define EXTI_D3PMR1_MR1_Pos (1U)
10169 #define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos)
10170 #define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk
10171 #define EXTI_D3PMR1_MR2_Pos (2U)
10172 #define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos)
10173 #define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk
10174 #define EXTI_D3PMR1_MR3_Pos (3U)
10175 #define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos)
10176 #define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk
10177 #define EXTI_D3PMR1_MR4_Pos (4U)
10178 #define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos)
10179 #define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk
10180 #define EXTI_D3PMR1_MR5_Pos (5U)
10181 #define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos)
10182 #define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk
10183 #define EXTI_D3PMR1_MR6_Pos (6U)
10184 #define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos)
10185 #define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk
10186 #define EXTI_D3PMR1_MR7_Pos (7U)
10187 #define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos)
10188 #define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk
10189 #define EXTI_D3PMR1_MR8_Pos (8U)
10190 #define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos)
10191 #define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk
10192 #define EXTI_D3PMR1_MR9_Pos (9U)
10193 #define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos)
10194 #define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk
10195 #define EXTI_D3PMR1_MR10_Pos (10U)
10196 #define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos)
10197 #define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk
10198 #define EXTI_D3PMR1_MR11_Pos (11U)
10199 #define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos)
10200 #define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk
10201 #define EXTI_D3PMR1_MR12_Pos (12U)
10202 #define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos)
10203 #define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk
10204 #define EXTI_D3PMR1_MR13_Pos (13U)
10205 #define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos)
10206 #define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk
10207 #define EXTI_D3PMR1_MR14_Pos (14U)
10208 #define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos)
10209 #define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk
10210 #define EXTI_D3PMR1_MR15_Pos (15U)
10211 #define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos)
10212 #define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk
10213 #define EXTI_D3PMR1_MR19_Pos (19U)
10214 #define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos)
10215 #define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk
10216 #define EXTI_D3PMR1_MR20_Pos (20U)
10217 #define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos)
10218 #define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk
10219 #define EXTI_D3PMR1_MR21_Pos (21U)
10220 #define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos)
10221 #define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk
10222 #define EXTI_D3PMR1_MR25_Pos (24U)
10223 #define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos)
10224 #define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk
10226 /******************* Bit definition for EXTI_D3PCR1L register ****************/
10227 #define EXTI_D3PCR1L_PCS0_Pos (0U)
10228 #define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos)
10229 #define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk
10230 #define EXTI_D3PCR1L_PCS1_Pos (2U)
10231 #define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos)
10232 #define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk
10233 #define EXTI_D3PCR1L_PCS2_Pos (4U)
10234 #define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos)
10235 #define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk
10236 #define EXTI_D3PCR1L_PCS3_Pos (6U)
10237 #define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos)
10238 #define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk
10239 #define EXTI_D3PCR1L_PCS4_Pos (8U)
10240 #define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos)
10241 #define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk
10242 #define EXTI_D3PCR1L_PCS5_Pos (10U)
10243 #define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos)
10244 #define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk
10245 #define EXTI_D3PCR1L_PCS6_Pos (12U)
10246 #define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos)
10247 #define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk
10248 #define EXTI_D3PCR1L_PCS7_Pos (14U)
10249 #define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos)
10250 #define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk
10251 #define EXTI_D3PCR1L_PCS8_Pos (16U)
10252 #define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos)
10253 #define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk
10254 #define EXTI_D3PCR1L_PCS9_Pos (18U)
10255 #define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos)
10256 #define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk
10257 #define EXTI_D3PCR1L_PCS10_Pos (20U)
10258 #define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos)
10259 #define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk
10260 #define EXTI_D3PCR1L_PCS11_Pos (22U)
10261 #define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos)
10262 #define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk
10263 #define EXTI_D3PCR1L_PCS12_Pos (24U)
10264 #define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos)
10265 #define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk
10266 #define EXTI_D3PCR1L_PCS13_Pos (26U)
10267 #define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos)
10268 #define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk
10269 #define EXTI_D3PCR1L_PCS14_Pos (28U)
10270 #define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos)
10271 #define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk
10272 #define EXTI_D3PCR1L_PCS15_Pos (30U)
10273 #define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos)
10274 #define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk
10276 /******************* Bit definition for EXTI_D3PCR1H register ****************/
10277 #define EXTI_D3PCR1H_PCS19_Pos (6U)
10278 #define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos)
10279 #define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk
10280 #define EXTI_D3PCR1H_PCS20_Pos (8U)
10281 #define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos)
10282 #define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk
10283 #define EXTI_D3PCR1H_PCS21_Pos (10U)
10284 #define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos)
10285 #define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk
10286 #define EXTI_D3PCR1H_PCS25_Pos (18U)
10287 #define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos)
10288 #define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk
10290 /****************** Bit definition for EXTI_RTSR2 register *******************/
10291 #define EXTI_RTSR2_TR_Pos (17U)
10292 #define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos)
10293 #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk
10294 #define EXTI_RTSR2_TR49_Pos (17U)
10295 #define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos)
10296 #define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk
10297 #define EXTI_RTSR2_TR51_Pos (19U)
10298 #define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos)
10299 #define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk
10301 /****************** Bit definition for EXTI_FTSR2 register *******************/
10302 #define EXTI_FTSR2_TR_Pos (17U)
10303 #define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos)
10304 #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk
10305 #define EXTI_FTSR2_TR49_Pos (17U)
10306 #define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos)
10307 #define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk
10308 #define EXTI_FTSR2_TR51_Pos (19U)
10309 #define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos)
10310 #define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk
10312 /****************** Bit definition for EXTI_SWIER2 register ******************/
10313 #define EXTI_SWIER2_SWIER49_Pos (17U)
10314 #define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos)
10315 #define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk
10316 #define EXTI_SWIER2_SWIER51_Pos (19U)
10317 #define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos)
10318 #define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk
10320 /****************** Bit definition for EXTI_D3PMR2 register ******************/
10321 #define EXTI_D3PMR2_MR34_Pos (2U)
10322 #define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos)
10323 #define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk
10324 #define EXTI_D3PMR2_MR35_Pos (3U)
10325 #define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos)
10326 #define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk
10327 #define EXTI_D3PMR2_MR41_Pos (9U)
10328 #define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos)
10329 #define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk
10330 #define EXTI_D3PMR2_MR48_Pos (16U)
10331 #define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos)
10332 #define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk
10333 #define EXTI_D3PMR2_MR49_Pos (17U)
10334 #define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos)
10335 #define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk
10336 #define EXTI_D3PMR2_MR50_Pos (18U)
10337 #define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos)
10338 #define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk
10339 #define EXTI_D3PMR2_MR51_Pos (19U)
10340 #define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos)
10341 #define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk
10342 #define EXTI_D3PMR2_MR52_Pos (20U)
10343 #define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos)
10344 #define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk
10345 #define EXTI_D3PMR2_MR53_Pos (21U)
10346 #define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos)
10347 #define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk
10348 /******************* Bit definition for EXTI_D3PCR2L register ****************/
10349 #define EXTI_D3PCR2L_PCS34_Pos (4U)
10350 #define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos)
10351 #define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk
10352 #define EXTI_D3PCR2L_PCS35_Pos (6U)
10353 #define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos)
10354 #define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk
10355 #define EXTI_D3PCR2L_PCS41_Pos (18U)
10356 #define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos)
10357 #define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk
10360 /******************* Bit definition for EXTI_D3PCR2H register ****************/
10361 #define EXTI_D3PCR2H_PCS48_Pos (0U)
10362 #define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos)
10363 #define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk
10364 #define EXTI_D3PCR2H_PCS49_Pos (2U)
10365 #define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos)
10366 #define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk
10367 #define EXTI_D3PCR2H_PCS50_Pos (4U)
10368 #define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos)
10369 #define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk
10370 #define EXTI_D3PCR2H_PCS51_Pos (6U)
10371 #define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos)
10372 #define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk
10373 #define EXTI_D3PCR2H_PCS52_Pos (8U)
10374 #define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos)
10375 #define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk
10376 #define EXTI_D3PCR2H_PCS53_Pos (10U)
10377 #define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos)
10378 #define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk
10379 /****************** Bit definition for EXTI_RTSR3 register *******************/
10380 #define EXTI_RTSR3_TR_Pos (21U)
10381 #define EXTI_RTSR3_TR_Msk (0x3UL << EXTI_RTSR3_TR_Pos)
10382 #define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk
10383 #define EXTI_RTSR3_TR85_Pos (21U)
10384 #define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos)
10385 #define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk
10386 #define EXTI_RTSR3_TR86_Pos (22U)
10387 #define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos)
10388 #define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk
10390 /****************** Bit definition for EXTI_FTSR3 register *******************/
10391 #define EXTI_FTSR3_TR_Pos (21U)
10392 #define EXTI_FTSR3_TR_Msk (0x3UL << EXTI_FTSR3_TR_Pos)
10393 #define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk
10394 #define EXTI_FTSR3_TR85_Pos (21U)
10395 #define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos)
10396 #define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk
10397 #define EXTI_FTSR3_TR86_Pos (22U)
10398 #define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos)
10399 #define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk
10401 /****************** Bit definition for EXTI_SWIER3 register ******************/
10402 #define EXTI_SWIER3_SWI_Pos (21U)
10403 #define EXTI_SWIER3_SWI_Msk (0x3UL << EXTI_SWIER3_SWI_Pos)
10404 #define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk
10405 #define EXTI_SWIER3_SWIER85_Pos (21U)
10406 #define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos)
10407 #define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk
10408 #define EXTI_SWIER3_SWIER86_Pos (22U)
10409 #define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos)
10410 #define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk
10412 /****************** Bit definition for EXTI_D3PMR3 register ******************/
10413 #define EXTI_D3PMR3_MR88_Pos (24U)
10414 #define EXTI_D3PMR3_MR88_Msk (0x1UL << EXTI_D3PMR3_MR88_Pos)
10415 #define EXTI_D3PMR3_MR88 EXTI_D3PMR3_MR88_Msk
10417 /******************* Bit definition for EXTI_D3PCR3H register ****************/
10418 #define EXTI_D3PCR3H_PCS88_Pos (16U)
10419 #define EXTI_D3PCR3H_PCS88_Msk (0x3UL << EXTI_D3PCR3H_PCS88_Pos)
10420 #define EXTI_D3PCR3H_PCS88 EXTI_D3PCR3H_PCS88_Msk
10422 /******************* Bit definition for EXTI_IMR1 register *******************/
10423 #define EXTI_IMR1_IM_Pos (0U)
10424 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
10425 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
10426 #define EXTI_IMR1_IM0_Pos (0U)
10427 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
10428 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
10429 #define EXTI_IMR1_IM1_Pos (1U)
10430 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
10431 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
10432 #define EXTI_IMR1_IM2_Pos (2U)
10433 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
10434 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
10435 #define EXTI_IMR1_IM3_Pos (3U)
10436 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
10437 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
10438 #define EXTI_IMR1_IM4_Pos (4U)
10439 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
10440 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
10441 #define EXTI_IMR1_IM5_Pos (5U)
10442 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
10443 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
10444 #define EXTI_IMR1_IM6_Pos (6U)
10445 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
10446 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
10447 #define EXTI_IMR1_IM7_Pos (7U)
10448 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
10449 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
10450 #define EXTI_IMR1_IM8_Pos (8U)
10451 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
10452 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
10453 #define EXTI_IMR1_IM9_Pos (9U)
10454 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
10455 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
10456 #define EXTI_IMR1_IM10_Pos (10U)
10457 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
10458 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
10459 #define EXTI_IMR1_IM11_Pos (11U)
10460 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
10461 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
10462 #define EXTI_IMR1_IM12_Pos (12U)
10463 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
10464 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
10465 #define EXTI_IMR1_IM13_Pos (13U)
10466 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
10467 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
10468 #define EXTI_IMR1_IM14_Pos (14U)
10469 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
10470 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
10471 #define EXTI_IMR1_IM15_Pos (15U)
10472 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
10473 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
10474 #define EXTI_IMR1_IM16_Pos (16U)
10475 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
10476 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
10477 #define EXTI_IMR1_IM17_Pos (17U)
10478 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
10479 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
10480 #define EXTI_IMR1_IM18_Pos (18U)
10481 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
10482 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
10483 #define EXTI_IMR1_IM19_Pos (19U)
10484 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
10485 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
10486 #define EXTI_IMR1_IM20_Pos (20U)
10487 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
10488 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
10489 #define EXTI_IMR1_IM21_Pos (21U)
10490 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
10491 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
10492 #define EXTI_IMR1_IM22_Pos (22U)
10493 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
10494 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
10495 #define EXTI_IMR1_IM23_Pos (23U)
10496 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
10497 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
10498 #define EXTI_IMR1_IM24_Pos (24U)
10499 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
10500 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
10501 #define EXTI_IMR1_IM25_Pos (25U)
10502 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
10503 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
10504 #define EXTI_IMR1_IM26_Pos (26U)
10505 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
10506 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
10507 #define EXTI_IMR1_IM27_Pos (27U)
10508 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
10509 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
10510 #define EXTI_IMR1_IM28_Pos (28U)
10511 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
10512 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
10513 #define EXTI_IMR1_IM29_Pos (29U)
10514 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
10515 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
10516 #define EXTI_IMR1_IM30_Pos (30U)
10517 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
10518 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
10519 #define EXTI_IMR1_IM31_Pos (31U)
10520 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
10521 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
10523 /******************* Bit definition for EXTI_EMR1 register *******************/
10524 #define EXTI_EMR1_EM_Pos (0U)
10525 #define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)
10526 #define EXTI_EMR1_EM EXTI_EMR1_EM_Msk
10527 #define EXTI_EMR1_EM0_Pos (0U)
10528 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
10529 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
10530 #define EXTI_EMR1_EM1_Pos (1U)
10531 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
10532 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
10533 #define EXTI_EMR1_EM2_Pos (2U)
10534 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
10535 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
10536 #define EXTI_EMR1_EM3_Pos (3U)
10537 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
10538 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
10539 #define EXTI_EMR1_EM4_Pos (4U)
10540 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
10541 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
10542 #define EXTI_EMR1_EM5_Pos (5U)
10543 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
10544 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
10545 #define EXTI_EMR1_EM6_Pos (6U)
10546 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
10547 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
10548 #define EXTI_EMR1_EM7_Pos (7U)
10549 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
10550 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
10551 #define EXTI_EMR1_EM8_Pos (8U)
10552 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
10553 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
10554 #define EXTI_EMR1_EM9_Pos (9U)
10555 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
10556 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
10557 #define EXTI_EMR1_EM10_Pos (10U)
10558 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
10559 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
10560 #define EXTI_EMR1_EM11_Pos (11U)
10561 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
10562 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
10563 #define EXTI_EMR1_EM12_Pos (12U)
10564 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
10565 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
10566 #define EXTI_EMR1_EM13_Pos (13U)
10567 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
10568 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
10569 #define EXTI_EMR1_EM14_Pos (14U)
10570 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
10571 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
10572 #define EXTI_EMR1_EM15_Pos (15U)
10573 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
10574 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
10575 #define EXTI_EMR1_EM16_Pos (16U)
10576 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
10577 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
10578 #define EXTI_EMR1_EM17_Pos (17U)
10579 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
10580 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
10581 #define EXTI_EMR1_EM18_Pos (18U)
10582 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
10583 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
10584 #define EXTI_EMR1_EM20_Pos (20U)
10585 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
10586 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
10587 #define EXTI_EMR1_EM21_Pos (21U)
10588 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
10589 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
10590 #define EXTI_EMR1_EM22_Pos (22U)
10591 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
10592 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
10593 #define EXTI_EMR1_EM23_Pos (23U)
10594 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
10595 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
10596 #define EXTI_EMR1_EM24_Pos (24U)
10597 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
10598 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
10599 #define EXTI_EMR1_EM25_Pos (25U)
10600 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
10601 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
10602 #define EXTI_EMR1_EM26_Pos (26U)
10603 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
10604 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
10605 #define EXTI_EMR1_EM27_Pos (27U)
10606 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
10607 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
10608 #define EXTI_EMR1_EM28_Pos (28U)
10609 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
10610 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
10611 #define EXTI_EMR1_EM29_Pos (29U)
10612 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
10613 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
10614 #define EXTI_EMR1_EM30_Pos (30U)
10615 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
10616 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
10617 #define EXTI_EMR1_EM31_Pos (31U)
10618 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
10619 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
10621 /******************* Bit definition for EXTI_PR1 register ********************/
10622 #define EXTI_PR1_PR_Pos (0U)
10623 #define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos)
10624 #define EXTI_PR1_PR EXTI_PR1_PR_Msk
10625 #define EXTI_PR1_PR0_Pos (0U)
10626 #define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos)
10627 #define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk
10628 #define EXTI_PR1_PR1_Pos (1U)
10629 #define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos)
10630 #define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk
10631 #define EXTI_PR1_PR2_Pos (2U)
10632 #define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos)
10633 #define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk
10634 #define EXTI_PR1_PR3_Pos (3U)
10635 #define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos)
10636 #define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk
10637 #define EXTI_PR1_PR4_Pos (4U)
10638 #define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos)
10639 #define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk
10640 #define EXTI_PR1_PR5_Pos (5U)
10641 #define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos)
10642 #define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk
10643 #define EXTI_PR1_PR6_Pos (6U)
10644 #define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos)
10645 #define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk
10646 #define EXTI_PR1_PR7_Pos (7U)
10647 #define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos)
10648 #define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk
10649 #define EXTI_PR1_PR8_Pos (8U)
10650 #define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos)
10651 #define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk
10652 #define EXTI_PR1_PR9_Pos (9U)
10653 #define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos)
10654 #define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk
10655 #define EXTI_PR1_PR10_Pos (10U)
10656 #define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos)
10657 #define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk
10658 #define EXTI_PR1_PR11_Pos (11U)
10659 #define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos)
10660 #define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk
10661 #define EXTI_PR1_PR12_Pos (12U)
10662 #define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos)
10663 #define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk
10664 #define EXTI_PR1_PR13_Pos (13U)
10665 #define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos)
10666 #define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk
10667 #define EXTI_PR1_PR14_Pos (14U)
10668 #define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos)
10669 #define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk
10670 #define EXTI_PR1_PR15_Pos (15U)
10671 #define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos)
10672 #define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk
10673 #define EXTI_PR1_PR16_Pos (16U)
10674 #define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos)
10675 #define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk
10676 #define EXTI_PR1_PR17_Pos (17U)
10677 #define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos)
10678 #define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk
10679 #define EXTI_PR1_PR18_Pos (18U)
10680 #define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos)
10681 #define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk
10682 #define EXTI_PR1_PR19_Pos (19U)
10683 #define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos)
10684 #define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk
10685 #define EXTI_PR1_PR20_Pos (20U)
10686 #define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos)
10687 #define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk
10688 #define EXTI_PR1_PR21_Pos (21U)
10689 #define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos)
10690 #define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk
10692 /******************* Bit definition for EXTI_IMR2 register *******************/
10693 #define EXTI_IMR2_IM_Pos (0U)
10694 #define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)
10695 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
10696 #define EXTI_IMR2_IM32_Pos (0U)
10697 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
10698 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
10699 #define EXTI_IMR2_IM33_Pos (1U)
10700 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
10701 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
10702 #define EXTI_IMR2_IM34_Pos (2U)
10703 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
10704 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
10705 #define EXTI_IMR2_IM35_Pos (3U)
10706 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
10707 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
10708 #define EXTI_IMR2_IM36_Pos (4U)
10709 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
10710 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
10711 #define EXTI_IMR2_IM37_Pos (5U)
10712 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
10713 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
10714 #define EXTI_IMR2_IM38_Pos (6U)
10715 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
10716 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
10717 #define EXTI_IMR2_IM39_Pos (7U)
10718 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
10719 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
10720 #define EXTI_IMR2_IM40_Pos (8U)
10721 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)
10722 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk
10723 #define EXTI_IMR2_IM41_Pos (9U)
10724 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)
10725 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk
10726 #define EXTI_IMR2_IM42_Pos (10U)
10727 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos)
10728 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk
10729 #define EXTI_IMR2_IM43_Pos (11U)
10730 #define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos)
10731 #define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk
10732 #define EXTI_IMR2_IM47_Pos (15U)
10733 #define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos)
10734 #define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk
10735 #define EXTI_IMR2_IM48_Pos (16U)
10736 #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos)
10737 #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk
10738 #define EXTI_IMR2_IM49_Pos (17U)
10739 #define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos)
10740 #define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk
10741 #define EXTI_IMR2_IM50_Pos (18U)
10742 #define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos)
10743 #define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk
10744 #define EXTI_IMR2_IM51_Pos (19U)
10745 #define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos)
10746 #define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk
10747 #define EXTI_IMR2_IM52_Pos (20U)
10748 #define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos)
10749 #define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk
10750 #define EXTI_IMR2_IM53_Pos (21U)
10751 #define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos)
10752 #define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk
10753 #define EXTI_IMR2_IM54_Pos (22U)
10754 #define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos)
10755 #define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk
10756 #define EXTI_IMR2_IM55_Pos (23U)
10757 #define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos)
10758 #define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk
10759 #define EXTI_IMR2_IM56_Pos (24U)
10760 #define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos)
10761 #define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk
10762 #define EXTI_IMR2_IM58_Pos (26U)
10763 #define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos)
10764 #define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk
10765 #define EXTI_IMR2_IM60_Pos (28U)
10766 #define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos)
10767 #define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk
10768 #define EXTI_IMR2_IM61_Pos (29U)
10769 #define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos)
10770 #define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk
10771 #define EXTI_IMR2_IM62_Pos (30U)
10772 #define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos)
10773 #define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk
10774 #define EXTI_IMR2_IM63_Pos (31U)
10775 #define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos)
10776 #define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk
10778 /******************* Bit definition for EXTI_EMR2 register *******************/
10779 #define EXTI_EMR2_EM_Pos (0U)
10780 #define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)
10781 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
10782 #define EXTI_EMR2_EM32_Pos (0U)
10783 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
10784 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
10785 #define EXTI_EMR2_EM33_Pos (1U)
10786 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
10787 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
10788 #define EXTI_EMR2_EM34_Pos (2U)
10789 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
10790 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
10791 #define EXTI_EMR2_EM35_Pos (3U)
10792 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
10793 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
10794 #define EXTI_EMR2_EM36_Pos (4U)
10795 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
10796 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
10797 #define EXTI_EMR2_EM37_Pos (5U)
10798 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
10799 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
10800 #define EXTI_EMR2_EM38_Pos (6U)
10801 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
10802 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
10803 #define EXTI_EMR2_EM39_Pos (7U)
10804 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
10805 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
10806 #define EXTI_EMR2_EM40_Pos (8U)
10807 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)
10808 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk
10809 #define EXTI_EMR2_EM41_Pos (9U)
10810 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)
10811 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk
10812 #define EXTI_EMR2_EM42_Pos (10U)
10813 #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos)
10814 #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk
10815 #define EXTI_EMR2_EM43_Pos (11U)
10816 #define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos)
10817 #define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk
10818 #define EXTI_EMR2_EM47_Pos (15U)
10819 #define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos)
10820 #define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk
10821 #define EXTI_EMR2_EM48_Pos (16U)
10822 #define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos)
10823 #define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk
10824 #define EXTI_EMR2_EM49_Pos (17U)
10825 #define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos)
10826 #define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk
10827 #define EXTI_EMR2_EM50_Pos (18U)
10828 #define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos)
10829 #define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk
10830 #define EXTI_EMR2_EM51_Pos (19U)
10831 #define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos)
10832 #define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk
10833 #define EXTI_EMR2_EM52_Pos (20U)
10834 #define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos)
10835 #define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk
10836 #define EXTI_EMR2_EM53_Pos (21U)
10837 #define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos)
10838 #define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk
10839 #define EXTI_EMR2_EM54_Pos (22U)
10840 #define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos)
10841 #define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk
10842 #define EXTI_EMR2_EM55_Pos (23U)
10843 #define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos)
10844 #define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk
10845 #define EXTI_EMR2_EM56_Pos (24U)
10846 #define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos)
10847 #define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk
10848 #define EXTI_EMR2_EM58_Pos (26U)
10849 #define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos)
10850 #define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk
10851 #define EXTI_EMR2_EM60_Pos (28U)
10852 #define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos)
10853 #define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk
10854 #define EXTI_EMR2_EM61_Pos (29U)
10855 #define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos)
10856 #define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk
10857 #define EXTI_EMR2_EM62_Pos (30U)
10858 #define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos)
10859 #define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk
10860 #define EXTI_EMR2_EM63_Pos (31U)
10861 #define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos)
10862 #define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk
10864 /******************* Bit definition for EXTI_PR2 register ********************/
10865 #define EXTI_PR2_PR_Pos (17U)
10866 #define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos)
10867 #define EXTI_PR2_PR EXTI_PR2_PR_Msk
10868 #define EXTI_PR2_PR49_Pos (17U)
10869 #define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos)
10870 #define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk
10871 #define EXTI_PR2_PR51_Pos (19U)
10872 #define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos)
10873 #define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk
10875 /******************* Bit definition for EXTI_IMR3 register *******************/
10876 #define EXTI_IMR3_IM_Pos (0U)
10877 #define EXTI_IMR3_IM_Msk (0x0FE17FFFUL << EXTI_IMR3_IM_Pos)
10878 #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk
10879 #define EXTI_IMR3_IM64_Pos (0U)
10880 #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos)
10881 #define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk
10882 #define EXTI_IMR3_IM65_Pos (1U)
10883 #define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos)
10884 #define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk
10885 #define EXTI_IMR3_IM66_Pos (2U)
10886 #define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos)
10887 #define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk
10888 #define EXTI_IMR3_IM67_Pos (3U)
10889 #define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos)
10890 #define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk
10891 #define EXTI_IMR3_IM68_Pos (4U)
10892 #define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos)
10893 #define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk
10894 #define EXTI_IMR3_IM69_Pos (5U)
10895 #define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos)
10896 #define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk
10897 #define EXTI_IMR3_IM70_Pos (6U)
10898 #define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos)
10899 #define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk
10900 #define EXTI_IMR3_IM71_Pos (7U)
10901 #define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos)
10902 #define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk
10903 #define EXTI_IMR3_IM72_Pos (8U)
10904 #define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos)
10905 #define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk
10906 #define EXTI_IMR3_IM73_Pos (9U)
10907 #define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos)
10908 #define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk
10909 #define EXTI_IMR3_IM74_Pos (10U)
10910 #define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos)
10911 #define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk
10912 #define EXTI_IMR3_IM75_Pos (11U)
10913 #define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos)
10914 #define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk
10915 #define EXTI_IMR3_IM76_Pos (12U)
10916 #define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos)
10917 #define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk
10918 #define EXTI_IMR3_IM77_Pos (13U)
10919 #define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos)
10920 #define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk
10921 #define EXTI_IMR3_IM78_Pos (14U)
10922 #define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos)
10923 #define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk
10924 #define EXTI_IMR3_IM80_Pos (16U)
10925 #define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos)
10926 #define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk
10927 #define EXTI_IMR3_IM85_Pos (21U)
10928 #define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos)
10929 #define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk
10930 #define EXTI_IMR3_IM86_Pos (22U)
10931 #define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos)
10932 #define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk
10933 #define EXTI_IMR3_IM87_Pos (23U)
10934 #define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos)
10935 #define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk
10938 #define EXTI_IMR3_IM88_Pos (24U)
10939 #define EXTI_IMR3_IM88_Msk (0x1UL << EXTI_IMR3_IM88_Pos)
10940 #define EXTI_IMR3_IM88 EXTI_IMR3_IM88_Msk
10942 #define EXTI_IMR3_IM89_Pos (25U)
10943 #define EXTI_IMR3_IM89_Msk (0x1UL << EXTI_IMR3_IM89_Pos)
10944 #define EXTI_IMR3_IM89 EXTI_IMR3_IM89_Msk
10945 #define EXTI_IMR3_IM90_Pos (26U)
10946 #define EXTI_IMR3_IM90_Msk (0x1UL << EXTI_IMR3_IM90_Pos)
10947 #define EXTI_IMR3_IM90 EXTI_IMR3_IM90_Msk
10948 #define EXTI_IMR3_IM91_Pos (27U)
10949 #define EXTI_IMR3_IM91_Msk (0x1UL << EXTI_IMR3_IM91_Pos)
10950 #define EXTI_IMR3_IM91 EXTI_IMR3_IM91_Msk
10952 /******************* Bit definition for EXTI_EMR3 register *******************/
10953 #define EXTI_EMR3_EM_Pos (0U)
10954 #define EXTI_EMR3_EM_Msk (0x0FE17FFFUL << EXTI_EMR3_EM_Pos)
10955 #define EXTI_EMR3_EM EXTI_EMR3_EM_Msk
10956 #define EXTI_EMR3_EM64_Pos (0U)
10957 #define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos)
10958 #define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk
10959 #define EXTI_EMR3_EM65_Pos (1U)
10960 #define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos)
10961 #define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk
10962 #define EXTI_EMR3_EM66_Pos (2U)
10963 #define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos)
10964 #define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk
10965 #define EXTI_EMR3_EM67_Pos (3U)
10966 #define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos)
10967 #define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk
10968 #define EXTI_EMR3_EM68_Pos (4U)
10969 #define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos)
10970 #define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk
10971 #define EXTI_EMR3_EM69_Pos (5U)
10972 #define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos)
10973 #define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk
10974 #define EXTI_EMR3_EM70_Pos (6U)
10975 #define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos)
10976 #define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk
10977 #define EXTI_EMR3_EM71_Pos (7U)
10978 #define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos)
10979 #define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk
10980 #define EXTI_EMR3_EM72_Pos (8U)
10981 #define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos)
10982 #define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk
10983 #define EXTI_EMR3_EM73_Pos (9U)
10984 #define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos)
10985 #define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk
10986 #define EXTI_EMR3_EM74_Pos (10U)
10987 #define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos)
10988 #define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk
10989 #define EXTI_EMR3_EM75_Pos (11U)
10990 #define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos)
10991 #define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk
10992 #define EXTI_EMR3_EM76_Pos (12U)
10993 #define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos)
10994 #define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk
10995 #define EXTI_EMR3_EM77_Pos (13U)
10996 #define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos)
10997 #define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk
10998 #define EXTI_EMR3_EM78_Pos (14U)
10999 #define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos)
11000 #define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk
11001 #define EXTI_EMR3_EM80_Pos (16U)
11002 #define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos)
11003 #define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk
11004 #define EXTI_EMR3_EM85_Pos (21U)
11005 #define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos)
11006 #define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk
11007 #define EXTI_EMR3_EM86_Pos (22U)
11008 #define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos)
11009 #define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk
11010 #define EXTI_EMR3_EM87_Pos (23U)
11011 #define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos)
11012 #define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk
11014 #define EXTI_EMR3_EM88_Pos (24U)
11015 #define EXTI_EMR3_EM88_Msk (0x1UL << EXTI_EMR3_EM88_Pos)
11016 #define EXTI_EMR3_EM88 EXTI_EMR3_EM88_Msk
11018 #define EXTI_EMR3_EM89_Pos (25U)
11019 #define EXTI_EMR3_EM89_Msk (0x1UL << EXTI_EMR3_EM89_Pos)
11020 #define EXTI_EMR3_EM89 EXTI_EMR3_EM89_Msk
11021 #define EXTI_EMR3_EM90_Pos (26U)
11022 #define EXTI_EMR3_EM90_Msk (0x1UL << EXTI_EMR3_EM90_Pos)
11023 #define EXTI_EMR3_EM90 EXTI_EMR3_EM90_Msk
11024 #define EXTI_EMR3_EM91_Pos (27U)
11025 #define EXTI_EMR3_EM91_Msk (0x1UL << EXTI_EMR3_EM91_Pos)
11026 #define EXTI_EMR3_EM91 EXTI_EMR3_EM91_Msk
11028 /******************* Bit definition for EXTI_PR3 register ********************/
11029 #define EXTI_PR3_PR_Pos (20U)
11030 #define EXTI_PR3_PR_Msk (0x7UL << EXTI_PR3_PR_Pos)
11031 #define EXTI_PR3_PR EXTI_PR3_PR_Msk
11032 #define EXTI_PR3_PR84_Pos (20U)
11033 #define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos)
11034 #define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk
11035 #define EXTI_PR3_PR85_Pos (21U)
11036 #define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos)
11037 #define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk
11038 #define EXTI_PR3_PR86_Pos (22U)
11039 #define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos)
11040 #define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk
11041 /******************************************************************************/
11042 /* */
11043 /* FLASH */
11044 /* */
11045 /******************************************************************************/
11046 /*
11047 * @brief FLASH Global Defines
11048 */
11049 #define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
11050 #define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
11051 #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x100000U : \
11052  ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x100000U : \
11053  (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 1 MB */
11054 #define FLASH_BANK_SIZE FLASH_SIZE /* 1 MB */
11055 #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
11056 #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
11057 #define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
11058 
11059 /******************* Bits definition for FLASH_ACR register **********************/
11060 #define FLASH_ACR_LATENCY_Pos (0U)
11061 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
11062 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
11063 #define FLASH_ACR_LATENCY_0WS (0x00000000UL)
11064 #define FLASH_ACR_LATENCY_1WS (0x00000001UL)
11065 #define FLASH_ACR_LATENCY_2WS (0x00000002UL)
11066 #define FLASH_ACR_LATENCY_3WS (0x00000003UL)
11067 #define FLASH_ACR_LATENCY_4WS (0x00000004UL)
11068 #define FLASH_ACR_LATENCY_5WS (0x00000005UL)
11069 #define FLASH_ACR_LATENCY_6WS (0x00000006UL)
11070 #define FLASH_ACR_LATENCY_7WS (0x00000007UL)
11071 #define FLASH_ACR_LATENCY_8WS (0x00000008UL)
11072 #define FLASH_ACR_LATENCY_9WS (0x00000009UL)
11073 #define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
11074 #define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
11075 #define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
11076 #define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
11077 #define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
11078 #define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
11079 #define FLASH_ACR_WRHIGHFREQ_Pos (4U)
11080 #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)
11081 #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
11082 #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)
11083 #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)
11085 /******************* Bits definition for FLASH_CR register ***********************/
11086 #define FLASH_CR_LOCK_Pos (0U)
11087 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
11088 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
11089 #define FLASH_CR_PG_Pos (1U)
11090 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
11091 #define FLASH_CR_PG FLASH_CR_PG_Msk
11092 #define FLASH_CR_SER_Pos (2U)
11093 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
11094 #define FLASH_CR_SER FLASH_CR_SER_Msk
11095 #define FLASH_CR_BER_Pos (3U)
11096 #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos)
11097 #define FLASH_CR_BER FLASH_CR_BER_Msk
11098 #define FLASH_CR_PSIZE_Pos (4U)
11099 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
11100 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
11101 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
11102 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
11103 #define FLASH_CR_FW_Pos (6U)
11104 #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos)
11105 #define FLASH_CR_FW FLASH_CR_FW_Msk
11106 #define FLASH_CR_START_Pos (7U)
11107 #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos)
11108 #define FLASH_CR_START FLASH_CR_START_Msk
11109 #define FLASH_CR_SNB_Pos (8U)
11110 #define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos)
11111 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
11112 #define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos)
11113 #define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos)
11114 #define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos)
11115 #define FLASH_CR_CRC_EN_Pos (15U)
11116 #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos)
11117 #define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
11118 #define FLASH_CR_EOPIE_Pos (16U)
11119 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
11120 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
11121 #define FLASH_CR_WRPERRIE_Pos (17U)
11122 #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos)
11123 #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
11124 #define FLASH_CR_PGSERRIE_Pos (18U)
11125 #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos)
11126 #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
11127 #define FLASH_CR_STRBERRIE_Pos (19U)
11128 #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos)
11129 #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
11130 #define FLASH_CR_INCERRIE_Pos (21U)
11131 #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos)
11132 #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
11133 #define FLASH_CR_OPERRIE_Pos (22U)
11134 #define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos)
11135 #define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
11136 #define FLASH_CR_RDPERRIE_Pos (23U)
11137 #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos)
11138 #define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
11139 #define FLASH_CR_RDSERRIE_Pos (24U)
11140 #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos)
11141 #define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
11142 #define FLASH_CR_SNECCERRIE_Pos (25U)
11143 #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos)
11144 #define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
11145 #define FLASH_CR_DBECCERRIE_Pos (26U)
11146 #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos)
11147 #define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
11148 #define FLASH_CR_CRCENDIE_Pos (27U)
11149 #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos)
11150 #define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
11151 #define FLASH_CR_CRCRDERRIE_Pos (28U)
11152 #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos)
11153 #define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
11155 /******************* Bits definition for FLASH_SR register ***********************/
11156 #define FLASH_SR_BSY_Pos (0U)
11157 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
11158 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
11159 #define FLASH_SR_WBNE_Pos (1U)
11160 #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos)
11161 #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
11162 #define FLASH_SR_QW_Pos (2U)
11163 #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos)
11164 #define FLASH_SR_QW FLASH_SR_QW_Msk
11165 #define FLASH_SR_CRC_BUSY_Pos (3U)
11166 #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos)
11167 #define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
11168 #define FLASH_SR_EOP_Pos (16U)
11169 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
11170 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
11171 #define FLASH_SR_WRPERR_Pos (17U)
11172 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
11173 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
11174 #define FLASH_SR_PGSERR_Pos (18U)
11175 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
11176 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
11177 #define FLASH_SR_STRBERR_Pos (19U)
11178 #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos)
11179 #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
11180 #define FLASH_SR_INCERR_Pos (21U)
11181 #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos)
11182 #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
11183 #define FLASH_SR_OPERR_Pos (22U)
11184 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
11185 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
11186 #define FLASH_SR_RDPERR_Pos (23U)
11187 #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos)
11188 #define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
11189 #define FLASH_SR_RDSERR_Pos (24U)
11190 #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos)
11191 #define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
11192 #define FLASH_SR_SNECCERR_Pos (25U)
11193 #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos)
11194 #define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
11195 #define FLASH_SR_DBECCERR_Pos (26U)
11196 #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos)
11197 #define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
11198 #define FLASH_SR_CRCEND_Pos (27U)
11199 #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos)
11200 #define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
11201 #define FLASH_SR_CRCRDERR_Pos (28U)
11202 #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos)
11203 #define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
11205 /******************* Bits definition for FLASH_CCR register *******************/
11206 #define FLASH_CCR_CLR_EOP_Pos (16U)
11207 #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos)
11208 #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
11209 #define FLASH_CCR_CLR_WRPERR_Pos (17U)
11210 #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)
11211 #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
11212 #define FLASH_CCR_CLR_PGSERR_Pos (18U)
11213 #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)
11214 #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
11215 #define FLASH_CCR_CLR_STRBERR_Pos (19U)
11216 #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)
11217 #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
11218 #define FLASH_CCR_CLR_INCERR_Pos (21U)
11219 #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos)
11220 #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
11221 #define FLASH_CCR_CLR_OPERR_Pos (22U)
11222 #define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos)
11223 #define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
11224 #define FLASH_CCR_CLR_RDPERR_Pos (23U)
11225 #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos)
11226 #define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
11227 #define FLASH_CCR_CLR_RDSERR_Pos (24U)
11228 #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos)
11229 #define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
11230 #define FLASH_CCR_CLR_SNECCERR_Pos (25U)
11231 #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos)
11232 #define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
11233 #define FLASH_CCR_CLR_DBECCERR_Pos (26U)
11234 #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos)
11235 #define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
11236 #define FLASH_CCR_CLR_CRCEND_Pos (27U)
11237 #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos)
11238 #define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
11239 #define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
11240 #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos)
11241 #define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
11243 /******************* Bits definition for FLASH_OPTCR register *******************/
11244 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
11245 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
11246 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
11247 #define FLASH_OPTCR_OPTSTART_Pos (1U)
11248 #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos)
11249 #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
11250 #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
11251 #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos)
11252 #define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
11254 /******************* Bits definition for FLASH_OPTSR register ***************/
11255 #define FLASH_OPTSR_OPT_BUSY_Pos (0U)
11256 #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos)
11257 #define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
11258 #define FLASH_OPTSR_BOR_LEV_Pos (2U)
11259 #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)
11260 #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
11261 #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)
11262 #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)
11263 #define FLASH_OPTSR_IWDG1_SW_Pos (4U)
11264 #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos)
11265 #define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
11266 #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
11267 #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos)
11268 #define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
11269 #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
11270 #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos)
11271 #define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
11272 #define FLASH_OPTSR_RDP_Pos (8U)
11273 #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos)
11274 #define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
11275 #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
11276 #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos)
11277 #define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
11278 #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
11279 #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos)
11280 #define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
11281 #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
11282 #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11283 #define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
11284 #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11285 #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11286 #define FLASH_OPTSR_SECURITY_Pos (21U)
11287 #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos)
11288 #define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
11289 #define FLASH_OPTSR_NRST_STOP_D2_Pos (24U)
11290 #define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos)
11291 #define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk
11292 #define FLASH_OPTSR_NRST_STBY_D2_Pos (25U)
11293 #define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos)
11294 #define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk
11295 #define FLASH_OPTSR_IO_HSLV_Pos (29U)
11296 #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos)
11297 #define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
11298 #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
11299 #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos)
11300 #define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
11302 /******************* Bits definition for FLASH_OPTCCR register *******************/
11303 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
11304 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos)
11305 #define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
11307 /******************* Bits definition for FLASH_PRAR register *********************/
11308 #define FLASH_PRAR_PROT_AREA_START_Pos (0U)
11309 #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos)
11310 #define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
11311 #define FLASH_PRAR_PROT_AREA_END_Pos (16U)
11312 #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos)
11313 #define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
11314 #define FLASH_PRAR_DMEP_Pos (31U)
11315 #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos)
11316 #define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
11318 /******************* Bits definition for FLASH_SCAR register *********************/
11319 #define FLASH_SCAR_SEC_AREA_START_Pos (0U)
11320 #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos)
11321 #define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
11322 #define FLASH_SCAR_SEC_AREA_END_Pos (16U)
11323 #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos)
11324 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
11325 #define FLASH_SCAR_DMES_Pos (31U)
11326 #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos)
11327 #define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
11329 /******************* Bits definition for FLASH_WPSN register *********************/
11330 #define FLASH_WPSN_WRPSN_Pos (0U)
11331 #define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos)
11332 #define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
11334 /******************* Bits definition for FLASH_BOOT_CUR register ****************/
11335 #define FLASH_BOOT_ADD0_Pos (0U)
11336 #define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos)
11337 #define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk
11338 #define FLASH_BOOT_ADD1_Pos (16U)
11339 #define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos)
11340 #define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk
11343 /******************* Bits definition for FLASH_CRCCR register ********************/
11344 #define FLASH_CRCCR_CRC_SECT_Pos (0U)
11345 #define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos)
11346 #define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
11347 #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
11348 #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos)
11349 #define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
11350 #define FLASH_CRCCR_ADD_SECT_Pos (9U)
11351 #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos)
11352 #define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
11353 #define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
11354 #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos)
11355 #define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
11356 #define FLASH_CRCCR_START_CRC_Pos (16U)
11357 #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos)
11358 #define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
11359 #define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
11360 #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos)
11361 #define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
11362 #define FLASH_CRCCR_CRC_BURST_Pos (20U)
11363 #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos)
11364 #define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
11365 #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos)
11366 #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos)
11367 #define FLASH_CRCCR_ALL_BANK_Pos (22U)
11368 #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos)
11369 #define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
11371 /******************* Bits definition for FLASH_CRCSADD register ****************/
11372 #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
11373 #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos)
11374 #define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
11376 /******************* Bits definition for FLASH_CRCEADD register ****************/
11377 #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
11378 #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos)
11379 #define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
11381 /******************* Bits definition for FLASH_CRCDATA register ***************/
11382 #define FLASH_CRCDATA_CRC_DATA_Pos (0U)
11383 #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos)
11384 #define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
11386 /******************* Bits definition for FLASH_ECC_FA register *******************/
11387 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
11388 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos)
11389 #define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
11391 /******************* Bits definition for FLASH_OPTSR2 register *******************/
11392 #define FLASH_OPTSR2_TCM_AXI_SHARED_Pos (0U)
11393 #define FLASH_OPTSR2_TCM_AXI_SHARED_Msk (0x3UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
11394 #define FLASH_OPTSR2_TCM_AXI_SHARED FLASH_OPTSR2_TCM_AXI_SHARED_Msk
11395 #define FLASH_OPTSR2_TCM_AXI_SHARED_0 (0x1UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
11396 #define FLASH_OPTSR2_TCM_AXI_SHARED_1 (0x2UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
11397 #define FLASH_OPTSR2_CPUFREQ_BOOST_Pos (2U)
11398 #define FLASH_OPTSR2_CPUFREQ_BOOST_Msk (0x1UL << FLASH_OPTSR2_CPUFREQ_BOOST_Pos)
11399 #define FLASH_OPTSR2_CPUFREQ_BOOST FLASH_OPTSR2_CPUFREQ_BOOST_Msk
11401 /******************************************************************************/
11402 /* */
11403 /* Filter Mathematical ACcelerator unit (FMAC) */
11404 /* */
11405 /******************************************************************************/
11406 /***************** Bit definition for FMAC_X1BUFCFG register ****************/
11407 #define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
11408 #define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)
11409 #define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk
11410 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
11411 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)
11412 #define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk
11413 #define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
11414 #define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos)
11415 #define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk
11416 /***************** Bit definition for FMAC_X2BUFCFG register ****************/
11417 #define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
11418 #define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)
11419 #define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk
11420 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
11421 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)
11422 #define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk
11423 /***************** Bit definition for FMAC_YBUFCFG register *****************/
11424 #define FMAC_YBUFCFG_Y_BASE_Pos (0U)
11425 #define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)
11426 #define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk
11427 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
11428 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)
11429 #define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk
11430 #define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
11431 #define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos)
11432 #define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk
11433 /****************** Bit definition for FMAC_PARAM register ******************/
11434 #define FMAC_PARAM_P_Pos (0U)
11435 #define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos)
11436 #define FMAC_PARAM_P FMAC_PARAM_P_Msk
11437 #define FMAC_PARAM_Q_Pos (8U)
11438 #define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos)
11439 #define FMAC_PARAM_Q FMAC_PARAM_Q_Msk
11440 #define FMAC_PARAM_R_Pos (16U)
11441 #define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos)
11442 #define FMAC_PARAM_R FMAC_PARAM_R_Msk
11443 #define FMAC_PARAM_FUNC_Pos (24U)
11444 #define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos)
11445 #define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk
11446 #define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos)
11447 #define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos)
11448 #define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos)
11449 #define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos)
11450 #define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos)
11451 #define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos)
11452 #define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos)
11453 #define FMAC_PARAM_START_Pos (31U)
11454 #define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos)
11455 #define FMAC_PARAM_START FMAC_PARAM_START_Msk
11456 /******************** Bit definition for FMAC_CR register *******************/
11457 #define FMAC_CR_RIEN_Pos (0U)
11458 #define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos)
11459 #define FMAC_CR_RIEN FMAC_CR_RIEN_Msk
11460 #define FMAC_CR_WIEN_Pos (1U)
11461 #define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos)
11462 #define FMAC_CR_WIEN FMAC_CR_WIEN_Msk
11463 #define FMAC_CR_OVFLIEN_Pos (2U)
11464 #define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos)
11465 #define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk
11466 #define FMAC_CR_UNFLIEN_Pos (3U)
11467 #define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos)
11468 #define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk
11469 #define FMAC_CR_SATIEN_Pos (4U)
11470 #define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos)
11471 #define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk
11472 #define FMAC_CR_DMAREN_Pos (8U)
11473 #define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos)
11474 #define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk
11475 #define FMAC_CR_DMAWEN_Pos (9U)
11476 #define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos)
11477 #define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk
11478 #define FMAC_CR_CLIPEN_Pos (15U)
11479 #define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos)
11480 #define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk
11481 #define FMAC_CR_RESET_Pos (16U)
11482 #define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos)
11483 #define FMAC_CR_RESET FMAC_CR_RESET_Msk
11484 /******************* Bit definition for FMAC_SR register ********************/
11485 #define FMAC_SR_YEMPTY_Pos (0U)
11486 #define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos)
11487 #define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk
11488 #define FMAC_SR_X1FULL_Pos (1U)
11489 #define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos)
11490 #define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk
11491 #define FMAC_SR_OVFL_Pos (8U)
11492 #define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos)
11493 #define FMAC_SR_OVFL FMAC_SR_OVFL_Msk
11494 #define FMAC_SR_UNFL_Pos (9U)
11495 #define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos)
11496 #define FMAC_SR_UNFL FMAC_SR_UNFL_Msk
11497 #define FMAC_SR_SAT_Pos (10U)
11498 #define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos)
11499 #define FMAC_SR_SAT FMAC_SR_SAT_Msk
11500 /****************** Bit definition for FMAC_WDATA register ******************/
11501 #define FMAC_WDATA_WDATA_Pos (0U)
11502 #define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos)
11503 #define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk
11504 /****************** Bit definition for FMACX_RDATA register *****************/
11505 #define FMAC_RDATA_RDATA_Pos (0U)
11506 #define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos)
11507 #define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk
11509 /******************************************************************************/
11510 /* */
11511 /* Flexible Memory Controller */
11512 /* */
11513 /******************************************************************************/
11514 /****************** Bit definition for FMC_BCR1 register *******************/
11515 #define FMC_BCR1_CCLKEN_Pos (20U)
11516 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
11517 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
11518 #define FMC_BCR1_WFDIS_Pos (21U)
11519 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
11520 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
11522 #define FMC_BCR1_BMAP_Pos (24U)
11523 #define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos)
11524 #define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk
11525 #define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos)
11526 #define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos)
11528 #define FMC_BCR1_FMCEN_Pos (31U)
11529 #define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos)
11530 #define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk
11531 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
11532 #define FMC_BCRx_MBKEN_Pos (0U)
11533 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
11534 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
11535 #define FMC_BCRx_MUXEN_Pos (1U)
11536 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
11537 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
11539 #define FMC_BCRx_MTYP_Pos (2U)
11540 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
11541 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
11542 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
11543 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
11545 #define FMC_BCRx_MWID_Pos (4U)
11546 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
11547 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
11548 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
11549 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
11551 #define FMC_BCRx_FACCEN_Pos (6U)
11552 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
11553 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
11554 #define FMC_BCRx_BURSTEN_Pos (8U)
11555 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
11556 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
11557 #define FMC_BCRx_WAITPOL_Pos (9U)
11558 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
11559 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
11560 #define FMC_BCRx_WAITCFG_Pos (11U)
11561 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
11562 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
11563 #define FMC_BCRx_WREN_Pos (12U)
11564 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
11565 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
11566 #define FMC_BCRx_WAITEN_Pos (13U)
11567 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
11568 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
11569 #define FMC_BCRx_EXTMOD_Pos (14U)
11570 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
11571 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
11572 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
11573 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
11574 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
11576 #define FMC_BCRx_CPSIZE_Pos (16U)
11577 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
11578 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
11579 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
11580 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
11581 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
11583 #define FMC_BCRx_CBURSTRW_Pos (19U)
11584 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
11585 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
11587 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
11588 #define FMC_BTRx_ADDSET_Pos (0U)
11589 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
11590 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
11591 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
11592 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
11593 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
11594 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
11596 #define FMC_BTRx_ADDHLD_Pos (4U)
11597 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
11598 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
11599 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
11600 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
11601 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
11602 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
11604 #define FMC_BTRx_DATAST_Pos (8U)
11605 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
11606 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
11607 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
11608 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
11609 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
11610 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
11611 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
11612 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
11613 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
11614 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
11616 #define FMC_BTRx_BUSTURN_Pos (16U)
11617 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
11618 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
11619 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
11620 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
11621 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
11622 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
11624 #define FMC_BTRx_CLKDIV_Pos (20U)
11625 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
11626 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
11627 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
11628 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
11629 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
11630 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
11632 #define FMC_BTRx_DATLAT_Pos (24U)
11633 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
11634 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
11635 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
11636 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
11637 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
11638 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
11640 #define FMC_BTRx_ACCMOD_Pos (28U)
11641 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
11642 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
11643 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
11644 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
11646 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
11647 #define FMC_BWTRx_ADDSET_Pos (0U)
11648 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
11649 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
11650 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
11651 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
11652 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
11653 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
11655 #define FMC_BWTRx_ADDHLD_Pos (4U)
11656 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
11657 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
11658 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
11659 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
11660 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
11661 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
11663 #define FMC_BWTRx_DATAST_Pos (8U)
11664 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
11665 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
11666 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
11667 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
11668 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
11669 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
11670 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
11671 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
11672 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
11673 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
11675 #define FMC_BWTRx_BUSTURN_Pos (16U)
11676 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
11677 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
11678 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
11679 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
11680 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
11681 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
11683 #define FMC_BWTRx_ACCMOD_Pos (28U)
11684 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
11685 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
11686 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
11687 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
11689 /****************** Bit definition for FMC_PCR register *******************/
11690 #define FMC_PCR_PWAITEN_Pos (1U)
11691 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
11692 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
11693 #define FMC_PCR_PBKEN_Pos (2U)
11694 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
11695 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
11697 #define FMC_PCR_PWID_Pos (4U)
11698 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
11699 #define FMC_PCR_PWID FMC_PCR_PWID_Msk
11700 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
11701 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
11703 #define FMC_PCR_ECCEN_Pos (6U)
11704 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
11705 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
11707 #define FMC_PCR_TCLR_Pos (9U)
11708 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
11709 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
11710 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
11711 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
11712 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
11713 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
11715 #define FMC_PCR_TAR_Pos (13U)
11716 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
11717 #define FMC_PCR_TAR FMC_PCR_TAR_Msk
11718 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
11719 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
11720 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
11721 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
11723 #define FMC_PCR_ECCPS_Pos (17U)
11724 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
11725 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
11726 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
11727 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
11728 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
11730 /******************* Bit definition for FMC_SR register *******************/
11731 #define FMC_SR_IRS_Pos (0U)
11732 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
11733 #define FMC_SR_IRS FMC_SR_IRS_Msk
11734 #define FMC_SR_ILS_Pos (1U)
11735 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
11736 #define FMC_SR_ILS FMC_SR_ILS_Msk
11737 #define FMC_SR_IFS_Pos (2U)
11738 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
11739 #define FMC_SR_IFS FMC_SR_IFS_Msk
11740 #define FMC_SR_IREN_Pos (3U)
11741 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
11742 #define FMC_SR_IREN FMC_SR_IREN_Msk
11743 #define FMC_SR_ILEN_Pos (4U)
11744 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
11745 #define FMC_SR_ILEN FMC_SR_ILEN_Msk
11746 #define FMC_SR_IFEN_Pos (5U)
11747 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
11748 #define FMC_SR_IFEN FMC_SR_IFEN_Msk
11749 #define FMC_SR_FEMPT_Pos (6U)
11750 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
11751 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
11753 /****************** Bit definition for FMC_PMEM register ******************/
11754 #define FMC_PMEM_MEMSET_Pos (0U)
11755 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
11756 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
11757 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
11758 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
11759 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
11760 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
11761 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
11762 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
11763 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
11764 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
11766 #define FMC_PMEM_MEMWAIT_Pos (8U)
11767 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
11768 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
11769 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
11770 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
11771 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
11772 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
11773 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
11774 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
11775 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
11776 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
11778 #define FMC_PMEM_MEMHOLD_Pos (16U)
11779 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
11780 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
11781 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
11782 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
11783 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
11784 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
11785 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
11786 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
11787 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
11788 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
11790 #define FMC_PMEM_MEMHIZ_Pos (24U)
11791 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
11792 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
11793 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
11794 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
11795 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
11796 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
11797 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
11798 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
11799 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
11800 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
11802 /****************** Bit definition for FMC_PATT register ******************/
11803 #define FMC_PATT_ATTSET_Pos (0U)
11804 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
11805 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
11806 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
11807 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
11808 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
11809 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
11810 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
11811 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
11812 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
11813 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
11815 #define FMC_PATT_ATTWAIT_Pos (8U)
11816 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
11817 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
11818 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
11819 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
11820 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
11821 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
11822 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
11823 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
11824 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
11825 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
11827 #define FMC_PATT_ATTHOLD_Pos (16U)
11828 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
11829 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
11830 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
11831 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
11832 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
11833 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
11834 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
11835 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
11836 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
11837 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
11839 #define FMC_PATT_ATTHIZ_Pos (24U)
11840 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
11841 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
11842 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
11843 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
11844 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
11845 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
11846 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
11847 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
11848 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
11849 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
11851 /****************** Bit definition for FMC_ECCR3 register ******************/
11852 #define FMC_ECCR3_ECC3_Pos (0U)
11853 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
11854 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
11856 /****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
11857 #define FMC_SDCRx_NC_Pos (0U)
11858 #define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos)
11859 #define FMC_SDCRx_NC FMC_SDCRx_NC_Msk
11860 #define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos)
11861 #define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos)
11863 #define FMC_SDCRx_NR_Pos (2U)
11864 #define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos)
11865 #define FMC_SDCRx_NR FMC_SDCRx_NR_Msk
11866 #define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos)
11867 #define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos)
11869 #define FMC_SDCRx_MWID_Pos (4U)
11870 #define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos)
11871 #define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk
11872 #define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos)
11873 #define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos)
11875 #define FMC_SDCRx_NB_Pos (6U)
11876 #define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos)
11877 #define FMC_SDCRx_NB FMC_SDCRx_NB_Msk
11879 #define FMC_SDCRx_CAS_Pos (7U)
11880 #define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos)
11881 #define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk
11882 #define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos)
11883 #define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos)
11885 #define FMC_SDCRx_WP_Pos (9U)
11886 #define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos)
11887 #define FMC_SDCRx_WP FMC_SDCRx_WP_Msk
11889 #define FMC_SDCRx_SDCLK_Pos (10U)
11890 #define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos)
11891 #define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk
11892 #define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos)
11893 #define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos)
11895 #define FMC_SDCRx_RBURST_Pos (12U)
11896 #define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos)
11897 #define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk
11899 #define FMC_SDCRx_RPIPE_Pos (13U)
11900 #define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos)
11901 #define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk
11902 #define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos)
11903 #define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos)
11905 /****************** Bit definition for FMC_SDTRx(1,2) register ******************/
11906 #define FMC_SDTRx_TMRD_Pos (0U)
11907 #define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos)
11908 #define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk
11909 #define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos)
11910 #define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos)
11911 #define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos)
11912 #define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos)
11914 #define FMC_SDTRx_TXSR_Pos (4U)
11915 #define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos)
11916 #define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk
11917 #define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos)
11918 #define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos)
11919 #define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos)
11920 #define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos)
11922 #define FMC_SDTRx_TRAS_Pos (8U)
11923 #define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos)
11924 #define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk
11925 #define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos)
11926 #define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos)
11927 #define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos)
11928 #define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos)
11930 #define FMC_SDTRx_TRC_Pos (12U)
11931 #define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos)
11932 #define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk
11933 #define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos)
11934 #define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos)
11935 #define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos)
11937 #define FMC_SDTRx_TWR_Pos (16U)
11938 #define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos)
11939 #define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk
11940 #define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos)
11941 #define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos)
11942 #define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos)
11944 #define FMC_SDTRx_TRP_Pos (20U)
11945 #define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos)
11946 #define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk
11947 #define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos)
11948 #define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos)
11949 #define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos)
11951 #define FMC_SDTRx_TRCD_Pos (24U)
11952 #define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos)
11953 #define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk
11954 #define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos)
11955 #define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos)
11956 #define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos)
11958 /****************** Bit definition for FMC_SDCMR register ******************/
11959 #define FMC_SDCMR_MODE_Pos (0U)
11960 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
11961 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
11962 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
11963 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
11964 #define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos)
11966 #define FMC_SDCMR_CTB2_Pos (3U)
11967 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
11968 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
11970 #define FMC_SDCMR_CTB1_Pos (4U)
11971 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
11972 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
11974 #define FMC_SDCMR_NRFS_Pos (5U)
11975 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
11976 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
11977 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
11978 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
11979 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
11980 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
11982 #define FMC_SDCMR_MRD_Pos (9U)
11983 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
11984 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
11986 /****************** Bit definition for FMC_SDRTR register ******************/
11987 #define FMC_SDRTR_CRE_Pos (0U)
11988 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
11989 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
11991 #define FMC_SDRTR_COUNT_Pos (1U)
11992 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
11993 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
11995 #define FMC_SDRTR_REIE_Pos (14U)
11996 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
11997 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
11999 /****************** Bit definition for FMC_SDSR register ******************/
12000 #define FMC_SDSR_RE_Pos (0U)
12001 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
12002 #define FMC_SDSR_RE FMC_SDSR_RE_Msk
12004 #define FMC_SDSR_MODES1_Pos (1U)
12005 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
12006 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
12007 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
12008 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
12010 #define FMC_SDSR_MODES2_Pos (3U)
12011 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
12012 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
12013 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
12014 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
12016 /******************************************************************************/
12017 /* */
12018 /* General Purpose I/O */
12019 /* */
12020 /******************************************************************************/
12021 /****************** Bits definition for GPIO_MODER register *****************/
12022 #define GPIO_MODER_MODE0_Pos (0U)
12023 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
12024 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
12025 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
12026 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
12028 #define GPIO_MODER_MODE1_Pos (2U)
12029 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
12030 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
12031 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
12032 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
12034 #define GPIO_MODER_MODE2_Pos (4U)
12035 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
12036 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
12037 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
12038 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
12040 #define GPIO_MODER_MODE3_Pos (6U)
12041 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
12042 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
12043 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
12044 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
12046 #define GPIO_MODER_MODE4_Pos (8U)
12047 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
12048 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
12049 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
12050 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
12052 #define GPIO_MODER_MODE5_Pos (10U)
12053 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
12054 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
12055 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
12056 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
12058 #define GPIO_MODER_MODE6_Pos (12U)
12059 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
12060 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
12061 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
12062 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
12064 #define GPIO_MODER_MODE7_Pos (14U)
12065 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
12066 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
12067 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
12068 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
12070 #define GPIO_MODER_MODE8_Pos (16U)
12071 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
12072 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
12073 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
12074 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
12076 #define GPIO_MODER_MODE9_Pos (18U)
12077 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
12078 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
12079 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
12080 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
12082 #define GPIO_MODER_MODE10_Pos (20U)
12083 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
12084 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
12085 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
12086 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
12088 #define GPIO_MODER_MODE11_Pos (22U)
12089 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
12090 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
12091 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
12092 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
12094 #define GPIO_MODER_MODE12_Pos (24U)
12095 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
12096 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
12097 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
12098 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
12100 #define GPIO_MODER_MODE13_Pos (26U)
12101 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
12102 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
12103 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
12104 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
12106 #define GPIO_MODER_MODE14_Pos (28U)
12107 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
12108 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
12109 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
12110 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
12112 #define GPIO_MODER_MODE15_Pos (30U)
12113 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
12114 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
12115 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
12116 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
12118 /****************** Bits definition for GPIO_OTYPER register ****************/
12119 #define GPIO_OTYPER_OT0_Pos (0U)
12120 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
12121 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
12122 #define GPIO_OTYPER_OT1_Pos (1U)
12123 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
12124 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
12125 #define GPIO_OTYPER_OT2_Pos (2U)
12126 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
12127 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
12128 #define GPIO_OTYPER_OT3_Pos (3U)
12129 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
12130 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
12131 #define GPIO_OTYPER_OT4_Pos (4U)
12132 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
12133 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
12134 #define GPIO_OTYPER_OT5_Pos (5U)
12135 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
12136 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
12137 #define GPIO_OTYPER_OT6_Pos (6U)
12138 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
12139 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
12140 #define GPIO_OTYPER_OT7_Pos (7U)
12141 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
12142 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
12143 #define GPIO_OTYPER_OT8_Pos (8U)
12144 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
12145 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
12146 #define GPIO_OTYPER_OT9_Pos (9U)
12147 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
12148 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
12149 #define GPIO_OTYPER_OT10_Pos (10U)
12150 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
12151 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
12152 #define GPIO_OTYPER_OT11_Pos (11U)
12153 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
12154 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
12155 #define GPIO_OTYPER_OT12_Pos (12U)
12156 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
12157 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
12158 #define GPIO_OTYPER_OT13_Pos (13U)
12159 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
12160 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
12161 #define GPIO_OTYPER_OT14_Pos (14U)
12162 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
12163 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
12164 #define GPIO_OTYPER_OT15_Pos (15U)
12165 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
12166 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
12167 
12168 /****************** Bits definition for GPIO_OSPEEDR register ***************/
12169 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
12170 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
12171 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
12172 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
12173 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
12175 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
12176 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
12177 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
12178 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
12179 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
12181 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
12182 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
12183 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
12184 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
12185 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
12187 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
12188 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
12189 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
12190 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
12191 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
12193 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
12194 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
12195 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
12196 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
12197 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
12199 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
12200 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
12201 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
12202 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
12203 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
12205 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
12206 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
12207 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
12208 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
12209 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
12211 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
12212 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
12213 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
12214 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
12215 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
12217 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
12218 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
12219 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
12220 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
12221 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
12223 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
12224 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
12225 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
12226 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
12227 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
12229 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
12230 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
12231 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
12232 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
12233 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
12235 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
12236 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
12237 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
12238 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
12239 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
12241 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
12242 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
12243 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
12244 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
12245 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
12247 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
12248 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
12249 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
12250 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
12251 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
12253 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
12254 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
12255 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
12256 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
12257 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
12259 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
12260 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
12261 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
12262 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
12263 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
12265 /****************** Bits definition for GPIO_PUPDR register *****************/
12266 #define GPIO_PUPDR_PUPD0_Pos (0U)
12267 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
12268 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
12269 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
12270 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
12272 #define GPIO_PUPDR_PUPD1_Pos (2U)
12273 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
12274 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
12275 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
12276 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
12278 #define GPIO_PUPDR_PUPD2_Pos (4U)
12279 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
12280 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
12281 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
12282 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
12284 #define GPIO_PUPDR_PUPD3_Pos (6U)
12285 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
12286 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
12287 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
12288 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
12290 #define GPIO_PUPDR_PUPD4_Pos (8U)
12291 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
12292 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
12293 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
12294 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
12296 #define GPIO_PUPDR_PUPD5_Pos (10U)
12297 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
12298 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
12299 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
12300 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
12302 #define GPIO_PUPDR_PUPD6_Pos (12U)
12303 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
12304 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
12305 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
12306 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
12308 #define GPIO_PUPDR_PUPD7_Pos (14U)
12309 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
12310 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
12311 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
12312 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
12314 #define GPIO_PUPDR_PUPD8_Pos (16U)
12315 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
12316 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
12317 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
12318 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
12320 #define GPIO_PUPDR_PUPD9_Pos (18U)
12321 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
12322 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
12323 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
12324 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
12326 #define GPIO_PUPDR_PUPD10_Pos (20U)
12327 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
12328 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
12329 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
12330 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
12332 #define GPIO_PUPDR_PUPD11_Pos (22U)
12333 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
12334 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
12335 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
12336 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
12338 #define GPIO_PUPDR_PUPD12_Pos (24U)
12339 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
12340 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
12341 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
12342 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
12344 #define GPIO_PUPDR_PUPD13_Pos (26U)
12345 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
12346 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
12347 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
12348 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
12350 #define GPIO_PUPDR_PUPD14_Pos (28U)
12351 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
12352 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
12353 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
12354 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
12356 #define GPIO_PUPDR_PUPD15_Pos (30U)
12357 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
12358 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
12359 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
12360 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
12362 /****************** Bits definition for GPIO_IDR register *******************/
12363 #define GPIO_IDR_ID0_Pos (0U)
12364 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
12365 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
12366 #define GPIO_IDR_ID1_Pos (1U)
12367 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
12368 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
12369 #define GPIO_IDR_ID2_Pos (2U)
12370 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
12371 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
12372 #define GPIO_IDR_ID3_Pos (3U)
12373 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
12374 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
12375 #define GPIO_IDR_ID4_Pos (4U)
12376 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
12377 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
12378 #define GPIO_IDR_ID5_Pos (5U)
12379 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
12380 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
12381 #define GPIO_IDR_ID6_Pos (6U)
12382 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
12383 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
12384 #define GPIO_IDR_ID7_Pos (7U)
12385 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
12386 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
12387 #define GPIO_IDR_ID8_Pos (8U)
12388 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
12389 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
12390 #define GPIO_IDR_ID9_Pos (9U)
12391 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
12392 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
12393 #define GPIO_IDR_ID10_Pos (10U)
12394 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
12395 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
12396 #define GPIO_IDR_ID11_Pos (11U)
12397 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
12398 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
12399 #define GPIO_IDR_ID12_Pos (12U)
12400 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
12401 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
12402 #define GPIO_IDR_ID13_Pos (13U)
12403 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
12404 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
12405 #define GPIO_IDR_ID14_Pos (14U)
12406 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
12407 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
12408 #define GPIO_IDR_ID15_Pos (15U)
12409 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
12410 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
12411 
12412 /****************** Bits definition for GPIO_ODR register *******************/
12413 #define GPIO_ODR_OD0_Pos (0U)
12414 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
12415 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
12416 #define GPIO_ODR_OD1_Pos (1U)
12417 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
12418 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
12419 #define GPIO_ODR_OD2_Pos (2U)
12420 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
12421 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
12422 #define GPIO_ODR_OD3_Pos (3U)
12423 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
12424 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
12425 #define GPIO_ODR_OD4_Pos (4U)
12426 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
12427 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
12428 #define GPIO_ODR_OD5_Pos (5U)
12429 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
12430 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
12431 #define GPIO_ODR_OD6_Pos (6U)
12432 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
12433 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
12434 #define GPIO_ODR_OD7_Pos (7U)
12435 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
12436 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
12437 #define GPIO_ODR_OD8_Pos (8U)
12438 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
12439 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
12440 #define GPIO_ODR_OD9_Pos (9U)
12441 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
12442 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
12443 #define GPIO_ODR_OD10_Pos (10U)
12444 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
12445 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
12446 #define GPIO_ODR_OD11_Pos (11U)
12447 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
12448 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
12449 #define GPIO_ODR_OD12_Pos (12U)
12450 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
12451 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
12452 #define GPIO_ODR_OD13_Pos (13U)
12453 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
12454 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
12455 #define GPIO_ODR_OD14_Pos (14U)
12456 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
12457 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
12458 #define GPIO_ODR_OD15_Pos (15U)
12459 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
12460 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
12461 
12462 /****************** Bits definition for GPIO_BSRR register ******************/
12463 #define GPIO_BSRR_BS0_Pos (0U)
12464 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
12465 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
12466 #define GPIO_BSRR_BS1_Pos (1U)
12467 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
12468 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
12469 #define GPIO_BSRR_BS2_Pos (2U)
12470 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
12471 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
12472 #define GPIO_BSRR_BS3_Pos (3U)
12473 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
12474 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
12475 #define GPIO_BSRR_BS4_Pos (4U)
12476 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
12477 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
12478 #define GPIO_BSRR_BS5_Pos (5U)
12479 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
12480 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
12481 #define GPIO_BSRR_BS6_Pos (6U)
12482 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
12483 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
12484 #define GPIO_BSRR_BS7_Pos (7U)
12485 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
12486 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
12487 #define GPIO_BSRR_BS8_Pos (8U)
12488 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
12489 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
12490 #define GPIO_BSRR_BS9_Pos (9U)
12491 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
12492 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
12493 #define GPIO_BSRR_BS10_Pos (10U)
12494 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
12495 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
12496 #define GPIO_BSRR_BS11_Pos (11U)
12497 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
12498 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
12499 #define GPIO_BSRR_BS12_Pos (12U)
12500 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
12501 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
12502 #define GPIO_BSRR_BS13_Pos (13U)
12503 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
12504 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
12505 #define GPIO_BSRR_BS14_Pos (14U)
12506 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
12507 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
12508 #define GPIO_BSRR_BS15_Pos (15U)
12509 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
12510 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
12511 #define GPIO_BSRR_BR0_Pos (16U)
12512 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
12513 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
12514 #define GPIO_BSRR_BR1_Pos (17U)
12515 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
12516 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
12517 #define GPIO_BSRR_BR2_Pos (18U)
12518 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
12519 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
12520 #define GPIO_BSRR_BR3_Pos (19U)
12521 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
12522 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
12523 #define GPIO_BSRR_BR4_Pos (20U)
12524 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
12525 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
12526 #define GPIO_BSRR_BR5_Pos (21U)
12527 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
12528 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
12529 #define GPIO_BSRR_BR6_Pos (22U)
12530 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
12531 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
12532 #define GPIO_BSRR_BR7_Pos (23U)
12533 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
12534 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
12535 #define GPIO_BSRR_BR8_Pos (24U)
12536 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
12537 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
12538 #define GPIO_BSRR_BR9_Pos (25U)
12539 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
12540 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
12541 #define GPIO_BSRR_BR10_Pos (26U)
12542 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
12543 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
12544 #define GPIO_BSRR_BR11_Pos (27U)
12545 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
12546 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
12547 #define GPIO_BSRR_BR12_Pos (28U)
12548 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
12549 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
12550 #define GPIO_BSRR_BR13_Pos (29U)
12551 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
12552 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
12553 #define GPIO_BSRR_BR14_Pos (30U)
12554 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
12555 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
12556 #define GPIO_BSRR_BR15_Pos (31U)
12557 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
12558 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
12559 
12560 /****************** Bit definition for GPIO_LCKR register *********************/
12561 #define GPIO_LCKR_LCK0_Pos (0U)
12562 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
12563 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
12564 #define GPIO_LCKR_LCK1_Pos (1U)
12565 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
12566 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
12567 #define GPIO_LCKR_LCK2_Pos (2U)
12568 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
12569 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
12570 #define GPIO_LCKR_LCK3_Pos (3U)
12571 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
12572 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
12573 #define GPIO_LCKR_LCK4_Pos (4U)
12574 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
12575 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
12576 #define GPIO_LCKR_LCK5_Pos (5U)
12577 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
12578 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
12579 #define GPIO_LCKR_LCK6_Pos (6U)
12580 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
12581 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
12582 #define GPIO_LCKR_LCK7_Pos (7U)
12583 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
12584 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
12585 #define GPIO_LCKR_LCK8_Pos (8U)
12586 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
12587 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
12588 #define GPIO_LCKR_LCK9_Pos (9U)
12589 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
12590 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
12591 #define GPIO_LCKR_LCK10_Pos (10U)
12592 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
12593 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12594 #define GPIO_LCKR_LCK11_Pos (11U)
12595 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
12596 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12597 #define GPIO_LCKR_LCK12_Pos (12U)
12598 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
12599 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12600 #define GPIO_LCKR_LCK13_Pos (13U)
12601 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
12602 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12603 #define GPIO_LCKR_LCK14_Pos (14U)
12604 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
12605 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12606 #define GPIO_LCKR_LCK15_Pos (15U)
12607 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
12608 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12609 #define GPIO_LCKR_LCKK_Pos (16U)
12610 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
12611 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12612 
12613 /****************** Bit definition for GPIO_AFRL register ********************/
12614 #define GPIO_AFRL_AFSEL0_Pos (0U)
12615 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
12616 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12617 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
12618 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
12619 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
12620 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
12621 #define GPIO_AFRL_AFSEL1_Pos (4U)
12622 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
12623 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12624 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
12625 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
12626 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
12627 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
12628 #define GPIO_AFRL_AFSEL2_Pos (8U)
12629 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
12630 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12631 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
12632 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
12633 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
12634 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
12635 #define GPIO_AFRL_AFSEL3_Pos (12U)
12636 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
12637 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12638 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
12639 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
12640 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
12641 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
12642 #define GPIO_AFRL_AFSEL4_Pos (16U)
12643 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
12644 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12645 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
12646 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
12647 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
12648 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
12649 #define GPIO_AFRL_AFSEL5_Pos (20U)
12650 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
12651 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12652 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
12653 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
12654 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
12655 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
12656 #define GPIO_AFRL_AFSEL6_Pos (24U)
12657 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
12658 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12659 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
12660 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
12661 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
12662 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
12663 #define GPIO_AFRL_AFSEL7_Pos (28U)
12664 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
12665 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12666 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
12667 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
12668 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
12669 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
12671 /* Legacy defines */
12672 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12673 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12674 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12675 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12676 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12677 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12678 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12679 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12680 
12681 /****************** Bit definition for GPIO_AFRH register ********************/
12682 #define GPIO_AFRH_AFSEL8_Pos (0U)
12683 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
12684 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12685 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
12686 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
12687 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
12688 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
12689 #define GPIO_AFRH_AFSEL9_Pos (4U)
12690 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
12691 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12692 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
12693 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
12694 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
12695 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
12696 #define GPIO_AFRH_AFSEL10_Pos (8U)
12697 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
12698 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12699 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
12700 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
12701 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
12702 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
12703 #define GPIO_AFRH_AFSEL11_Pos (12U)
12704 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
12705 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12706 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
12707 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
12708 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
12709 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
12710 #define GPIO_AFRH_AFSEL12_Pos (16U)
12711 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
12712 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12713 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
12714 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
12715 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
12716 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
12717 #define GPIO_AFRH_AFSEL13_Pos (20U)
12718 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
12719 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12720 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
12721 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
12722 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
12723 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
12724 #define GPIO_AFRH_AFSEL14_Pos (24U)
12725 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
12726 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12727 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
12728 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
12729 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
12730 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
12731 #define GPIO_AFRH_AFSEL15_Pos (28U)
12732 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
12733 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12734 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
12735 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
12736 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
12737 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
12739 /* Legacy defines */
12740 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12741 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12742 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12743 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12744 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12745 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12746 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12747 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12748 
12749 /******************************************************************************/
12750 /* */
12751 /* HSEM HW Semaphore */
12752 /* */
12753 /******************************************************************************/
12754 /******************** Bit definition for HSEM_R register ********************/
12755 #define HSEM_R_PROCID_Pos (0U)
12756 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos)
12757 #define HSEM_R_PROCID HSEM_R_PROCID_Msk
12758 #define HSEM_R_COREID_Pos (8U)
12759 #define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos)
12760 #define HSEM_R_COREID HSEM_R_COREID_Msk
12761 #define HSEM_R_LOCK_Pos (31U)
12762 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos)
12763 #define HSEM_R_LOCK HSEM_R_LOCK_Msk
12765 /******************** Bit definition for HSEM_RLR register ******************/
12766 #define HSEM_RLR_PROCID_Pos (0U)
12767 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos)
12768 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk
12769 #define HSEM_RLR_COREID_Pos (8U)
12770 #define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos)
12771 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk
12772 #define HSEM_RLR_LOCK_Pos (31U)
12773 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos)
12774 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk
12776 /******************** Bit definition for HSEM_C1IER register *****************/
12777 #define HSEM_C1IER_ISE0_Pos (0U)
12778 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos)
12779 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk
12780 #define HSEM_C1IER_ISE1_Pos (1U)
12781 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos)
12782 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk
12783 #define HSEM_C1IER_ISE2_Pos (2U)
12784 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos)
12785 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk
12786 #define HSEM_C1IER_ISE3_Pos (3U)
12787 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos)
12788 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk
12789 #define HSEM_C1IER_ISE4_Pos (4U)
12790 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos)
12791 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk
12792 #define HSEM_C1IER_ISE5_Pos (5U)
12793 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos)
12794 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk
12795 #define HSEM_C1IER_ISE6_Pos (6U)
12796 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos)
12797 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk
12798 #define HSEM_C1IER_ISE7_Pos (7U)
12799 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos)
12800 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk
12801 #define HSEM_C1IER_ISE8_Pos (8U)
12802 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos)
12803 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk
12804 #define HSEM_C1IER_ISE9_Pos (9U)
12805 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos)
12806 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk
12807 #define HSEM_C1IER_ISE10_Pos (10U)
12808 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos)
12809 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk
12810 #define HSEM_C1IER_ISE11_Pos (11U)
12811 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos)
12812 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk
12813 #define HSEM_C1IER_ISE12_Pos (12U)
12814 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos)
12815 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk
12816 #define HSEM_C1IER_ISE13_Pos (13U)
12817 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos)
12818 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk
12819 #define HSEM_C1IER_ISE14_Pos (14U)
12820 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos)
12821 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk
12822 #define HSEM_C1IER_ISE15_Pos (15U)
12823 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos)
12824 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk
12825 #define HSEM_C1IER_ISE16_Pos (16U)
12826 #define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos)
12827 #define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk
12828 #define HSEM_C1IER_ISE17_Pos (17U)
12829 #define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos)
12830 #define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk
12831 #define HSEM_C1IER_ISE18_Pos (18U)
12832 #define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos)
12833 #define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk
12834 #define HSEM_C1IER_ISE19_Pos (19U)
12835 #define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos)
12836 #define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk
12837 #define HSEM_C1IER_ISE20_Pos (20U)
12838 #define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos)
12839 #define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk
12840 #define HSEM_C1IER_ISE21_Pos (21U)
12841 #define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos)
12842 #define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk
12843 #define HSEM_C1IER_ISE22_Pos (22U)
12844 #define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos)
12845 #define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk
12846 #define HSEM_C1IER_ISE23_Pos (23U)
12847 #define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos)
12848 #define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk
12849 #define HSEM_C1IER_ISE24_Pos (24U)
12850 #define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos)
12851 #define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk
12852 #define HSEM_C1IER_ISE25_Pos (25U)
12853 #define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos)
12854 #define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk
12855 #define HSEM_C1IER_ISE26_Pos (26U)
12856 #define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos)
12857 #define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk
12858 #define HSEM_C1IER_ISE27_Pos (27U)
12859 #define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos)
12860 #define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk
12861 #define HSEM_C1IER_ISE28_Pos (28U)
12862 #define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos)
12863 #define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk
12864 #define HSEM_C1IER_ISE29_Pos (29U)
12865 #define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos)
12866 #define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk
12867 #define HSEM_C1IER_ISE30_Pos (30U)
12868 #define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos)
12869 #define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk
12870 #define HSEM_C1IER_ISE31_Pos (31U)
12871 #define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos)
12872 #define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk
12874 /******************** Bit definition for HSEM_C1ICR register *****************/
12875 #define HSEM_C1ICR_ISC0_Pos (0U)
12876 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos)
12877 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk
12878 #define HSEM_C1ICR_ISC1_Pos (1U)
12879 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos)
12880 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk
12881 #define HSEM_C1ICR_ISC2_Pos (2U)
12882 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos)
12883 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk
12884 #define HSEM_C1ICR_ISC3_Pos (3U)
12885 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos)
12886 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk
12887 #define HSEM_C1ICR_ISC4_Pos (4U)
12888 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos)
12889 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk
12890 #define HSEM_C1ICR_ISC5_Pos (5U)
12891 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos)
12892 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk
12893 #define HSEM_C1ICR_ISC6_Pos (6U)
12894 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos)
12895 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk
12896 #define HSEM_C1ICR_ISC7_Pos (7U)
12897 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos)
12898 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk
12899 #define HSEM_C1ICR_ISC8_Pos (8U)
12900 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos)
12901 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk
12902 #define HSEM_C1ICR_ISC9_Pos (9U)
12903 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos)
12904 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk
12905 #define HSEM_C1ICR_ISC10_Pos (10U)
12906 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos)
12907 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk
12908 #define HSEM_C1ICR_ISC11_Pos (11U)
12909 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos)
12910 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk
12911 #define HSEM_C1ICR_ISC12_Pos (12U)
12912 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos)
12913 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk
12914 #define HSEM_C1ICR_ISC13_Pos (13U)
12915 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos)
12916 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk
12917 #define HSEM_C1ICR_ISC14_Pos (14U)
12918 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos)
12919 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk
12920 #define HSEM_C1ICR_ISC15_Pos (15U)
12921 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos)
12922 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk
12923 #define HSEM_C1ICR_ISC16_Pos (16U)
12924 #define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos)
12925 #define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk
12926 #define HSEM_C1ICR_ISC17_Pos (17U)
12927 #define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos)
12928 #define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk
12929 #define HSEM_C1ICR_ISC18_Pos (18U)
12930 #define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos)
12931 #define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk
12932 #define HSEM_C1ICR_ISC19_Pos (19U)
12933 #define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos)
12934 #define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk
12935 #define HSEM_C1ICR_ISC20_Pos (20U)
12936 #define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos)
12937 #define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk
12938 #define HSEM_C1ICR_ISC21_Pos (21U)
12939 #define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos)
12940 #define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk
12941 #define HSEM_C1ICR_ISC22_Pos (22U)
12942 #define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos)
12943 #define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk
12944 #define HSEM_C1ICR_ISC23_Pos (23U)
12945 #define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos)
12946 #define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk
12947 #define HSEM_C1ICR_ISC24_Pos (24U)
12948 #define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos)
12949 #define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk
12950 #define HSEM_C1ICR_ISC25_Pos (25U)
12951 #define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos)
12952 #define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk
12953 #define HSEM_C1ICR_ISC26_Pos (26U)
12954 #define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos)
12955 #define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk
12956 #define HSEM_C1ICR_ISC27_Pos (27U)
12957 #define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos)
12958 #define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk
12959 #define HSEM_C1ICR_ISC28_Pos (28U)
12960 #define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos)
12961 #define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk
12962 #define HSEM_C1ICR_ISC29_Pos (29U)
12963 #define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos)
12964 #define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk
12965 #define HSEM_C1ICR_ISC30_Pos (30U)
12966 #define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos)
12967 #define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk
12968 #define HSEM_C1ICR_ISC31_Pos (31U)
12969 #define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos)
12970 #define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk
12972 /******************** Bit definition for HSEM_C1ISR register *****************/
12973 #define HSEM_C1ISR_ISF0_Pos (0U)
12974 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos)
12975 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk
12976 #define HSEM_C1ISR_ISF1_Pos (1U)
12977 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos)
12978 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk
12979 #define HSEM_C1ISR_ISF2_Pos (2U)
12980 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos)
12981 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk
12982 #define HSEM_C1ISR_ISF3_Pos (3U)
12983 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos)
12984 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk
12985 #define HSEM_C1ISR_ISF4_Pos (4U)
12986 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos)
12987 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk
12988 #define HSEM_C1ISR_ISF5_Pos (5U)
12989 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos)
12990 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk
12991 #define HSEM_C1ISR_ISF6_Pos (6U)
12992 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos)
12993 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk
12994 #define HSEM_C1ISR_ISF7_Pos (7U)
12995 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos)
12996 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk
12997 #define HSEM_C1ISR_ISF8_Pos (8U)
12998 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos)
12999 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk
13000 #define HSEM_C1ISR_ISF9_Pos (9U)
13001 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos)
13002 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk
13003 #define HSEM_C1ISR_ISF10_Pos (10U)
13004 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos)
13005 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk
13006 #define HSEM_C1ISR_ISF11_Pos (11U)
13007 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos)
13008 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk
13009 #define HSEM_C1ISR_ISF12_Pos (12U)
13010 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos)
13011 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk
13012 #define HSEM_C1ISR_ISF13_Pos (13U)
13013 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos)
13014 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk
13015 #define HSEM_C1ISR_ISF14_Pos (14U)
13016 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos)
13017 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk
13018 #define HSEM_C1ISR_ISF15_Pos (15U)
13019 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos)
13020 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk
13021 #define HSEM_C1ISR_ISF16_Pos (16U)
13022 #define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos)
13023 #define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk
13024 #define HSEM_C1ISR_ISF17_Pos (17U)
13025 #define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos)
13026 #define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk
13027 #define HSEM_C1ISR_ISF18_Pos (18U)
13028 #define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos)
13029 #define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk
13030 #define HSEM_C1ISR_ISF19_Pos (19U)
13031 #define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos)
13032 #define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk
13033 #define HSEM_C1ISR_ISF20_Pos (20U)
13034 #define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos)
13035 #define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk
13036 #define HSEM_C1ISR_ISF21_Pos (21U)
13037 #define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos)
13038 #define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk
13039 #define HSEM_C1ISR_ISF22_Pos (22U)
13040 #define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos)
13041 #define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk
13042 #define HSEM_C1ISR_ISF23_Pos (23U)
13043 #define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos)
13044 #define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk
13045 #define HSEM_C1ISR_ISF24_Pos (24U)
13046 #define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos)
13047 #define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk
13048 #define HSEM_C1ISR_ISF25_Pos (25U)
13049 #define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos)
13050 #define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk
13051 #define HSEM_C1ISR_ISF26_Pos (26U)
13052 #define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos)
13053 #define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk
13054 #define HSEM_C1ISR_ISF27_Pos (27U)
13055 #define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos)
13056 #define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk
13057 #define HSEM_C1ISR_ISF28_Pos (28U)
13058 #define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos)
13059 #define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk
13060 #define HSEM_C1ISR_ISF29_Pos (29U)
13061 #define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos)
13062 #define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk
13063 #define HSEM_C1ISR_ISF30_Pos (30U)
13064 #define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos)
13065 #define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk
13066 #define HSEM_C1ISR_ISF31_Pos (31U)
13067 #define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos)
13068 #define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk
13070 /******************** Bit definition for HSEM_C1MISR register *****************/
13071 #define HSEM_C1MISR_MISF0_Pos (0U)
13072 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos)
13073 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk
13074 #define HSEM_C1MISR_MISF1_Pos (1U)
13075 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos)
13076 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk
13077 #define HSEM_C1MISR_MISF2_Pos (2U)
13078 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos)
13079 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk
13080 #define HSEM_C1MISR_MISF3_Pos (3U)
13081 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos)
13082 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk
13083 #define HSEM_C1MISR_MISF4_Pos (4U)
13084 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos)
13085 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk
13086 #define HSEM_C1MISR_MISF5_Pos (5U)
13087 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos)
13088 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk
13089 #define HSEM_C1MISR_MISF6_Pos (6U)
13090 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos)
13091 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk
13092 #define HSEM_C1MISR_MISF7_Pos (7U)
13093 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos)
13094 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk
13095 #define HSEM_C1MISR_MISF8_Pos (8U)
13096 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos)
13097 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk
13098 #define HSEM_C1MISR_MISF9_Pos (9U)
13099 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos)
13100 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk
13101 #define HSEM_C1MISR_MISF10_Pos (10U)
13102 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos)
13103 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk
13104 #define HSEM_C1MISR_MISF11_Pos (11U)
13105 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos)
13106 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk
13107 #define HSEM_C1MISR_MISF12_Pos (12U)
13108 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos)
13109 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk
13110 #define HSEM_C1MISR_MISF13_Pos (13U)
13111 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos)
13112 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk
13113 #define HSEM_C1MISR_MISF14_Pos (14U)
13114 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos)
13115 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk
13116 #define HSEM_C1MISR_MISF15_Pos (15U)
13117 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos)
13118 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk
13119 #define HSEM_C1MISR_MISF16_Pos (16U)
13120 #define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos)
13121 #define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk
13122 #define HSEM_C1MISR_MISF17_Pos (17U)
13123 #define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos)
13124 #define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk
13125 #define HSEM_C1MISR_MISF18_Pos (18U)
13126 #define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos)
13127 #define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk
13128 #define HSEM_C1MISR_MISF19_Pos (19U)
13129 #define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos)
13130 #define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk
13131 #define HSEM_C1MISR_MISF20_Pos (20U)
13132 #define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos)
13133 #define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk
13134 #define HSEM_C1MISR_MISF21_Pos (21U)
13135 #define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos)
13136 #define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk
13137 #define HSEM_C1MISR_MISF22_Pos (22U)
13138 #define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos)
13139 #define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk
13140 #define HSEM_C1MISR_MISF23_Pos (23U)
13141 #define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos)
13142 #define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk
13143 #define HSEM_C1MISR_MISF24_Pos (24U)
13144 #define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos)
13145 #define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk
13146 #define HSEM_C1MISR_MISF25_Pos (25U)
13147 #define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos)
13148 #define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk
13149 #define HSEM_C1MISR_MISF26_Pos (26U)
13150 #define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos)
13151 #define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk
13152 #define HSEM_C1MISR_MISF27_Pos (27U)
13153 #define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos)
13154 #define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk
13155 #define HSEM_C1MISR_MISF28_Pos (28U)
13156 #define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos)
13157 #define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk
13158 #define HSEM_C1MISR_MISF29_Pos (29U)
13159 #define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos)
13160 #define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk
13161 #define HSEM_C1MISR_MISF30_Pos (30U)
13162 #define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos)
13163 #define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk
13164 #define HSEM_C1MISR_MISF31_Pos (31U)
13165 #define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos)
13166 #define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk
13168 /******************** Bit definition for HSEM_CR register *****************/
13169 #define HSEM_CR_COREID_Pos (8U)
13170 #define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos)
13171 #define HSEM_CR_COREID HSEM_CR_COREID_Msk
13172 #define HSEM_CR_KEY_Pos (16U)
13173 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos)
13174 #define HSEM_CR_KEY HSEM_CR_KEY_Msk
13176 /******************** Bit definition for HSEM_KEYR register *****************/
13177 #define HSEM_KEYR_KEY_Pos (16U)
13178 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos)
13179 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk
13181 /******************************************************************************/
13182 /* */
13183 /* HASH */
13184 /* */
13185 /******************************************************************************/
13186 /****************** Bits definition for HASH_CR register ********************/
13187 #define HASH_CR_INIT_Pos (2U)
13188 #define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos)
13189 #define HASH_CR_INIT HASH_CR_INIT_Msk
13190 #define HASH_CR_DMAE_Pos (3U)
13191 #define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos)
13192 #define HASH_CR_DMAE HASH_CR_DMAE_Msk
13193 #define HASH_CR_DATATYPE_Pos (4U)
13194 #define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)
13195 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
13196 #define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos)
13197 #define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos)
13198 #define HASH_CR_MODE_Pos (6U)
13199 #define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos)
13200 #define HASH_CR_MODE HASH_CR_MODE_Msk
13201 #define HASH_CR_ALGO_Pos (7U)
13202 #define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos)
13203 #define HASH_CR_ALGO HASH_CR_ALGO_Msk
13204 #define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos)
13205 #define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos)
13206 #define HASH_CR_NBW_Pos (8U)
13207 #define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos)
13208 #define HASH_CR_NBW HASH_CR_NBW_Msk
13209 #define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos)
13210 #define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos)
13211 #define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos)
13212 #define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos)
13213 #define HASH_CR_DINNE_Pos (12U)
13214 #define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos)
13215 #define HASH_CR_DINNE HASH_CR_DINNE_Msk
13216 #define HASH_CR_MDMAT_Pos (13U)
13217 #define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos)
13218 #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
13219 #define HASH_CR_LKEY_Pos (16U)
13220 #define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos)
13221 #define HASH_CR_LKEY HASH_CR_LKEY_Msk
13222 
13223 /****************** Bits definition for HASH_STR register *******************/
13224 #define HASH_STR_NBLW_Pos (0U)
13225 #define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos)
13226 #define HASH_STR_NBLW HASH_STR_NBLW_Msk
13227 #define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos)
13228 #define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos)
13229 #define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos)
13230 #define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos)
13231 #define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos)
13232 #define HASH_STR_DCAL_Pos (8U)
13233 #define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos)
13234 #define HASH_STR_DCAL HASH_STR_DCAL_Msk
13235 
13236 /****************** Bits definition for HASH_IMR register *******************/
13237 #define HASH_IMR_DINIE_Pos (0U)
13238 #define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos)
13239 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
13240 #define HASH_IMR_DCIE_Pos (1U)
13241 #define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos)
13242 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
13243 
13244 /****************** Bits definition for HASH_SR register ********************/
13245 #define HASH_SR_DINIS_Pos (0U)
13246 #define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos)
13247 #define HASH_SR_DINIS HASH_SR_DINIS_Msk
13248 #define HASH_SR_DCIS_Pos (1U)
13249 #define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos)
13250 #define HASH_SR_DCIS HASH_SR_DCIS_Msk
13251 #define HASH_SR_DMAS_Pos (2U)
13252 #define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos)
13253 #define HASH_SR_DMAS HASH_SR_DMAS_Msk
13254 #define HASH_SR_BUSY_Pos (3U)
13255 #define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos)
13256 #define HASH_SR_BUSY HASH_SR_BUSY_Msk
13257 /******************************************************************************/
13258 /* */
13259 /* Inter-integrated Circuit Interface (I2C) */
13260 /* */
13261 /******************************************************************************/
13262 /******************* Bit definition for I2C_CR1 register *******************/
13263 #define I2C_CR1_PE_Pos (0U)
13264 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
13265 #define I2C_CR1_PE I2C_CR1_PE_Msk
13266 #define I2C_CR1_TXIE_Pos (1U)
13267 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
13268 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
13269 #define I2C_CR1_RXIE_Pos (2U)
13270 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
13271 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
13272 #define I2C_CR1_ADDRIE_Pos (3U)
13273 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
13274 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
13275 #define I2C_CR1_NACKIE_Pos (4U)
13276 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
13277 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
13278 #define I2C_CR1_STOPIE_Pos (5U)
13279 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
13280 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
13281 #define I2C_CR1_TCIE_Pos (6U)
13282 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
13283 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
13284 #define I2C_CR1_ERRIE_Pos (7U)
13285 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
13286 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
13287 #define I2C_CR1_DNF_Pos (8U)
13288 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
13289 #define I2C_CR1_DNF I2C_CR1_DNF_Msk
13290 #define I2C_CR1_ANFOFF_Pos (12U)
13291 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
13292 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
13293 #define I2C_CR1_TXDMAEN_Pos (14U)
13294 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
13295 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
13296 #define I2C_CR1_RXDMAEN_Pos (15U)
13297 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
13298 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
13299 #define I2C_CR1_SBC_Pos (16U)
13300 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
13301 #define I2C_CR1_SBC I2C_CR1_SBC_Msk
13302 #define I2C_CR1_NOSTRETCH_Pos (17U)
13303 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
13304 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
13305 #define I2C_CR1_WUPEN_Pos (18U)
13306 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
13307 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
13308 #define I2C_CR1_GCEN_Pos (19U)
13309 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
13310 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
13311 #define I2C_CR1_SMBHEN_Pos (20U)
13312 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
13313 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
13314 #define I2C_CR1_SMBDEN_Pos (21U)
13315 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
13316 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
13317 #define I2C_CR1_ALERTEN_Pos (22U)
13318 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
13319 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
13320 #define I2C_CR1_PECEN_Pos (23U)
13321 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
13322 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
13324 /****************** Bit definition for I2C_CR2 register ********************/
13325 #define I2C_CR2_SADD_Pos (0U)
13326 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
13327 #define I2C_CR2_SADD I2C_CR2_SADD_Msk
13328 #define I2C_CR2_RD_WRN_Pos (10U)
13329 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
13330 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
13331 #define I2C_CR2_ADD10_Pos (11U)
13332 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
13333 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
13334 #define I2C_CR2_HEAD10R_Pos (12U)
13335 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
13336 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
13337 #define I2C_CR2_START_Pos (13U)
13338 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
13339 #define I2C_CR2_START I2C_CR2_START_Msk
13340 #define I2C_CR2_STOP_Pos (14U)
13341 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
13342 #define I2C_CR2_STOP I2C_CR2_STOP_Msk
13343 #define I2C_CR2_NACK_Pos (15U)
13344 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
13345 #define I2C_CR2_NACK I2C_CR2_NACK_Msk
13346 #define I2C_CR2_NBYTES_Pos (16U)
13347 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
13348 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
13349 #define I2C_CR2_RELOAD_Pos (24U)
13350 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
13351 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
13352 #define I2C_CR2_AUTOEND_Pos (25U)
13353 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
13354 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
13355 #define I2C_CR2_PECBYTE_Pos (26U)
13356 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
13357 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
13359 /******************* Bit definition for I2C_OAR1 register ******************/
13360 #define I2C_OAR1_OA1_Pos (0U)
13361 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
13362 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
13363 #define I2C_OAR1_OA1MODE_Pos (10U)
13364 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
13365 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
13366 #define I2C_OAR1_OA1EN_Pos (15U)
13367 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
13368 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
13370 /******************* Bit definition for I2C_OAR2 register ******************/
13371 #define I2C_OAR2_OA2_Pos (1U)
13372 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
13373 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
13374 #define I2C_OAR2_OA2MSK_Pos (8U)
13375 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
13376 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
13377 #define I2C_OAR2_OA2NOMASK 0x00000000UL
13378 #define I2C_OAR2_OA2MASK01_Pos (8U)
13379 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
13380 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
13381 #define I2C_OAR2_OA2MASK02_Pos (9U)
13382 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
13383 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
13384 #define I2C_OAR2_OA2MASK03_Pos (8U)
13385 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
13386 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
13387 #define I2C_OAR2_OA2MASK04_Pos (10U)
13388 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
13389 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
13390 #define I2C_OAR2_OA2MASK05_Pos (8U)
13391 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
13392 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
13393 #define I2C_OAR2_OA2MASK06_Pos (9U)
13394 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
13395 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
13396 #define I2C_OAR2_OA2MASK07_Pos (8U)
13397 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
13398 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
13399 #define I2C_OAR2_OA2EN_Pos (15U)
13400 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
13401 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
13403 /******************* Bit definition for I2C_TIMINGR register *******************/
13404 #define I2C_TIMINGR_SCLL_Pos (0U)
13405 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
13406 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
13407 #define I2C_TIMINGR_SCLH_Pos (8U)
13408 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
13409 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
13410 #define I2C_TIMINGR_SDADEL_Pos (16U)
13411 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
13412 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
13413 #define I2C_TIMINGR_SCLDEL_Pos (20U)
13414 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
13415 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
13416 #define I2C_TIMINGR_PRESC_Pos (28U)
13417 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
13418 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
13420 /******************* Bit definition for I2C_TIMEOUTR register *******************/
13421 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
13422 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
13423 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
13424 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
13425 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
13426 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
13427 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
13428 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
13429 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
13430 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
13431 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
13432 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
13433 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
13434 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
13435 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
13437 /****************** Bit definition for I2C_ISR register *********************/
13438 #define I2C_ISR_TXE_Pos (0U)
13439 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
13440 #define I2C_ISR_TXE I2C_ISR_TXE_Msk
13441 #define I2C_ISR_TXIS_Pos (1U)
13442 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
13443 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
13444 #define I2C_ISR_RXNE_Pos (2U)
13445 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
13446 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
13447 #define I2C_ISR_ADDR_Pos (3U)
13448 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
13449 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
13450 #define I2C_ISR_NACKF_Pos (4U)
13451 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
13452 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
13453 #define I2C_ISR_STOPF_Pos (5U)
13454 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
13455 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
13456 #define I2C_ISR_TC_Pos (6U)
13457 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
13458 #define I2C_ISR_TC I2C_ISR_TC_Msk
13459 #define I2C_ISR_TCR_Pos (7U)
13460 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
13461 #define I2C_ISR_TCR I2C_ISR_TCR_Msk
13462 #define I2C_ISR_BERR_Pos (8U)
13463 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
13464 #define I2C_ISR_BERR I2C_ISR_BERR_Msk
13465 #define I2C_ISR_ARLO_Pos (9U)
13466 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
13467 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
13468 #define I2C_ISR_OVR_Pos (10U)
13469 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
13470 #define I2C_ISR_OVR I2C_ISR_OVR_Msk
13471 #define I2C_ISR_PECERR_Pos (11U)
13472 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
13473 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
13474 #define I2C_ISR_TIMEOUT_Pos (12U)
13475 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
13476 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
13477 #define I2C_ISR_ALERT_Pos (13U)
13478 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
13479 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
13480 #define I2C_ISR_BUSY_Pos (15U)
13481 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
13482 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
13483 #define I2C_ISR_DIR_Pos (16U)
13484 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
13485 #define I2C_ISR_DIR I2C_ISR_DIR_Msk
13486 #define I2C_ISR_ADDCODE_Pos (17U)
13487 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
13488 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
13490 /****************** Bit definition for I2C_ICR register *********************/
13491 #define I2C_ICR_ADDRCF_Pos (3U)
13492 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
13493 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
13494 #define I2C_ICR_NACKCF_Pos (4U)
13495 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
13496 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
13497 #define I2C_ICR_STOPCF_Pos (5U)
13498 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
13499 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
13500 #define I2C_ICR_BERRCF_Pos (8U)
13501 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
13502 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
13503 #define I2C_ICR_ARLOCF_Pos (9U)
13504 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
13505 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
13506 #define I2C_ICR_OVRCF_Pos (10U)
13507 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
13508 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
13509 #define I2C_ICR_PECCF_Pos (11U)
13510 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
13511 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
13512 #define I2C_ICR_TIMOUTCF_Pos (12U)
13513 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
13514 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
13515 #define I2C_ICR_ALERTCF_Pos (13U)
13516 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
13517 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
13519 /****************** Bit definition for I2C_PECR register *********************/
13520 #define I2C_PECR_PEC_Pos (0U)
13521 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
13522 #define I2C_PECR_PEC I2C_PECR_PEC_Msk
13524 /****************** Bit definition for I2C_RXDR register *********************/
13525 #define I2C_RXDR_RXDATA_Pos (0U)
13526 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
13527 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
13529 /****************** Bit definition for I2C_TXDR register *********************/
13530 #define I2C_TXDR_TXDATA_Pos (0U)
13531 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
13532 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
13534 /******************************************************************************/
13535 /* */
13536 /* Independent WATCHDOG */
13537 /* */
13538 /******************************************************************************/
13539 /******************* Bit definition for IWDG_KR register ********************/
13540 #define IWDG_KR_KEY_Pos (0U)
13541 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
13542 #define IWDG_KR_KEY IWDG_KR_KEY_Msk
13544 /******************* Bit definition for IWDG_PR register ********************/
13545 #define IWDG_PR_PR_Pos (0U)
13546 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
13547 #define IWDG_PR_PR IWDG_PR_PR_Msk
13548 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
13549 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
13550 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
13552 /******************* Bit definition for IWDG_RLR register *******************/
13553 #define IWDG_RLR_RL_Pos (0U)
13554 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
13555 #define IWDG_RLR_RL IWDG_RLR_RL_Msk
13557 /******************* Bit definition for IWDG_SR register ********************/
13558 #define IWDG_SR_PVU_Pos (0U)
13559 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
13560 #define IWDG_SR_PVU IWDG_SR_PVU_Msk
13561 #define IWDG_SR_RVU_Pos (1U)
13562 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
13563 #define IWDG_SR_RVU IWDG_SR_RVU_Msk
13564 #define IWDG_SR_WVU_Pos (2U)
13565 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
13566 #define IWDG_SR_WVU IWDG_SR_WVU_Msk
13568 /******************* Bit definition for IWDG_KR register ********************/
13569 #define IWDG_WINR_WIN_Pos (0U)
13570 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
13571 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
13573 /******************************************************************************/
13574 /* */
13575 /* LCD-TFT Display Controller (LTDC) */
13576 /* */
13577 /******************************************************************************/
13578 
13579 /******************** Bit definition for LTDC_SSCR register *****************/
13580 
13581 #define LTDC_SSCR_VSH_Pos (0U)
13582 #define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
13583 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
13584 #define LTDC_SSCR_HSW_Pos (16U)
13585 #define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
13586 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
13588 /******************** Bit definition for LTDC_BPCR register *****************/
13589 
13590 #define LTDC_BPCR_AVBP_Pos (0U)
13591 #define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
13592 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
13593 #define LTDC_BPCR_AHBP_Pos (16U)
13594 #define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
13595 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
13597 /******************** Bit definition for LTDC_AWCR register *****************/
13598 
13599 #define LTDC_AWCR_AAH_Pos (0U)
13600 #define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
13601 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
13602 #define LTDC_AWCR_AAW_Pos (16U)
13603 #define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
13604 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
13606 /******************** Bit definition for LTDC_TWCR register *****************/
13607 
13608 #define LTDC_TWCR_TOTALH_Pos (0U)
13609 #define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
13610 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
13611 #define LTDC_TWCR_TOTALW_Pos (16U)
13612 #define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
13613 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
13615 /******************** Bit definition for LTDC_GCR register ******************/
13616 
13617 #define LTDC_GCR_LTDCEN_Pos (0U)
13618 #define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
13619 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
13620 #define LTDC_GCR_DBW_Pos (4U)
13621 #define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
13622 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
13623 #define LTDC_GCR_DGW_Pos (8U)
13624 #define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
13625 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
13626 #define LTDC_GCR_DRW_Pos (12U)
13627 #define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
13628 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
13629 #define LTDC_GCR_DEN_Pos (16U)
13630 #define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
13631 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
13632 #define LTDC_GCR_PCPOL_Pos (28U)
13633 #define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
13634 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
13635 #define LTDC_GCR_DEPOL_Pos (29U)
13636 #define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
13637 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
13638 #define LTDC_GCR_VSPOL_Pos (30U)
13639 #define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
13640 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
13641 #define LTDC_GCR_HSPOL_Pos (31U)
13642 #define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
13643 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
13646 /******************** Bit definition for LTDC_SRCR register *****************/
13647 
13648 #define LTDC_SRCR_IMR_Pos (0U)
13649 #define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
13650 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
13651 #define LTDC_SRCR_VBR_Pos (1U)
13652 #define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
13653 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
13655 /******************** Bit definition for LTDC_BCCR register *****************/
13656 
13657 #define LTDC_BCCR_BCBLUE_Pos (0U)
13658 #define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
13659 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
13660 #define LTDC_BCCR_BCGREEN_Pos (8U)
13661 #define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
13662 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
13663 #define LTDC_BCCR_BCRED_Pos (16U)
13664 #define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
13665 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
13667 /******************** Bit definition for LTDC_IER register ******************/
13668 
13669 #define LTDC_IER_LIE_Pos (0U)
13670 #define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
13671 #define LTDC_IER_LIE LTDC_IER_LIE_Msk
13672 #define LTDC_IER_FUIE_Pos (1U)
13673 #define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
13674 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
13675 #define LTDC_IER_TERRIE_Pos (2U)
13676 #define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
13677 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
13678 #define LTDC_IER_RRIE_Pos (3U)
13679 #define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
13680 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
13682 /******************** Bit definition for LTDC_ISR register ******************/
13683 
13684 #define LTDC_ISR_LIF_Pos (0U)
13685 #define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
13686 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
13687 #define LTDC_ISR_FUIF_Pos (1U)
13688 #define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
13689 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
13690 #define LTDC_ISR_TERRIF_Pos (2U)
13691 #define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
13692 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
13693 #define LTDC_ISR_RRIF_Pos (3U)
13694 #define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
13695 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
13697 /******************** Bit definition for LTDC_ICR register ******************/
13698 
13699 #define LTDC_ICR_CLIF_Pos (0U)
13700 #define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
13701 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
13702 #define LTDC_ICR_CFUIF_Pos (1U)
13703 #define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
13704 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
13705 #define LTDC_ICR_CTERRIF_Pos (2U)
13706 #define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
13707 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
13708 #define LTDC_ICR_CRRIF_Pos (3U)
13709 #define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
13710 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
13712 /******************** Bit definition for LTDC_LIPCR register ****************/
13713 
13714 #define LTDC_LIPCR_LIPOS_Pos (0U)
13715 #define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
13716 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
13718 /******************** Bit definition for LTDC_CPSR register *****************/
13719 
13720 #define LTDC_CPSR_CYPOS_Pos (0U)
13721 #define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
13722 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
13723 #define LTDC_CPSR_CXPOS_Pos (16U)
13724 #define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
13725 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
13727 /******************** Bit definition for LTDC_CDSR register *****************/
13728 
13729 #define LTDC_CDSR_VDES_Pos (0U)
13730 #define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
13731 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
13732 #define LTDC_CDSR_HDES_Pos (1U)
13733 #define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
13734 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
13735 #define LTDC_CDSR_VSYNCS_Pos (2U)
13736 #define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
13737 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
13738 #define LTDC_CDSR_HSYNCS_Pos (3U)
13739 #define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
13740 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
13742 /******************** Bit definition for LTDC_LxCR register *****************/
13743 
13744 #define LTDC_LxCR_LEN_Pos (0U)
13745 #define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
13746 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
13747 #define LTDC_LxCR_COLKEN_Pos (1U)
13748 #define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
13749 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
13750 #define LTDC_LxCR_CLUTEN_Pos (4U)
13751 #define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
13752 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
13754 /******************** Bit definition for LTDC_LxWHPCR register **************/
13755 
13756 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13757 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
13758 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
13759 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13760 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
13761 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
13763 /******************** Bit definition for LTDC_LxWVPCR register **************/
13764 
13765 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13766 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
13767 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
13768 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13769 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
13770 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
13772 /******************** Bit definition for LTDC_LxCKCR register ***************/
13773 
13774 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
13775 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
13776 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
13777 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
13778 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
13779 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
13780 #define LTDC_LxCKCR_CKRED_Pos (16U)
13781 #define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
13782 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
13784 /******************** Bit definition for LTDC_LxPFCR register ***************/
13785 
13786 #define LTDC_LxPFCR_PF_Pos (0U)
13787 #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
13788 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
13790 /******************** Bit definition for LTDC_LxCACR register ***************/
13791 
13792 #define LTDC_LxCACR_CONSTA_Pos (0U)
13793 #define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
13794 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
13796 /******************** Bit definition for LTDC_LxDCCR register ***************/
13797 
13798 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
13799 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
13800 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
13801 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
13802 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
13803 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
13804 #define LTDC_LxDCCR_DCRED_Pos (16U)
13805 #define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
13806 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
13807 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
13808 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
13809 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
13811 /******************** Bit definition for LTDC_LxBFCR register ***************/
13812 
13813 #define LTDC_LxBFCR_BF2_Pos (0U)
13814 #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
13815 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
13816 #define LTDC_LxBFCR_BF1_Pos (8U)
13817 #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
13818 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
13820 /******************** Bit definition for LTDC_LxCFBAR register **************/
13821 
13822 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
13823 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
13824 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
13826 /******************** Bit definition for LTDC_LxCFBLR register **************/
13827 
13828 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
13829 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
13830 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
13831 #define LTDC_LxCFBLR_CFBP_Pos (16U)
13832 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
13833 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
13835 /******************** Bit definition for LTDC_LxCFBLNR register *************/
13836 
13837 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
13838 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
13839 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
13841 /******************** Bit definition for LTDC_LxCLUTWR register *************/
13842 
13843 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
13844 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
13845 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
13846 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
13847 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
13848 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
13849 #define LTDC_LxCLUTWR_RED_Pos (16U)
13850 #define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
13851 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
13852 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
13853 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
13854 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
13856 /******************************************************************************/
13857 /* */
13858 /* MDMA */
13859 /* */
13860 /******************************************************************************/
13861 /******************** Bit definition for MDMA_GISR0 register ****************/
13862 #define MDMA_GISR0_GIF0_Pos (0U)
13863 #define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos)
13864 #define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk
13865 #define MDMA_GISR0_GIF1_Pos (1U)
13866 #define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos)
13867 #define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk
13868 #define MDMA_GISR0_GIF2_Pos (2U)
13869 #define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos)
13870 #define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk
13871 #define MDMA_GISR0_GIF3_Pos (3U)
13872 #define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos)
13873 #define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk
13874 #define MDMA_GISR0_GIF4_Pos (4U)
13875 #define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos)
13876 #define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk
13877 #define MDMA_GISR0_GIF5_Pos (5U)
13878 #define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos)
13879 #define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk
13880 #define MDMA_GISR0_GIF6_Pos (6U)
13881 #define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos)
13882 #define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk
13883 #define MDMA_GISR0_GIF7_Pos (7U)
13884 #define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos)
13885 #define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk
13886 #define MDMA_GISR0_GIF8_Pos (8U)
13887 #define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos)
13888 #define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk
13889 #define MDMA_GISR0_GIF9_Pos (9U)
13890 #define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos)
13891 #define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk
13892 #define MDMA_GISR0_GIF10_Pos (10U)
13893 #define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos)
13894 #define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk
13895 #define MDMA_GISR0_GIF11_Pos (11U)
13896 #define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos)
13897 #define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk
13898 #define MDMA_GISR0_GIF12_Pos (12U)
13899 #define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos)
13900 #define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk
13901 #define MDMA_GISR0_GIF13_Pos (13U)
13902 #define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos)
13903 #define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk
13904 #define MDMA_GISR0_GIF14_Pos (14U)
13905 #define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos)
13906 #define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk
13907 #define MDMA_GISR0_GIF15_Pos (15U)
13908 #define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos)
13909 #define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk
13911 /******************** Bit definition for MDMA_CxISR register ****************/
13912 #define MDMA_CISR_TEIF_Pos (0U)
13913 #define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos)
13914 #define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk
13915 #define MDMA_CISR_CTCIF_Pos (1U)
13916 #define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos)
13917 #define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk
13918 #define MDMA_CISR_BRTIF_Pos (2U)
13919 #define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos)
13920 #define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk
13921 #define MDMA_CISR_BTIF_Pos (3U)
13922 #define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos)
13923 #define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk
13924 #define MDMA_CISR_TCIF_Pos (4U)
13925 #define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos)
13926 #define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk
13927 #define MDMA_CISR_CRQA_Pos (16U)
13928 #define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos)
13929 #define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk
13931 /******************** Bit definition for MDMA_CxIFCR register ****************/
13932 #define MDMA_CIFCR_CTEIF_Pos (0U)
13933 #define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos)
13934 #define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk
13935 #define MDMA_CIFCR_CCTCIF_Pos (1U)
13936 #define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos)
13937 #define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk
13938 #define MDMA_CIFCR_CBRTIF_Pos (2U)
13939 #define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos)
13940 #define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk
13941 #define MDMA_CIFCR_CBTIF_Pos (3U)
13942 #define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos)
13943 #define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk
13944 #define MDMA_CIFCR_CLTCIF_Pos (4U)
13945 #define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos)
13946 #define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk
13948 /******************** Bit definition for MDMA_CxESR register ****************/
13949 #define MDMA_CESR_TEA_Pos (0U)
13950 #define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos)
13951 #define MDMA_CESR_TEA MDMA_CESR_TEA_Msk
13952 #define MDMA_CESR_TED_Pos (7U)
13953 #define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos)
13954 #define MDMA_CESR_TED MDMA_CESR_TED_Msk
13955 #define MDMA_CESR_TELD_Pos (8U)
13956 #define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos)
13957 #define MDMA_CESR_TELD MDMA_CESR_TELD_Msk
13958 #define MDMA_CESR_TEMD_Pos (9U)
13959 #define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos)
13960 #define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk
13961 #define MDMA_CESR_ASE_Pos (10U)
13962 #define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos)
13963 #define MDMA_CESR_ASE MDMA_CESR_ASE_Msk
13964 #define MDMA_CESR_BSE_Pos (11U)
13965 #define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos)
13966 #define MDMA_CESR_BSE MDMA_CESR_BSE_Msk
13968 /******************** Bit definition for MDMA_CxCR register ****************/
13969 #define MDMA_CCR_EN_Pos (0U)
13970 #define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos)
13971 #define MDMA_CCR_EN MDMA_CCR_EN_Msk
13972 #define MDMA_CCR_TEIE_Pos (1U)
13973 #define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos)
13974 #define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk
13975 #define MDMA_CCR_CTCIE_Pos (2U)
13976 #define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos)
13977 #define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk
13978 #define MDMA_CCR_BRTIE_Pos (3U)
13979 #define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos)
13980 #define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk
13981 #define MDMA_CCR_BTIE_Pos (4U)
13982 #define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos)
13983 #define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk
13984 #define MDMA_CCR_TCIE_Pos (5U)
13985 #define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos)
13986 #define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk
13987 #define MDMA_CCR_PL_Pos (6U)
13988 #define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos)
13989 #define MDMA_CCR_PL MDMA_CCR_PL_Msk
13990 #define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos)
13991 #define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos)
13992 #define MDMA_CCR_BEX_Pos (12U)
13993 #define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos)
13994 #define MDMA_CCR_BEX MDMA_CCR_BEX_Msk
13995 #define MDMA_CCR_HEX_Pos (13U)
13996 #define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos)
13997 #define MDMA_CCR_HEX MDMA_CCR_HEX_Msk
13998 #define MDMA_CCR_WEX_Pos (14U)
13999 #define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos)
14000 #define MDMA_CCR_WEX MDMA_CCR_WEX_Msk
14001 #define MDMA_CCR_SWRQ_Pos (16U)
14002 #define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos)
14003 #define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk
14005 /******************** Bit definition for MDMA_CxTCR register ****************/
14006 #define MDMA_CTCR_SINC_Pos (0U)
14007 #define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos)
14008 #define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk
14009 #define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos)
14010 #define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos)
14011 #define MDMA_CTCR_DINC_Pos (2U)
14012 #define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos)
14013 #define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk
14014 #define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos)
14015 #define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos)
14016 #define MDMA_CTCR_SSIZE_Pos (4U)
14017 #define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos)
14018 #define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk
14019 #define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos)
14020 #define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos)
14021 #define MDMA_CTCR_DSIZE_Pos (6U)
14022 #define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos)
14023 #define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk
14024 #define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos)
14025 #define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos)
14026 #define MDMA_CTCR_SINCOS_Pos (8U)
14027 #define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos)
14028 #define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk
14029 #define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos)
14030 #define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos)
14031 #define MDMA_CTCR_DINCOS_Pos (10U)
14032 #define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos)
14033 #define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk
14034 #define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos)
14035 #define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos)
14036 #define MDMA_CTCR_SBURST_Pos (12U)
14037 #define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos)
14038 #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk
14039 #define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos)
14040 #define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos)
14041 #define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos)
14042 #define MDMA_CTCR_DBURST_Pos (15U)
14043 #define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos)
14044 #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk
14045 #define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos)
14046 #define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos)
14047 #define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos)
14048 #define MDMA_CTCR_TLEN_Pos (18U)
14049 #define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos)
14050 #define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk
14051 #define MDMA_CTCR_PKE_Pos (25U)
14052 #define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos)
14053 #define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk
14054 #define MDMA_CTCR_PAM_Pos (26U)
14055 #define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos)
14056 #define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk
14057 #define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos)
14058 #define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos)
14059 #define MDMA_CTCR_TRGM_Pos (28U)
14060 #define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos)
14061 #define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk
14062 #define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos)
14063 #define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos)
14064 #define MDMA_CTCR_SWRM_Pos (30U)
14065 #define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos)
14066 #define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk
14067 #define MDMA_CTCR_BWM_Pos (31U)
14068 #define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos)
14069 #define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk
14071 /******************** Bit definition for MDMA_CxBNDTR register ****************/
14072 #define MDMA_CBNDTR_BNDT_Pos (0U)
14073 #define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)
14074 #define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk
14075 #define MDMA_CBNDTR_BRSUM_Pos (18U)
14076 #define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos)
14077 #define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk
14078 #define MDMA_CBNDTR_BRDUM_Pos (19U)
14079 #define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos)
14080 #define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk
14081 #define MDMA_CBNDTR_BRC_Pos (20U)
14082 #define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos)
14083 #define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk
14085 /******************** Bit definition for MDMA_CxSAR register ****************/
14086 #define MDMA_CSAR_SAR_Pos (0U)
14087 #define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)
14088 #define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk
14090 /******************** Bit definition for MDMA_CxDAR register ****************/
14091 #define MDMA_CDAR_DAR_Pos (0U)
14092 #define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)
14093 #define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk
14095 /******************** Bit definition for MDMA_CxBRUR ************************/
14096 #define MDMA_CBRUR_SUV_Pos (0U)
14097 #define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos)
14098 #define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk
14099 #define MDMA_CBRUR_DUV_Pos (16U)
14100 #define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos)
14101 #define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk
14103 /******************** Bit definition for MDMA_CxLAR *************************/
14104 #define MDMA_CLAR_LAR_Pos (0U)
14105 #define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)
14106 #define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk
14108 /******************** Bit definition for MDMA_CxTBR) ************************/
14109 #define MDMA_CTBR_TSEL_Pos (0U)
14110 #define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos)
14111 #define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk
14112 #define MDMA_CTBR_SBUS_Pos (16U)
14113 #define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos)
14114 #define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk
14115 #define MDMA_CTBR_DBUS_Pos (17U)
14116 #define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos)
14117 #define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk
14119 /******************** Bit definition for MDMA_CxMAR) ************************/
14120 #define MDMA_CMAR_MAR_Pos (0U)
14121 #define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)
14122 #define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk
14124 /******************** Bit definition for MDMA_CxMDR) ************************/
14125 #define MDMA_CMDR_MDR_Pos (0U)
14126 #define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)
14127 #define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk
14129 /******************************************************************************/
14130 /* */
14131 /* Operational Amplifier (OPAMP) */
14132 /* */
14133 /******************************************************************************/
14134 /********************* Bit definition for OPAMPx_CSR register ***************/
14135 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
14136 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
14137 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
14138 #define OPAMP_CSR_FORCEVP_Pos (1U)
14139 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)
14140 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk
14142 #define OPAMP_CSR_VPSEL_Pos (2U)
14143 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)
14144 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
14145 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)
14146 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)
14148 #define OPAMP_CSR_VMSEL_Pos (5U)
14149 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
14150 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
14151 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
14152 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
14154 #define OPAMP_CSR_OPAHSM_Pos (8U)
14155 #define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos)
14156 #define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk
14157 #define OPAMP_CSR_CALON_Pos (11U)
14158 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
14159 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
14161 #define OPAMP_CSR_CALSEL_Pos (12U)
14162 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)
14163 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
14164 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)
14165 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)
14167 #define OPAMP_CSR_PGGAIN_Pos (14U)
14168 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)
14169 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
14170 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
14171 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
14172 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)
14173 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)
14175 #define OPAMP_CSR_USERTRIM_Pos (18U)
14176 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
14177 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
14178 #define OPAMP_CSR_TSTREF_Pos (29U)
14179 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)
14180 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk
14181 #define OPAMP_CSR_CALOUT_Pos (30U)
14182 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
14183 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
14185 /********************* Bit definition for OPAMP1_CSR register ***************/
14186 #define OPAMP1_CSR_OPAEN_Pos (0U)
14187 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
14188 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
14189 #define OPAMP1_CSR_FORCEVP_Pos (1U)
14190 #define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)
14191 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk
14193 #define OPAMP1_CSR_VPSEL_Pos (2U)
14194 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)
14195 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
14196 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)
14197 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)
14199 #define OPAMP1_CSR_VMSEL_Pos (5U)
14200 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
14201 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
14202 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
14203 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
14205 #define OPAMP1_CSR_OPAHSM_Pos (8U)
14206 #define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos)
14207 #define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk
14208 #define OPAMP1_CSR_CALON_Pos (11U)
14209 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
14210 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
14212 #define OPAMP1_CSR_CALSEL_Pos (12U)
14213 #define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)
14214 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
14215 #define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)
14216 #define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)
14218 #define OPAMP1_CSR_PGGAIN_Pos (14U)
14219 #define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)
14220 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk
14221 #define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)
14222 #define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)
14223 #define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)
14224 #define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)
14226 #define OPAMP1_CSR_USERTRIM_Pos (18U)
14227 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
14228 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
14229 #define OPAMP1_CSR_TSTREF_Pos (29U)
14230 #define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)
14231 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk
14232 #define OPAMP1_CSR_CALOUT_Pos (30U)
14233 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
14234 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
14236 /********************* Bit definition for OPAMP2_CSR register ***************/
14237 #define OPAMP2_CSR_OPAEN_Pos (0U)
14238 #define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
14239 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
14240 #define OPAMP2_CSR_FORCEVP_Pos (1U)
14241 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)
14242 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk
14244 #define OPAMP2_CSR_VPSEL_Pos (2U)
14245 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)
14246 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
14247 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)
14248 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)
14250 #define OPAMP2_CSR_VMSEL_Pos (5U)
14251 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
14252 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
14253 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
14254 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
14256 #define OPAMP2_CSR_OPAHSM_Pos (8U)
14257 #define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos)
14258 #define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk
14259 #define OPAMP2_CSR_CALON_Pos (11U)
14260 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
14261 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
14263 #define OPAMP2_CSR_CALSEL_Pos (12U)
14264 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)
14265 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
14266 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)
14267 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)
14269 #define OPAMP2_CSR_PGGAIN_Pos (14U)
14270 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)
14271 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk
14272 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)
14273 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)
14274 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)
14275 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)
14277 #define OPAMP2_CSR_USERTRIM_Pos (18U)
14278 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
14279 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
14280 #define OPAMP2_CSR_TSTREF_Pos (29U)
14281 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)
14282 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk
14283 #define OPAMP2_CSR_CALOUT_Pos (30U)
14284 #define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
14285 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
14287 /******************* Bit definition for OPAMP_OTR register ******************/
14288 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
14289 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
14290 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
14291 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
14292 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
14293 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
14295 /******************* Bit definition for OPAMP1_OTR register ******************/
14296 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
14297 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
14298 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
14299 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
14300 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
14301 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
14303 /******************* Bit definition for OPAMP2_OTR register ******************/
14304 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
14305 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
14306 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
14307 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
14308 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
14309 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
14311 /******************* Bit definition for OPAMP_HSOTR register ****************/
14312 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
14313 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos)
14314 #define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk
14315 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
14316 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos)
14317 #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk
14319 /******************* Bit definition for OPAMP1_HSOTR register ****************/
14320 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
14321 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos)
14322 #define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk
14323 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
14324 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos)
14325 #define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk
14327 /******************* Bit definition for OPAMP2_HSOTR register ****************/
14328 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
14329 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos)
14330 #define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk
14331 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
14332 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos)
14333 #define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk
14335 /******************************************************************************/
14336 /* */
14337 /* Parallel Synchronous Slave Interface (PSSI ) */
14338 /* */
14339 /******************************************************************************/
14340 
14341 /******************** Bit definition for PSSI_CR register *******************/
14342 #define PSSI_CR_OUTEN_Pos (31U)
14343 #define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos)
14344 #define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk
14345 #define PSSI_CR_DMAEN_Pos (30U)
14346 #define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos)
14347 #define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk
14348 #define PSSI_CR_DERDYCFG_Pos (18U)
14349 #define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos)
14350 #define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk
14351 #define PSSI_CR_ENABLE_Pos (14U)
14352 #define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos)
14353 #define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk
14354 #define PSSI_CR_EDM_Pos (10U)
14355 #define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos)
14356 #define PSSI_CR_EDM PSSI_CR_EDM_Msk
14357 #define PSSI_CR_RDYPOL_Pos (8U)
14358 #define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos)
14359 #define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk
14360 #define PSSI_CR_DEPOL_Pos (6U)
14361 #define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos)
14362 #define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk
14363 #define PSSI_CR_CKPOL_Pos (5U)
14364 #define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos)
14365 #define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk
14366 /******************** Bit definition for PSSI_SR register *******************/
14367 #define PSSI_SR_RTT1B_Pos (3U)
14368 #define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos)
14369 #define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk
14370 #define PSSI_SR_RTT4B_Pos (2U)
14371 #define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos)
14372 #define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk
14373 /******************** Bit definition for PSSI_RIS register *******************/
14374 #define PSSI_RIS_OVR_RIS_Pos (1U)
14375 #define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos)
14376 #define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk
14377 /******************** Bit definition for PSSI_IER register *******************/
14378 #define PSSI_IER_OVR_IE_Pos (1U)
14379 #define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos)
14380 #define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk
14381 /******************** Bit definition for PSSI_MIS register *******************/
14382 #define PSSI_MIS_OVR_MIS_Pos (1U)
14383 #define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos)
14384 #define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk
14385 /******************** Bit definition for PSSI_ICR register *******************/
14386 #define PSSI_ICR_OVR_ISC_Pos (1U)
14387 #define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos)
14388 #define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk
14389 /******************** Bit definition for PSSI_DR register *******************/
14390 #define PSSI_DR_DR_Pos (0U)
14391 #define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos)
14392 #define PSSI_DR_DR PSSI_DR_DR_Msk
14394 /******************************************************************************/
14395 /* */
14396 /* On The Fly Decryption */
14397 /* */
14398 /******************************************************************************/
14399 /****************** Bit definition for OTFDEC_CR register ******************/
14400 #define OTFDEC_CR_ENC_Pos (0U)
14401 #define OTFDEC_CR_ENC_Msk (0x1UL << OTFDEC_CR_ENC_Pos)
14402 #define OTFDEC_CR_ENC OTFDEC_CR_ENC_Msk
14404 /****************** Bit definition for OTFDEC_PRIVCFGR register ************/
14405 #define OTFDEC_PRIVCFGR_PRIV_Pos (0U)
14406 #define OTFDEC_PRIVCFGR_PRIV_Msk (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)
14407 #define OTFDEC_PRIVCFGR_PRIV OTFDEC_PRIVCFGR_PRIV_Msk
14409 /****************** Bit definition for OTFDEC_REG_CONFIGR register *********/
14410 #define OTFDEC_REG_CONFIGR_REG_EN_Pos (0U)
14411 #define OTFDEC_REG_CONFIGR_REG_EN_Msk (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)
14412 #define OTFDEC_REG_CONFIGR_REG_EN OTFDEC_REG_CONFIGR_REG_EN_Msk
14414 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos (1U)
14415 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)
14416 #define OTFDEC_REG_CONFIGR_CONFIGLOCK OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk
14418 #define OTFDEC_REG_CONFIGR_KEYLOCK_Pos (2U)
14419 #define OTFDEC_REG_CONFIGR_KEYLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)
14420 #define OTFDEC_REG_CONFIGR_KEYLOCK OTFDEC_REG_CONFIGR_KEYLOCK_Msk
14422 #define OTFDEC_REG_CONFIGR_MODE_Pos (4U)
14423 #define OTFDEC_REG_CONFIGR_MODE_Msk (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)
14424 #define OTFDEC_REG_CONFIGR_MODE OTFDEC_REG_CONFIGR_MODE_Msk
14425 #define OTFDEC_REG_CONFIGR_MODE_0 (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)
14426 #define OTFDEC_REG_CONFIGR_MODE_1 (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)
14428 #define OTFDEC_REG_CONFIGR_KEYCRC_Pos (8U)
14429 #define OTFDEC_REG_CONFIGR_KEYCRC_Msk (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)
14430 #define OTFDEC_REG_CONFIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk
14432 #define OTFDEC_REG_CONFIGR_VERSION_Pos (16U)
14433 #define OTFDEC_REG_CONFIGR_VERSION_Msk (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)
14434 #define OTFDEC_REG_CONFIGR_VERSION OTFDEC_REG_CONFIGR_VERSION_Msk
14436 /****************** Bit definition for OTFDEC_REG_START_ADDR register ******/
14437 #define OTFDEC_REG_START_ADDR_Pos (0U)
14438 #define OTFDEC_REG_START_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)
14439 #define OTFDEC_REG_START_ADDR OTFDEC_REG_START_ADDR_Msk
14441 /****************** Bit definition for OTFDEC_REG_END_ADDR register ********/
14442 #define OTFDEC_REG_END_ADDR_Pos (0U)
14443 #define OTFDEC_REG_END_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)
14444 #define OTFDEC_REG_END_ADDR OTFDEC_REG_END_ADDR_Msk
14446 /****************** Bit definition for OTFDEC_REG_NONCER0 register *********/
14447 #define OTFDEC_REG_NONCER0_Pos (0U)
14448 #define OTFDEC_REG_NONCER0_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)
14449 #define OTFDEC_REG_NONCER0 OTFDEC_REG_NONCER0_Msk
14451 /****************** Bit definition for OTFDEC_REG_NONCER1 register *********/
14452 #define OTFDEC_REG_NONCER1_Pos (0U)
14453 #define OTFDEC_REG_NONCER1_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)
14454 #define OTFDEC_REG_NONCER1 OTFDEC_REG_NONCER1_Msk
14456 /****************** Bit definition for OTFDEC_REG_KEYR0 register ***********/
14457 #define OTFDEC_REG_KEYR0_Pos (0U)
14458 #define OTFDEC_REG_KEYR0_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)
14459 #define OTFDEC_REG_KEYR0 OTFDEC_REG_KEYR0_Msk
14461 /****************** Bit definition for OTFDEC_REG_KEYR1 register ***********/
14462 #define OTFDEC_REG_KEYR1_Pos (0U)
14463 #define OTFDEC_REG_KEYR1_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)
14464 #define OTFDEC_REG_KEYR1 OTFDEC_REG_KEYR1_Msk
14466 /****************** Bit definition for OTFDEC_REG_KEYR2 register ***********/
14467 #define OTFDEC_REG_KEYR2_Pos (0U)
14468 #define OTFDEC_REG_KEYR2_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)
14469 #define OTFDEC_REG_KEYR2 OTFDEC_REG_KEYR2_Msk
14471 /****************** Bit definition for OTFDEC_REG_KEYR3 register ***********/
14472 #define OTFDEC_REG_KEYR3_Pos (0U)
14473 #define OTFDEC_REG_KEYR3_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)
14474 #define OTFDEC_REG_KEYR3 OTFDEC_REG_KEYR3_Msk
14476 /****************** Bit definition for OTFDEC_ISR register *****************/
14477 #define OTFDEC_ISR_SEIF_Pos (0U)
14478 #define OTFDEC_ISR_SEIF_Msk (0x1UL << OTFDEC_ISR_SEIF_Pos)
14479 #define OTFDEC_ISR_SEIF OTFDEC_ISR_SEIF_Msk
14481 #define OTFDEC_ISR_XONEIF_Pos (1U)
14482 #define OTFDEC_ISR_XONEIF_Msk (0x1UL << OTFDEC_ISR_XONEIF_Pos)
14483 #define OTFDEC_ISR_XONEIF OTFDEC_ISR_XONEIF_Msk
14485 #define OTFDEC_ISR_KEIF_Pos (2U)
14486 #define OTFDEC_ISR_KEIF_Msk (0x1UL << OTFDEC_ISR_KEIF_Pos)
14487 #define OTFDEC_ISR_KEIF OTFDEC_ISR_KEIF_Msk
14489 /****************** Bit definition for OTFDEC_ICR register *****************/
14490 #define OTFDEC_ICR_SEIF_Pos (0U)
14491 #define OTFDEC_ICR_SEIF_Msk (0x1UL << OTFDEC_ICR_SEIF_Pos)
14492 #define OTFDEC_ICR_SEIF OTFDEC_ICR_SEIF_Msk
14494 #define OTFDEC_ICR_XONEIF_Pos (1U)
14495 #define OTFDEC_ICR_XONEIF_Msk (0x1UL << OTFDEC_ICR_XONEIF_Pos)
14496 #define OTFDEC_ICR_XONEIF OTFDEC_ICR_XONEIF_Msk
14498 #define OTFDEC_ICR_KEIF_Pos (2U)
14499 #define OTFDEC_ICR_KEIF_Msk (0x1UL << OTFDEC_ICR_KEIF_Pos)
14500 #define OTFDEC_ICR_KEIF OTFDEC_ICR_KEIF_Msk
14502 /****************** Bit definition for OTFDEC_IER register *****************/
14503 #define OTFDEC_IER_SEIE_Pos (0U)
14504 #define OTFDEC_IER_SEIE_Msk (0x1UL << OTFDEC_IER_SEIE_Pos)
14505 #define OTFDEC_IER_SEIE OTFDEC_IER_SEIE_Msk
14507 #define OTFDEC_IER_XONEIE_Pos (1U)
14508 #define OTFDEC_IER_XONEIE_Msk (0x1UL << OTFDEC_IER_XONEIE_Pos)
14509 #define OTFDEC_IER_XONEIE OTFDEC_IER_XONEIE_Msk
14511 #define OTFDEC_IER_KEIE_Pos (2U)
14512 #define OTFDEC_IER_KEIE_Msk (0x1UL << OTFDEC_IER_KEIE_Pos)
14513 #define OTFDEC_IER_KEIE OTFDEC_IER_KEIE_Msk
14514 
14515 /******************************************************************************/
14516 /* */
14517 /* Power Control */
14518 /* */
14519 /******************************************************************************/
14520 /************************* NUMBER OF POWER DOMAINS **************************/
14521 #define POWER_DOMAINS_NUMBER 3U
14523 /******************** Bit definition for PWR_CR1 register *******************/
14524 #define PWR_CR1_ALS_Pos (17U)
14525 #define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos)
14526 #define PWR_CR1_ALS PWR_CR1_ALS_Msk
14527 #define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos)
14528 #define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos)
14529 #define PWR_CR1_AVDEN_Pos (16U)
14530 #define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos)
14531 #define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk
14532 #define PWR_CR1_SVOS_Pos (14U)
14533 #define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos)
14534 #define PWR_CR1_SVOS PWR_CR1_SVOS_Msk
14535 #define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos)
14536 #define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos)
14537 #define PWR_CR1_FLPS_Pos (9U)
14538 #define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos)
14539 #define PWR_CR1_FLPS PWR_CR1_FLPS_Msk
14540 #define PWR_CR1_DBP_Pos (8U)
14541 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
14542 #define PWR_CR1_DBP PWR_CR1_DBP_Msk
14543 #define PWR_CR1_PLS_Pos (5U)
14544 #define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
14545 #define PWR_CR1_PLS PWR_CR1_PLS_Msk
14546 #define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
14547 #define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
14548 #define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
14549 #define PWR_CR1_PVDEN_Pos (4U)
14550 #define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos)
14551 #define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk
14552 #define PWR_CR1_LPDS_Pos (0U)
14553 #define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
14554 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
14557 #define PWR_CR1_PLS_LEV0 (0UL)
14558 #define PWR_CR1_PLS_LEV1_Pos (5U)
14559 #define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
14560 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
14561 #define PWR_CR1_PLS_LEV2_Pos (6U)
14562 #define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
14563 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
14564 #define PWR_CR1_PLS_LEV3_Pos (5U)
14565 #define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
14566 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
14567 #define PWR_CR1_PLS_LEV4_Pos (7U)
14568 #define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
14569 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
14570 #define PWR_CR1_PLS_LEV5_Pos (5U)
14571 #define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
14572 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
14573 #define PWR_CR1_PLS_LEV6_Pos (6U)
14574 #define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
14575 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
14576 #define PWR_CR1_PLS_LEV7_Pos (5U)
14577 #define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
14578 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
14581 #define PWR_CR1_ALS_LEV0 (0UL)
14582 #define PWR_CR1_ALS_LEV1_Pos (17U)
14583 #define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos)
14584 #define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk
14585 #define PWR_CR1_ALS_LEV2_Pos (18U)
14586 #define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos)
14587 #define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk
14588 #define PWR_CR1_ALS_LEV3_Pos (17U)
14589 #define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos)
14590 #define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk
14592 /******************** Bit definition for PWR_CSR1 register ******************/
14593 #define PWR_CSR1_AVDO_Pos (16U)
14594 #define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos)
14595 #define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk
14596 #define PWR_CSR1_ACTVOS_Pos (14U)
14597 #define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos)
14598 #define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk
14599 #define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos)
14600 #define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos)
14601 #define PWR_CSR1_ACTVOSRDY_Pos (13U)
14602 #define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)
14603 #define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk
14604 #define PWR_CSR1_PVDO_Pos (4U)
14605 #define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
14606 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
14608 /******************** Bit definition for PWR_CR2 register *******************/
14609 #define PWR_CR2_TEMPH_Pos (23U)
14610 #define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos)
14611 #define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk
14612 #define PWR_CR2_TEMPL_Pos (22U)
14613 #define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos)
14614 #define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk
14615 #define PWR_CR2_VBATH_Pos (21U)
14616 #define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos)
14617 #define PWR_CR2_VBATH PWR_CR2_VBATH_Msk
14618 #define PWR_CR2_VBATL_Pos (20U)
14619 #define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos)
14620 #define PWR_CR2_VBATL PWR_CR2_VBATL_Msk
14621 #define PWR_CR2_BRRDY_Pos (16U)
14622 #define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos)
14623 #define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk
14624 #define PWR_CR2_MONEN_Pos (4U)
14625 #define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos)
14626 #define PWR_CR2_MONEN PWR_CR2_MONEN_Msk
14627 #define PWR_CR2_BREN_Pos (0U)
14628 #define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos)
14629 #define PWR_CR2_BREN PWR_CR2_BREN_Msk
14631 /******************** Bit definition for PWR_CR3 register *******************/
14632 #define PWR_CR3_USB33RDY_Pos (26U)
14633 #define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos)
14634 #define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk
14635 #define PWR_CR3_USBREGEN_Pos (25U)
14636 #define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos)
14637 #define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk
14638 #define PWR_CR3_USB33DEN_Pos (24U)
14639 #define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos)
14640 #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk
14641 #define PWR_CR3_SMPSEXTRDY_Pos (16U)
14642 #define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)
14643 #define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk
14644 #define PWR_CR3_VBRS_Pos (9U)
14645 #define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos)
14646 #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk
14647 #define PWR_CR3_VBE_Pos (8U)
14648 #define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos)
14649 #define PWR_CR3_VBE PWR_CR3_VBE_Msk
14650 #define PWR_CR3_SMPSLEVEL_Pos (4U)
14651 #define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos)
14652 #define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk
14653 #define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos)
14654 #define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos)
14655 #define PWR_CR3_SMPSEXTHP_Pos (3U)
14656 #define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos)
14657 #define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk
14658 #define PWR_CR3_SMPSEN_Pos (2U)
14659 #define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos)
14660 #define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk
14661 #define PWR_CR3_LDOEN_Pos (1U)
14662 #define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos)
14663 #define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk
14664 #define PWR_CR3_BYPASS_Pos (0U)
14665 #define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos)
14666 #define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk
14668 /******************** Bit definition for PWR_CPUCR register *****************/
14669 #define PWR_CPUCR_RUN_D3_Pos (11U)
14670 #define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos)
14671 #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk
14672 #define PWR_CPUCR_CSSF_Pos (9U)
14673 #define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos)
14674 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk
14675 #define PWR_CPUCR_SBF_D2_Pos (8U)
14676 #define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos)
14677 #define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk
14678 #define PWR_CPUCR_SBF_D1_Pos (7U)
14679 #define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos)
14680 #define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk
14681 #define PWR_CPUCR_SBF_Pos (6U)
14682 #define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos)
14683 #define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk
14684 #define PWR_CPUCR_STOPF_Pos (5U)
14685 #define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos)
14686 #define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk
14687 #define PWR_CPUCR_PDDS_D3_Pos (2U)
14688 #define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos)
14689 #define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk
14690 #define PWR_CPUCR_PDDS_D2_Pos (1U)
14691 #define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos)
14692 #define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk
14693 #define PWR_CPUCR_PDDS_D1_Pos (0U)
14694 #define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos)
14695 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk
14698 /******************** Bit definition for PWR_D3CR register ******************/
14699 #define PWR_D3CR_VOS_Pos (14U)
14700 #define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos)
14701 #define PWR_D3CR_VOS PWR_D3CR_VOS_Msk
14702 #define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos)
14703 #define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos)
14704 #define PWR_D3CR_VOSRDY_Pos (13U)
14705 #define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos)
14706 #define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk
14708 /****************** Bit definition for PWR_WKUPCR register ******************/
14709 #define PWR_WKUPCR_WKUPC6_Pos (5U)
14710 #define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos)
14711 #define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk
14712 #define PWR_WKUPCR_WKUPC4_Pos (3U)
14713 #define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos)
14714 #define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk
14715 #define PWR_WKUPCR_WKUPC2_Pos (1U)
14716 #define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos)
14717 #define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk
14718 #define PWR_WKUPCR_WKUPC1_Pos (0U)
14719 #define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos)
14720 #define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk
14722 /******************** Bit definition for PWR_WKUPFR register ****************/
14723 #define PWR_WKUPFR_WKUPF6_Pos (5U)
14724 #define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos)
14725 #define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk
14726 #define PWR_WKUPFR_WKUPF4_Pos (3U)
14727 #define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos)
14728 #define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk
14729 #define PWR_WKUPFR_WKUPF2_Pos (1U)
14730 #define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos)
14731 #define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk
14732 #define PWR_WKUPFR_WKUPF1_Pos (0U)
14733 #define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos)
14734 #define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk
14736 /****************** Bit definition for PWR_WKUPEPR register *****************/
14737 #define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
14738 #define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14739 #define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk
14740 #define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14741 #define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14742 #define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
14743 #define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14744 #define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk
14745 #define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14746 #define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14747 #define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
14748 #define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14749 #define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk
14750 #define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14751 #define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14752 #define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
14753 #define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14754 #define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk
14755 #define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14756 #define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14757 #define PWR_WKUPEPR_WKUPP6_Pos (13U)
14758 #define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)
14759 #define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk
14760 #define PWR_WKUPEPR_WKUPP4_Pos (11U)
14761 #define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)
14762 #define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk
14763 #define PWR_WKUPEPR_WKUPP2_Pos (9U)
14764 #define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)
14765 #define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk
14766 #define PWR_WKUPEPR_WKUPP1_Pos (8U)
14767 #define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)
14768 #define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk
14769 #define PWR_WKUPEPR_WKUPEN6_Pos (5U)
14770 #define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)
14771 #define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk
14772 #define PWR_WKUPEPR_WKUPEN4_Pos (3U)
14773 #define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)
14774 #define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk
14775 #define PWR_WKUPEPR_WKUPEN2_Pos (1U)
14776 #define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)
14777 #define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk
14778 #define PWR_WKUPEPR_WKUPEN1_Pos (0U)
14779 #define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)
14780 #define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk
14781 #define PWR_WKUPEPR_WKUPEN_Pos (0U)
14782 #define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)
14783 #define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk
14785 /******************************************************************************/
14786 /* */
14787 /* Reset and Clock Control */
14788 /* */
14789 /******************************************************************************/
14790 /******************************* RCC VERSION ********************************/
14791 #define RCC_VER_3_0
14792 
14793 /******************** Bit definition for RCC_CR register ********************/
14794 #define RCC_CR_HSION_Pos (0U)
14795 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
14796 #define RCC_CR_HSION RCC_CR_HSION_Msk
14797 #define RCC_CR_HSIKERON_Pos (1U)
14798 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
14799 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
14800 #define RCC_CR_HSIRDY_Pos (2U)
14801 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
14802 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
14803 #define RCC_CR_HSIDIV_Pos (3U)
14804 #define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos)
14805 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk
14806 #define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos)
14807 #define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos)
14808 #define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos)
14809 #define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos)
14811 #define RCC_CR_HSIDIVF_Pos (5U)
14812 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos)
14813 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk
14814 #define RCC_CR_CSION_Pos (7U)
14815 #define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos)
14816 #define RCC_CR_CSION RCC_CR_CSION_Msk
14817 #define RCC_CR_CSIRDY_Pos (8U)
14818 #define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos)
14819 #define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk
14820 #define RCC_CR_CSIKERON_Pos (9U)
14821 #define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos)
14822 #define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk
14823 #define RCC_CR_HSI48ON_Pos (12U)
14824 #define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos)
14825 #define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk
14826 #define RCC_CR_HSI48RDY_Pos (13U)
14827 #define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos)
14828 #define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk
14830 #define RCC_CR_D1CKRDY_Pos (14U)
14831 #define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos)
14832 #define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk
14833 #define RCC_CR_D2CKRDY_Pos (15U)
14834 #define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos)
14835 #define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk
14837 #define RCC_CR_HSEON_Pos (16U)
14838 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
14839 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
14840 #define RCC_CR_HSERDY_Pos (17U)
14841 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
14842 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
14843 #define RCC_CR_HSEBYP_Pos (18U)
14844 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
14845 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
14846 #define RCC_CR_CSSHSEON_Pos (19U)
14847 #define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos)
14848 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk
14851 #define RCC_CR_PLL1ON_Pos (24U)
14852 #define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos)
14853 #define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk
14854 #define RCC_CR_PLL1RDY_Pos (25U)
14855 #define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos)
14856 #define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk
14857 #define RCC_CR_PLL2ON_Pos (26U)
14858 #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos)
14859 #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk
14860 #define RCC_CR_PLL2RDY_Pos (27U)
14861 #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos)
14862 #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk
14863 #define RCC_CR_PLL3ON_Pos (28U)
14864 #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos)
14865 #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk
14866 #define RCC_CR_PLL3RDY_Pos (29U)
14867 #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos)
14868 #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk
14870 /*Legacy */
14871 #define RCC_CR_PLLON_Pos (24U)
14872 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
14873 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
14874 #define RCC_CR_PLLRDY_Pos (25U)
14875 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
14876 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
14878 /******************** Bit definition for RCC_HSICFGR register ***************/
14879 
14880 #define RCC_HSICFGR_HSICAL_Pos (0U)
14881 #define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)
14882 #define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk
14883 #define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos)
14884 #define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos)
14885 #define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos)
14886 #define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos)
14887 #define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos)
14888 #define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos)
14889 #define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos)
14890 #define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos)
14891 #define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos)
14892 #define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos)
14893 #define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos)
14894 #define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos)
14897 #define RCC_HSICFGR_HSITRIM_Pos (24U)
14898 #define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)
14899 #define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk
14900 #define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos)
14901 #define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos)
14902 #define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos)
14903 #define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos)
14904 #define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos)
14905 #define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos)
14906 #define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos)
14909 /******************** Bit definition for RCC_CRRCR register *****************/
14910 
14912 #define RCC_CRRCR_HSI48CAL_Pos (0U)
14913 #define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)
14914 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
14915 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
14916 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
14917 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
14918 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
14919 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
14920 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
14921 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
14922 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
14923 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
14924 #define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos)
14927 /******************** Bit definition for RCC_CSICFGR register *****************/
14928 
14929 #define RCC_CSICFGR_CSICAL_Pos (0U)
14930 #define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos)
14931 #define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk
14932 #define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos)
14933 #define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos)
14934 #define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos)
14935 #define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos)
14936 #define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos)
14937 #define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos)
14938 #define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos)
14939 #define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos)
14942 #define RCC_CSICFGR_CSITRIM_Pos (24U)
14943 #define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)
14944 #define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk
14945 #define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos)
14946 #define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos)
14947 #define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos)
14948 #define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos)
14949 #define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos)
14950 #define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos)
14952 /******************** Bit definition for RCC_CFGR register ******************/
14953 
14954 #define RCC_CFGR_SW_Pos (0U)
14955 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos)
14956 #define RCC_CFGR_SW RCC_CFGR_SW_Msk
14957 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
14958 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
14959 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos)
14961 #define RCC_CFGR_SW_HSI (0x00000000UL)
14962 #define RCC_CFGR_SW_CSI (0x00000001UL)
14963 #define RCC_CFGR_SW_HSE (0x00000002UL)
14964 #define RCC_CFGR_SW_PLL1 (0x00000003UL)
14967 #define RCC_CFGR_SWS_Pos (3U)
14968 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos)
14969 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
14970 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
14971 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
14972 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos)
14974 #define RCC_CFGR_SWS_HSI (0x00000000UL)
14975 #define RCC_CFGR_SWS_CSI (0x00000008UL)
14976 #define RCC_CFGR_SWS_HSE (0x00000010UL)
14977 #define RCC_CFGR_SWS_PLL1 (0x00000018UL)
14979 #define RCC_CFGR_STOPWUCK_Pos (6U)
14980 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
14981 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
14983 #define RCC_CFGR_STOPKERWUCK_Pos (7U)
14984 #define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)
14985 #define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk
14988 #define RCC_CFGR_RTCPRE_Pos (8U)
14989 #define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
14990 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
14991 #define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos)
14992 #define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos)
14993 #define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos)
14994 #define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos)
14995 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
14996 #define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos)
15000 #define RCC_CFGR_TIMPRE_Pos (15U)
15001 #define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
15002 #define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk
15005 #define RCC_CFGR_MCO1_Pos (22U)
15006 #define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
15007 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
15008 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
15009 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
15010 #define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos)
15012 #define RCC_CFGR_MCO1PRE_Pos (18U)
15013 #define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
15014 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
15015 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
15016 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
15017 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
15018 #define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos)
15020 #define RCC_CFGR_MCO2PRE_Pos (25U)
15021 #define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
15022 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
15023 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
15024 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
15025 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
15026 #define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos)
15028 #define RCC_CFGR_MCO2_Pos (29U)
15029 #define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
15030 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
15031 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
15032 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
15033 #define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos)
15035 /******************** Bit definition for RCC_D1CFGR register ******************/
15036 
15037 #define RCC_D1CFGR_HPRE_Pos (0U)
15038 #define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos)
15039 #define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk
15040 #define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos)
15041 #define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos)
15042 #define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos)
15043 #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos)
15046 #define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000)
15047 #define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
15048 #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos)
15049 #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk
15050 #define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
15051 #define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos)
15052 #define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk
15053 #define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
15054 #define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos)
15055 #define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk
15056 #define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
15057 #define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos)
15058 #define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk
15059 #define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
15060 #define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos)
15061 #define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk
15062 #define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
15063 #define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos)
15064 #define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk
15065 #define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
15066 #define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos)
15067 #define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk
15068 #define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
15069 #define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos)
15070 #define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk
15073 #define RCC_D1CFGR_D1PPRE_Pos (4U)
15074 #define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos)
15075 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk
15076 #define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos)
15077 #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos)
15078 #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos)
15080 #define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000)
15081 #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
15082 #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos)
15083 #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk
15084 #define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
15085 #define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos)
15086 #define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk
15087 #define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
15088 #define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos)
15089 #define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk
15090 #define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
15091 #define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos)
15092 #define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk
15094 #define RCC_D1CFGR_D1CPRE_Pos (8U)
15095 #define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos)
15096 #define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk
15097 #define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos)
15098 #define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos)
15099 #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos)
15100 #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos)
15102 #define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000)
15103 #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
15104 #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos)
15105 #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk
15106 #define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
15107 #define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos)
15108 #define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk
15109 #define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
15110 #define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos)
15111 #define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk
15112 #define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
15113 #define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos)
15114 #define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk
15115 #define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
15116 #define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos)
15117 #define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk
15118 #define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
15119 #define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos)
15120 #define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk
15121 #define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
15122 #define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos)
15123 #define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk
15124 #define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
15125 #define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos)
15126 #define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk
15128 /******************** Bit definition for RCC_D2CFGR register ******************/
15129 
15130 #define RCC_D2CFGR_D2PPRE1_Pos (4U)
15131 #define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos)
15132 #define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk
15133 #define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos)
15134 #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos)
15135 #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos)
15137 #define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000)
15138 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
15139 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos)
15140 #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk
15141 #define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
15142 #define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos)
15143 #define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk
15144 #define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
15145 #define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos)
15146 #define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk
15147 #define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
15148 #define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos)
15149 #define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk
15152 #define RCC_D2CFGR_D2PPRE2_Pos (8U)
15153 #define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos)
15154 #define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk
15155 #define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos)
15156 #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos)
15157 #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos)
15159 #define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000)
15160 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
15161 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos)
15162 #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk
15163 #define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
15164 #define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos)
15165 #define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk
15166 #define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
15167 #define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos)
15168 #define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk
15169 #define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
15170 #define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos)
15171 #define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk
15173 /******************** Bit definition for RCC_D3CFGR register ******************/
15174 
15175 #define RCC_D3CFGR_D3PPRE_Pos (4U)
15176 #define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos)
15177 #define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk
15178 #define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos)
15179 #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos)
15180 #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos)
15182 #define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000)
15183 #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
15184 #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos)
15185 #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk
15186 #define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
15187 #define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos)
15188 #define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk
15189 #define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
15190 #define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos)
15191 #define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk
15192 #define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
15193 #define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos)
15194 #define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk
15196 /******************** Bit definition for RCC_PLLCKSELR register *************/
15197 
15198 #define RCC_PLLCKSELR_PLLSRC_Pos (0U)
15199 #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos)
15200 #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
15201 
15202 #define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000)
15203 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
15204 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos)
15205 #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk
15206 #define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
15207 #define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos)
15208 #define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk
15209 #define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
15210 #define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos)
15211 #define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk
15213 #define RCC_PLLCKSELR_DIVM1_Pos (4U)
15214 #define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos)
15215 #define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
15216 #define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos)
15217 #define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos)
15218 #define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos)
15219 #define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos)
15220 #define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos)
15221 #define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos)
15223 #define RCC_PLLCKSELR_DIVM2_Pos (12U)
15224 #define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos)
15225 #define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
15226 #define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos)
15227 #define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos)
15228 #define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos)
15229 #define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos)
15230 #define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)
15231 #define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos)
15233 #define RCC_PLLCKSELR_DIVM3_Pos (20U)
15234 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos)
15235 #define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
15236 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos)
15237 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos)
15238 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos)
15239 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos)
15240 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos)
15241 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos)
15243 /******************** Bit definition for RCC_PLLCFGR register ***************/
15244 
15245 #define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
15246 #define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos)
15247 #define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
15248 #define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
15249 #define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos)
15250 #define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
15251 #define RCC_PLLCFGR_PLL1RGE_Pos (2U)
15252 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
15253 #define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
15254 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos)
15255 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos)
15256 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos)
15257 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
15259 #define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
15260 #define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos)
15261 #define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
15262 #define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
15263 #define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos)
15264 #define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
15265 #define RCC_PLLCFGR_PLL2RGE_Pos (6U)
15266 #define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
15267 #define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
15268 #define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos)
15269 #define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos)
15270 #define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos)
15271 #define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
15273 #define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
15274 #define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos)
15275 #define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
15276 #define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
15277 #define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos)
15278 #define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
15279 #define RCC_PLLCFGR_PLL3RGE_Pos (10U)
15280 #define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
15281 #define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
15282 #define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos)
15283 #define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos)
15284 #define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos)
15285 #define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
15287 #define RCC_PLLCFGR_DIVP1EN_Pos (16U)
15288 #define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos)
15289 #define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
15290 #define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
15291 #define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos)
15292 #define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
15293 #define RCC_PLLCFGR_DIVR1EN_Pos (18U)
15294 #define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos)
15295 #define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
15296 
15297 #define RCC_PLLCFGR_DIVP2EN_Pos (19U)
15298 #define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos)
15299 #define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
15300 #define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
15301 #define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos)
15302 #define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
15303 #define RCC_PLLCFGR_DIVR2EN_Pos (21U)
15304 #define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos)
15305 #define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
15306 
15307 #define RCC_PLLCFGR_DIVP3EN_Pos (22U)
15308 #define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos)
15309 #define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
15310 #define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
15311 #define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos)
15312 #define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
15313 #define RCC_PLLCFGR_DIVR3EN_Pos (24U)
15314 #define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos)
15315 #define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
15316 
15317 
15318 /******************** Bit definition for RCC_PLL1DIVR register ***************/
15319 #define RCC_PLL1DIVR_N1_Pos (0U)
15320 #define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos)
15321 #define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
15322 #define RCC_PLL1DIVR_P1_Pos (9U)
15323 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos)
15324 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
15325 #define RCC_PLL1DIVR_Q1_Pos (16U)
15326 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos)
15327 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
15328 #define RCC_PLL1DIVR_R1_Pos (24U)
15329 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos)
15330 #define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
15331 
15332 /******************** Bit definition for RCC_PLL1FRACR register ***************/
15333 #define RCC_PLL1FRACR_FRACN1_Pos (3U)
15334 #define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos)
15335 #define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
15336 
15337 /******************** Bit definition for RCC_PLL2DIVR register ***************/
15338 #define RCC_PLL2DIVR_N2_Pos (0U)
15339 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos)
15340 #define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
15341 #define RCC_PLL2DIVR_P2_Pos (9U)
15342 #define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos)
15343 #define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
15344 #define RCC_PLL2DIVR_Q2_Pos (16U)
15345 #define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos)
15346 #define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
15347 #define RCC_PLL2DIVR_R2_Pos (24U)
15348 #define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos)
15349 #define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
15350 
15351 /******************** Bit definition for RCC_PLL2FRACR register ***************/
15352 #define RCC_PLL2FRACR_FRACN2_Pos (3U)
15353 #define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos)
15354 #define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
15355 
15356 /******************** Bit definition for RCC_PLL3DIVR register ***************/
15357 #define RCC_PLL3DIVR_N3_Pos (0U)
15358 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos)
15359 #define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
15360 #define RCC_PLL3DIVR_P3_Pos (9U)
15361 #define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos)
15362 #define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
15363 #define RCC_PLL3DIVR_Q3_Pos (16U)
15364 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos)
15365 #define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
15366 #define RCC_PLL3DIVR_R3_Pos (24U)
15367 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos)
15368 #define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
15369 
15370 /******************** Bit definition for RCC_PLL3FRACR register ***************/
15371 #define RCC_PLL3FRACR_FRACN3_Pos (3U)
15372 #define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos)
15373 #define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
15374 
15375 /******************** Bit definition for RCC_D1CCIPR register ***************/
15376 #define RCC_D1CCIPR_FMCSEL_Pos (0U)
15377 #define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos)
15378 #define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
15379 #define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos)
15380 #define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos)
15381 #define RCC_D1CCIPR_OCTOSPISEL_Pos (4U)
15382 #define RCC_D1CCIPR_OCTOSPISEL_Msk (0x3UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
15383 #define RCC_D1CCIPR_OCTOSPISEL RCC_D1CCIPR_OCTOSPISEL_Msk
15384 #define RCC_D1CCIPR_OCTOSPISEL_0 (0x1UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
15385 #define RCC_D1CCIPR_OCTOSPISEL_1 (0x2UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
15386 #define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
15387 #define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos)
15388 #define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
15389 #define RCC_D1CCIPR_CKPERSEL_Pos (28U)
15390 #define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos)
15391 #define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
15392 #define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos)
15393 #define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos)
15395 /******************** Bit definition for RCC_D2CCIP1R register ***************/
15396 #define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
15397 #define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15398 #define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
15399 #define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15400 #define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15401 #define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15404 #define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
15405 #define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15406 #define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
15407 #define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15408 #define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15409 #define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15411 #define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
15412 #define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15413 #define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
15414 #define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15415 #define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15416 #define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15418 #define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
15419 #define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15420 #define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
15421 #define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15422 #define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15424 #define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
15425 #define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos)
15426 #define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
15427 
15428 #define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
15429 #define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15430 #define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
15431 #define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15432 #define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15434 #define RCC_D2CCIP1R_SWPSEL_Pos (31U)
15435 #define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos)
15436 #define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
15437 
15438 /******************** Bit definition for RCC_D2CCIP2R register ***************/
15439 #define RCC_D2CCIP2R_USART16910SEL_Pos (3U)
15440 #define RCC_D2CCIP2R_USART16910SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16910SEL_Pos)
15441 #define RCC_D2CCIP2R_USART16910SEL RCC_D2CCIP2R_USART16910SEL_Msk
15442 #define RCC_D2CCIP2R_USART16910SEL_0 (0x1UL << RCC_D2CCIP2R_USART16910SEL_Pos)
15443 #define RCC_D2CCIP2R_USART16910SEL_1 (0x2UL << RCC_D2CCIP2R_USART16910SEL_Pos)
15444 #define RCC_D2CCIP2R_USART16910SEL_2 (0x4UL << RCC_D2CCIP2R_USART16910SEL_Pos)
15446 #define RCC_D2CCIP2R_USART28SEL_Pos (0U)
15447 #define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos)
15448 #define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
15449 #define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos)
15450 #define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos)
15451 #define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos)
15453 #define RCC_D2CCIP2R_RNGSEL_Pos (8U)
15454 #define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos)
15455 #define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
15456 #define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos)
15457 #define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos)
15459 #define RCC_D2CCIP2R_I2C1235SEL_Pos (12U)
15460 #define RCC_D2CCIP2R_I2C1235SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
15461 #define RCC_D2CCIP2R_I2C1235SEL RCC_D2CCIP2R_I2C1235SEL_Msk
15462 #define RCC_D2CCIP2R_I2C1235SEL_0 (0x1UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
15463 #define RCC_D2CCIP2R_I2C1235SEL_1 (0x2UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
15465 #define RCC_D2CCIP2R_USBSEL_Pos (20U)
15466 #define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos)
15467 #define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
15468 #define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos)
15469 #define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos)
15471 #define RCC_D2CCIP2R_CECSEL_Pos (22U)
15472 #define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos)
15473 #define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
15474 #define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos)
15475 #define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos)
15477 #define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
15478 #define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15479 #define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
15480 #define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15481 #define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15482 #define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15484 /******************** Bit definition for RCC_D3CCIPR register ***************/
15485 #define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
15486 #define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15487 #define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
15488 #define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15489 #define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15490 #define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15492 #define RCC_D3CCIPR_I2C4SEL_Pos (8U)
15493 #define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos)
15494 #define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
15495 #define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos)
15496 #define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos)
15498 #define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
15499 #define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15500 #define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
15501 #define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15502 #define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15503 #define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15505 #define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
15506 #define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15507 #define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
15508 #define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15509 #define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15510 #define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15512 #define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
15513 #define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15514 #define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
15515 #define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15516 #define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15517 #define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15519 #define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
15520 #define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15521 #define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
15522 #define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15523 #define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15524 #define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15526 #define RCC_D3CCIPR_ADCSEL_Pos (16U)
15527 #define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos)
15528 #define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
15529 #define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos)
15530 #define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos)
15532 #define RCC_D3CCIPR_SPI6SEL_Pos (28U)
15533 #define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos)
15534 #define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
15535 #define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos)
15536 #define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos)
15537 #define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos)
15538 /******************** Bit definition for RCC_CIER register ******************/
15539 #define RCC_CIER_LSIRDYIE_Pos (0U)
15540 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
15541 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
15542 #define RCC_CIER_LSERDYIE_Pos (1U)
15543 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
15544 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
15545 #define RCC_CIER_HSIRDYIE_Pos (2U)
15546 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
15547 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
15548 #define RCC_CIER_HSERDYIE_Pos (3U)
15549 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
15550 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
15551 #define RCC_CIER_CSIRDYIE_Pos (4U)
15552 #define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos)
15553 #define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
15554 #define RCC_CIER_HSI48RDYIE_Pos (5U)
15555 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
15556 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
15557 #define RCC_CIER_PLL1RDYIE_Pos (6U)
15558 #define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos)
15559 #define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
15560 #define RCC_CIER_PLL2RDYIE_Pos (7U)
15561 #define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos)
15562 #define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
15563 #define RCC_CIER_PLL3RDYIE_Pos (8U)
15564 #define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos)
15565 #define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
15566 #define RCC_CIER_LSECSSIE_Pos (9U)
15567 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
15568 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
15569 
15570 /******************** Bit definition for RCC_CIFR register ******************/
15571 #define RCC_CIFR_LSIRDYF_Pos (0U)
15572 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
15573 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
15574 #define RCC_CIFR_LSERDYF_Pos (1U)
15575 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
15576 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
15577 #define RCC_CIFR_HSIRDYF_Pos (2U)
15578 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
15579 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
15580 #define RCC_CIFR_HSERDYF_Pos (3U)
15581 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
15582 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
15583 #define RCC_CIFR_CSIRDYF_Pos (4U)
15584 #define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos)
15585 #define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
15586 #define RCC_CIFR_HSI48RDYF_Pos (5U)
15587 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
15588 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
15589 #define RCC_CIFR_PLLRDYF_Pos (6U)
15590 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
15591 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
15592 #define RCC_CIFR_PLL2RDYF_Pos (7U)
15593 #define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos)
15594 #define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
15595 #define RCC_CIFR_PLL3RDYF_Pos (8U)
15596 #define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos)
15597 #define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
15598 #define RCC_CIFR_LSECSSF_Pos (9U)
15599 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
15600 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
15601 #define RCC_CIFR_HSECSSF_Pos (10U)
15602 #define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos)
15603 #define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
15604 
15605 /******************** Bit definition for RCC_CICR register ******************/
15606 #define RCC_CICR_LSIRDYC_Pos (0U)
15607 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
15608 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
15609 #define RCC_CICR_LSERDYC_Pos (1U)
15610 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
15611 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
15612 #define RCC_CICR_HSIRDYC_Pos (2U)
15613 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
15614 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
15615 #define RCC_CICR_HSERDYC_Pos (3U)
15616 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
15617 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
15618 #define RCC_CICR_CSIRDYC_Pos (4U)
15619 #define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos)
15620 #define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
15621 #define RCC_CICR_HSI48RDYC_Pos (5U)
15622 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
15623 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
15624 #define RCC_CICR_PLLRDYC_Pos (6U)
15625 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
15626 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
15627 #define RCC_CICR_PLL2RDYC_Pos (7U)
15628 #define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos)
15629 #define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
15630 #define RCC_CICR_PLL3RDYC_Pos (8U)
15631 #define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos)
15632 #define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
15633 #define RCC_CICR_LSECSSC_Pos (9U)
15634 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
15635 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
15636 #define RCC_CICR_HSECSSC_Pos (10U)
15637 #define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos)
15638 #define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
15639 
15640 /******************** Bit definition for RCC_BDCR register ******************/
15641 #define RCC_BDCR_LSEON_Pos (0U)
15642 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
15643 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
15644 #define RCC_BDCR_LSERDY_Pos (1U)
15645 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
15646 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
15647 #define RCC_BDCR_LSEBYP_Pos (2U)
15648 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
15649 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
15650 
15651 #define RCC_BDCR_LSEDRV_Pos (3U)
15652 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
15653 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
15654 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
15655 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
15657 #define RCC_BDCR_LSECSSON_Pos (5U)
15658 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
15659 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
15660 #define RCC_BDCR_LSECSSD_Pos (6U)
15661 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
15662 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
15663 
15664 #define RCC_BDCR_RTCSEL_Pos (8U)
15665 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
15666 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
15667 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
15668 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
15670 #define RCC_BDCR_RTCEN_Pos (15U)
15671 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
15672 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
15673 #define RCC_BDCR_VSWRST_Pos (16U)
15674 #define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos)
15675 #define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk
15676 /* Legacy define */
15677 #define RCC_BDCR_BDRST_Pos RCC_BDCR_VSWRST_Pos
15678 #define RCC_BDCR_BDRST_Msk RCC_BDCR_VSWRST_Msk
15679 #define RCC_BDCR_BDRST RCC_BDCR_VSWRST
15680 /******************** Bit definition for RCC_CSR register *******************/
15681 #define RCC_CSR_LSION_Pos (0U)
15682 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
15683 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
15684 #define RCC_CSR_LSIRDY_Pos (1U)
15685 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
15686 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
15687 
15688 
15689 /******************** Bit definition for RCC_AHB3ENR register **************/
15690 #define RCC_AHB3ENR_MDMAEN_Pos (0U)
15691 #define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)
15692 #define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
15693 #define RCC_AHB3ENR_DMA2DEN_Pos (4U)
15694 #define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)
15695 #define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
15696 #define RCC_AHB3ENR_FMCEN_Pos (12U)
15697 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
15698 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
15699 #define RCC_AHB3ENR_OSPI1EN_Pos (14U)
15700 #define RCC_AHB3ENR_OSPI1EN_Msk (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)
15701 #define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk
15702 #define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
15703 #define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)
15704 #define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
15705 #define RCC_AHB3ENR_OSPI2EN_Pos (19U)
15706 #define RCC_AHB3ENR_OSPI2EN_Msk (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)
15707 #define RCC_AHB3ENR_OSPI2EN RCC_AHB3ENR_OSPI2EN_Msk
15708 #define RCC_AHB3ENR_IOMNGREN_Pos (21U)
15709 #define RCC_AHB3ENR_IOMNGREN_Msk (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)
15710 #define RCC_AHB3ENR_IOMNGREN RCC_AHB3ENR_IOMNGREN_Msk
15711 #define RCC_AHB3ENR_OTFDEC1EN_Pos (22U)
15712 #define RCC_AHB3ENR_OTFDEC1EN_Msk (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)
15713 #define RCC_AHB3ENR_OTFDEC1EN RCC_AHB3ENR_OTFDEC1EN_Msk
15714 #define RCC_AHB3ENR_OTFDEC2EN_Pos (23U)
15715 #define RCC_AHB3ENR_OTFDEC2EN_Msk (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)
15716 #define RCC_AHB3ENR_OTFDEC2EN RCC_AHB3ENR_OTFDEC2EN_Msk
15717 
15718 /******************** Bit definition for RCC_AHB1ENR register ***************/
15719 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
15720 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
15721 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
15722 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
15723 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
15724 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
15725 #define RCC_AHB1ENR_ADC12EN_Pos (5U)
15726 #define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)
15727 #define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
15728 #define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
15729 #define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)
15730 #define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
15731 #define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
15732 #define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)
15733 #define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
15734 #define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
15735 #define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)
15736 #define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
15737 #define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
15738 #define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)
15739 #define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
15740 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
15741 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos)
15742 #define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
15743 
15744 /******************** Bit definition for RCC_AHB2ENR register ***************/
15745 #define RCC_AHB2ENR_DCMI_PSSIEN_Pos (0U)
15746 #define RCC_AHB2ENR_DCMI_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)
15747 #define RCC_AHB2ENR_DCMI_PSSIEN RCC_AHB2ENR_DCMI_PSSIEN_Msk
15748 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
15749 #define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)
15750 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
15751 #define RCC_AHB2ENR_HASHEN_Pos (5U)
15752 #define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos)
15753 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
15754 #define RCC_AHB2ENR_RNGEN_Pos (6U)
15755 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
15756 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
15757 #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
15758 #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)
15759 #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
15760 #define RCC_AHB2ENR_FMACEN_Pos (16U)
15761 #define RCC_AHB2ENR_FMACEN_Msk (0x1UL << RCC_AHB2ENR_FMACEN_Pos)
15762 #define RCC_AHB2ENR_FMACEN RCC_AHB2ENR_FMACEN_Msk
15763 #define RCC_AHB2ENR_CORDICEN_Pos (17U)
15764 #define RCC_AHB2ENR_CORDICEN_Msk (0x1UL << RCC_AHB2ENR_CORDICEN_Pos)
15765 #define RCC_AHB2ENR_CORDICEN RCC_AHB2ENR_CORDICEN_Msk
15766 #define RCC_AHB2ENR_SRAM1EN_Pos (29U)
15767 #define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)
15768 #define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
15769 #define RCC_AHB2ENR_SRAM2EN_Pos (30U)
15770 #define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)
15771 #define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
15772 
15773 /* Legacy define */
15774 #define RCC_AHB2ENR_DCMIEN_Pos RCC_AHB2ENR_DCMI_PSSIEN_Pos
15775 #define RCC_AHB2ENR_DCMIEN_Msk RCC_AHB2ENR_DCMI_PSSIEN_Msk
15776 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMI_PSSIEN
15777 /* Legacy define */
15778 #define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
15779 #define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
15780 #define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
15781 #define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
15782 #define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
15783 #define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
15784 
15785 /******************** Bit definition for RCC_AHB4ENR register ******************/
15786 #define RCC_AHB4ENR_GPIOAEN_Pos (0U)
15787 #define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)
15788 #define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
15789 #define RCC_AHB4ENR_GPIOBEN_Pos (1U)
15790 #define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)
15791 #define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
15792 #define RCC_AHB4ENR_GPIOCEN_Pos (2U)
15793 #define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)
15794 #define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
15795 #define RCC_AHB4ENR_GPIODEN_Pos (3U)
15796 #define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)
15797 #define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
15798 #define RCC_AHB4ENR_GPIOEEN_Pos (4U)
15799 #define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)
15800 #define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
15801 #define RCC_AHB4ENR_GPIOFEN_Pos (5U)
15802 #define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)
15803 #define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
15804 #define RCC_AHB4ENR_GPIOGEN_Pos (6U)
15805 #define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)
15806 #define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
15807 #define RCC_AHB4ENR_GPIOHEN_Pos (7U)
15808 #define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)
15809 #define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
15810 #define RCC_AHB4ENR_GPIOJEN_Pos (9U)
15811 #define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)
15812 #define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
15813 #define RCC_AHB4ENR_GPIOKEN_Pos (10U)
15814 #define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)
15815 #define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
15816 #define RCC_AHB4ENR_CRCEN_Pos (19U)
15817 #define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos)
15818 #define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
15819 #define RCC_AHB4ENR_BDMAEN_Pos (21U)
15820 #define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)
15821 #define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
15822 #define RCC_AHB4ENR_ADC3EN_Pos (24U)
15823 #define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)
15824 #define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
15825 #define RCC_AHB4ENR_HSEMEN_Pos (25U)
15826 #define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)
15827 #define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
15828 #define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
15829 #define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)
15830 #define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
15831 
15832 /******************** Bit definition for RCC_APB3ENR register ******************/
15833 #define RCC_APB3ENR_LTDCEN_Pos (3U)
15834 #define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos)
15835 #define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
15836 #define RCC_APB3ENR_WWDG1EN_Pos (6U)
15837 #define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos)
15838 #define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
15839 
15840 /******************** Bit definition for RCC_APB1LENR register ******************/
15841 
15842 #define RCC_APB1LENR_TIM2EN_Pos (0U)
15843 #define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos)
15844 #define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
15845 #define RCC_APB1LENR_TIM3EN_Pos (1U)
15846 #define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos)
15847 #define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
15848 #define RCC_APB1LENR_TIM4EN_Pos (2U)
15849 #define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos)
15850 #define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
15851 #define RCC_APB1LENR_TIM5EN_Pos (3U)
15852 #define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos)
15853 #define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
15854 #define RCC_APB1LENR_TIM6EN_Pos (4U)
15855 #define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos)
15856 #define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
15857 #define RCC_APB1LENR_TIM7EN_Pos (5U)
15858 #define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos)
15859 #define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
15860 #define RCC_APB1LENR_TIM12EN_Pos (6U)
15861 #define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos)
15862 #define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
15863 #define RCC_APB1LENR_TIM13EN_Pos (7U)
15864 #define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos)
15865 #define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
15866 #define RCC_APB1LENR_TIM14EN_Pos (8U)
15867 #define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos)
15868 #define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
15869 #define RCC_APB1LENR_LPTIM1EN_Pos (9U)
15870 #define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos)
15871 #define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
15872 
15873 
15874 #define RCC_APB1LENR_SPI2EN_Pos (14U)
15875 #define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos)
15876 #define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
15877 #define RCC_APB1LENR_SPI3EN_Pos (15U)
15878 #define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos)
15879 #define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
15880 #define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
15881 #define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos)
15882 #define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
15883 #define RCC_APB1LENR_USART2EN_Pos (17U)
15884 #define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos)
15885 #define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
15886 #define RCC_APB1LENR_USART3EN_Pos (18U)
15887 #define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos)
15888 #define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
15889 #define RCC_APB1LENR_UART4EN_Pos (19U)
15890 #define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos)
15891 #define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
15892 #define RCC_APB1LENR_UART5EN_Pos (20U)
15893 #define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos)
15894 #define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
15895 #define RCC_APB1LENR_I2C1EN_Pos (21U)
15896 #define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos)
15897 #define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
15898 #define RCC_APB1LENR_I2C2EN_Pos (22U)
15899 #define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos)
15900 #define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
15901 #define RCC_APB1LENR_I2C3EN_Pos (23U)
15902 #define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos)
15903 #define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
15904 #define RCC_APB1LENR_I2C5EN_Pos (25U)
15905 #define RCC_APB1LENR_I2C5EN_Msk (0x1UL << RCC_APB1LENR_I2C5EN_Pos)
15906 #define RCC_APB1LENR_I2C5EN RCC_APB1LENR_I2C5EN_Msk
15907 #define RCC_APB1LENR_CECEN_Pos (27U)
15908 #define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos)
15909 #define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
15910 #define RCC_APB1LENR_DAC12EN_Pos (29U)
15911 #define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos)
15912 #define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
15913 #define RCC_APB1LENR_UART7EN_Pos (30U)
15914 #define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos)
15915 #define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
15916 #define RCC_APB1LENR_UART8EN_Pos (31U)
15917 #define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos)
15918 #define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
15919 
15920 /* Legacy define */
15921 #define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
15922 #define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
15923 #define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
15924 /******************** Bit definition for RCC_APB1HENR register ******************/
15925 #define RCC_APB1HENR_CRSEN_Pos (1U)
15926 #define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos)
15927 #define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
15928 #define RCC_APB1HENR_SWPMIEN_Pos (2U)
15929 #define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos)
15930 #define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
15931 #define RCC_APB1HENR_OPAMPEN_Pos (4U)
15932 #define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos)
15933 #define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
15934 #define RCC_APB1HENR_MDIOSEN_Pos (5U)
15935 #define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos)
15936 #define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
15937 #define RCC_APB1HENR_FDCANEN_Pos (8U)
15938 #define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos)
15939 #define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
15940 #define RCC_APB1HENR_TIM23EN_Pos (24U)
15941 #define RCC_APB1HENR_TIM23EN_Msk (0x1UL << RCC_APB1HENR_TIM23EN_Pos)
15942 #define RCC_APB1HENR_TIM23EN RCC_APB1HENR_TIM23EN_Msk
15943 #define RCC_APB1HENR_TIM24EN_Pos (25U)
15944 #define RCC_APB1HENR_TIM24EN_Msk (0x1UL << RCC_APB1HENR_TIM24EN_Pos)
15945 #define RCC_APB1HENR_TIM24EN RCC_APB1HENR_TIM24EN_Msk
15946 
15947 /******************** Bit definition for RCC_APB2ENR register ******************/
15948 #define RCC_APB2ENR_TIM1EN_Pos (0U)
15949 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
15950 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
15951 #define RCC_APB2ENR_TIM8EN_Pos (1U)
15952 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
15953 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
15954 #define RCC_APB2ENR_USART1EN_Pos (4U)
15955 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
15956 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
15957 #define RCC_APB2ENR_USART6EN_Pos (5U)
15958 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
15959 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
15960 #define RCC_APB2ENR_UART9EN_Pos (6U)
15961 #define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos)
15962 #define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
15963 #define RCC_APB2ENR_USART10EN_Pos (7U)
15964 #define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos)
15965 #define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk
15966 #define RCC_APB2ENR_SPI1EN_Pos (12U)
15967 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
15968 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
15969 #define RCC_APB2ENR_SPI4EN_Pos (13U)
15970 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
15971 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
15972 #define RCC_APB2ENR_TIM15EN_Pos (16U)
15973 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
15974 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
15975 #define RCC_APB2ENR_TIM16EN_Pos (17U)
15976 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
15977 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
15978 #define RCC_APB2ENR_TIM17EN_Pos (18U)
15979 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
15980 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
15981 #define RCC_APB2ENR_SPI5EN_Pos (20U)
15982 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
15983 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
15984 #define RCC_APB2ENR_SAI1EN_Pos (22U)
15985 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
15986 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
15987 #define RCC_APB2ENR_DFSDM1EN_Pos (30U)
15988 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
15989 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
15990 
15991 /******************** Bit definition for RCC_APB4ENR register ******************/
15992 #define RCC_APB4ENR_SYSCFGEN_Pos (1U)
15993 #define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos)
15994 #define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
15995 #define RCC_APB4ENR_LPUART1EN_Pos (3U)
15996 #define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos)
15997 #define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
15998 #define RCC_APB4ENR_SPI6EN_Pos (5U)
15999 #define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos)
16000 #define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
16001 #define RCC_APB4ENR_I2C4EN_Pos (7U)
16002 #define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos)
16003 #define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
16004 #define RCC_APB4ENR_LPTIM2EN_Pos (9U)
16005 #define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos)
16006 #define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
16007 #define RCC_APB4ENR_LPTIM3EN_Pos (10U)
16008 #define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos)
16009 #define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
16010 #define RCC_APB4ENR_LPTIM4EN_Pos (11U)
16011 #define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos)
16012 #define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
16013 #define RCC_APB4ENR_LPTIM5EN_Pos (12U)
16014 #define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos)
16015 #define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
16016 #define RCC_APB4ENR_COMP12EN_Pos (14U)
16017 #define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos)
16018 #define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
16019 #define RCC_APB4ENR_VREFEN_Pos (15U)
16020 #define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos)
16021 #define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
16022 #define RCC_APB4ENR_RTCAPBEN_Pos (16U)
16023 #define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos)
16024 #define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
16025 #define RCC_APB4ENR_SAI4EN_Pos (21U)
16026 #define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos)
16027 #define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
16028 
16029 #define RCC_APB4ENR_DTSEN_Pos (26U)
16030 #define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos)
16031 #define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk
16032 
16033 /******************** Bit definition for RCC_AHB3RSTR register ***************/
16034 #define RCC_AHB3RSTR_MDMARST_Pos (0U)
16035 #define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)
16036 #define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
16037 #define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
16038 #define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)
16039 #define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
16040 #define RCC_AHB3RSTR_FMCRST_Pos (12U)
16041 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
16042 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
16043 #define RCC_AHB3RSTR_OSPI1RST_Pos (14U)
16044 #define RCC_AHB3RSTR_OSPI1RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)
16045 #define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk
16046 #define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
16047 #define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)
16048 #define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
16049 #define RCC_AHB3RSTR_OSPI2RST_Pos (19U)
16050 #define RCC_AHB3RSTR_OSPI2RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)
16051 #define RCC_AHB3RSTR_OSPI2RST RCC_AHB3RSTR_OSPI2RST_Msk
16052 #define RCC_AHB3RSTR_IOMNGRRST_Pos (21U)
16053 #define RCC_AHB3RSTR_IOMNGRRST_Msk (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)
16054 #define RCC_AHB3RSTR_IOMNGRRST RCC_AHB3RSTR_IOMNGRRST_Msk
16055 #define RCC_AHB3RSTR_OTFDEC1RST_Pos (22U)
16056 #define RCC_AHB3RSTR_OTFDEC1RST_Msk (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)
16057 #define RCC_AHB3RSTR_OTFDEC1RST RCC_AHB3RSTR_OTFDEC1RST_Msk
16058 #define RCC_AHB3RSTR_OTFDEC2RST_Pos (23U)
16059 #define RCC_AHB3RSTR_OTFDEC2RST_Msk (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)
16060 #define RCC_AHB3RSTR_OTFDEC2RST RCC_AHB3RSTR_OTFDEC2RST_Msk
16061 #define RCC_AHB3RSTR_CPURST_Pos (31U)
16062 #define RCC_AHB3RSTR_CPURST_Msk (0x1UL << RCC_AHB3RSTR_CPURST_Pos)
16063 #define RCC_AHB3RSTR_CPURST RCC_AHB3RSTR_CPURST_Msk
16064 
16065 
16066 /******************** Bit definition for RCC_AHB1RSTR register ***************/
16067 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
16068 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
16069 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
16070 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
16071 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
16072 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
16073 #define RCC_AHB1RSTR_ADC12RST_Pos (5U)
16074 #define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)
16075 #define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
16076 #define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
16077 #define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)
16078 #define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
16079 #define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
16080 #define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos)
16081 #define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
16082 
16083 /******************** Bit definition for RCC_AHB2RSTR register ***************/
16084 #define RCC_AHB2RSTR_DCMI_PSSIRST_Pos (0U)
16085 #define RCC_AHB2RSTR_DCMI_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)
16086 #define RCC_AHB2RSTR_DCMI_PSSIRST RCC_AHB2RSTR_DCMI_PSSIRST_Msk
16087 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
16088 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)
16089 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
16090 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
16091 #define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)
16092 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
16093 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
16094 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
16095 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
16096 #define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
16097 #define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)
16098 #define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
16099 #define RCC_AHB2RSTR_FMACRST_Pos (16U)
16100 #define RCC_AHB2RSTR_FMACRST_Msk (0x1UL << RCC_AHB2RSTR_FMACRST_Pos)
16101 #define RCC_AHB2RSTR_FMACRST RCC_AHB2RSTR_FMACRST_Msk
16102 #define RCC_AHB2RSTR_CORDICRST_Pos (17U)
16103 #define RCC_AHB2RSTR_CORDICRST_Msk (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos)
16104 #define RCC_AHB2RSTR_CORDICRST RCC_AHB2RSTR_CORDICRST_Msk
16105 
16106 /* Legacy define */
16107 #define RCC_AHB2RSTR_DCMIRST_Pos RCC_AHB2RSTR_DCMI_PSSIRST_Pos
16108 #define RCC_AHB2RSTR_DCMIRST_Msk RCC_AHB2RSTR_DCMI_PSSIRST_Msk
16109 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMI_PSSIRST
16110 /******************** Bit definition for RCC_AHB4RSTR register ******************/
16111 #define RCC_AHB4RSTR_GPIOARST_Pos (0U)
16112 #define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)
16113 #define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
16114 #define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
16115 #define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)
16116 #define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
16117 #define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
16118 #define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)
16119 #define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
16120 #define RCC_AHB4RSTR_GPIODRST_Pos (3U)
16121 #define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)
16122 #define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
16123 #define RCC_AHB4RSTR_GPIOERST_Pos (4U)
16124 #define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)
16125 #define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
16126 #define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
16127 #define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)
16128 #define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
16129 #define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
16130 #define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)
16131 #define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
16132 #define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
16133 #define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)
16134 #define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
16135 #define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
16136 #define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)
16137 #define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
16138 #define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
16139 #define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)
16140 #define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
16141 #define RCC_AHB4RSTR_CRCRST_Pos (19U)
16142 #define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)
16143 #define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
16144 #define RCC_AHB4RSTR_BDMARST_Pos (21U)
16145 #define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)
16146 #define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
16147 #define RCC_AHB4RSTR_ADC3RST_Pos (24U)
16148 #define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)
16149 #define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
16150 #define RCC_AHB4RSTR_HSEMRST_Pos (25U)
16151 #define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)
16152 #define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
16153 
16154 
16155 /******************** Bit definition for RCC_APB3RSTR register ******************/
16156 #define RCC_APB3RSTR_LTDCRST_Pos (3U)
16157 #define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos)
16158 #define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
16159 
16160 /******************** Bit definition for RCC_APB1LRSTR register ******************/
16161 
16162 #define RCC_APB1LRSTR_TIM2RST_Pos (0U)
16163 #define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)
16164 #define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
16165 #define RCC_APB1LRSTR_TIM3RST_Pos (1U)
16166 #define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)
16167 #define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
16168 #define RCC_APB1LRSTR_TIM4RST_Pos (2U)
16169 #define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos)
16170 #define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
16171 #define RCC_APB1LRSTR_TIM5RST_Pos (3U)
16172 #define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)
16173 #define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
16174 #define RCC_APB1LRSTR_TIM6RST_Pos (4U)
16175 #define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)
16176 #define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
16177 #define RCC_APB1LRSTR_TIM7RST_Pos (5U)
16178 #define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)
16179 #define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
16180 #define RCC_APB1LRSTR_TIM12RST_Pos (6U)
16181 #define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)
16182 #define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
16183 #define RCC_APB1LRSTR_TIM13RST_Pos (7U)
16184 #define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos)
16185 #define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
16186 #define RCC_APB1LRSTR_TIM14RST_Pos (8U)
16187 #define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos)
16188 #define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
16189 #define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
16190 #define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos)
16191 #define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
16192 #define RCC_APB1LRSTR_SPI2RST_Pos (14U)
16193 #define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)
16194 #define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
16195 #define RCC_APB1LRSTR_SPI3RST_Pos (15U)
16196 #define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)
16197 #define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
16198 #define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
16199 #define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos)
16200 #define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
16201 #define RCC_APB1LRSTR_USART2RST_Pos (17U)
16202 #define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)
16203 #define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
16204 #define RCC_APB1LRSTR_USART3RST_Pos (18U)
16205 #define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)
16206 #define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
16207 #define RCC_APB1LRSTR_UART4RST_Pos (19U)
16208 #define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)
16209 #define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
16210 #define RCC_APB1LRSTR_UART5RST_Pos (20U)
16211 #define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)
16212 #define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
16213 #define RCC_APB1LRSTR_I2C1RST_Pos (21U)
16214 #define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)
16215 #define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
16216 #define RCC_APB1LRSTR_I2C2RST_Pos (22U)
16217 #define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)
16218 #define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
16219 #define RCC_APB1LRSTR_I2C3RST_Pos (23U)
16220 #define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos)
16221 #define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
16222 #define RCC_APB1LRSTR_I2C5RST_Pos (25U)
16223 #define RCC_APB1LRSTR_I2C5RST_Msk (0x1UL << RCC_APB1LRSTR_I2C5RST_Pos)
16224 #define RCC_APB1LRSTR_I2C5RST RCC_APB1LRSTR_I2C5RST_Msk
16225 #define RCC_APB1LRSTR_CECRST_Pos (27U)
16226 #define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos)
16227 #define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
16228 #define RCC_APB1LRSTR_DAC12RST_Pos (29U)
16229 #define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos)
16230 #define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
16231 #define RCC_APB1LRSTR_UART7RST_Pos (30U)
16232 #define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos)
16233 #define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
16234 #define RCC_APB1LRSTR_UART8RST_Pos (31U)
16235 #define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos)
16236 #define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
16237 
16238 /* Legacy define */
16239 #define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
16240 #define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
16241 #define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
16242 /******************** Bit definition for RCC_APB1HRSTR register ******************/
16243 #define RCC_APB1HRSTR_CRSRST_Pos (1U)
16244 #define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos)
16245 #define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
16246 #define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
16247 #define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos)
16248 #define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
16249 #define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
16250 #define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos)
16251 #define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
16252 #define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
16253 #define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos)
16254 #define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
16255 #define RCC_APB1HRSTR_FDCANRST_Pos (8U)
16256 #define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)
16257 #define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
16258 #define RCC_APB1HRSTR_TIM23RST_Pos (24U)
16259 #define RCC_APB1HRSTR_TIM23RST_Msk (0x1UL << RCC_APB1HRSTR_TIM23RST_Pos)
16260 #define RCC_APB1HRSTR_TIM23RST RCC_APB1HRSTR_TIM23RST_Msk
16261 #define RCC_APB1HRSTR_TIM24RST_Pos (25U)
16262 #define RCC_APB1HRSTR_TIM24RST_Msk (0x1UL << RCC_APB1HRSTR_TIM24RST_Pos)
16263 #define RCC_APB1HRSTR_TIM24RST RCC_APB1HRSTR_TIM24RST_Msk
16264 
16265 /******************** Bit definition for RCC_APB2RSTR register ******************/
16266 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
16267 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
16268 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
16269 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
16270 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
16271 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
16272 #define RCC_APB2RSTR_USART1RST_Pos (4U)
16273 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
16274 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
16275 #define RCC_APB2RSTR_USART6RST_Pos (5U)
16276 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
16277 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
16278 #define RCC_APB2RSTR_UART9RST_Pos (6U)
16279 #define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos)
16280 #define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
16281 #define RCC_APB2RSTR_USART10RST_Pos (7U)
16282 #define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)
16283 #define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk
16284 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
16285 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
16286 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
16287 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
16288 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
16289 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
16290 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
16291 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
16292 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
16293 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
16294 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
16295 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
16296 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
16297 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
16298 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
16299 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
16300 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
16301 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
16302 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
16303 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
16304 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
16305 #define RCC_APB2RSTR_DFSDM1RST_Pos (30U)
16306 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
16307 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
16308 
16309 /******************** Bit definition for RCC_APB4RSTR register ******************/
16310 #define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
16311 #define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos)
16312 #define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
16313 #define RCC_APB4RSTR_LPUART1RST_Pos (3U)
16314 #define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos)
16315 #define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
16316 #define RCC_APB4RSTR_SPI6RST_Pos (5U)
16317 #define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos)
16318 #define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
16319 #define RCC_APB4RSTR_I2C4RST_Pos (7U)
16320 #define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos)
16321 #define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
16322 #define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
16323 #define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos)
16324 #define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
16325 #define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
16326 #define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos)
16327 #define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
16328 #define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
16329 #define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos)
16330 #define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
16331 #define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
16332 #define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos)
16333 #define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
16334 #define RCC_APB4RSTR_COMP12RST_Pos (14U)
16335 #define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos)
16336 #define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
16337 #define RCC_APB4RSTR_VREFRST_Pos (15U)
16338 #define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos)
16339 #define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
16340 #define RCC_APB4RSTR_SAI4RST_Pos (21U)
16341 #define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos)
16342 #define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
16343 
16344 #define RCC_APB4RSTR_DTSRST_Pos (26U)
16345 #define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos)
16346 #define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk
16347 
16348 /******************** Bit definition for RCC_GCR register ********************/
16349 #define RCC_GCR_WW1RSC_Pos (0U)
16350 #define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos)
16351 #define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
16352 
16353 /******************** Bit definition for RCC_D3AMR register ********************/
16354 #define RCC_D3AMR_BDMAAMEN_Pos (0U)
16355 #define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos)
16356 #define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
16357 #define RCC_D3AMR_LPUART1AMEN_Pos (3U)
16358 #define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos)
16359 #define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
16360 #define RCC_D3AMR_SPI6AMEN_Pos (5U)
16361 #define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos)
16362 #define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
16363 #define RCC_D3AMR_I2C4AMEN_Pos (7U)
16364 #define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos)
16365 #define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
16366 #define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
16367 #define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos)
16368 #define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
16369 #define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
16370 #define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos)
16371 #define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
16372 #define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
16373 #define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos)
16374 #define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
16375 #define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
16376 #define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos)
16377 #define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
16378 #define RCC_D3AMR_COMP12AMEN_Pos (14U)
16379 #define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos)
16380 #define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
16381 #define RCC_D3AMR_VREFAMEN_Pos (15U)
16382 #define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos)
16383 #define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
16384 #define RCC_D3AMR_RTCAMEN_Pos (16U)
16385 #define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos)
16386 #define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
16387 #define RCC_D3AMR_CRCAMEN_Pos (19U)
16388 #define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos)
16389 #define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
16390 #define RCC_D3AMR_SAI4AMEN_Pos (21U)
16391 #define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos)
16392 #define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
16393 #define RCC_D3AMR_ADC3AMEN_Pos (24U)
16394 #define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos)
16395 #define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
16396 
16397 #define RCC_D3AMR_DTSAMEN_Pos (26U)
16398 #define RCC_D3AMR_DTSAMEN_Msk (0x1UL << RCC_D3AMR_DTSAMEN_Pos)
16399 #define RCC_D3AMR_DTSAMEN RCC_D3AMR_DTSAMEN_Msk
16400 
16401 #define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
16402 #define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos)
16403 #define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
16404 #define RCC_D3AMR_SRAM4AMEN_Pos (29U)
16405 #define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos)
16406 #define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
16407 /******************** Bit definition for RCC_AHB3LPENR register **************/
16408 #define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
16409 #define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)
16410 #define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
16411 #define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
16412 #define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)
16413 #define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
16414 #define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
16415 #define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)
16416 #define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
16417 #define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
16418 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
16419 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
16420 #define RCC_AHB3LPENR_OSPI1LPEN_Pos (14U)
16421 #define RCC_AHB3LPENR_OSPI1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)
16422 #define RCC_AHB3LPENR_OSPI1LPEN RCC_AHB3LPENR_OSPI1LPEN_Msk
16423 #define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
16424 #define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)
16425 #define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
16426 #define RCC_AHB3LPENR_OSPI2LPEN_Pos (19U)
16427 #define RCC_AHB3LPENR_OSPI2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)
16428 #define RCC_AHB3LPENR_OSPI2LPEN RCC_AHB3LPENR_OSPI2LPEN_Msk
16429 #define RCC_AHB3LPENR_IOMNGRLPEN_Pos (21U)
16430 #define RCC_AHB3LPENR_IOMNGRLPEN_Msk (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)
16431 #define RCC_AHB3LPENR_IOMNGRLPEN RCC_AHB3LPENR_IOMNGRLPEN_Msk
16432 #define RCC_AHB3LPENR_OTFDEC1LPEN_Pos (22U)
16433 #define RCC_AHB3LPENR_OTFDEC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)
16434 #define RCC_AHB3LPENR_OTFDEC1LPEN RCC_AHB3LPENR_OTFDEC1LPEN_Msk
16435 #define RCC_AHB3LPENR_OTFDEC2LPEN_Pos (23U)
16436 #define RCC_AHB3LPENR_OTFDEC2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)
16437 #define RCC_AHB3LPENR_OTFDEC2LPEN RCC_AHB3LPENR_OTFDEC2LPEN_Msk
16438 #define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
16439 #define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)
16440 #define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
16441 #define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
16442 #define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)
16443 #define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
16444 #define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
16445 #define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)
16446 #define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
16447 #define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
16448 #define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)
16449 #define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
16450 
16451 
16452 /******************** Bit definition for RCC_AHB1LPENR register ***************/
16453 #define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
16454 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
16455 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
16456 #define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
16457 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
16458 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
16459 #define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
16460 #define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)
16461 #define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
16462 #define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
16463 #define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos)
16464 #define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
16465 #define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
16466 #define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos)
16467 #define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
16468 #define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
16469 #define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos)
16470 #define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
16471 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
16472 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos)
16473 #define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
16474 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
16475 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos)
16476 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
16477 
16478 /******************** Bit definition for RCC_AHB2LPENR register ***************/
16479 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U)
16480 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos)
16481 #define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
16482 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
16483 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos)
16484 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
16485 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
16486 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)
16487 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
16488 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
16489 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
16490 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
16491 #define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
16492 #define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos)
16493 #define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
16494 #define RCC_AHB2LPENR_FMACLPEN_Pos (16U)
16495 #define RCC_AHB2LPENR_FMACLPEN_Msk (0x1UL << RCC_AHB2LPENR_FMACLPEN_Pos)
16496 #define RCC_AHB2LPENR_FMACLPEN RCC_AHB2LPENR_FMACLPEN_Msk
16497 #define RCC_AHB2LPENR_CORDICLPEN_Pos (17U)
16498 #define RCC_AHB2LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos)
16499 #define RCC_AHB2LPENR_CORDICLPEN RCC_AHB2LPENR_CORDICLPEN_Msk
16500 #define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
16501 #define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos)
16502 #define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
16503 #define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
16504 #define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)
16505 #define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
16506 
16507 /* Legacy define */
16508 #define RCC_AHB2LPENR_DCMILPEN_Pos RCC_AHB2LPENR_DCMI_PSSILPEN_Pos
16509 #define RCC_AHB2LPENR_DCMILPEN_Msk RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
16510 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMI_PSSILPEN
16511 #define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
16512 #define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
16513 #define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
16514 #define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
16515 #define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
16516 #define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
16517 
16518 /******************** Bit definition for RCC_AHB4LPENR register ******************/
16519 #define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
16520 #define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)
16521 #define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
16522 #define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
16523 #define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)
16524 #define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
16525 #define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
16526 #define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)
16527 #define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
16528 #define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
16529 #define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)
16530 #define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
16531 #define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
16532 #define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)
16533 #define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
16534 #define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
16535 #define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)
16536 #define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
16537 #define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
16538 #define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)
16539 #define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
16540 #define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
16541 #define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)
16542 #define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
16543 #define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
16544 #define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos)
16545 #define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
16546 #define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
16547 #define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos)
16548 #define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
16549 #define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
16550 #define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)
16551 #define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
16552 #define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
16553 #define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos)
16554 #define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
16555 #define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
16556 #define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos)
16557 #define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
16558 #define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
16559 #define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos)
16560 #define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
16561 #define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
16562 #define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos)
16563 #define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
16564 
16565 /* Legacy define */
16566 #define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
16567 #define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
16568 #define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
16569 /******************** Bit definition for RCC_APB3LPENR register ******************/
16570 #define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
16571 #define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos)
16572 #define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
16573 #define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
16574 #define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos)
16575 #define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
16576 
16577 /******************** Bit definition for RCC_APB1LLPENR register ******************/
16578 
16579 #define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
16580 #define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)
16581 #define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
16582 #define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
16583 #define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)
16584 #define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
16585 #define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
16586 #define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos)
16587 #define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
16588 #define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
16589 #define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)
16590 #define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
16591 #define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
16592 #define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)
16593 #define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
16594 #define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
16595 #define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)
16596 #define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
16597 #define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
16598 #define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos)
16599 #define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
16600 #define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
16601 #define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos)
16602 #define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
16603 #define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
16604 #define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos)
16605 #define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
16606 #define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
16607 #define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos)
16608 #define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
16609 
16610 
16611 #define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
16612 #define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)
16613 #define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
16614 #define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
16615 #define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)
16616 #define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
16617 #define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
16618 #define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos)
16619 #define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
16620 #define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
16621 #define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos)
16622 #define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
16623 #define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
16624 #define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos)
16625 #define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
16626 #define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
16627 #define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos)
16628 #define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
16629 #define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
16630 #define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos)
16631 #define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
16632 #define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
16633 #define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)
16634 #define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
16635 #define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
16636 #define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)
16637 #define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
16638 #define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
16639 #define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos)
16640 #define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
16641 #define RCC_APB1LLPENR_I2C5LPEN_Pos (25U)
16642 #define RCC_APB1LLPENR_I2C5LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C5LPEN_Pos)
16643 #define RCC_APB1LLPENR_I2C5LPEN RCC_APB1LLPENR_I2C5LPEN_Msk
16644 #define RCC_APB1LLPENR_CECLPEN_Pos (27U)
16645 #define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos)
16646 #define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
16647 #define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
16648 #define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos)
16649 #define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
16650 #define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
16651 #define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos)
16652 #define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
16653 #define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
16654 #define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos)
16655 #define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
16656 
16657 /* Legacy define */
16658 #define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
16659 #define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
16660 #define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
16661 /******************** Bit definition for RCC_APB1HLPENR register ******************/
16662 #define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
16663 #define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos)
16664 #define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
16665 #define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
16666 #define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos)
16667 #define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
16668 #define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
16669 #define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos)
16670 #define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
16671 #define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
16672 #define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos)
16673 #define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
16674 #define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
16675 #define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)
16676 #define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
16677 #define RCC_APB1HLPENR_TIM23LPEN_Pos (24U)
16678 #define RCC_APB1HLPENR_TIM23LPEN_Msk (0x1UL << RCC_APB1HLPENR_TIM23LPEN_Pos)
16679 #define RCC_APB1HLPENR_TIM23LPEN RCC_APB1HLPENR_TIM23LPEN_Msk
16680 #define RCC_APB1HLPENR_TIM24LPEN_Pos (25U)
16681 #define RCC_APB1HLPENR_TIM24LPEN_Msk (0x1UL << RCC_APB1HLPENR_TIM24LPEN_Pos)
16682 #define RCC_APB1HLPENR_TIM24LPEN RCC_APB1HLPENR_TIM24LPEN_Msk
16683 
16684 /******************** Bit definition for RCC_APB2LPENR register ******************/
16685 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
16686 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
16687 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
16688 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
16689 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
16690 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
16691 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
16692 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
16693 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
16694 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
16695 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
16696 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
16697 #define RCC_APB2LPENR_UART9LPEN_Pos (6U)
16698 #define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)
16699 #define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
16700 #define RCC_APB2LPENR_USART10LPEN_Pos (7U)
16701 #define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)
16702 #define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk
16703 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
16704 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
16705 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
16706 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
16707 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
16708 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
16709 #define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
16710 #define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)
16711 #define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
16712 #define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
16713 #define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)
16714 #define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
16715 #define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
16716 #define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)
16717 #define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
16718 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
16719 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
16720 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
16721 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
16722 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
16723 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
16724 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (30U)
16725 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
16726 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
16727 
16728 /******************** Bit definition for RCC_APB4LPENR register ******************/
16729 #define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
16730 #define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos)
16731 #define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
16732 #define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
16733 #define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)
16734 #define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
16735 #define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
16736 #define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos)
16737 #define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
16738 #define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
16739 #define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos)
16740 #define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
16741 #define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
16742 #define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos)
16743 #define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
16744 #define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
16745 #define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos)
16746 #define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
16747 #define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
16748 #define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos)
16749 #define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
16750 #define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
16751 #define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos)
16752 #define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
16753 #define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
16754 #define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos)
16755 #define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
16756 #define RCC_APB4LPENR_VREFLPEN_Pos (15U)
16757 #define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos)
16758 #define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
16759 #define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
16760 #define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos)
16761 #define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
16762 #define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
16763 #define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos)
16764 #define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
16765 
16766 #define RCC_APB4LPENR_DTSLPEN_Pos (26U)
16767 #define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos)
16768 #define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk
16769 
16770 /******************** Bit definition for RCC_RSR register *******************/
16771 #define RCC_RSR_RMVF_Pos (16U)
16772 #define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos)
16773 #define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
16774 #define RCC_RSR_CPURSTF_Pos (17U)
16775 #define RCC_RSR_CPURSTF_Msk (0x1UL << RCC_RSR_CPURSTF_Pos)
16776 #define RCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk
16777 #define RCC_RSR_D1RSTF_Pos (19U)
16778 #define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos)
16779 #define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
16780 #define RCC_RSR_D2RSTF_Pos (20U)
16781 #define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos)
16782 #define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
16783 #define RCC_RSR_BORRSTF_Pos (21U)
16784 #define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos)
16785 #define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
16786 #define RCC_RSR_PINRSTF_Pos (22U)
16787 #define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos)
16788 #define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
16789 #define RCC_RSR_PORRSTF_Pos (23U)
16790 #define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos)
16791 #define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
16792 #define RCC_RSR_SFTRSTF_Pos (24U)
16793 #define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos)
16794 #define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
16795 #define RCC_RSR_IWDG1RSTF_Pos (26U)
16796 #define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos)
16797 #define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
16798 #define RCC_RSR_WWDG1RSTF_Pos (28U)
16799 #define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos)
16800 #define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
16801 
16802 #define RCC_RSR_LPWRRSTF_Pos (30U)
16803 #define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos)
16804 #define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
16805 
16806 
16807 /******************************************************************************/
16808 /* */
16809 /* RNG */
16810 /* */
16811 /******************************************************************************/
16812 /*************************** RNG VER **************************************/
16813 #define RNG_VER_3_2
16814 /******************** Bits definition for RNG_CR register *******************/
16815 #define RNG_CR_RNGEN_Pos (2U)
16816 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
16817 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
16818 #define RNG_CR_IE_Pos (3U)
16819 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
16820 #define RNG_CR_IE RNG_CR_IE_Msk
16821 #define RNG_CR_CED_Pos (5U)
16822 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos)
16823 #define RNG_CR_CED RNG_CR_CED_Msk
16824 #define RNG_CR_RNG_CONFIG3_Pos (8U)
16825 #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
16826 #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
16827 #define RNG_CR_NISTC_Pos (12U)
16828 #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
16829 #define RNG_CR_NISTC RNG_CR_NISTC_Msk
16830 #define RNG_CR_RNG_CONFIG2_Pos (13U)
16831 #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
16832 #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
16833 #define RNG_CR_CLKDIV_Pos (16U)
16834 #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
16835 #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
16836 #define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos)
16837 #define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos)
16838 #define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos)
16839 #define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos)
16840 #define RNG_CR_RNG_CONFIG1_Pos (20U)
16841 #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
16842 #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
16843 #define RNG_CR_CONDRST_Pos (30U)
16844 #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
16845 #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
16846 #define RNG_CR_CONFIGLOCK_Pos (31U)
16847 #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
16848 #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
16849 
16850 /******************** Bits definition for RNG_SR register *******************/
16851 #define RNG_SR_DRDY_Pos (0U)
16852 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
16853 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
16854 #define RNG_SR_CECS_Pos (1U)
16855 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
16856 #define RNG_SR_CECS RNG_SR_CECS_Msk
16857 #define RNG_SR_SECS_Pos (2U)
16858 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
16859 #define RNG_SR_SECS RNG_SR_SECS_Msk
16860 #define RNG_SR_CEIS_Pos (5U)
16861 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
16862 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
16863 #define RNG_SR_SEIS_Pos (6U)
16864 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
16865 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
16866 
16867 /******************************************************************************/
16868 /* */
16869 /* Real-Time Clock (RTC) */
16870 /* */
16871 /******************************************************************************/
16872 /******************** Bits definition for RTC_TR register *******************/
16873 #define RTC_TR_PM_Pos (22U)
16874 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
16875 #define RTC_TR_PM RTC_TR_PM_Msk
16876 #define RTC_TR_HT_Pos (20U)
16877 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
16878 #define RTC_TR_HT RTC_TR_HT_Msk
16879 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
16880 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
16881 #define RTC_TR_HU_Pos (16U)
16882 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
16883 #define RTC_TR_HU RTC_TR_HU_Msk
16884 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
16885 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
16886 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
16887 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
16888 #define RTC_TR_MNT_Pos (12U)
16889 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
16890 #define RTC_TR_MNT RTC_TR_MNT_Msk
16891 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
16892 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
16893 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
16894 #define RTC_TR_MNU_Pos (8U)
16895 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
16896 #define RTC_TR_MNU RTC_TR_MNU_Msk
16897 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
16898 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
16899 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
16900 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
16901 #define RTC_TR_ST_Pos (4U)
16902 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
16903 #define RTC_TR_ST RTC_TR_ST_Msk
16904 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
16905 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
16906 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
16907 #define RTC_TR_SU_Pos (0U)
16908 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
16909 #define RTC_TR_SU RTC_TR_SU_Msk
16910 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
16911 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
16912 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
16913 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
16915 /******************** Bits definition for RTC_DR register *******************/
16916 #define RTC_DR_YT_Pos (20U)
16917 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
16918 #define RTC_DR_YT RTC_DR_YT_Msk
16919 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
16920 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
16921 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
16922 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
16923 #define RTC_DR_YU_Pos (16U)
16924 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
16925 #define RTC_DR_YU RTC_DR_YU_Msk
16926 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
16927 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
16928 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
16929 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
16930 #define RTC_DR_WDU_Pos (13U)
16931 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
16932 #define RTC_DR_WDU RTC_DR_WDU_Msk
16933 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
16934 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
16935 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
16936 #define RTC_DR_MT_Pos (12U)
16937 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
16938 #define RTC_DR_MT RTC_DR_MT_Msk
16939 #define RTC_DR_MU_Pos (8U)
16940 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
16941 #define RTC_DR_MU RTC_DR_MU_Msk
16942 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
16943 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
16944 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
16945 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
16946 #define RTC_DR_DT_Pos (4U)
16947 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
16948 #define RTC_DR_DT RTC_DR_DT_Msk
16949 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
16950 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
16951 #define RTC_DR_DU_Pos (0U)
16952 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
16953 #define RTC_DR_DU RTC_DR_DU_Msk
16954 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
16955 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
16956 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
16957 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
16959 /******************** Bits definition for RTC_CR register *******************/
16960 #define RTC_CR_ITSE_Pos (24U)
16961 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
16962 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
16963 #define RTC_CR_COE_Pos (23U)
16964 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
16965 #define RTC_CR_COE RTC_CR_COE_Msk
16966 #define RTC_CR_OSEL_Pos (21U)
16967 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
16968 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
16969 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
16970 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
16971 #define RTC_CR_POL_Pos (20U)
16972 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
16973 #define RTC_CR_POL RTC_CR_POL_Msk
16974 #define RTC_CR_COSEL_Pos (19U)
16975 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
16976 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
16977 #define RTC_CR_BKP_Pos (18U)
16978 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
16979 #define RTC_CR_BKP RTC_CR_BKP_Msk
16980 #define RTC_CR_SUB1H_Pos (17U)
16981 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
16982 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
16983 #define RTC_CR_ADD1H_Pos (16U)
16984 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
16985 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
16986 #define RTC_CR_TSIE_Pos (15U)
16987 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
16988 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
16989 #define RTC_CR_WUTIE_Pos (14U)
16990 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
16991 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
16992 #define RTC_CR_ALRBIE_Pos (13U)
16993 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
16994 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
16995 #define RTC_CR_ALRAIE_Pos (12U)
16996 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
16997 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
16998 #define RTC_CR_TSE_Pos (11U)
16999 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
17000 #define RTC_CR_TSE RTC_CR_TSE_Msk
17001 #define RTC_CR_WUTE_Pos (10U)
17002 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
17003 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
17004 #define RTC_CR_ALRBE_Pos (9U)
17005 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
17006 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
17007 #define RTC_CR_ALRAE_Pos (8U)
17008 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
17009 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
17010 #define RTC_CR_FMT_Pos (6U)
17011 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
17012 #define RTC_CR_FMT RTC_CR_FMT_Msk
17013 #define RTC_CR_BYPSHAD_Pos (5U)
17014 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
17015 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
17016 #define RTC_CR_REFCKON_Pos (4U)
17017 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
17018 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
17019 #define RTC_CR_TSEDGE_Pos (3U)
17020 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
17021 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
17022 #define RTC_CR_WUCKSEL_Pos (0U)
17023 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
17024 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
17025 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
17026 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
17027 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
17029 /******************** Bits definition for RTC_ISR register ******************/
17030 #define RTC_ISR_ITSF_Pos (17U)
17031 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
17032 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
17033 #define RTC_ISR_RECALPF_Pos (16U)
17034 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
17035 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
17036 #define RTC_ISR_TAMP3F_Pos (15U)
17037 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
17038 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
17039 #define RTC_ISR_TAMP2F_Pos (14U)
17040 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
17041 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
17042 #define RTC_ISR_TAMP1F_Pos (13U)
17043 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
17044 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
17045 #define RTC_ISR_TSOVF_Pos (12U)
17046 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
17047 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
17048 #define RTC_ISR_TSF_Pos (11U)
17049 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
17050 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
17051 #define RTC_ISR_WUTF_Pos (10U)
17052 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
17053 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
17054 #define RTC_ISR_ALRBF_Pos (9U)
17055 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
17056 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
17057 #define RTC_ISR_ALRAF_Pos (8U)
17058 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
17059 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
17060 #define RTC_ISR_INIT_Pos (7U)
17061 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
17062 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
17063 #define RTC_ISR_INITF_Pos (6U)
17064 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
17065 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
17066 #define RTC_ISR_RSF_Pos (5U)
17067 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
17068 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
17069 #define RTC_ISR_INITS_Pos (4U)
17070 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
17071 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
17072 #define RTC_ISR_SHPF_Pos (3U)
17073 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
17074 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
17075 #define RTC_ISR_WUTWF_Pos (2U)
17076 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
17077 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
17078 #define RTC_ISR_ALRBWF_Pos (1U)
17079 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
17080 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
17081 #define RTC_ISR_ALRAWF_Pos (0U)
17082 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
17083 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
17084 
17085 /******************** Bits definition for RTC_PRER register *****************/
17086 #define RTC_PRER_PREDIV_A_Pos (16U)
17087 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
17088 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
17089 #define RTC_PRER_PREDIV_S_Pos (0U)
17090 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
17091 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
17092 
17093 /******************** Bits definition for RTC_WUTR register *****************/
17094 #define RTC_WUTR_WUT_Pos (0U)
17095 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
17096 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
17097 
17098 /******************** Bits definition for RTC_ALRMAR register ***************/
17099 #define RTC_ALRMAR_MSK4_Pos (31U)
17100 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
17101 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
17102 #define RTC_ALRMAR_WDSEL_Pos (30U)
17103 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
17104 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
17105 #define RTC_ALRMAR_DT_Pos (28U)
17106 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
17107 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
17108 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
17109 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
17110 #define RTC_ALRMAR_DU_Pos (24U)
17111 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
17112 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
17113 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
17114 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
17115 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
17116 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
17117 #define RTC_ALRMAR_MSK3_Pos (23U)
17118 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
17119 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
17120 #define RTC_ALRMAR_PM_Pos (22U)
17121 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
17122 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
17123 #define RTC_ALRMAR_HT_Pos (20U)
17124 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
17125 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
17126 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
17127 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
17128 #define RTC_ALRMAR_HU_Pos (16U)
17129 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
17130 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
17131 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
17132 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
17133 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
17134 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
17135 #define RTC_ALRMAR_MSK2_Pos (15U)
17136 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
17137 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
17138 #define RTC_ALRMAR_MNT_Pos (12U)
17139 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
17140 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
17141 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
17142 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
17143 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
17144 #define RTC_ALRMAR_MNU_Pos (8U)
17145 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
17146 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
17147 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
17148 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
17149 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
17150 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
17151 #define RTC_ALRMAR_MSK1_Pos (7U)
17152 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
17153 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
17154 #define RTC_ALRMAR_ST_Pos (4U)
17155 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
17156 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
17157 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
17158 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
17159 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
17160 #define RTC_ALRMAR_SU_Pos (0U)
17161 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
17162 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
17163 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
17164 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
17165 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
17166 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
17168 /******************** Bits definition for RTC_ALRMBR register ***************/
17169 #define RTC_ALRMBR_MSK4_Pos (31U)
17170 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
17171 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
17172 #define RTC_ALRMBR_WDSEL_Pos (30U)
17173 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
17174 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
17175 #define RTC_ALRMBR_DT_Pos (28U)
17176 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
17177 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
17178 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
17179 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
17180 #define RTC_ALRMBR_DU_Pos (24U)
17181 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
17182 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
17183 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
17184 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
17185 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
17186 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
17187 #define RTC_ALRMBR_MSK3_Pos (23U)
17188 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
17189 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
17190 #define RTC_ALRMBR_PM_Pos (22U)
17191 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
17192 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
17193 #define RTC_ALRMBR_HT_Pos (20U)
17194 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
17195 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
17196 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
17197 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
17198 #define RTC_ALRMBR_HU_Pos (16U)
17199 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
17200 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
17201 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
17202 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
17203 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
17204 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
17205 #define RTC_ALRMBR_MSK2_Pos (15U)
17206 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
17207 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
17208 #define RTC_ALRMBR_MNT_Pos (12U)
17209 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
17210 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
17211 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
17212 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
17213 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
17214 #define RTC_ALRMBR_MNU_Pos (8U)
17215 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
17216 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
17217 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
17218 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
17219 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
17220 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
17221 #define RTC_ALRMBR_MSK1_Pos (7U)
17222 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
17223 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
17224 #define RTC_ALRMBR_ST_Pos (4U)
17225 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
17226 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
17227 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
17228 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
17229 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
17230 #define RTC_ALRMBR_SU_Pos (0U)
17231 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
17232 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
17233 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
17234 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
17235 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
17236 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
17238 /******************** Bits definition for RTC_WPR register ******************/
17239 #define RTC_WPR_KEY_Pos (0U)
17240 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
17241 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
17242 
17243 /******************** Bits definition for RTC_SSR register ******************/
17244 #define RTC_SSR_SS_Pos (0U)
17245 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
17246 #define RTC_SSR_SS RTC_SSR_SS_Msk
17247 
17248 /******************** Bits definition for RTC_SHIFTR register ***************/
17249 #define RTC_SHIFTR_SUBFS_Pos (0U)
17250 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
17251 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
17252 #define RTC_SHIFTR_ADD1S_Pos (31U)
17253 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
17254 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
17255 
17256 /******************** Bits definition for RTC_TSTR register *****************/
17257 #define RTC_TSTR_PM_Pos (22U)
17258 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
17259 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
17260 #define RTC_TSTR_HT_Pos (20U)
17261 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
17262 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
17263 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
17264 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
17265 #define RTC_TSTR_HU_Pos (16U)
17266 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
17267 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
17268 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
17269 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
17270 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
17271 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
17272 #define RTC_TSTR_MNT_Pos (12U)
17273 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
17274 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
17275 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
17276 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
17277 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
17278 #define RTC_TSTR_MNU_Pos (8U)
17279 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
17280 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
17281 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
17282 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
17283 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
17284 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
17285 #define RTC_TSTR_ST_Pos (4U)
17286 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
17287 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
17288 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
17289 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
17290 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
17291 #define RTC_TSTR_SU_Pos (0U)
17292 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
17293 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
17294 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
17295 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
17296 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
17297 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
17299 /******************** Bits definition for RTC_TSDR register *****************/
17300 #define RTC_TSDR_WDU_Pos (13U)
17301 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
17302 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
17303 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
17304 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
17305 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
17306 #define RTC_TSDR_MT_Pos (12U)
17307 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
17308 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
17309 #define RTC_TSDR_MU_Pos (8U)
17310 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
17311 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
17312 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
17313 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
17314 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
17315 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
17316 #define RTC_TSDR_DT_Pos (4U)
17317 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
17318 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
17319 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
17320 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
17321 #define RTC_TSDR_DU_Pos (0U)
17322 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
17323 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
17324 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
17325 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
17326 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
17327 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
17329 /******************** Bits definition for RTC_TSSSR register ****************/
17330 #define RTC_TSSSR_SS_Pos (0U)
17331 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
17332 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
17333 
17334 /******************** Bits definition for RTC_CALR register *****************/
17335 #define RTC_CALR_CALP_Pos (15U)
17336 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
17337 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
17338 #define RTC_CALR_CALW8_Pos (14U)
17339 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
17340 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
17341 #define RTC_CALR_CALW16_Pos (13U)
17342 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
17343 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
17344 #define RTC_CALR_CALM_Pos (0U)
17345 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
17346 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
17347 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
17348 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
17349 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
17350 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
17351 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
17352 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
17353 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
17354 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
17355 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
17357 /******************** Bits definition for RTC_TAMPCR register ***************/
17358 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
17359 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
17360 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
17361 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
17362 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
17363 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
17364 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
17365 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
17366 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
17367 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
17368 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
17369 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
17370 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
17371 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
17372 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
17373 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
17374 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
17375 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
17376 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
17377 #define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
17378 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
17379 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
17380 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
17381 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
17382 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
17383 #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
17384 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
17385 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
17386 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
17387 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
17388 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
17389 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
17390 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
17391 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
17392 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
17393 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
17394 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
17395 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
17396 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
17397 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
17398 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
17399 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
17400 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
17401 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
17402 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
17403 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
17404 #define RTC_TAMPCR_TAMPTS_Pos (7U)
17405 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
17406 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
17407 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
17408 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
17409 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
17410 #define RTC_TAMPCR_TAMP3E_Pos (5U)
17411 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
17412 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
17413 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
17414 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
17415 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
17416 #define RTC_TAMPCR_TAMP2E_Pos (3U)
17417 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
17418 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
17419 #define RTC_TAMPCR_TAMPIE_Pos (2U)
17420 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
17421 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
17422 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
17423 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
17424 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
17425 #define RTC_TAMPCR_TAMP1E_Pos (0U)
17426 #define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
17427 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
17428 
17429 /******************** Bits definition for RTC_ALRMASSR register *************/
17430 #define RTC_ALRMASSR_MASKSS_Pos (24U)
17431 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
17432 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
17433 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
17434 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
17435 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
17436 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
17437 #define RTC_ALRMASSR_SS_Pos (0U)
17438 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
17439 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
17440 
17441 /******************** Bits definition for RTC_ALRMBSSR register *************/
17442 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
17443 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
17444 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
17445 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
17446 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
17447 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
17448 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
17449 #define RTC_ALRMBSSR_SS_Pos (0U)
17450 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
17451 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
17452 
17453 /******************** Bits definition for RTC_OR register *******************/
17454 #define RTC_OR_OUT_RMP_Pos (1U)
17455 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
17456 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
17457 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
17458 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
17459 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
17460 
17461 /******************** Bits definition for RTC_BKP0R register ****************/
17462 #define RTC_BKP0R_Pos (0U)
17463 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
17464 #define RTC_BKP0R RTC_BKP0R_Msk
17465 
17466 /******************** Bits definition for RTC_BKP1R register ****************/
17467 #define RTC_BKP1R_Pos (0U)
17468 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
17469 #define RTC_BKP1R RTC_BKP1R_Msk
17470 
17471 /******************** Bits definition for RTC_BKP2R register ****************/
17472 #define RTC_BKP2R_Pos (0U)
17473 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
17474 #define RTC_BKP2R RTC_BKP2R_Msk
17475 
17476 /******************** Bits definition for RTC_BKP3R register ****************/
17477 #define RTC_BKP3R_Pos (0U)
17478 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
17479 #define RTC_BKP3R RTC_BKP3R_Msk
17480 
17481 /******************** Bits definition for RTC_BKP4R register ****************/
17482 #define RTC_BKP4R_Pos (0U)
17483 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
17484 #define RTC_BKP4R RTC_BKP4R_Msk
17485 
17486 /******************** Bits definition for RTC_BKP5R register ****************/
17487 #define RTC_BKP5R_Pos (0U)
17488 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
17489 #define RTC_BKP5R RTC_BKP5R_Msk
17490 
17491 /******************** Bits definition for RTC_BKP6R register ****************/
17492 #define RTC_BKP6R_Pos (0U)
17493 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
17494 #define RTC_BKP6R RTC_BKP6R_Msk
17495 
17496 /******************** Bits definition for RTC_BKP7R register ****************/
17497 #define RTC_BKP7R_Pos (0U)
17498 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
17499 #define RTC_BKP7R RTC_BKP7R_Msk
17500 
17501 /******************** Bits definition for RTC_BKP8R register ****************/
17502 #define RTC_BKP8R_Pos (0U)
17503 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
17504 #define RTC_BKP8R RTC_BKP8R_Msk
17505 
17506 /******************** Bits definition for RTC_BKP9R register ****************/
17507 #define RTC_BKP9R_Pos (0U)
17508 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
17509 #define RTC_BKP9R RTC_BKP9R_Msk
17510 
17511 /******************** Bits definition for RTC_BKP10R register ***************/
17512 #define RTC_BKP10R_Pos (0U)
17513 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
17514 #define RTC_BKP10R RTC_BKP10R_Msk
17515 
17516 /******************** Bits definition for RTC_BKP11R register ***************/
17517 #define RTC_BKP11R_Pos (0U)
17518 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
17519 #define RTC_BKP11R RTC_BKP11R_Msk
17520 
17521 /******************** Bits definition for RTC_BKP12R register ***************/
17522 #define RTC_BKP12R_Pos (0U)
17523 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
17524 #define RTC_BKP12R RTC_BKP12R_Msk
17525 
17526 /******************** Bits definition for RTC_BKP13R register ***************/
17527 #define RTC_BKP13R_Pos (0U)
17528 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
17529 #define RTC_BKP13R RTC_BKP13R_Msk
17530 
17531 /******************** Bits definition for RTC_BKP14R register ***************/
17532 #define RTC_BKP14R_Pos (0U)
17533 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
17534 #define RTC_BKP14R RTC_BKP14R_Msk
17535 
17536 /******************** Bits definition for RTC_BKP15R register ***************/
17537 #define RTC_BKP15R_Pos (0U)
17538 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
17539 #define RTC_BKP15R RTC_BKP15R_Msk
17540 
17541 /******************** Bits definition for RTC_BKP16R register ***************/
17542 #define RTC_BKP16R_Pos (0U)
17543 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
17544 #define RTC_BKP16R RTC_BKP16R_Msk
17545 
17546 /******************** Bits definition for RTC_BKP17R register ***************/
17547 #define RTC_BKP17R_Pos (0U)
17548 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
17549 #define RTC_BKP17R RTC_BKP17R_Msk
17550 
17551 /******************** Bits definition for RTC_BKP18R register ***************/
17552 #define RTC_BKP18R_Pos (0U)
17553 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
17554 #define RTC_BKP18R RTC_BKP18R_Msk
17555 
17556 /******************** Bits definition for RTC_BKP19R register ***************/
17557 #define RTC_BKP19R_Pos (0U)
17558 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
17559 #define RTC_BKP19R RTC_BKP19R_Msk
17560 
17561 /******************** Bits definition for RTC_BKP20R register ***************/
17562 #define RTC_BKP20R_Pos (0U)
17563 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
17564 #define RTC_BKP20R RTC_BKP20R_Msk
17565 
17566 /******************** Bits definition for RTC_BKP21R register ***************/
17567 #define RTC_BKP21R_Pos (0U)
17568 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
17569 #define RTC_BKP21R RTC_BKP21R_Msk
17570 
17571 /******************** Bits definition for RTC_BKP22R register ***************/
17572 #define RTC_BKP22R_Pos (0U)
17573 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
17574 #define RTC_BKP22R RTC_BKP22R_Msk
17575 
17576 /******************** Bits definition for RTC_BKP23R register ***************/
17577 #define RTC_BKP23R_Pos (0U)
17578 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
17579 #define RTC_BKP23R RTC_BKP23R_Msk
17580 
17581 /******************** Bits definition for RTC_BKP24R register ***************/
17582 #define RTC_BKP24R_Pos (0U)
17583 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
17584 #define RTC_BKP24R RTC_BKP24R_Msk
17585 
17586 /******************** Bits definition for RTC_BKP25R register ***************/
17587 #define RTC_BKP25R_Pos (0U)
17588 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
17589 #define RTC_BKP25R RTC_BKP25R_Msk
17590 
17591 /******************** Bits definition for RTC_BKP26R register ***************/
17592 #define RTC_BKP26R_Pos (0U)
17593 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
17594 #define RTC_BKP26R RTC_BKP26R_Msk
17595 
17596 /******************** Bits definition for RTC_BKP27R register ***************/
17597 #define RTC_BKP27R_Pos (0U)
17598 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
17599 #define RTC_BKP27R RTC_BKP27R_Msk
17600 
17601 /******************** Bits definition for RTC_BKP28R register ***************/
17602 #define RTC_BKP28R_Pos (0U)
17603 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
17604 #define RTC_BKP28R RTC_BKP28R_Msk
17605 
17606 /******************** Bits definition for RTC_BKP29R register ***************/
17607 #define RTC_BKP29R_Pos (0U)
17608 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
17609 #define RTC_BKP29R RTC_BKP29R_Msk
17610 
17611 /******************** Bits definition for RTC_BKP30R register ***************/
17612 #define RTC_BKP30R_Pos (0U)
17613 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
17614 #define RTC_BKP30R RTC_BKP30R_Msk
17615 
17616 /******************** Bits definition for RTC_BKP31R register ***************/
17617 #define RTC_BKP31R_Pos (0U)
17618 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
17619 #define RTC_BKP31R RTC_BKP31R_Msk
17620 
17621 /******************** Number of backup registers ******************************/
17622 #define RTC_BKP_NUMBER_Pos (5U)
17623 #define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos)
17624 #define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
17625 
17626 /******************************************************************************/
17627 /* */
17628 /* SPDIF-RX Interface */
17629 /* */
17630 /******************************************************************************/
17631 /******************** Bit definition for SPDIF_CR register ******************/
17632 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
17633 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
17634 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
17635 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
17636 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
17637 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
17638 #define SPDIFRX_CR_RXSTEO_Pos (3U)
17639 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
17640 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
17641 #define SPDIFRX_CR_DRFMT_Pos (4U)
17642 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
17643 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
17644 #define SPDIFRX_CR_PMSK_Pos (6U)
17645 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
17646 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
17647 #define SPDIFRX_CR_VMSK_Pos (7U)
17648 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
17649 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
17650 #define SPDIFRX_CR_CUMSK_Pos (8U)
17651 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
17652 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
17653 #define SPDIFRX_CR_PTMSK_Pos (9U)
17654 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
17655 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
17656 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
17657 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
17658 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
17659 #define SPDIFRX_CR_CHSEL_Pos (11U)
17660 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
17661 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
17662 #define SPDIFRX_CR_NBTR_Pos (12U)
17663 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
17664 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
17665 #define SPDIFRX_CR_WFA_Pos (14U)
17666 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
17667 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
17668 #define SPDIFRX_CR_INSEL_Pos (16U)
17669 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
17670 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
17671 #define SPDIFRX_CR_CKSEN_Pos (20U)
17672 #define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos)
17673 #define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk
17674 #define SPDIFRX_CR_CKSBKPEN_Pos (21U)
17675 #define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)
17676 #define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk
17678 /******************* Bit definition for SPDIFRX_IMR register *******************/
17679 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
17680 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
17681 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
17682 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
17683 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
17684 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
17685 #define SPDIFRX_IMR_PERRIE_Pos (2U)
17686 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
17687 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
17688 #define SPDIFRX_IMR_OVRIE_Pos (3U)
17689 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
17690 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
17691 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
17692 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
17693 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
17694 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
17695 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
17696 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
17697 #define SPDIFRX_IMR_IFEIE_Pos (6U)
17698 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
17699 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
17701 /******************* Bit definition for SPDIFRX_SR register *******************/
17702 #define SPDIFRX_SR_RXNE_Pos (0U)
17703 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
17704 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
17705 #define SPDIFRX_SR_CSRNE_Pos (1U)
17706 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
17707 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
17708 #define SPDIFRX_SR_PERR_Pos (2U)
17709 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
17710 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
17711 #define SPDIFRX_SR_OVR_Pos (3U)
17712 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
17713 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
17714 #define SPDIFRX_SR_SBD_Pos (4U)
17715 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
17716 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
17717 #define SPDIFRX_SR_SYNCD_Pos (5U)
17718 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
17719 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
17720 #define SPDIFRX_SR_FERR_Pos (6U)
17721 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
17722 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
17723 #define SPDIFRX_SR_SERR_Pos (7U)
17724 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
17725 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
17726 #define SPDIFRX_SR_TERR_Pos (8U)
17727 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
17728 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
17729 #define SPDIFRX_SR_WIDTH5_Pos (16U)
17730 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
17731 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
17733 /******************* Bit definition for SPDIFRX_IFCR register *******************/
17734 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
17735 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
17736 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
17737 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
17738 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
17739 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
17740 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
17741 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
17742 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
17743 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
17744 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
17745 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
17747 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
17748 #define SPDIFRX_DR0_DR_Pos (0U)
17749 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
17750 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
17751 #define SPDIFRX_DR0_PE_Pos (24U)
17752 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
17753 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
17754 #define SPDIFRX_DR0_V_Pos (25U)
17755 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
17756 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
17757 #define SPDIFRX_DR0_U_Pos (26U)
17758 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
17759 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
17760 #define SPDIFRX_DR0_C_Pos (27U)
17761 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
17762 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
17763 #define SPDIFRX_DR0_PT_Pos (28U)
17764 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
17765 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
17767 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
17768 #define SPDIFRX_DR1_DR_Pos (8U)
17769 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
17770 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
17771 #define SPDIFRX_DR1_PT_Pos (4U)
17772 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
17773 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
17774 #define SPDIFRX_DR1_C_Pos (3U)
17775 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
17776 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
17777 #define SPDIFRX_DR1_U_Pos (2U)
17778 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
17779 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
17780 #define SPDIFRX_DR1_V_Pos (1U)
17781 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
17782 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
17783 #define SPDIFRX_DR1_PE_Pos (0U)
17784 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
17785 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
17787 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
17788 #define SPDIFRX_DR1_DRNL1_Pos (16U)
17789 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
17790 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
17791 #define SPDIFRX_DR1_DRNL2_Pos (0U)
17792 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
17793 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
17795 /******************* Bit definition for SPDIFRX_CSR register *******************/
17796 #define SPDIFRX_CSR_USR_Pos (0U)
17797 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
17798 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
17799 #define SPDIFRX_CSR_CS_Pos (16U)
17800 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
17801 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
17802 #define SPDIFRX_CSR_SOB_Pos (24U)
17803 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
17804 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
17806 /******************* Bit definition for SPDIFRX_DIR register *******************/
17807 #define SPDIFRX_DIR_THI_Pos (0U)
17808 #define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos)
17809 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
17810 #define SPDIFRX_DIR_TLO_Pos (16U)
17811 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
17812 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
17814 /******************* Bit definition for SPDIFRX_VERR register *******************/
17815 #define SPDIFRX_VERR_MINREV_Pos (0U)
17816 #define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos)
17817 #define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk
17818 #define SPDIFRX_VERR_MAJREV_Pos (4U)
17819 #define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos)
17820 #define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk
17822 /******************* Bit definition for SPDIFRX_IDR register *******************/
17823 #define SPDIFRX_IDR_ID_Pos (0U)
17824 #define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)
17825 #define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk
17827 /******************* Bit definition for SPDIFRX_SIDR register *******************/
17828 #define SPDIFRX_SIDR_SID_Pos (0U)
17829 #define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)
17830 #define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk
17832 /******************************************************************************/
17833 /* */
17834 /* Serial Audio Interface */
17835 /* */
17836 /******************************************************************************/
17837 /******************************* SAI VERSION ********************************/
17838 #define SAI_VER_V2_1
17839 
17840 /******************** Bit definition for SAI_GCR register *******************/
17841 #define SAI_GCR_SYNCIN_Pos (0U)
17842 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
17843 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
17844 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
17845 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
17847 #define SAI_GCR_SYNCOUT_Pos (4U)
17848 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
17849 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
17850 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
17851 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
17853 /******************* Bit definition for SAI_xCR1 register *******************/
17854 #define SAI_xCR1_MODE_Pos (0U)
17855 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
17856 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
17857 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
17858 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
17860 #define SAI_xCR1_PRTCFG_Pos (2U)
17861 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
17862 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
17863 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
17864 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
17866 #define SAI_xCR1_DS_Pos (5U)
17867 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
17868 #define SAI_xCR1_DS SAI_xCR1_DS_Msk
17869 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
17870 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
17871 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
17873 #define SAI_xCR1_LSBFIRST_Pos (8U)
17874 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
17875 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
17876 #define SAI_xCR1_CKSTR_Pos (9U)
17877 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
17878 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
17880 #define SAI_xCR1_SYNCEN_Pos (10U)
17881 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
17882 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
17883 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
17884 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
17886 #define SAI_xCR1_MONO_Pos (12U)
17887 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
17888 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
17889 #define SAI_xCR1_OUTDRIV_Pos (13U)
17890 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
17891 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
17892 #define SAI_xCR1_SAIEN_Pos (16U)
17893 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
17894 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
17895 #define SAI_xCR1_DMAEN_Pos (17U)
17896 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
17897 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
17898 #define SAI_xCR1_NODIV_Pos (19U)
17899 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
17900 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
17902 #define SAI_xCR1_MCKDIV_Pos (20U)
17903 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)
17904 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
17905 #define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos)
17906 #define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos)
17907 #define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos)
17908 #define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos)
17909 #define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos)
17910 #define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos)
17912 #define SAI_xCR1_MCKEN_Pos (27U)
17913 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)
17914 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk
17916 #define SAI_xCR1_OSR_Pos (26U)
17917 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)
17918 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk
17920 /* Legacy define */
17921 #define SAI_xCR1_NOMCK SAI_xCR1_NODIV
17922 
17923 /******************* Bit definition for SAI_xCR2 register *******************/
17924 #define SAI_xCR2_FTH_Pos (0U)
17925 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
17926 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
17927 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
17928 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
17929 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
17931 #define SAI_xCR2_FFLUSH_Pos (3U)
17932 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
17933 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
17934 #define SAI_xCR2_TRIS_Pos (4U)
17935 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
17936 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
17937 #define SAI_xCR2_MUTE_Pos (5U)
17938 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
17939 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
17940 #define SAI_xCR2_MUTEVAL_Pos (6U)
17941 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
17942 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
17944 #define SAI_xCR2_MUTECNT_Pos (7U)
17945 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
17946 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
17947 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
17948 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
17949 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
17950 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
17951 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
17952 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
17954 #define SAI_xCR2_CPL_Pos (13U)
17955 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
17956 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
17958 #define SAI_xCR2_COMP_Pos (14U)
17959 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
17960 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
17961 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
17962 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
17964 /****************** Bit definition for SAI_xFRCR register *******************/
17965 #define SAI_xFRCR_FRL_Pos (0U)
17966 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
17967 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
17968 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
17969 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
17970 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
17971 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
17972 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
17973 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
17974 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
17975 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
17977 #define SAI_xFRCR_FSALL_Pos (8U)
17978 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
17979 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
17980 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
17981 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
17982 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
17983 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
17984 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
17985 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
17986 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
17988 #define SAI_xFRCR_FSDEF_Pos (16U)
17989 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
17990 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
17991 #define SAI_xFRCR_FSPOL_Pos (17U)
17992 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
17993 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
17994 #define SAI_xFRCR_FSOFF_Pos (18U)
17995 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
17996 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
17998 /* Legacy define */
17999 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
18000 
18001 /****************** Bit definition for SAI_xSLOTR register *******************/
18002 #define SAI_xSLOTR_FBOFF_Pos (0U)
18003 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
18004 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
18005 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
18006 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
18007 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
18008 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
18009 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
18011 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
18012 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
18013 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
18014 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
18015 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
18017 #define SAI_xSLOTR_NBSLOT_Pos (8U)
18018 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
18019 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
18020 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
18021 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
18022 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
18023 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
18025 #define SAI_xSLOTR_SLOTEN_Pos (16U)
18026 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
18027 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
18029 /******************* Bit definition for SAI_xIMR register *******************/
18030 #define SAI_xIMR_OVRUDRIE_Pos (0U)
18031 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
18032 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
18033 #define SAI_xIMR_MUTEDETIE_Pos (1U)
18034 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
18035 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
18036 #define SAI_xIMR_WCKCFGIE_Pos (2U)
18037 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
18038 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
18039 #define SAI_xIMR_FREQIE_Pos (3U)
18040 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
18041 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
18042 #define SAI_xIMR_CNRDYIE_Pos (4U)
18043 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
18044 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
18045 #define SAI_xIMR_AFSDETIE_Pos (5U)
18046 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
18047 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
18048 #define SAI_xIMR_LFSDETIE_Pos (6U)
18049 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
18050 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
18052 /******************** Bit definition for SAI_xSR register *******************/
18053 #define SAI_xSR_OVRUDR_Pos (0U)
18054 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
18055 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
18056 #define SAI_xSR_MUTEDET_Pos (1U)
18057 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
18058 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
18059 #define SAI_xSR_WCKCFG_Pos (2U)
18060 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
18061 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
18062 #define SAI_xSR_FREQ_Pos (3U)
18063 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
18064 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
18065 #define SAI_xSR_CNRDY_Pos (4U)
18066 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
18067 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
18068 #define SAI_xSR_AFSDET_Pos (5U)
18069 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
18070 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
18071 #define SAI_xSR_LFSDET_Pos (6U)
18072 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
18073 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
18075 #define SAI_xSR_FLVL_Pos (16U)
18076 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
18077 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
18078 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
18079 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
18080 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
18082 /****************** Bit definition for SAI_xCLRFR register ******************/
18083 #define SAI_xCLRFR_COVRUDR_Pos (0U)
18084 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
18085 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
18086 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
18087 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
18088 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
18089 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
18090 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
18091 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
18092 #define SAI_xCLRFR_CFREQ_Pos (3U)
18093 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
18094 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
18095 #define SAI_xCLRFR_CCNRDY_Pos (4U)
18096 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
18097 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
18098 #define SAI_xCLRFR_CAFSDET_Pos (5U)
18099 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
18100 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
18101 #define SAI_xCLRFR_CLFSDET_Pos (6U)
18102 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
18103 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
18105 /****************** Bit definition for SAI_xDR register *********************/
18106 #define SAI_xDR_DATA_Pos (0U)
18107 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
18108 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
18109 
18110 /******************* Bit definition for SAI_PDMCR register ******************/
18111 #define SAI_PDMCR_PDMEN_Pos (0U)
18112 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)
18113 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk
18115 #define SAI_PDMCR_MICNBR_Pos (4U)
18116 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)
18117 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk
18118 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)
18119 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)
18121 #define SAI_PDMCR_CKEN1_Pos (8U)
18122 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)
18123 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk
18124 #define SAI_PDMCR_CKEN2_Pos (9U)
18125 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)
18126 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk
18127 #define SAI_PDMCR_CKEN3_Pos (10U)
18128 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)
18129 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk
18130 #define SAI_PDMCR_CKEN4_Pos (11U)
18131 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)
18132 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk
18134 /****************** Bit definition for SAI_PDMDLY register ******************/
18135 #define SAI_PDMDLY_DLYM1L_Pos (0U)
18136 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)
18137 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk
18138 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)
18139 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)
18140 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)
18142 #define SAI_PDMDLY_DLYM1R_Pos (4U)
18143 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)
18144 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk
18145 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)
18146 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)
18147 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)
18149 #define SAI_PDMDLY_DLYM2L_Pos (8U)
18150 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)
18151 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk
18152 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)
18153 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)
18154 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)
18156 #define SAI_PDMDLY_DLYM2R_Pos (12U)
18157 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)
18158 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk
18159 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)
18160 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)
18161 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)
18163 #define SAI_PDMDLY_DLYM3L_Pos (16U)
18164 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)
18165 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk
18166 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)
18167 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)
18168 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)
18170 #define SAI_PDMDLY_DLYM3R_Pos (20U)
18171 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)
18172 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk
18173 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)
18174 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)
18175 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)
18177 #define SAI_PDMDLY_DLYM4L_Pos (24U)
18178 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)
18179 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk
18180 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)
18181 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)
18182 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)
18184 #define SAI_PDMDLY_DLYM4R_Pos (28U)
18185 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)
18186 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk
18187 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)
18188 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)
18189 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)
18191 /******************************************************************************/
18192 /* */
18193 /* SDMMC Interface */
18194 /* */
18195 /******************************************************************************/
18196 /****************** Bit definition for SDMMC_POWER register ******************/
18197 #define SDMMC_POWER_PWRCTRL_Pos (0U)
18198 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
18199 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
18200 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
18201 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
18202 #define SDMMC_POWER_VSWITCH_Pos (2U)
18203 #define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos)
18204 #define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk
18205 #define SDMMC_POWER_VSWITCHEN_Pos (3U)
18206 #define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)
18207 #define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk
18208 #define SDMMC_POWER_DIRPOL_Pos (4U)
18209 #define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos)
18210 #define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk
18212 /****************** Bit definition for SDMMC_CLKCR register ******************/
18213 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
18214 #define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)
18215 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
18216 #define SDMMC_CLKCR_PWRSAV_Pos (12U)
18217 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
18218 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
18220 #define SDMMC_CLKCR_WIDBUS_Pos (14U)
18221 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
18222 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
18223 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
18224 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
18226 #define SDMMC_CLKCR_NEGEDGE_Pos (16U)
18227 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
18228 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
18229 #define SDMMC_CLKCR_HWFC_EN_Pos (17U)
18230 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
18231 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
18232 #define SDMMC_CLKCR_DDR_Pos (18U)
18233 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos)
18234 #define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk
18235 #define SDMMC_CLKCR_BUSSPEED_Pos (19U)
18236 #define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)
18237 #define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk
18238 #define SDMMC_CLKCR_SELCLKRX_Pos (20U)
18239 #define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)
18240 #define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk
18241 #define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)
18242 #define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)
18244 /******************* Bit definition for SDMMC_ARG register *******************/
18245 #define SDMMC_ARG_CMDARG_Pos (0U)
18246 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
18247 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
18249 /******************* Bit definition for SDMMC_CMD register *******************/
18250 #define SDMMC_CMD_CMDINDEX_Pos (0U)
18251 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
18252 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
18253 #define SDMMC_CMD_CMDTRANS_Pos (6U)
18254 #define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos)
18255 #define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk
18256 #define SDMMC_CMD_CMDSTOP_Pos (7U)
18257 #define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos)
18258 #define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk
18260 #define SDMMC_CMD_WAITRESP_Pos (8U)
18261 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
18262 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
18263 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
18264 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
18266 #define SDMMC_CMD_WAITINT_Pos (10U)
18267 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
18268 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
18269 #define SDMMC_CMD_WAITPEND_Pos (11U)
18270 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
18271 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
18272 #define SDMMC_CMD_CPSMEN_Pos (12U)
18273 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
18274 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
18275 #define SDMMC_CMD_DTHOLD_Pos (13U)
18276 #define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos)
18277 #define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk
18278 #define SDMMC_CMD_BOOTMODE_Pos (14U)
18279 #define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos)
18280 #define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk
18281 #define SDMMC_CMD_BOOTEN_Pos (15U)
18282 #define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos)
18283 #define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk
18284 #define SDMMC_CMD_CMDSUSPEND_Pos (16U)
18285 #define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)
18286 #define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk
18288 /***************** Bit definition for SDMMC_RESPCMD register *****************/
18289 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
18290 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
18291 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
18293 /****************** Bit definition for SDMMC_RESP0 register ******************/
18294 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
18295 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
18296 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
18298 /****************** Bit definition for SDMMC_RESP1 register ******************/
18299 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
18300 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
18301 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
18303 /****************** Bit definition for SDMMC_RESP2 register ******************/
18304 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
18305 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
18306 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
18308 /****************** Bit definition for SDMMC_RESP3 register ******************/
18309 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
18310 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
18311 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
18313 /****************** Bit definition for SDMMC_RESP4 register ******************/
18314 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
18315 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
18316 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
18318 /****************** Bit definition for SDMMC_DTIMER register *****************/
18319 #define SDMMC_DTIMER_DATATIME_Pos (0U)
18320 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
18321 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
18323 /****************** Bit definition for SDMMC_DLEN register *******************/
18324 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
18325 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
18326 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
18328 /****************** Bit definition for SDMMC_DCTRL register ******************/
18329 #define SDMMC_DCTRL_DTEN_Pos (0U)
18330 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
18331 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
18332 #define SDMMC_DCTRL_DTDIR_Pos (1U)
18333 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
18334 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
18335 #define SDMMC_DCTRL_DTMODE_Pos (2U)
18336 #define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos)
18337 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
18338 #define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
18339 #define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos)
18341 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
18342 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18343 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
18344 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18345 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18346 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18347 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18349 #define SDMMC_DCTRL_RWSTART_Pos (8U)
18350 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
18351 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
18352 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
18353 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
18354 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
18355 #define SDMMC_DCTRL_RWMOD_Pos (10U)
18356 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
18357 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
18358 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
18359 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
18360 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
18361 #define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
18362 #define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)
18363 #define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk
18364 #define SDMMC_DCTRL_FIFORST_Pos (13U)
18365 #define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos)
18366 #define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk
18368 /****************** Bit definition for SDMMC_DCOUNT register *****************/
18369 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
18370 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
18371 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
18373 /****************** Bit definition for SDMMC_STA register ********************/
18374 #define SDMMC_STA_CCRCFAIL_Pos (0U)
18375 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
18376 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
18377 #define SDMMC_STA_DCRCFAIL_Pos (1U)
18378 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
18379 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
18380 #define SDMMC_STA_CTIMEOUT_Pos (2U)
18381 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
18382 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
18383 #define SDMMC_STA_DTIMEOUT_Pos (3U)
18384 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
18385 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
18386 #define SDMMC_STA_TXUNDERR_Pos (4U)
18387 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
18388 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
18389 #define SDMMC_STA_RXOVERR_Pos (5U)
18390 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
18391 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
18392 #define SDMMC_STA_CMDREND_Pos (6U)
18393 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
18394 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
18395 #define SDMMC_STA_CMDSENT_Pos (7U)
18396 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
18397 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
18398 #define SDMMC_STA_DATAEND_Pos (8U)
18399 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
18400 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
18401 #define SDMMC_STA_DHOLD_Pos (9U)
18402 #define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos)
18403 #define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk
18404 #define SDMMC_STA_DBCKEND_Pos (10U)
18405 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
18406 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
18407 #define SDMMC_STA_DABORT_Pos (11U)
18408 #define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos)
18409 #define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk
18410 #define SDMMC_STA_DPSMACT_Pos (12U)
18411 #define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos)
18412 #define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk
18413 #define SDMMC_STA_CPSMACT_Pos (13U)
18414 #define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos)
18415 #define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk
18416 #define SDMMC_STA_TXFIFOHE_Pos (14U)
18417 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
18418 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
18419 #define SDMMC_STA_RXFIFOHF_Pos (15U)
18420 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
18421 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
18422 #define SDMMC_STA_TXFIFOF_Pos (16U)
18423 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
18424 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
18425 #define SDMMC_STA_RXFIFOF_Pos (17U)
18426 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
18427 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
18428 #define SDMMC_STA_TXFIFOE_Pos (18U)
18429 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
18430 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
18431 #define SDMMC_STA_RXFIFOE_Pos (19U)
18432 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
18433 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
18434 #define SDMMC_STA_BUSYD0_Pos (20U)
18435 #define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos)
18436 #define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk
18437 #define SDMMC_STA_BUSYD0END_Pos (21U)
18438 #define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos)
18439 #define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk
18440 #define SDMMC_STA_SDIOIT_Pos (22U)
18441 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
18442 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
18443 #define SDMMC_STA_ACKFAIL_Pos (23U)
18444 #define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos)
18445 #define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk
18446 #define SDMMC_STA_ACKTIMEOUT_Pos (24U)
18447 #define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)
18448 #define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk
18449 #define SDMMC_STA_VSWEND_Pos (25U)
18450 #define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos)
18451 #define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk
18452 #define SDMMC_STA_CKSTOP_Pos (26U)
18453 #define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos)
18454 #define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk
18455 #define SDMMC_STA_IDMATE_Pos (27U)
18456 #define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos)
18457 #define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk
18458 #define SDMMC_STA_IDMABTC_Pos (28U)
18459 #define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos)
18460 #define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk
18462 /******************* Bit definition for SDMMC_ICR register *******************/
18463 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
18464 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
18465 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
18466 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
18467 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
18468 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
18469 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
18470 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
18471 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
18472 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
18473 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
18474 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
18475 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
18476 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
18477 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
18478 #define SDMMC_ICR_RXOVERRC_Pos (5U)
18479 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
18480 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
18481 #define SDMMC_ICR_CMDRENDC_Pos (6U)
18482 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
18483 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
18484 #define SDMMC_ICR_CMDSENTC_Pos (7U)
18485 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
18486 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
18487 #define SDMMC_ICR_DATAENDC_Pos (8U)
18488 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
18489 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
18490 #define SDMMC_ICR_DHOLDC_Pos (9U)
18491 #define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos)
18492 #define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk
18493 #define SDMMC_ICR_DBCKENDC_Pos (10U)
18494 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
18495 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
18496 #define SDMMC_ICR_DABORTC_Pos (11U)
18497 #define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos)
18498 #define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk
18499 #define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
18500 #define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)
18501 #define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk
18502 #define SDMMC_ICR_SDIOITC_Pos (22U)
18503 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
18504 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
18505 #define SDMMC_ICR_ACKFAILC_Pos (23U)
18506 #define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos)
18507 #define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk
18508 #define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
18509 #define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)
18510 #define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk
18511 #define SDMMC_ICR_VSWENDC_Pos (25U)
18512 #define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos)
18513 #define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk
18514 #define SDMMC_ICR_CKSTOPC_Pos (26U)
18515 #define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos)
18516 #define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk
18517 #define SDMMC_ICR_IDMATEC_Pos (27U)
18518 #define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos)
18519 #define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk
18520 #define SDMMC_ICR_IDMABTCC_Pos (28U)
18521 #define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos)
18522 #define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk
18524 /****************** Bit definition for SDMMC_MASK register *******************/
18525 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
18526 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
18527 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
18528 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
18529 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
18530 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
18531 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
18532 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
18533 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
18534 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
18535 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
18536 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
18537 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
18538 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
18539 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
18540 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
18541 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
18542 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
18543 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
18544 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
18545 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
18546 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
18547 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
18548 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
18549 #define SDMMC_MASK_DATAENDIE_Pos (8U)
18550 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
18551 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
18552 #define SDMMC_MASK_DHOLDIE_Pos (9U)
18553 #define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos)
18554 #define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk
18555 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
18556 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
18557 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
18558 #define SDMMC_MASK_DABORTIE_Pos (11U)
18559 #define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos)
18560 #define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk
18562 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
18563 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
18564 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
18565 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
18566 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
18567 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
18569 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
18570 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
18571 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
18572 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
18573 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
18574 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
18576 #define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
18577 #define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)
18578 #define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk
18579 #define SDMMC_MASK_SDIOITIE_Pos (22U)
18580 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
18581 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
18582 #define SDMMC_MASK_ACKFAILIE_Pos (23U)
18583 #define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)
18584 #define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk
18585 #define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
18586 #define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)
18587 #define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk
18588 #define SDMMC_MASK_VSWENDIE_Pos (25U)
18589 #define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos)
18590 #define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk
18591 #define SDMMC_MASK_CKSTOPIE_Pos (26U)
18592 #define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)
18593 #define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk
18594 #define SDMMC_MASK_IDMABTCIE_Pos (28U)
18595 #define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)
18596 #define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk
18598 /***************** Bit definition for SDMMC_ACKTIME register *****************/
18599 #define SDMMC_ACKTIME_ACKTIME_Pos (0U)
18600 #define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)
18601 #define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk
18603 /****************** Bit definition for SDMMC_FIFO register *******************/
18604 #define SDMMC_FIFO_FIFODATA_Pos (0U)
18605 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
18606 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
18608 /****************** Bit definition for SDMMC_IDMACTRL register ****************/
18609 #define SDMMC_IDMA_IDMAEN_Pos (0U)
18610 #define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos)
18611 #define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk
18612 #define SDMMC_IDMA_IDMABMODE_Pos (1U)
18613 #define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)
18614 #define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk
18615 #define SDMMC_IDMA_IDMABACT_Pos (2U)
18616 #define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos)
18617 #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk
18619 /***************** Bit definition for SDMMC_IDMABSIZE register ***************/
18620 #define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
18621 #define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos)
18622 #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk
18624 /***************** Bit definition for SDMMC_IDMABASE0 register ***************/
18625 #define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF)
18627 /***************** Bit definition for SDMMC_IDMABASE1 register ***************/
18628 #define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF)
18630 /******************************************************************************/
18631 /* */
18632 /* Delay Block Interface (DLYB) */
18633 /* */
18634 /******************************************************************************/
18635 /******************* Bit definition for DLYB_CR register ********************/
18636 #define DLYB_CR_DEN_Pos (0U)
18637 #define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos)
18638 #define DLYB_CR_DEN DLYB_CR_DEN_Msk
18639 #define DLYB_CR_SEN_Pos (1U)
18640 #define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos)
18641 #define DLYB_CR_SEN DLYB_CR_SEN_Msk
18644 /******************* Bit definition for DLYB_CFGR register ********************/
18645 #define DLYB_CFGR_SEL_Pos (0U)
18646 #define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos)
18647 #define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk
18648 #define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos)
18649 #define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos)
18650 #define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos)
18651 #define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos)
18653 #define DLYB_CFGR_UNIT_Pos (8U)
18654 #define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos)
18655 #define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk
18656 #define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos)
18657 #define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos)
18658 #define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos)
18659 #define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos)
18660 #define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos)
18661 #define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos)
18662 #define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos)
18664 #define DLYB_CFGR_LNG_Pos (16U)
18665 #define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos)
18666 #define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk
18667 #define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos)
18668 #define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos)
18669 #define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos)
18670 #define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos)
18671 #define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos)
18672 #define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos)
18673 #define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos)
18674 #define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos)
18675 #define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos)
18676 #define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos)
18677 #define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos)
18678 #define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos)
18680 #define DLYB_CFGR_LNGF_Pos (31U)
18681 #define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos)
18682 #define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk
18684 /******************************************************************************/
18685 /* */
18686 /* Serial Peripheral Interface (SPI/I2S) */
18687 /* */
18688 /******************************************************************************/
18689 /******************* Bit definition for SPI_CR1 register ********************/
18690 #define SPI_CR1_SPE_Pos (0U)
18691 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
18692 #define SPI_CR1_SPE SPI_CR1_SPE_Msk
18693 #define SPI_CR1_MASRX_Pos (8U)
18694 #define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos)
18695 #define SPI_CR1_MASRX SPI_CR1_MASRX_Msk
18696 #define SPI_CR1_CSTART_Pos (9U)
18697 #define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos)
18698 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk
18699 #define SPI_CR1_CSUSP_Pos (10U)
18700 #define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos)
18701 #define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk
18702 #define SPI_CR1_HDDIR_Pos (11U)
18703 #define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos)
18704 #define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk
18705 #define SPI_CR1_SSI_Pos (12U)
18706 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
18707 #define SPI_CR1_SSI SPI_CR1_SSI_Msk
18708 #define SPI_CR1_CRC33_17_Pos (13U)
18709 #define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos)
18710 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk
18711 #define SPI_CR1_RCRCINI_Pos (14U)
18712 #define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos)
18713 #define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk
18714 #define SPI_CR1_TCRCINI_Pos (15U)
18715 #define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos)
18716 #define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk
18717 #define SPI_CR1_IOLOCK_Pos (16U)
18718 #define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos)
18719 #define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk
18721 /******************* Bit definition for SPI_CR2 register ********************/
18722 #define SPI_CR2_TSER_Pos (16U)
18723 #define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos)
18724 #define SPI_CR2_TSER SPI_CR2_TSER_Msk
18725 #define SPI_CR2_TSIZE_Pos (0U)
18726 #define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos)
18727 #define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk
18729 /******************* Bit definition for SPI_CFG1 register ********************/
18730 #define SPI_CFG1_DSIZE_Pos (0U)
18731 #define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos)
18732 #define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk
18733 #define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos)
18734 #define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos)
18735 #define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos)
18736 #define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos)
18737 #define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos)
18739 #define SPI_CFG1_FTHLV_Pos (5U)
18740 #define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos)
18741 #define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk
18742 #define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos)
18743 #define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos)
18744 #define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos)
18745 #define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos)
18747 #define SPI_CFG1_UDRCFG_Pos (9U)
18748 #define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos)
18749 #define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk
18750 #define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos)
18751 #define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos)
18754 #define SPI_CFG1_UDRDET_Pos (11U)
18755 #define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos)
18756 #define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk
18757 #define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos)
18758 #define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos)
18760 #define SPI_CFG1_RXDMAEN_Pos (14U)
18761 #define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos)
18762 #define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk
18763 #define SPI_CFG1_TXDMAEN_Pos (15U)
18764 #define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos)
18765 #define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk
18767 #define SPI_CFG1_CRCSIZE_Pos (16U)
18768 #define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos)
18769 #define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk
18770 #define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos)
18771 #define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos)
18772 #define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos)
18773 #define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos)
18774 #define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos)
18776 #define SPI_CFG1_CRCEN_Pos (22U)
18777 #define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos)
18778 #define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk
18780 #define SPI_CFG1_MBR_Pos (28U)
18781 #define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos)
18782 #define SPI_CFG1_MBR SPI_CFG1_MBR_Msk
18783 #define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos)
18784 #define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos)
18785 #define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos)
18787 /******************* Bit definition for SPI_CFG2 register ********************/
18788 #define SPI_CFG2_MSSI_Pos (0U)
18789 #define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos)
18790 #define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk
18791 #define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos)
18792 #define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos)
18793 #define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos)
18794 #define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos)
18796 #define SPI_CFG2_MIDI_Pos (4U)
18797 #define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos)
18798 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk
18799 #define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos)
18800 #define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos)
18801 #define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos)
18802 #define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos)
18804 #define SPI_CFG2_IOSWP_Pos (15U)
18805 #define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos)
18806 #define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk
18808 #define SPI_CFG2_COMM_Pos (17U)
18809 #define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos)
18810 #define SPI_CFG2_COMM SPI_CFG2_COMM_Msk
18811 #define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos)
18812 #define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos)
18814 #define SPI_CFG2_SP_Pos (19U)
18815 #define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos)
18816 #define SPI_CFG2_SP SPI_CFG2_SP_Msk
18817 #define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos)
18818 #define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos)
18819 #define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos)
18821 #define SPI_CFG2_MASTER_Pos (22U)
18822 #define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos)
18823 #define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk
18824 #define SPI_CFG2_LSBFRST_Pos (23U)
18825 #define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos)
18826 #define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk
18827 #define SPI_CFG2_CPHA_Pos (24U)
18828 #define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos)
18829 #define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk
18830 #define SPI_CFG2_CPOL_Pos (25U)
18831 #define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos)
18832 #define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk
18833 #define SPI_CFG2_SSM_Pos (26U)
18834 #define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos)
18835 #define SPI_CFG2_SSM SPI_CFG2_SSM_Msk
18837 #define SPI_CFG2_SSIOP_Pos (28U)
18838 #define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos)
18839 #define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk
18840 #define SPI_CFG2_SSOE_Pos (29U)
18841 #define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos)
18842 #define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk
18843 #define SPI_CFG2_SSOM_Pos (30U)
18844 #define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos)
18845 #define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk
18847 #define SPI_CFG2_AFCNTR_Pos (31U)
18848 #define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos)
18849 #define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk
18851 /******************* Bit definition for SPI_IER register ********************/
18852 #define SPI_IER_RXPIE_Pos (0U)
18853 #define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos)
18854 #define SPI_IER_RXPIE SPI_IER_RXPIE_Msk
18855 #define SPI_IER_TXPIE_Pos (1U)
18856 #define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos)
18857 #define SPI_IER_TXPIE SPI_IER_TXPIE_Msk
18858 #define SPI_IER_DXPIE_Pos (2U)
18859 #define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos)
18860 #define SPI_IER_DXPIE SPI_IER_DXPIE_Msk
18861 #define SPI_IER_EOTIE_Pos (3U)
18862 #define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos)
18863 #define SPI_IER_EOTIE SPI_IER_EOTIE_Msk
18864 #define SPI_IER_TXTFIE_Pos (4U)
18865 #define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos)
18866 #define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk
18867 #define SPI_IER_UDRIE_Pos (5U)
18868 #define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos)
18869 #define SPI_IER_UDRIE SPI_IER_UDRIE_Msk
18870 #define SPI_IER_OVRIE_Pos (6U)
18871 #define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos)
18872 #define SPI_IER_OVRIE SPI_IER_OVRIE_Msk
18873 #define SPI_IER_CRCEIE_Pos (7U)
18874 #define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos)
18875 #define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk
18876 #define SPI_IER_TIFREIE_Pos (8U)
18877 #define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos)
18878 #define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk
18879 #define SPI_IER_MODFIE_Pos (9U)
18880 #define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos)
18881 #define SPI_IER_MODFIE SPI_IER_MODFIE_Msk
18882 #define SPI_IER_TSERFIE_Pos (10U)
18883 #define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos)
18884 #define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk
18886 /******************* Bit definition for SPI_SR register ********************/
18887 #define SPI_SR_RXP_Pos (0U)
18888 #define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos)
18889 #define SPI_SR_RXP SPI_SR_RXP_Msk
18890 #define SPI_SR_TXP_Pos (1U)
18891 #define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos)
18892 #define SPI_SR_TXP SPI_SR_TXP_Msk
18893 #define SPI_SR_DXP_Pos (2U)
18894 #define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos)
18895 #define SPI_SR_DXP SPI_SR_DXP_Msk
18896 #define SPI_SR_EOT_Pos (3U)
18897 #define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos)
18898 #define SPI_SR_EOT SPI_SR_EOT_Msk
18899 #define SPI_SR_TXTF_Pos (4U)
18900 #define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos)
18901 #define SPI_SR_TXTF SPI_SR_TXTF_Msk
18902 #define SPI_SR_UDR_Pos (5U)
18903 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
18904 #define SPI_SR_UDR SPI_SR_UDR_Msk
18905 #define SPI_SR_OVR_Pos (6U)
18906 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
18907 #define SPI_SR_OVR SPI_SR_OVR_Msk
18908 #define SPI_SR_CRCE_Pos (7U)
18909 #define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos)
18910 #define SPI_SR_CRCE SPI_SR_CRCE_Msk
18911 #define SPI_SR_TIFRE_Pos (8U)
18912 #define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos)
18913 #define SPI_SR_TIFRE SPI_SR_TIFRE_Msk
18914 #define SPI_SR_MODF_Pos (9U)
18915 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
18916 #define SPI_SR_MODF SPI_SR_MODF_Msk
18917 #define SPI_SR_TSERF_Pos (10U)
18918 #define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos)
18919 #define SPI_SR_TSERF SPI_SR_TSERF_Msk
18920 #define SPI_SR_SUSP_Pos (11U)
18921 #define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos)
18922 #define SPI_SR_SUSP SPI_SR_SUSP_Msk
18923 #define SPI_SR_TXC_Pos (12U)
18924 #define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos)
18925 #define SPI_SR_TXC SPI_SR_TXC_Msk
18926 #define SPI_SR_RXPLVL_Pos (13U)
18927 #define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos)
18928 #define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk
18929 #define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos)
18930 #define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos)
18931 #define SPI_SR_RXWNE_Pos (15U)
18932 #define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos)
18933 #define SPI_SR_RXWNE SPI_SR_RXWNE_Msk
18934 #define SPI_SR_CTSIZE_Pos (16U)
18935 #define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos)
18936 #define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk
18938 /******************* Bit definition for SPI_IFCR register ********************/
18939 #define SPI_IFCR_EOTC_Pos (3U)
18940 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos)
18941 #define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk
18942 #define SPI_IFCR_TXTFC_Pos (4U)
18943 #define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos)
18944 #define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk
18945 #define SPI_IFCR_UDRC_Pos (5U)
18946 #define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos)
18947 #define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk
18948 #define SPI_IFCR_OVRC_Pos (6U)
18949 #define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos)
18950 #define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk
18951 #define SPI_IFCR_CRCEC_Pos (7U)
18952 #define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos)
18953 #define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk
18954 #define SPI_IFCR_TIFREC_Pos (8U)
18955 #define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos)
18956 #define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk
18957 #define SPI_IFCR_MODFC_Pos (9U)
18958 #define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos)
18959 #define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk
18960 #define SPI_IFCR_TSERFC_Pos (10U)
18961 #define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos)
18962 #define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk
18963 #define SPI_IFCR_SUSPC_Pos (11U)
18964 #define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos)
18965 #define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk
18967 /******************* Bit definition for SPI_TXDR register ********************/
18968 #define SPI_TXDR_TXDR_Pos (0U)
18969 #define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)
18970 #define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
18971 
18972 /******************* Bit definition for SPI_RXDR register ********************/
18973 #define SPI_RXDR_RXDR_Pos (0U)
18974 #define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)
18975 #define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
18976 
18977 /******************* Bit definition for SPI_CRCPOLY register ********************/
18978 #define SPI_CRCPOLY_CRCPOLY_Pos (0U)
18979 #define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)
18980 #define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
18981 
18982 /******************* Bit definition for SPI_TXCRC register ********************/
18983 #define SPI_TXCRC_TXCRC_Pos (0U)
18984 #define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)
18985 #define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
18986 
18987 /******************* Bit definition for SPI_RXCRC register ********************/
18988 #define SPI_RXCRC_RXCRC_Pos (0U)
18989 #define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)
18990 #define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
18991 
18992 /******************* Bit definition for SPI_UDRDR register ********************/
18993 #define SPI_UDRDR_UDRDR_Pos (0U)
18994 #define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)
18995 #define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
18996 
18997 /****************** Bit definition for SPI_I2SCFGR register *****************/
18998 #define SPI_I2SCFGR_I2SMOD_Pos (0U)
18999 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
19000 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
19001 #define SPI_I2SCFGR_I2SCFG_Pos (1U)
19002 #define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)
19003 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
19004 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
19005 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
19006 #define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)
19007 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
19008 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
19009 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
19010 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
19011 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
19012 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
19013 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
19014 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
19015 #define SPI_I2SCFGR_DATLEN_Pos (8U)
19016 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
19017 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
19018 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
19019 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
19020 #define SPI_I2SCFGR_CHLEN_Pos (10U)
19021 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
19022 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
19023 #define SPI_I2SCFGR_CKPOL_Pos (11U)
19024 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
19025 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
19026 #define SPI_I2SCFGR_FIXCH_Pos (12U)
19027 #define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos)
19028 #define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk
19029 #define SPI_I2SCFGR_WSINV_Pos (13U)
19030 #define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos)
19031 #define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk
19032 #define SPI_I2SCFGR_DATFMT_Pos (14U)
19033 #define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos)
19034 #define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk
19035 #define SPI_I2SCFGR_I2SDIV_Pos (16U)
19036 #define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)
19037 #define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk
19038 #define SPI_I2SCFGR_ODD_Pos (24U)
19039 #define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos)
19040 #define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk
19041 #define SPI_I2SCFGR_MCKOE_Pos (25U)
19042 #define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos)
19043 #define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk
19047 /******************************************************************************/
19048 /* */
19049 /* SYSCFG */
19050 /* */
19051 /******************************************************************************/
19052 
19053 /****************** Bit definition for SYSCFG_PMCR register ******************/
19054 #define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
19055 #define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)
19056 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk
19057 #define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
19058 #define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)
19059 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk
19060 #define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
19061 #define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)
19062 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk
19063 #define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
19064 #define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)
19065 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk
19066 #define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
19067 #define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos)
19068 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk
19069 #define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
19070 #define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos)
19071 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk
19072 #define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
19073 #define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos)
19074 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk
19075 #define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
19076 #define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos)
19077 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk
19078 #define SYSCFG_PMCR_BOOSTEN_Pos (8U)
19079 #define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)
19080 #define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk
19082 #define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
19083 #define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos)
19084 #define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk
19086 #define SYSCFG_PMCR_I2C5_FMP_Pos (10U)
19087 #define SYSCFG_PMCR_I2C5_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C5_FMP_Pos)
19088 #define SYSCFG_PMCR_I2C5_FMP SYSCFG_PMCR_I2C5_FMP_Msk
19090 #define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
19091 #define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19092 #define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk
19093 #define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19094 #define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19095 #define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19096 #define SYSCFG_PMCR_PA0SO_Pos (24U)
19097 #define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos)
19098 #define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk
19099 #define SYSCFG_PMCR_PA1SO_Pos (25U)
19100 #define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos)
19101 #define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk
19102 #define SYSCFG_PMCR_PC2SO_Pos (26U)
19103 #define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos)
19104 #define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk
19105 #define SYSCFG_PMCR_PC3SO_Pos (27U)
19106 #define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos)
19107 #define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk
19109 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
19110 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
19111 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
19112 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
19113 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
19114 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
19115 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
19116 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
19117 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
19118 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
19119 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
19120 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
19121 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
19125 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000)
19126 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001)
19127 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002)
19128 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003)
19129 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004)
19130 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005)
19131 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006)
19132 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007)
19133 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009)
19134 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A)
19139 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000)
19140 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010)
19141 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020)
19142 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030)
19143 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040)
19144 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050)
19145 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060)
19146 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070)
19147 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090)
19148 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0)
19152 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000)
19153 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100)
19154 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200)
19155 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300)
19156 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400)
19157 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500)
19158 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600)
19159 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700)
19160 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900)
19161 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00)
19166 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000)
19167 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000)
19168 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000)
19169 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000)
19170 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000)
19171 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000)
19172 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000)
19173 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000)
19174 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000)
19175 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000)
19177 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
19178 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
19179 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
19180 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
19181 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
19182 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
19183 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
19184 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
19185 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
19186 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
19187 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
19188 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
19189 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
19193 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000)
19194 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001)
19195 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002)
19196 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003)
19197 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004)
19198 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005)
19199 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006)
19200 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007)
19201 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009)
19202 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A)
19206 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000)
19207 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010)
19208 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020)
19209 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030)
19210 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040)
19211 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050)
19212 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060)
19213 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070)
19214 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090)
19215 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0)
19219 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000)
19220 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100)
19221 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200)
19222 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300)
19223 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400)
19224 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500)
19225 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600)
19226 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700)
19227 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900)
19228 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00)
19233 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000)
19234 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000)
19235 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000)
19236 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000)
19237 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000)
19238 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000)
19239 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000)
19240 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000)
19241 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000)
19242 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000)
19244 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
19245 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
19246 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
19247 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
19248 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
19249 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
19250 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
19251 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
19252 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
19253 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
19254 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
19255 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
19256 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
19261 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000)
19262 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001)
19263 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002)
19264 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003)
19265 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004)
19266 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005)
19267 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006)
19268 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007)
19269 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009)
19270 #define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A)
19275 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000)
19276 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010)
19277 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020)
19278 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030)
19279 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040)
19280 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050)
19281 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060)
19282 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070)
19283 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090)
19284 #define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0)
19289 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000)
19290 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100)
19291 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200)
19292 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300)
19293 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400)
19294 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500)
19295 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600)
19296 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700)
19297 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900)
19298 #define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00)
19303 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000)
19304 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000)
19305 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000)
19306 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000)
19307 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000)
19308 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000)
19309 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000)
19310 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000)
19311 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000)
19312 #define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000)
19314 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
19315 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
19316 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
19317 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
19318 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
19319 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
19320 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
19321 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
19322 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
19323 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
19324 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
19325 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
19326 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
19330 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000)
19331 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001)
19332 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002)
19333 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003)
19334 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004)
19335 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005)
19336 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006)
19337 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007)
19338 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009)
19339 #define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A)
19343 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000)
19344 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010)
19345 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020)
19346 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030)
19347 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040)
19348 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050)
19349 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060)
19350 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070)
19351 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090)
19352 #define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0)
19356 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000)
19357 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100)
19358 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200)
19359 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300)
19360 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400)
19361 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500)
19362 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600)
19363 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700)
19364 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900)
19365 #define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00)
19369 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000)
19370 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000)
19371 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000)
19372 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000)
19373 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000)
19374 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000)
19375 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000)
19376 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000)
19377 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000)
19378 #define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000)
19380 /****************** Bit definition for SYSCFG_CFGR register ******************/
19381 #define SYSCFG_CFGR_PVDL_Pos (2U)
19382 #define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos)
19383 #define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk
19384 #define SYSCFG_CFGR_FLASHL_Pos (3U)
19385 #define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos)
19386 #define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk
19387 #define SYSCFG_CFGR_CM7L_Pos (6U)
19388 #define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos)
19389 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk
19390 #define SYSCFG_CFGR_BKRAML_Pos (7U)
19391 #define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos)
19392 #define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk
19393 #define SYSCFG_CFGR_SRAM4L_Pos (9U)
19394 #define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)
19395 #define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk
19396 #define SYSCFG_CFGR_SRAM2L_Pos (11U)
19397 #define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)
19398 #define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk
19399 #define SYSCFG_CFGR_SRAM1L_Pos (12U)
19400 #define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)
19401 #define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk
19402 #define SYSCFG_CFGR_DTCML_Pos (13U)
19403 #define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos)
19404 #define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk
19405 #define SYSCFG_CFGR_ITCML_Pos (14U)
19406 #define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos)
19407 #define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk
19408 #define SYSCFG_CFGR_AXISRAML_Pos (15U)
19409 #define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)
19410 #define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk
19412 /****************** Bit definition for SYSCFG_CCCSR register ******************/
19413 #define SYSCFG_CCCSR_EN_Pos (0U)
19414 #define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos)
19415 #define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk
19416 #define SYSCFG_CCCSR_CS_Pos (1U)
19417 #define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos)
19418 #define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk
19419 #define SYSCFG_CCCSR_READY_Pos (8U)
19420 #define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos)
19421 #define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk
19422 #define SYSCFG_CCCSR_HSLV_Pos (16U)
19423 #define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos)
19424 #define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk
19426 /****************** Bit definition for SYSCFG_CCVR register *******************/
19427 #define SYSCFG_CCVR_NCV_Pos (0U)
19428 #define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos)
19429 #define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk
19430 #define SYSCFG_CCVR_PCV_Pos (4U)
19431 #define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos)
19432 #define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk
19434 /****************** Bit definition for SYSCFG_CCCR register *******************/
19435 #define SYSCFG_CCCR_NCC_Pos (0U)
19436 #define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos)
19437 #define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk
19438 #define SYSCFG_CCCR_PCC_Pos (4U)
19439 #define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos)
19440 #define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk
19441 /****************** Bit definition for SYSCFG_ADC2ALT register *******************/
19442 #define SYSCFG_ADC2ALT_ADC2_ROUT0_Pos (0U)
19443 #define SYSCFG_ADC2ALT_ADC2_ROUT0_Msk (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT0_Pos)
19444 #define SYSCFG_ADC2ALT_ADC2_ROUT0 SYSCFG_ADC2ALT_ADC2_ROUT0_Msk
19445 #define SYSCFG_ADC2ALT_ADC2_ROUT1_Pos (1U)
19446 #define SYSCFG_ADC2ALT_ADC2_ROUT1_Msk (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT1_Pos)
19447 #define SYSCFG_ADC2ALT_ADC2_ROUT1 SYSCFG_ADC2ALT_ADC2_ROUT1_Msk
19449 /****************** Bit definition for SYSCFG_PKGR register *******************/
19450 #define SYSCFG_PKGR_PKG_Pos (0U)
19451 #define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos)
19452 #define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk
19454 /****************** Bit definition for SYSCFG_UR0 register *******************/
19455 #define SYSCFG_UR0_RDP_Pos (16U)
19456 #define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos)
19457 #define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk
19459 /****************** Bit definition for SYSCFG_UR2 register *******************/
19460 #define SYSCFG_UR2_BORH_Pos (0U)
19461 #define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos)
19462 #define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk
19463 #define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos)
19464 #define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos)
19465 #define SYSCFG_UR2_BOOT_ADD0_Pos (16U)
19466 #define SYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos)
19467 #define SYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk
19468 /****************** Bit definition for SYSCFG_UR3 register *******************/
19469 #define SYSCFG_UR3_BOOT_ADD1_Pos (0U)
19470 #define SYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos)
19471 #define SYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk
19473  /****************** Bit definition for SYSCFG_UR4 register *******************/
19474 
19475 #define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
19476 #define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)
19477 #define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk
19479 /****************** Bit definition for SYSCFG_UR5 register *******************/
19480 #define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
19481 #define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)
19482 #define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk
19483 #define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
19484 #define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)
19485 #define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk
19487 /****************** Bit definition for SYSCFG_UR6 register *******************/
19488 #define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
19489 #define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos)
19490 #define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk
19491 #define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
19492 #define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos)
19493 #define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk
19495 /****************** Bit definition for SYSCFG_UR7 register *******************/
19496 #define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
19497 #define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos)
19498 #define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk
19499 #define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
19500 #define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos)
19501 #define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk
19504 /****************** Bit definition for SYSCFG_UR11 register *******************/
19505 #define SYSCFG_UR11_IWDG1M_Pos (16U)
19506 #define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos)
19507 #define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk
19509 /****************** Bit definition for SYSCFG_UR12 register *******************/
19510 
19511 #define SYSCFG_UR12_SECURE_Pos (16U)
19512 #define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos)
19513 #define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk
19515 /****************** Bit definition for SYSCFG_UR13 register *******************/
19516 #define SYSCFG_UR13_SDRS_Pos (0U)
19517 #define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos)
19518 #define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk
19519 #define SYSCFG_UR13_D1SBRST_Pos (16U)
19520 #define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos)
19521 #define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk
19523 /****************** Bit definition for SYSCFG_UR14 register *******************/
19524 #define SYSCFG_UR14_D1STPRST_Pos (0U)
19525 #define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos)
19526 #define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk
19528 /****************** Bit definition for SYSCFG_UR15 register *******************/
19529 #define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
19530 #define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)
19531 #define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk
19533 /****************** Bit definition for SYSCFG_UR16 register *******************/
19534 #define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
19535 #define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)
19536 #define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk
19537 #define SYSCFG_UR16_PKP_Pos (16U)
19538 #define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos)
19539 #define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk
19541 /****************** Bit definition for SYSCFG_UR17 register *******************/
19542 #define SYSCFG_UR17_IOHSLV_Pos (0U)
19543 #define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos)
19544 #define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk
19545 #define SYSCFG_UR17_TCM_AXI_CFG_Pos (16U)
19546 #define SYSCFG_UR17_TCM_AXI_CFG_Msk (0x3UL << SYSCFG_UR17_TCM_AXI_CFG_Pos)
19547 #define SYSCFG_UR17_TCM_AXI_CFG SYSCFG_UR17_TCM_AXI_CFG_Msk
19549 /****************** Bit definition for SYSCFG_UR18 register *******************/
19550 #define SYSCFG_UR18_CPU_FREQ_BOOST_Pos (0U)
19551 #define SYSCFG_UR18_CPU_FREQ_BOOST_Msk (0x1UL << SYSCFG_UR18_CPU_FREQ_BOOST_Pos)
19552 #define SYSCFG_UR18_CPU_FREQ_BOOST SYSCFG_UR18_CPU_FREQ_BOOST_Msk
19554 /******************************************************************************/
19555 /* */
19556 /* Digital Temperature Sensor (DTS) */
19557 /* */
19558 /******************************************************************************/
19559 
19560 /****************** Bit definition for DTS_CFGR1 register ******************/
19561 #define DTS_CFGR1_TS1_EN_Pos (0U)
19562 #define DTS_CFGR1_TS1_EN_Msk (0x1UL << DTS_CFGR1_TS1_EN_Pos)
19563 #define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk
19564 #define DTS_CFGR1_TS1_START_Pos (4U)
19565 #define DTS_CFGR1_TS1_START_Msk (0x1UL << DTS_CFGR1_TS1_START_Pos)
19566 #define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk
19567 #define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U)
19568 #define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19569 #define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk
19570 #define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19571 #define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19572 #define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19573 #define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19574 #define DTS_CFGR1_TS1_SMP_TIME_Pos (16U)
19575 #define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19576 #define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk
19577 #define DTS_CFGR1_TS1_SMP_TIME_0 (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19578 #define DTS_CFGR1_TS1_SMP_TIME_1 (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19579 #define DTS_CFGR1_TS1_SMP_TIME_2 (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19580 #define DTS_CFGR1_TS1_SMP_TIME_3 (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19581 #define DTS_CFGR1_REFCLK_SEL_Pos (20U)
19582 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos)
19583 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk
19584 #define DTS_CFGR1_Q_MEAS_OPT_Pos (21U)
19585 #define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos)
19586 #define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk
19587 #define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U)
19588 #define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos)
19589 #define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk
19591 /****************** Bit definition for DTS_T0VALR1 register ******************/
19592 #define DTS_T0VALR1_TS1_FMT0_Pos (0U)
19593 #define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos)
19594 #define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk
19595 #define DTS_T0VALR1_TS1_T0_Pos (16U)
19596 #define DTS_T0VALR1_TS1_T0_Msk (0x3UL << DTS_T0VALR1_TS1_T0_Pos)
19597 #define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk
19599 /****************** Bit definition for DTS_RAMPVALR register ******************/
19600 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U)
19601 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos)
19602 #define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk
19604 /****************** Bit definition for DTS_ITR1 register ******************/
19605 #define DTS_ITR1_TS1_LITTHD_Pos (0U)
19606 #define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos)
19607 #define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk
19608 #define DTS_ITR1_TS1_HITTHD_Pos (16U)
19609 #define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos)
19610 #define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk
19612 /****************** Bit definition for DTS_DR register ******************/
19613 #define DTS_DR_TS1_MFREQ_Pos (0U)
19614 #define DTS_DR_TS1_MFREQ_Msk (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos)
19615 #define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk
19617 /****************** Bit definition for DTS_SR register ******************/
19618 #define DTS_SR_TS1_ITEF_Pos (0U)
19619 #define DTS_SR_TS1_ITEF_Msk (0x1UL << DTS_SR_TS1_ITEF_Pos)
19620 #define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk
19621 #define DTS_SR_TS1_ITLF_Pos (1U)
19622 #define DTS_SR_TS1_ITLF_Msk (0x1UL << DTS_SR_TS1_ITLF_Pos)
19623 #define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk
19624 #define DTS_SR_TS1_ITHF_Pos (2U)
19625 #define DTS_SR_TS1_ITHF_Msk (0x1UL << DTS_SR_TS1_ITHF_Pos)
19626 #define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk
19627 #define DTS_SR_TS1_AITEF_Pos (4U)
19628 #define DTS_SR_TS1_AITEF_Msk (0x1UL << DTS_SR_TS1_AITEF_Pos)
19629 #define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk
19630 #define DTS_SR_TS1_AITLF_Pos (5U)
19631 #define DTS_SR_TS1_AITLF_Msk (0x1UL << DTS_SR_TS1_AITLF_Pos)
19632 #define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk
19633 #define DTS_SR_TS1_AITHF_Pos (6U)
19634 #define DTS_SR_TS1_AITHF_Msk (0x1UL << DTS_SR_TS1_AITHF_Pos)
19635 #define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk
19636 #define DTS_SR_TS1_RDY_Pos (15U)
19637 #define DTS_SR_TS1_RDY_Msk (0x1UL << DTS_SR_TS1_RDY_Pos)
19638 #define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk
19640 /****************** Bit definition for DTS_ITENR register ******************/
19641 #define DTS_ITENR_TS1_ITEEN_Pos (0U)
19642 #define DTS_ITENR_TS1_ITEEN_Msk (0x1UL << DTS_ITENR_TS1_ITEEN_Pos)
19643 #define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk
19644 #define DTS_ITENR_TS1_ITLEN_Pos (1U)
19645 #define DTS_ITENR_TS1_ITLEN_Msk (0x1UL << DTS_ITENR_TS1_ITLEN_Pos)
19646 #define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk
19647 #define DTS_ITENR_TS1_ITHEN_Pos (2U)
19648 #define DTS_ITENR_TS1_ITHEN_Msk (0x1UL << DTS_ITENR_TS1_ITHEN_Pos)
19649 #define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk
19650 #define DTS_ITENR_TS1_AITEEN_Pos (4U)
19651 #define DTS_ITENR_TS1_AITEEN_Msk (0x1UL << DTS_ITENR_TS1_AITEEN_Pos)
19652 #define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk
19653 #define DTS_ITENR_TS1_AITLEN_Pos (5U)
19654 #define DTS_ITENR_TS1_AITLEN_Msk (0x1UL << DTS_ITENR_TS1_AITLEN_Pos)
19655 #define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk
19656 #define DTS_ITENR_TS1_AITHEN_Pos (6U)
19657 #define DTS_ITENR_TS1_AITHEN_Msk (0x1UL << DTS_ITENR_TS1_AITHEN_Pos)
19658 #define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk
19660 /****************** Bit definition for DTS_ICIFR register ******************/
19661 #define DTS_ICIFR_TS1_CITEF_Pos (0U)
19662 #define DTS_ICIFR_TS1_CITEF_Msk (0x1UL << DTS_ICIFR_TS1_CITEF_Pos)
19663 #define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk
19664 #define DTS_ICIFR_TS1_CITLF_Pos (1U)
19665 #define DTS_ICIFR_TS1_CITLF_Msk (0x1UL << DTS_ICIFR_TS1_CITLF_Pos)
19666 #define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk
19667 #define DTS_ICIFR_TS1_CITHF_Pos (2U)
19668 #define DTS_ICIFR_TS1_CITHF_Msk (0x1UL << DTS_ICIFR_TS1_CITHF_Pos)
19669 #define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk
19670 #define DTS_ICIFR_TS1_CAITEF_Pos (4U)
19671 #define DTS_ICIFR_TS1_CAITEF_Msk (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos)
19672 #define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk
19673 #define DTS_ICIFR_TS1_CAITLF_Pos (5U)
19674 #define DTS_ICIFR_TS1_CAITLF_Msk (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos)
19675 #define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk
19676 #define DTS_ICIFR_TS1_CAITHF_Pos (6U)
19677 #define DTS_ICIFR_TS1_CAITHF_Msk (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos)
19678 #define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk
19681 /******************************************************************************/
19682 /* */
19683 /* TIM */
19684 /* */
19685 /******************************************************************************/
19686 #define TIM_BREAK_INPUT_SUPPORT
19688 /******************* Bit definition for TIM_CR1 register ********************/
19689 #define TIM_CR1_CEN_Pos (0U)
19690 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
19691 #define TIM_CR1_CEN TIM_CR1_CEN_Msk
19692 #define TIM_CR1_UDIS_Pos (1U)
19693 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
19694 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
19695 #define TIM_CR1_URS_Pos (2U)
19696 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
19697 #define TIM_CR1_URS TIM_CR1_URS_Msk
19698 #define TIM_CR1_OPM_Pos (3U)
19699 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
19700 #define TIM_CR1_OPM TIM_CR1_OPM_Msk
19701 #define TIM_CR1_DIR_Pos (4U)
19702 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
19703 #define TIM_CR1_DIR TIM_CR1_DIR_Msk
19705 #define TIM_CR1_CMS_Pos (5U)
19706 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
19707 #define TIM_CR1_CMS TIM_CR1_CMS_Msk
19708 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
19709 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
19711 #define TIM_CR1_ARPE_Pos (7U)
19712 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
19713 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
19715 #define TIM_CR1_CKD_Pos (8U)
19716 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
19717 #define TIM_CR1_CKD TIM_CR1_CKD_Msk
19718 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
19719 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
19721 #define TIM_CR1_UIFREMAP_Pos (11U)
19722 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
19723 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
19725 /******************* Bit definition for TIM_CR2 register ********************/
19726 #define TIM_CR2_CCPC_Pos (0U)
19727 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
19728 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
19729 #define TIM_CR2_CCUS_Pos (2U)
19730 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
19731 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
19732 #define TIM_CR2_CCDS_Pos (3U)
19733 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
19734 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
19736 #define TIM_CR2_MMS_Pos (4U)
19737 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
19738 #define TIM_CR2_MMS TIM_CR2_MMS_Msk
19739 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
19740 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
19741 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
19743 #define TIM_CR2_TI1S_Pos (7U)
19744 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
19745 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
19746 #define TIM_CR2_OIS1_Pos (8U)
19747 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
19748 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
19749 #define TIM_CR2_OIS1N_Pos (9U)
19750 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
19751 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
19752 #define TIM_CR2_OIS2_Pos (10U)
19753 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
19754 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
19755 #define TIM_CR2_OIS2N_Pos (11U)
19756 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
19757 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
19758 #define TIM_CR2_OIS3_Pos (12U)
19759 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
19760 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
19761 #define TIM_CR2_OIS3N_Pos (13U)
19762 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
19763 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
19764 #define TIM_CR2_OIS4_Pos (14U)
19765 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
19766 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
19767 #define TIM_CR2_OIS5_Pos (16U)
19768 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
19769 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
19770 #define TIM_CR2_OIS6_Pos (17U)
19771 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
19772 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
19774 #define TIM_CR2_MMS2_Pos (20U)
19775 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
19776 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
19777 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
19778 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
19779 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
19780 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
19782 /******************* Bit definition for TIM_SMCR register *******************/
19783 #define TIM_SMCR_SMS_Pos (0U)
19784 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
19785 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
19786 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
19787 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
19788 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
19789 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
19791 #define TIM_SMCR_TS_Pos (4U)
19792 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)
19793 #define TIM_SMCR_TS TIM_SMCR_TS_Msk
19794 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)
19795 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)
19796 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)
19797 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)
19798 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)
19800 #define TIM_SMCR_MSM_Pos (7U)
19801 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
19802 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
19804 #define TIM_SMCR_ETF_Pos (8U)
19805 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
19806 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
19807 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
19808 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
19809 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
19810 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
19812 #define TIM_SMCR_ETPS_Pos (12U)
19813 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
19814 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
19815 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
19816 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
19818 #define TIM_SMCR_ECE_Pos (14U)
19819 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
19820 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
19821 #define TIM_SMCR_ETP_Pos (15U)
19822 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
19823 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
19825 /******************* Bit definition for TIM_DIER register *******************/
19826 #define TIM_DIER_UIE_Pos (0U)
19827 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
19828 #define TIM_DIER_UIE TIM_DIER_UIE_Msk
19829 #define TIM_DIER_CC1IE_Pos (1U)
19830 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
19831 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
19832 #define TIM_DIER_CC2IE_Pos (2U)
19833 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
19834 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
19835 #define TIM_DIER_CC3IE_Pos (3U)
19836 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
19837 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
19838 #define TIM_DIER_CC4IE_Pos (4U)
19839 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
19840 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
19841 #define TIM_DIER_COMIE_Pos (5U)
19842 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
19843 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
19844 #define TIM_DIER_TIE_Pos (6U)
19845 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
19846 #define TIM_DIER_TIE TIM_DIER_TIE_Msk
19847 #define TIM_DIER_BIE_Pos (7U)
19848 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
19849 #define TIM_DIER_BIE TIM_DIER_BIE_Msk
19850 #define TIM_DIER_UDE_Pos (8U)
19851 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
19852 #define TIM_DIER_UDE TIM_DIER_UDE_Msk
19853 #define TIM_DIER_CC1DE_Pos (9U)
19854 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
19855 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
19856 #define TIM_DIER_CC2DE_Pos (10U)
19857 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
19858 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
19859 #define TIM_DIER_CC3DE_Pos (11U)
19860 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
19861 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
19862 #define TIM_DIER_CC4DE_Pos (12U)
19863 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
19864 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
19865 #define TIM_DIER_COMDE_Pos (13U)
19866 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
19867 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
19868 #define TIM_DIER_TDE_Pos (14U)
19869 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
19870 #define TIM_DIER_TDE TIM_DIER_TDE_Msk
19872 /******************** Bit definition for TIM_SR register ********************/
19873 #define TIM_SR_UIF_Pos (0U)
19874 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
19875 #define TIM_SR_UIF TIM_SR_UIF_Msk
19876 #define TIM_SR_CC1IF_Pos (1U)
19877 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
19878 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
19879 #define TIM_SR_CC2IF_Pos (2U)
19880 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
19881 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
19882 #define TIM_SR_CC3IF_Pos (3U)
19883 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
19884 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
19885 #define TIM_SR_CC4IF_Pos (4U)
19886 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
19887 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
19888 #define TIM_SR_COMIF_Pos (5U)
19889 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
19890 #define TIM_SR_COMIF TIM_SR_COMIF_Msk
19891 #define TIM_SR_TIF_Pos (6U)
19892 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
19893 #define TIM_SR_TIF TIM_SR_TIF_Msk
19894 #define TIM_SR_BIF_Pos (7U)
19895 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
19896 #define TIM_SR_BIF TIM_SR_BIF_Msk
19897 #define TIM_SR_B2IF_Pos (8U)
19898 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
19899 #define TIM_SR_B2IF TIM_SR_B2IF_Msk
19900 #define TIM_SR_CC1OF_Pos (9U)
19901 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
19902 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
19903 #define TIM_SR_CC2OF_Pos (10U)
19904 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
19905 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
19906 #define TIM_SR_CC3OF_Pos (11U)
19907 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
19908 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
19909 #define TIM_SR_CC4OF_Pos (12U)
19910 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
19911 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
19912 #define TIM_SR_CC5IF_Pos (16U)
19913 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
19914 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
19915 #define TIM_SR_CC6IF_Pos (17U)
19916 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
19917 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
19918 #define TIM_SR_SBIF_Pos (13U)
19919 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
19920 #define TIM_SR_SBIF TIM_SR_SBIF_Msk
19922 /******************* Bit definition for TIM_EGR register ********************/
19923 #define TIM_EGR_UG_Pos (0U)
19924 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
19925 #define TIM_EGR_UG TIM_EGR_UG_Msk
19926 #define TIM_EGR_CC1G_Pos (1U)
19927 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
19928 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
19929 #define TIM_EGR_CC2G_Pos (2U)
19930 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
19931 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
19932 #define TIM_EGR_CC3G_Pos (3U)
19933 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
19934 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
19935 #define TIM_EGR_CC4G_Pos (4U)
19936 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
19937 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
19938 #define TIM_EGR_COMG_Pos (5U)
19939 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
19940 #define TIM_EGR_COMG TIM_EGR_COMG_Msk
19941 #define TIM_EGR_TG_Pos (6U)
19942 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
19943 #define TIM_EGR_TG TIM_EGR_TG_Msk
19944 #define TIM_EGR_BG_Pos (7U)
19945 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
19946 #define TIM_EGR_BG TIM_EGR_BG_Msk
19947 #define TIM_EGR_B2G_Pos (8U)
19948 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
19949 #define TIM_EGR_B2G TIM_EGR_B2G_Msk
19952 /****************** Bit definition for TIM_CCMR1 register *******************/
19953 #define TIM_CCMR1_CC1S_Pos (0U)
19954 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
19955 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
19956 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
19957 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
19959 #define TIM_CCMR1_OC1FE_Pos (2U)
19960 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
19961 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
19962 #define TIM_CCMR1_OC1PE_Pos (3U)
19963 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
19964 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
19966 #define TIM_CCMR1_OC1M_Pos (4U)
19967 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
19968 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
19969 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
19970 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
19971 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
19972 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
19974 #define TIM_CCMR1_OC1CE_Pos (7U)
19975 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
19976 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
19978 #define TIM_CCMR1_CC2S_Pos (8U)
19979 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
19980 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
19981 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
19982 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
19984 #define TIM_CCMR1_OC2FE_Pos (10U)
19985 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
19986 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
19987 #define TIM_CCMR1_OC2PE_Pos (11U)
19988 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
19989 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
19991 #define TIM_CCMR1_OC2M_Pos (12U)
19992 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
19993 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
19994 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
19995 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
19996 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
19997 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
19999 #define TIM_CCMR1_OC2CE_Pos (15U)
20000 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
20001 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
20003 /*----------------------------------------------------------------------------*/
20004 
20005 #define TIM_CCMR1_IC1PSC_Pos (2U)
20006 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
20007 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
20008 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
20009 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
20011 #define TIM_CCMR1_IC1F_Pos (4U)
20012 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
20013 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
20014 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
20015 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
20016 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
20017 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
20019 #define TIM_CCMR1_IC2PSC_Pos (10U)
20020 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
20021 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
20022 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
20023 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
20025 #define TIM_CCMR1_IC2F_Pos (12U)
20026 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
20027 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
20028 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
20029 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
20030 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
20031 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
20033 /****************** Bit definition for TIM_CCMR2 register *******************/
20034 #define TIM_CCMR2_CC3S_Pos (0U)
20035 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
20036 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
20037 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
20038 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
20040 #define TIM_CCMR2_OC3FE_Pos (2U)
20041 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
20042 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
20043 #define TIM_CCMR2_OC3PE_Pos (3U)
20044 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
20045 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
20047 #define TIM_CCMR2_OC3M_Pos (4U)
20048 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
20049 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
20050 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
20051 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
20052 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
20053 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
20055 #define TIM_CCMR2_OC3CE_Pos (7U)
20056 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
20057 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
20059 #define TIM_CCMR2_CC4S_Pos (8U)
20060 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
20061 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
20062 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
20063 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
20065 #define TIM_CCMR2_OC4FE_Pos (10U)
20066 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
20067 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
20068 #define TIM_CCMR2_OC4PE_Pos (11U)
20069 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
20070 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
20072 #define TIM_CCMR2_OC4M_Pos (12U)
20073 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
20074 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
20075 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
20076 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
20077 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
20078 #define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos)
20080 #define TIM_CCMR2_OC4CE_Pos (15U)
20081 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
20082 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
20084 /*----------------------------------------------------------------------------*/
20085 
20086 #define TIM_CCMR2_IC3PSC_Pos (2U)
20087 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
20088 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
20089 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
20090 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
20092 #define TIM_CCMR2_IC3F_Pos (4U)
20093 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
20094 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
20095 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
20096 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
20097 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
20098 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
20100 #define TIM_CCMR2_IC4PSC_Pos (10U)
20101 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
20102 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
20103 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
20104 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
20106 #define TIM_CCMR2_IC4F_Pos (12U)
20107 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
20108 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
20109 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
20110 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
20111 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
20112 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
20114 /******************* Bit definition for TIM_CCER register *******************/
20115 #define TIM_CCER_CC1E_Pos (0U)
20116 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
20117 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
20118 #define TIM_CCER_CC1P_Pos (1U)
20119 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
20120 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
20121 #define TIM_CCER_CC1NE_Pos (2U)
20122 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
20123 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
20124 #define TIM_CCER_CC1NP_Pos (3U)
20125 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
20126 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
20127 #define TIM_CCER_CC2E_Pos (4U)
20128 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
20129 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
20130 #define TIM_CCER_CC2P_Pos (5U)
20131 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
20132 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
20133 #define TIM_CCER_CC2NE_Pos (6U)
20134 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
20135 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
20136 #define TIM_CCER_CC2NP_Pos (7U)
20137 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
20138 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
20139 #define TIM_CCER_CC3E_Pos (8U)
20140 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
20141 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
20142 #define TIM_CCER_CC3P_Pos (9U)
20143 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
20144 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
20145 #define TIM_CCER_CC3NE_Pos (10U)
20146 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
20147 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
20148 #define TIM_CCER_CC3NP_Pos (11U)
20149 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
20150 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
20151 #define TIM_CCER_CC4E_Pos (12U)
20152 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
20153 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
20154 #define TIM_CCER_CC4P_Pos (13U)
20155 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
20156 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
20157 #define TIM_CCER_CC4NP_Pos (15U)
20158 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
20159 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
20160 #define TIM_CCER_CC5E_Pos (16U)
20161 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
20162 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
20163 #define TIM_CCER_CC5P_Pos (17U)
20164 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
20165 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
20166 #define TIM_CCER_CC6E_Pos (20U)
20167 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
20168 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
20169 #define TIM_CCER_CC6P_Pos (21U)
20170 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
20171 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
20172 /******************* Bit definition for TIM_CNT register ********************/
20173 #define TIM_CNT_CNT_Pos (0U)
20174 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
20175 #define TIM_CNT_CNT TIM_CNT_CNT_Msk
20176 #define TIM_CNT_UIFCPY_Pos (31U)
20177 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
20178 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
20179 /******************* Bit definition for TIM_PSC register ********************/
20180 #define TIM_PSC_PSC_Pos (0U)
20181 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
20182 #define TIM_PSC_PSC TIM_PSC_PSC_Msk
20184 /******************* Bit definition for TIM_ARR register ********************/
20185 #define TIM_ARR_ARR_Pos (0U)
20186 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
20187 #define TIM_ARR_ARR TIM_ARR_ARR_Msk
20189 /******************* Bit definition for TIM_RCR register ********************/
20190 #define TIM_RCR_REP_Pos (0U)
20191 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
20192 #define TIM_RCR_REP TIM_RCR_REP_Msk
20194 /******************* Bit definition for TIM_CCR1 register *******************/
20195 #define TIM_CCR1_CCR1_Pos (0U)
20196 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
20197 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
20199 /******************* Bit definition for TIM_CCR2 register *******************/
20200 #define TIM_CCR2_CCR2_Pos (0U)
20201 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
20202 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
20204 /******************* Bit definition for TIM_CCR3 register *******************/
20205 #define TIM_CCR3_CCR3_Pos (0U)
20206 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
20207 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
20209 /******************* Bit definition for TIM_CCR4 register *******************/
20210 #define TIM_CCR4_CCR4_Pos (0U)
20211 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
20212 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
20214 /******************* Bit definition for TIM_CCR5 register *******************/
20215 #define TIM_CCR5_CCR5_Pos (0U)
20216 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
20217 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
20218 #define TIM_CCR5_GC5C1_Pos (29U)
20219 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
20220 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
20221 #define TIM_CCR5_GC5C2_Pos (30U)
20222 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
20223 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
20224 #define TIM_CCR5_GC5C3_Pos (31U)
20225 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
20226 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
20228 /******************* Bit definition for TIM_CCR6 register *******************/
20229 #define TIM_CCR6_CCR6_Pos (0U)
20230 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
20231 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
20233 /******************* Bit definition for TIM_BDTR register *******************/
20234 #define TIM_BDTR_DTG_Pos (0U)
20235 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
20236 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
20237 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
20238 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
20239 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
20240 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
20241 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
20242 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
20243 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
20244 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
20246 #define TIM_BDTR_LOCK_Pos (8U)
20247 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
20248 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
20249 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
20250 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
20252 #define TIM_BDTR_OSSI_Pos (10U)
20253 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
20254 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
20255 #define TIM_BDTR_OSSR_Pos (11U)
20256 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
20257 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
20258 #define TIM_BDTR_BKE_Pos (12U)
20259 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
20260 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
20261 #define TIM_BDTR_BKP_Pos (13U)
20262 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
20263 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
20264 #define TIM_BDTR_AOE_Pos (14U)
20265 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
20266 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
20267 #define TIM_BDTR_MOE_Pos (15U)
20268 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
20269 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
20271 #define TIM_BDTR_BKF_Pos (16U)
20272 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
20273 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
20274 #define TIM_BDTR_BK2F_Pos (20U)
20275 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
20276 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
20278 #define TIM_BDTR_BK2E_Pos (24U)
20279 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
20280 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
20281 #define TIM_BDTR_BK2P_Pos (25U)
20282 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
20283 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
20285 /******************* Bit definition for TIM_DCR register ********************/
20286 #define TIM_DCR_DBA_Pos (0U)
20287 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
20288 #define TIM_DCR_DBA TIM_DCR_DBA_Msk
20289 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
20290 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
20291 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
20292 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
20293 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
20295 #define TIM_DCR_DBL_Pos (8U)
20296 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
20297 #define TIM_DCR_DBL TIM_DCR_DBL_Msk
20298 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
20299 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
20300 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
20301 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
20302 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
20304 /******************* Bit definition for TIM_DMAR register *******************/
20305 #define TIM_DMAR_DMAB_Pos (0U)
20306 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
20307 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
20309 /****************** Bit definition for TIM_CCMR3 register *******************/
20310 #define TIM_CCMR3_OC5FE_Pos (2U)
20311 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
20312 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
20313 #define TIM_CCMR3_OC5PE_Pos (3U)
20314 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
20315 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
20317 #define TIM_CCMR3_OC5M_Pos (4U)
20318 #define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos)
20319 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
20320 #define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos)
20321 #define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos)
20322 #define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos)
20323 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
20325 #define TIM_CCMR3_OC5CE_Pos (7U)
20326 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
20327 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
20329 #define TIM_CCMR3_OC6FE_Pos (10U)
20330 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
20331 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
20332 #define TIM_CCMR3_OC6PE_Pos (11U)
20333 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
20334 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
20336 #define TIM_CCMR3_OC6M_Pos (12U)
20337 #define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos)
20338 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
20339 #define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos)
20340 #define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos)
20341 #define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos)
20342 #define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos)
20344 #define TIM_CCMR3_OC6CE_Pos (15U)
20345 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
20346 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
20347 /******************* Bit definition for TIM1_AF1 register *********************/
20348 #define TIM1_AF1_BKINE_Pos (0U)
20349 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)
20350 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk
20351 #define TIM1_AF1_BKCMP1E_Pos (1U)
20352 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)
20353 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk
20354 #define TIM1_AF1_BKCMP2E_Pos (2U)
20355 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)
20356 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk
20357 #define TIM1_AF1_BKDF1BK0E_Pos (8U)
20358 #define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)
20359 #define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk
20360 #define TIM1_AF1_BKINP_Pos (9U)
20361 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)
20362 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk
20363 #define TIM1_AF1_BKCMP1P_Pos (10U)
20364 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)
20365 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk
20366 #define TIM1_AF1_BKCMP2P_Pos (11U)
20367 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)
20368 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk
20370 #define TIM1_AF1_ETRSEL_Pos (14U)
20371 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)
20372 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk
20373 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)
20374 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)
20375 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)
20376 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)
20378 /******************* Bit definition for TIM1_AF2 register *********************/
20379 #define TIM1_AF2_BK2INE_Pos (0U)
20380 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)
20381 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk
20382 #define TIM1_AF2_BK2CMP1E_Pos (1U)
20383 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)
20384 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk
20385 #define TIM1_AF2_BK2CMP2E_Pos (2U)
20386 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)
20387 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk
20388 #define TIM1_AF2_BK2DFBK1E_Pos (8U)
20389 #define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)
20390 #define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk
20391 #define TIM1_AF2_BK2INP_Pos (9U)
20392 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)
20393 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk
20394 #define TIM1_AF2_BK2CMP1P_Pos (10U)
20395 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)
20396 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk
20397 #define TIM1_AF2_BK2CMP2P_Pos (11U)
20398 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)
20399 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk
20401 /******************* Bit definition for TIM_TISEL register *********************/
20402 #define TIM_TISEL_TI1SEL_Pos (0U)
20403 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)
20404 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk
20405 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)
20406 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)
20407 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)
20408 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)
20410 #define TIM_TISEL_TI2SEL_Pos (8U)
20411 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)
20412 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk
20413 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)
20414 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)
20415 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)
20416 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)
20418 #define TIM_TISEL_TI3SEL_Pos (16U)
20419 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)
20420 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk
20421 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)
20422 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)
20423 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)
20424 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)
20426 #define TIM_TISEL_TI4SEL_Pos (24U)
20427 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)
20428 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk
20429 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)
20430 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)
20431 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)
20432 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)
20434 /******************* Bit definition for TIM8_AF1 register *********************/
20435 #define TIM8_AF1_BKINE_Pos (0U)
20436 #define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos)
20437 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk
20438 #define TIM8_AF1_BKCMP1E_Pos (1U)
20439 #define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos)
20440 #define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk
20441 #define TIM8_AF1_BKCMP2E_Pos (2U)
20442 #define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos)
20443 #define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk
20444 #define TIM8_AF1_BKDFBK2E_Pos (8U)
20445 #define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos)
20446 #define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk
20447 #define TIM8_AF1_BKINP_Pos (9U)
20448 #define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos)
20449 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk
20450 #define TIM8_AF1_BKCMP1P_Pos (10U)
20451 #define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos)
20452 #define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk
20453 #define TIM8_AF1_BKCMP2P_Pos (11U)
20454 #define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos)
20455 #define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk
20457 #define TIM8_AF1_ETRSEL_Pos (14U)
20458 #define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos)
20459 #define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk
20460 #define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos)
20461 #define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos)
20462 #define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos)
20463 #define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos)
20464 /******************* Bit definition for TIM8_AF2 register *********************/
20465 #define TIM8_AF2_BK2INE_Pos (0U)
20466 #define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos)
20467 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk
20468 #define TIM8_AF2_BK2CMP1E_Pos (1U)
20469 #define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos)
20470 #define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk
20471 #define TIM8_AF2_BK2CMP2E_Pos (2U)
20472 #define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos)
20473 #define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk
20474 #define TIM8_AF2_BK2DFBK3E_Pos (8U)
20475 #define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)
20476 #define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk
20477 #define TIM8_AF2_BK2INP_Pos (9U)
20478 #define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos)
20479 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk
20480 #define TIM8_AF2_BK2CMP1P_Pos (10U)
20481 #define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos)
20482 #define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk
20483 #define TIM8_AF2_BK2CMP2P_Pos (11U)
20484 #define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos)
20485 #define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk
20487 /******************* Bit definition for TIM2_AF1 register *********************/
20488 #define TIM2_AF1_ETRSEL_Pos (14U)
20489 #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos)
20490 #define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk
20491 #define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos)
20492 #define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos)
20493 #define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos)
20494 #define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos)
20496 /******************* Bit definition for TIM3_AF1 register *********************/
20497 #define TIM3_AF1_ETRSEL_Pos (14U)
20498 #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos)
20499 #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk
20500 #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos)
20501 #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos)
20502 #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos)
20503 #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos)
20505 /******************* Bit definition for TIM5_AF1 register *********************/
20506 #define TIM5_AF1_ETRSEL_Pos (14U)
20507 #define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos)
20508 #define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk
20509 #define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos)
20510 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos)
20511 #define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos)
20512 #define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos)
20514 /******************* Bit definition for TIM15_AF1 register *********************/
20515 #define TIM15_AF1_BKINE_Pos (0U)
20516 #define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos)
20517 #define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk
20518 #define TIM15_AF1_BKCMP1E_Pos (1U)
20519 #define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos)
20520 #define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk
20521 #define TIM15_AF1_BKCMP2E_Pos (2U)
20522 #define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos)
20523 #define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk
20524 #define TIM15_AF1_BKDF1BK2E_Pos (8U)
20525 #define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)
20526 #define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk
20527 #define TIM15_AF1_BKINP_Pos (9U)
20528 #define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos)
20529 #define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk
20530 #define TIM15_AF1_BKCMP1P_Pos (10U)
20531 #define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos)
20532 #define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk
20533 #define TIM15_AF1_BKCMP2P_Pos (11U)
20534 #define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos)
20535 #define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk
20537 /******************* Bit definition for TIM16_ register *********************/
20538 #define TIM16_AF1_BKINE_Pos (0U)
20539 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)
20540 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk
20541 #define TIM16_AF1_BKCMP1E_Pos (1U)
20542 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)
20543 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk
20544 #define TIM16_AF1_BKCMP2E_Pos (2U)
20545 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)
20546 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk
20547 #define TIM16_AF1_BKDF1BK2E_Pos (8U)
20548 #define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)
20549 #define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk
20550 #define TIM16_AF1_BKINP_Pos (9U)
20551 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)
20552 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk
20553 #define TIM16_AF1_BKCMP1P_Pos (10U)
20554 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)
20555 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk
20556 #define TIM16_AF1_BKCMP2P_Pos (11U)
20557 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)
20558 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk
20560 /******************* Bit definition for TIM17_AF1 register *********************/
20561 #define TIM17_AF1_BKINE_Pos (0U)
20562 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)
20563 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk
20564 #define TIM17_AF1_BKCMP1E_Pos (1U)
20565 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)
20566 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk
20567 #define TIM17_AF1_BKCMP2E_Pos (2U)
20568 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)
20569 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk
20570 #define TIM17_AF1_BKDF1BK2E_Pos (8U)
20571 #define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)
20572 #define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk
20573 #define TIM17_AF1_BKINP_Pos (9U)
20574 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)
20575 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk
20576 #define TIM17_AF1_BKCMP1P_Pos (10U)
20577 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)
20578 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk
20579 #define TIM17_AF1_BKCMP2P_Pos (11U)
20580 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)
20581 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk
20583 /******************************************************************************/
20584 /* */
20585 /* Low Power Timer (LPTTIM) */
20586 /* */
20587 /******************************************************************************/
20588 /****************** Bit definition for LPTIM_ISR register *******************/
20589 #define LPTIM_ISR_CMPM_Pos (0U)
20590 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
20591 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
20592 #define LPTIM_ISR_ARRM_Pos (1U)
20593 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
20594 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
20595 #define LPTIM_ISR_EXTTRIG_Pos (2U)
20596 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
20597 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
20598 #define LPTIM_ISR_CMPOK_Pos (3U)
20599 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
20600 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
20601 #define LPTIM_ISR_ARROK_Pos (4U)
20602 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
20603 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
20604 #define LPTIM_ISR_UP_Pos (5U)
20605 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
20606 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
20607 #define LPTIM_ISR_DOWN_Pos (6U)
20608 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
20609 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
20611 /****************** Bit definition for LPTIM_ICR register *******************/
20612 #define LPTIM_ICR_CMPMCF_Pos (0U)
20613 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
20614 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
20615 #define LPTIM_ICR_ARRMCF_Pos (1U)
20616 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
20617 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
20618 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
20619 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
20620 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
20621 #define LPTIM_ICR_CMPOKCF_Pos (3U)
20622 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
20623 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
20624 #define LPTIM_ICR_ARROKCF_Pos (4U)
20625 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
20626 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
20627 #define LPTIM_ICR_UPCF_Pos (5U)
20628 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
20629 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
20630 #define LPTIM_ICR_DOWNCF_Pos (6U)
20631 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
20632 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
20634 /****************** Bit definition for LPTIM_IER register ********************/
20635 #define LPTIM_IER_CMPMIE_Pos (0U)
20636 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
20637 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
20638 #define LPTIM_IER_ARRMIE_Pos (1U)
20639 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
20640 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
20641 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
20642 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
20643 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
20644 #define LPTIM_IER_CMPOKIE_Pos (3U)
20645 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
20646 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
20647 #define LPTIM_IER_ARROKIE_Pos (4U)
20648 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
20649 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
20650 #define LPTIM_IER_UPIE_Pos (5U)
20651 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
20652 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
20653 #define LPTIM_IER_DOWNIE_Pos (6U)
20654 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
20655 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
20657 /****************** Bit definition for LPTIM_CFGR register *******************/
20658 #define LPTIM_CFGR_CKSEL_Pos (0U)
20659 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
20660 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
20662 #define LPTIM_CFGR_CKPOL_Pos (1U)
20663 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
20664 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
20665 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
20666 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
20668 #define LPTIM_CFGR_CKFLT_Pos (3U)
20669 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
20670 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
20671 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
20672 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
20674 #define LPTIM_CFGR_TRGFLT_Pos (6U)
20675 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
20676 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
20677 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
20678 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
20680 #define LPTIM_CFGR_PRESC_Pos (9U)
20681 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
20682 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
20683 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
20684 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
20685 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
20687 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
20688 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
20689 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
20690 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
20691 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
20692 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
20694 #define LPTIM_CFGR_TRIGEN_Pos (17U)
20695 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
20696 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
20697 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
20698 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
20700 #define LPTIM_CFGR_TIMOUT_Pos (19U)
20701 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
20702 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
20703 #define LPTIM_CFGR_WAVE_Pos (20U)
20704 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
20705 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
20706 #define LPTIM_CFGR_WAVPOL_Pos (21U)
20707 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
20708 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
20709 #define LPTIM_CFGR_PRELOAD_Pos (22U)
20710 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
20711 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
20712 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
20713 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
20714 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
20715 #define LPTIM_CFGR_ENC_Pos (24U)
20716 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
20717 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
20719 /****************** Bit definition for LPTIM_CR register ********************/
20720 #define LPTIM_CR_ENABLE_Pos (0U)
20721 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
20722 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
20723 #define LPTIM_CR_SNGSTRT_Pos (1U)
20724 #define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos)
20725 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
20726 #define LPTIM_CR_CNTSTRT_Pos (2U)
20727 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
20728 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
20729 #define LPTIM_CR_COUNTRST_Pos (3U)
20730 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)
20731 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk
20732 #define LPTIM_CR_RSTARE_Pos (4U)
20733 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)
20734 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk
20737 /****************** Bit definition for LPTIM_CMP register *******************/
20738 #define LPTIM_CMP_CMP_Pos (0U)
20739 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
20740 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
20742 /****************** Bit definition for LPTIM_ARR register *******************/
20743 #define LPTIM_ARR_ARR_Pos (0U)
20744 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
20745 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
20747 /****************** Bit definition for LPTIM_CNT register *******************/
20748 #define LPTIM_CNT_CNT_Pos (0U)
20749 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
20750 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
20752 /****************** Bit definition for LPTIM_CFGR2 register *****************/
20753 #define LPTIM_CFGR2_IN1SEL_Pos (0U)
20754 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)
20755 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk
20756 #define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)
20757 #define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)
20758 #define LPTIM_CFGR2_IN2SEL_Pos (4U)
20759 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)
20760 #define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk
20761 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)
20762 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)
20764 /******************************************************************************/
20765 /* */
20766 /* OCTOSPI */
20767 /* */
20768 /******************************************************************************/
20769 /***************** Bit definition for OCTOSPI_CR register *******************/
20770 #define OCTOSPI_CR_EN_Pos (0U)
20771 #define OCTOSPI_CR_EN_Msk (0x1UL << OCTOSPI_CR_EN_Pos)
20772 #define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk
20773 #define OCTOSPI_CR_ABORT_Pos (1U)
20774 #define OCTOSPI_CR_ABORT_Msk (0x1UL << OCTOSPI_CR_ABORT_Pos)
20775 #define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk
20776 #define OCTOSPI_CR_DMAEN_Pos (2U)
20777 #define OCTOSPI_CR_DMAEN_Msk (0x1UL << OCTOSPI_CR_DMAEN_Pos)
20778 #define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk
20779 #define OCTOSPI_CR_TCEN_Pos (3U)
20780 #define OCTOSPI_CR_TCEN_Msk (0x1UL << OCTOSPI_CR_TCEN_Pos)
20781 #define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk
20782 #define OCTOSPI_CR_DQM_Pos (6U)
20783 #define OCTOSPI_CR_DQM_Msk (0x1UL << OCTOSPI_CR_DQM_Pos)
20784 #define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk
20785 #define OCTOSPI_CR_FSEL_Pos (7U)
20786 #define OCTOSPI_CR_FSEL_Msk (0x1UL << OCTOSPI_CR_FSEL_Pos)
20787 #define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk
20788 #define OCTOSPI_CR_FTHRES_Pos (8U)
20789 #define OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos)
20790 #define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk
20791 #define OCTOSPI_CR_TEIE_Pos (16U)
20792 #define OCTOSPI_CR_TEIE_Msk (0x1UL << OCTOSPI_CR_TEIE_Pos)
20793 #define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk
20794 #define OCTOSPI_CR_TCIE_Pos (17U)
20795 #define OCTOSPI_CR_TCIE_Msk (0x1UL << OCTOSPI_CR_TCIE_Pos)
20796 #define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk
20797 #define OCTOSPI_CR_FTIE_Pos (18U)
20798 #define OCTOSPI_CR_FTIE_Msk (0x1UL << OCTOSPI_CR_FTIE_Pos)
20799 #define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk
20800 #define OCTOSPI_CR_SMIE_Pos (19U)
20801 #define OCTOSPI_CR_SMIE_Msk (0x1UL << OCTOSPI_CR_SMIE_Pos)
20802 #define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk
20803 #define OCTOSPI_CR_TOIE_Pos (20U)
20804 #define OCTOSPI_CR_TOIE_Msk (0x1UL << OCTOSPI_CR_TOIE_Pos)
20805 #define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk
20806 #define OCTOSPI_CR_APMS_Pos (22U)
20807 #define OCTOSPI_CR_APMS_Msk (0x1UL << OCTOSPI_CR_APMS_Pos)
20808 #define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk
20809 #define OCTOSPI_CR_PMM_Pos (23U)
20810 #define OCTOSPI_CR_PMM_Msk (0x1UL << OCTOSPI_CR_PMM_Pos)
20811 #define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk
20812 #define OCTOSPI_CR_FMODE_Pos (28U)
20813 #define OCTOSPI_CR_FMODE_Msk (0x3UL << OCTOSPI_CR_FMODE_Pos)
20814 #define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk
20815 #define OCTOSPI_CR_FMODE_0 (0x1UL << OCTOSPI_CR_FMODE_Pos)
20816 #define OCTOSPI_CR_FMODE_1 (0x2UL << OCTOSPI_CR_FMODE_Pos)
20818 /**************** Bit definition for OCTOSPI_DCR1 register ******************/
20819 #define OCTOSPI_DCR1_CKMODE_Pos (0U)
20820 #define OCTOSPI_DCR1_CKMODE_Msk (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)
20821 #define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk
20822 #define OCTOSPI_DCR1_FRCK_Pos (1U)
20823 #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos)
20824 #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk
20825 #define OCTOSPI_DCR1_DLYBYP_Pos (3U)
20826 #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)
20827 #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk
20828 #define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20829 #define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)
20830 #define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk
20831 #define OCTOSPI_DCR1_CSHT_Pos (8U)
20832 #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos)
20833 #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk
20834 #define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
20835 #define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)
20836 #define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk
20837 #define OCTOSPI_DCR1_MTYP_Pos (24U)
20838 #define OCTOSPI_DCR1_MTYP_Msk (0x7UL << OCTOSPI_DCR1_MTYP_Pos)
20839 #define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk
20840 #define OCTOSPI_DCR1_MTYP_0 (0x1UL << OCTOSPI_DCR1_MTYP_Pos)
20841 #define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos)
20842 #define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos)
20844 /**************** Bit definition for OCTOSPI_DCR2 register ******************/
20845 #define OCTOSPI_DCR2_PRESCALER_Pos (0U)
20846 #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)
20847 #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk
20848 #define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
20849 #define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
20850 #define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk
20851 #define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
20852 #define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
20853 #define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
20855 /**************** Bit definition for OCTOSPI_DCR3 register ******************/
20856 #define OCTOSPI_DCR3_MAXTRAN_Pos (0U)
20857 #define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)
20858 #define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk
20859 #define OCTOSPI_DCR3_CSBOUND_Pos (16U)
20860 #define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)
20861 #define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk
20863 /**************** Bit definition for OCTOSPI_DCR4 register ******************/
20864 #define OCTOSPI_DCR4_REFRESH_Pos (0U)
20865 #define OCTOSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos)
20866 #define OCTOSPI_DCR4_REFRESH OCTOSPI_DCR4_REFRESH_Msk
20868 /***************** Bit definition for OCTOSPI_SR register *******************/
20869 #define OCTOSPI_SR_TEF_Pos (0U)
20870 #define OCTOSPI_SR_TEF_Msk (0x1UL << OCTOSPI_SR_TEF_Pos)
20871 #define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk
20872 #define OCTOSPI_SR_TCF_Pos (1U)
20873 #define OCTOSPI_SR_TCF_Msk (0x1UL << OCTOSPI_SR_TCF_Pos)
20874 #define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk
20875 #define OCTOSPI_SR_FTF_Pos (2U)
20876 #define OCTOSPI_SR_FTF_Msk (0x1UL << OCTOSPI_SR_FTF_Pos)
20877 #define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk
20878 #define OCTOSPI_SR_SMF_Pos (3U)
20879 #define OCTOSPI_SR_SMF_Msk (0x1UL << OCTOSPI_SR_SMF_Pos)
20880 #define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk
20881 #define OCTOSPI_SR_TOF_Pos (4U)
20882 #define OCTOSPI_SR_TOF_Msk (0x1UL << OCTOSPI_SR_TOF_Pos)
20883 #define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk
20884 #define OCTOSPI_SR_BUSY_Pos (5U)
20885 #define OCTOSPI_SR_BUSY_Msk (0x1UL << OCTOSPI_SR_BUSY_Pos)
20886 #define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk
20887 #define OCTOSPI_SR_FLEVEL_Pos (8U)
20888 #define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)
20889 #define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk
20891 /**************** Bit definition for OCTOSPI_FCR register *******************/
20892 #define OCTOSPI_FCR_CTEF_Pos (0U)
20893 #define OCTOSPI_FCR_CTEF_Msk (0x1UL << OCTOSPI_FCR_CTEF_Pos)
20894 #define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk
20895 #define OCTOSPI_FCR_CTCF_Pos (1U)
20896 #define OCTOSPI_FCR_CTCF_Msk (0x1UL << OCTOSPI_FCR_CTCF_Pos)
20897 #define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk
20898 #define OCTOSPI_FCR_CSMF_Pos (3U)
20899 #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos)
20900 #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk
20901 #define OCTOSPI_FCR_CTOF_Pos (4U)
20902 #define OCTOSPI_FCR_CTOF_Msk (0x1UL << OCTOSPI_FCR_CTOF_Pos)
20903 #define OCTOSPI_FCR_CTOF OCTOSPI_FCR_CTOF_Msk
20905 /**************** Bit definition for OCTOSPI_DLR register *******************/
20906 #define OCTOSPI_DLR_DL_Pos (0U)
20907 #define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)
20908 #define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk
20910 /***************** Bit definition for OCTOSPI_AR register *******************/
20911 #define OCTOSPI_AR_ADDRESS_Pos (0U)
20912 #define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos)
20913 #define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk
20915 /***************** Bit definition for OCTOSPI_DR register *******************/
20916 #define OCTOSPI_DR_DATA_Pos (0U)
20917 #define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)
20918 #define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk
20920 /*************** Bit definition for OCTOSPI_PSMKR register ******************/
20921 #define OCTOSPI_PSMKR_MASK_Pos (0U)
20922 #define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos)
20923 #define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk
20925 /*************** Bit definition for OCTOSPI_PSMAR register ******************/
20926 #define OCTOSPI_PSMAR_MATCH_Pos (0U)
20927 #define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos)
20928 #define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk
20930 /**************** Bit definition for OCTOSPI_PIR register *******************/
20931 #define OCTOSPI_PIR_INTERVAL_Pos (0U)
20932 #define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)
20933 #define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk
20935 /**************** Bit definition for OCTOSPI_CCR register *******************/
20936 #define OCTOSPI_CCR_IMODE_Pos (0U)
20937 #define OCTOSPI_CCR_IMODE_Msk (0x7UL << OCTOSPI_CCR_IMODE_Pos)
20938 #define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk
20939 #define OCTOSPI_CCR_IMODE_0 (0x1UL << OCTOSPI_CCR_IMODE_Pos)
20940 #define OCTOSPI_CCR_IMODE_1 (0x2UL << OCTOSPI_CCR_IMODE_Pos)
20941 #define OCTOSPI_CCR_IMODE_2 (0x4UL << OCTOSPI_CCR_IMODE_Pos)
20942 #define OCTOSPI_CCR_IDTR_Pos (3U)
20943 #define OCTOSPI_CCR_IDTR_Msk (0x1UL << OCTOSPI_CCR_IDTR_Pos)
20944 #define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk
20945 #define OCTOSPI_CCR_ISIZE_Pos (4U)
20946 #define OCTOSPI_CCR_ISIZE_Msk (0x3UL << OCTOSPI_CCR_ISIZE_Pos)
20947 #define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk
20948 #define OCTOSPI_CCR_ISIZE_0 (0x1UL << OCTOSPI_CCR_ISIZE_Pos)
20949 #define OCTOSPI_CCR_ISIZE_1 (0x2UL << OCTOSPI_CCR_ISIZE_Pos)
20950 #define OCTOSPI_CCR_ADMODE_Pos (8U)
20951 #define OCTOSPI_CCR_ADMODE_Msk (0x7UL << OCTOSPI_CCR_ADMODE_Pos)
20952 #define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk
20953 #define OCTOSPI_CCR_ADMODE_0 (0x1UL << OCTOSPI_CCR_ADMODE_Pos)
20954 #define OCTOSPI_CCR_ADMODE_1 (0x2UL << OCTOSPI_CCR_ADMODE_Pos)
20955 #define OCTOSPI_CCR_ADMODE_2 (0x4UL << OCTOSPI_CCR_ADMODE_Pos)
20956 #define OCTOSPI_CCR_ADDTR_Pos (11U)
20957 #define OCTOSPI_CCR_ADDTR_Msk (0x1UL << OCTOSPI_CCR_ADDTR_Pos)
20958 #define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk
20959 #define OCTOSPI_CCR_ADSIZE_Pos (12U)
20960 #define OCTOSPI_CCR_ADSIZE_Msk (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)
20961 #define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk
20962 #define OCTOSPI_CCR_ADSIZE_0 (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)
20963 #define OCTOSPI_CCR_ADSIZE_1 (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)
20964 #define OCTOSPI_CCR_ABMODE_Pos (16U)
20965 #define OCTOSPI_CCR_ABMODE_Msk (0x7UL << OCTOSPI_CCR_ABMODE_Pos)
20966 #define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk
20967 #define OCTOSPI_CCR_ABMODE_0 (0x1UL << OCTOSPI_CCR_ABMODE_Pos)
20968 #define OCTOSPI_CCR_ABMODE_1 (0x2UL << OCTOSPI_CCR_ABMODE_Pos)
20969 #define OCTOSPI_CCR_ABMODE_2 (0x4UL << OCTOSPI_CCR_ABMODE_Pos)
20970 #define OCTOSPI_CCR_ABDTR_Pos (19U)
20971 #define OCTOSPI_CCR_ABDTR_Msk (0x1UL << OCTOSPI_CCR_ABDTR_Pos)
20972 #define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk
20973 #define OCTOSPI_CCR_ABSIZE_Pos (20U)
20974 #define OCTOSPI_CCR_ABSIZE_Msk (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)
20975 #define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk
20976 #define OCTOSPI_CCR_ABSIZE_0 (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)
20977 #define OCTOSPI_CCR_ABSIZE_1 (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)
20978 #define OCTOSPI_CCR_DMODE_Pos (24U)
20979 #define OCTOSPI_CCR_DMODE_Msk (0x7UL << OCTOSPI_CCR_DMODE_Pos)
20980 #define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk
20981 #define OCTOSPI_CCR_DMODE_0 (0x1UL << OCTOSPI_CCR_DMODE_Pos)
20982 #define OCTOSPI_CCR_DMODE_1 (0x2UL << OCTOSPI_CCR_DMODE_Pos)
20983 #define OCTOSPI_CCR_DMODE_2 (0x4UL << OCTOSPI_CCR_DMODE_Pos)
20984 #define OCTOSPI_CCR_DDTR_Pos (27U)
20985 #define OCTOSPI_CCR_DDTR_Msk (0x1UL << OCTOSPI_CCR_DDTR_Pos)
20986 #define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk
20987 #define OCTOSPI_CCR_DQSE_Pos (29U)
20988 #define OCTOSPI_CCR_DQSE_Msk (0x1UL << OCTOSPI_CCR_DQSE_Pos)
20989 #define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk
20990 #define OCTOSPI_CCR_SIOO_Pos (31U)
20991 #define OCTOSPI_CCR_SIOO_Msk (0x1UL << OCTOSPI_CCR_SIOO_Pos)
20992 #define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk
20994 /**************** Bit definition for OCTOSPI_TCR register *******************/
20995 #define OCTOSPI_TCR_DCYC_Pos (0U)
20996 #define OCTOSPI_TCR_DCYC_Msk (0x1FUL << OCTOSPI_TCR_DCYC_Pos)
20997 #define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk
20998 #define OCTOSPI_TCR_DHQC_Pos (28U)
20999 #define OCTOSPI_TCR_DHQC_Msk (0x1UL << OCTOSPI_TCR_DHQC_Pos)
21000 #define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk
21001 #define OCTOSPI_TCR_SSHIFT_Pos (30U)
21002 #define OCTOSPI_TCR_SSHIFT_Msk (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)
21003 #define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk
21005 /***************** Bit definition for OCTOSPI_IR register *******************/
21006 #define OCTOSPI_IR_INSTRUCTION_Pos (0U)
21007 #define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos)
21008 #define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk
21010 /**************** Bit definition for OCTOSPI_ABR register *******************/
21011 #define OCTOSPI_ABR_ALTERNATE_Pos (0U)
21012 #define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos)
21013 #define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk
21015 /**************** Bit definition for OCTOSPI_LPTR register ******************/
21016 #define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
21017 #define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)
21018 #define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk
21020 /**************** Bit definition for OCTOSPI_WPCCR register *******************/
21021 #define OCTOSPI_WPCCR_IMODE_Pos (0U)
21022 #define OCTOSPI_WPCCR_IMODE_Msk (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)
21023 #define OCTOSPI_WPCCR_IMODE OCTOSPI_WPCCR_IMODE_Msk
21024 #define OCTOSPI_WPCCR_IMODE_0 (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)
21025 #define OCTOSPI_WPCCR_IMODE_1 (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)
21026 #define OCTOSPI_WPCCR_IMODE_2 (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)
21027 #define OCTOSPI_WPCCR_IDTR_Pos (3U)
21028 #define OCTOSPI_WPCCR_IDTR_Msk (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)
21029 #define OCTOSPI_WPCCR_IDTR OCTOSPI_WPCCR_IDTR_Msk
21030 #define OCTOSPI_WPCCR_ISIZE_Pos (4U)
21031 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)
21032 #define OCTOSPI_WPCCR_ISIZE OCTOSPI_WPCCR_ISIZE_Msk
21033 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)
21034 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)
21035 #define OCTOSPI_WPCCR_ADMODE_Pos (8U)
21036 #define OCTOSPI_WPCCR_ADMODE_Msk (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)
21037 #define OCTOSPI_WPCCR_ADMODE OCTOSPI_WPCCR_ADMODE_Msk
21038 #define OCTOSPI_WPCCR_ADMODE_0 (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)
21039 #define OCTOSPI_WPCCR_ADMODE_1 (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)
21040 #define OCTOSPI_WPCCR_ADMODE_2 (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)
21041 #define OCTOSPI_WPCCR_ADDTR_Pos (11U)
21042 #define OCTOSPI_WPCCR_ADDTR_Msk (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)
21043 #define OCTOSPI_WPCCR_ADDTR OCTOSPI_WPCCR_ADDTR_Msk
21044 #define OCTOSPI_WPCCR_ADSIZE_Pos (12U)
21045 #define OCTOSPI_WPCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)
21046 #define OCTOSPI_WPCCR_ADSIZE OCTOSPI_WPCCR_ADSIZE_Msk
21047 #define OCTOSPI_WPCCR_ADSIZE_0 (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)
21048 #define OCTOSPI_WPCCR_ADSIZE_1 (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)
21049 #define OCTOSPI_WPCCR_ABMODE_Pos (16U)
21050 #define OCTOSPI_WPCCR_ABMODE_Msk (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)
21051 #define OCTOSPI_WPCCR_ABMODE OCTOSPI_WPCCR_ABMODE_Msk
21052 #define OCTOSPI_WPCCR_ABMODE_0 (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)
21053 #define OCTOSPI_WPCCR_ABMODE_1 (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)
21054 #define OCTOSPI_WPCCR_ABMODE_2 (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)
21055 #define OCTOSPI_WPCCR_ABDTR_Pos (19U)
21056 #define OCTOSPI_WPCCR_ABDTR_Msk (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)
21057 #define OCTOSPI_WPCCR_ABDTR OCTOSPI_WPCCR_ABDTR_Msk
21058 #define OCTOSPI_WPCCR_ABSIZE_Pos (20U)
21059 #define OCTOSPI_WPCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)
21060 #define OCTOSPI_WPCCR_ABSIZE OCTOSPI_WPCCR_ABSIZE_Msk
21061 #define OCTOSPI_WPCCR_ABSIZE_0 (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)
21062 #define OCTOSPI_WPCCR_ABSIZE_1 (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)
21063 #define OCTOSPI_WPCCR_DMODE_Pos (24U)
21064 #define OCTOSPI_WPCCR_DMODE_Msk (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)
21065 #define OCTOSPI_WPCCR_DMODE OCTOSPI_WPCCR_DMODE_Msk
21066 #define OCTOSPI_WPCCR_DMODE_0 (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)
21067 #define OCTOSPI_WPCCR_DMODE_1 (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)
21068 #define OCTOSPI_WPCCR_DMODE_2 (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)
21069 #define OCTOSPI_WPCCR_DDTR_Pos (27U)
21070 #define OCTOSPI_WPCCR_DDTR_Msk (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)
21071 #define OCTOSPI_WPCCR_DDTR OCTOSPI_WPCCR_DDTR_Msk
21072 #define OCTOSPI_WPCCR_DQSE_Pos (29U)
21073 #define OCTOSPI_WPCCR_DQSE_Msk (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)
21074 #define OCTOSPI_WPCCR_DQSE OCTOSPI_WPCCR_DQSE_Msk
21075 #define OCTOSPI_WPCCR_SIOO_Pos (31U)
21076 #define OCTOSPI_WPCCR_SIOO_Msk (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)
21077 #define OCTOSPI_WPCCR_SIOO OCTOSPI_WPCCR_SIOO_Msk
21079 /**************** Bit definition for OCTOSPI_WPTCR register *******************/
21080 #define OCTOSPI_WPTCR_DCYC_Pos (0U)
21081 #define OCTOSPI_WPTCR_DCYC_Msk (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)
21082 #define OCTOSPI_WPTCR_DCYC OCTOSPI_WPTCR_DCYC_Msk
21083 #define OCTOSPI_WPTCR_DHQC_Pos (28U)
21084 #define OCTOSPI_WPTCR_DHQC_Msk (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)
21085 #define OCTOSPI_WPTCR_DHQC OCTOSPI_WPTCR_DHQC_Msk
21086 #define OCTOSPI_WPTCR_SSHIFT_Pos (30U)
21087 #define OCTOSPI_WPTCR_SSHIFT_Msk (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)
21088 #define OCTOSPI_WPTCR_SSHIFT OCTOSPI_WPTCR_SSHIFT_Msk
21090 /***************** Bit definition for OCTOSPI_WPIR register *******************/
21091 #define OCTOSPI_WPIR_INSTRUCTION_Pos (0U)
21092 #define OCTOSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos)
21093 #define OCTOSPI_WPIR_INSTRUCTION OCTOSPI_WPIR_INSTRUCTION_Msk
21095 /**************** Bit definition for OCTOSPI_WPABR register *******************/
21096 #define OCTOSPI_WPABR_ALTERNATE_Pos (0U)
21097 #define OCTOSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos)
21098 #define OCTOSPI_WPABR_ALTERNATE OCTOSPI_WPABR_ALTERNATE_Msk
21100 /**************** Bit definition for OCTOSPI_WCCR register ******************/
21101 #define OCTOSPI_WCCR_IMODE_Pos (0U)
21102 #define OCTOSPI_WCCR_IMODE_Msk (0x7UL << OCTOSPI_WCCR_IMODE_Pos)
21103 #define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk
21104 #define OCTOSPI_WCCR_IMODE_0 (0x1UL << OCTOSPI_WCCR_IMODE_Pos)
21105 #define OCTOSPI_WCCR_IMODE_1 (0x2UL << OCTOSPI_WCCR_IMODE_Pos)
21106 #define OCTOSPI_WCCR_IMODE_2 (0x4UL << OCTOSPI_WCCR_IMODE_Pos)
21107 #define OCTOSPI_WCCR_IDTR_Pos (3U)
21108 #define OCTOSPI_WCCR_IDTR_Msk (0x1UL << OCTOSPI_WCCR_IDTR_Pos)
21109 #define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk
21110 #define OCTOSPI_WCCR_ISIZE_Pos (4U)
21111 #define OCTOSPI_WCCR_ISIZE_Msk (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)
21112 #define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk
21113 #define OCTOSPI_WCCR_ISIZE_0 (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)
21114 #define OCTOSPI_WCCR_ISIZE_1 (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)
21115 #define OCTOSPI_WCCR_ADMODE_Pos (8U)
21116 #define OCTOSPI_WCCR_ADMODE_Msk (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)
21117 #define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk
21118 #define OCTOSPI_WCCR_ADMODE_0 (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)
21119 #define OCTOSPI_WCCR_ADMODE_1 (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)
21120 #define OCTOSPI_WCCR_ADMODE_2 (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)
21121 #define OCTOSPI_WCCR_ADDTR_Pos (11U)
21122 #define OCTOSPI_WCCR_ADDTR_Msk (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)
21123 #define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk
21124 #define OCTOSPI_WCCR_ADSIZE_Pos (12U)
21125 #define OCTOSPI_WCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)
21126 #define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk
21127 #define OCTOSPI_WCCR_ADSIZE_0 (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)
21128 #define OCTOSPI_WCCR_ADSIZE_1 (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)
21129 #define OCTOSPI_WCCR_ABMODE_Pos (16U)
21130 #define OCTOSPI_WCCR_ABMODE_Msk (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)
21131 #define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk
21132 #define OCTOSPI_WCCR_ABMODE_0 (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)
21133 #define OCTOSPI_WCCR_ABMODE_1 (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)
21134 #define OCTOSPI_WCCR_ABMODE_2 (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)
21135 #define OCTOSPI_WCCR_ABDTR_Pos (19U)
21136 #define OCTOSPI_WCCR_ABDTR_Msk (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)
21137 #define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk
21138 #define OCTOSPI_WCCR_ABSIZE_Pos (20U)
21139 #define OCTOSPI_WCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)
21140 #define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk
21141 #define OCTOSPI_WCCR_ABSIZE_0 (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)
21142 #define OCTOSPI_WCCR_ABSIZE_1 (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)
21143 #define OCTOSPI_WCCR_DMODE_Pos (24U)
21144 #define OCTOSPI_WCCR_DMODE_Msk (0x7UL << OCTOSPI_WCCR_DMODE_Pos)
21145 #define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk
21146 #define OCTOSPI_WCCR_DMODE_0 (0x1UL << OCTOSPI_WCCR_DMODE_Pos)
21147 #define OCTOSPI_WCCR_DMODE_1 (0x2UL << OCTOSPI_WCCR_DMODE_Pos)
21148 #define OCTOSPI_WCCR_DMODE_2 (0x4UL << OCTOSPI_WCCR_DMODE_Pos)
21149 #define OCTOSPI_WCCR_DDTR_Pos (27U)
21150 #define OCTOSPI_WCCR_DDTR_Msk (0x1UL << OCTOSPI_WCCR_DDTR_Pos)
21151 #define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk
21152 #define OCTOSPI_WCCR_DQSE_Pos (29U)
21153 #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos)
21154 #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk
21155 #define OCTOSPI_WCCR_SIOO_Pos (31U)
21156 #define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos)
21157 #define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk
21159 /**************** Bit definition for OCTOSPI_WTCR register ******************/
21160 #define OCTOSPI_WTCR_DCYC_Pos (0U)
21161 #define OCTOSPI_WTCR_DCYC_Msk (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)
21162 #define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk
21164 /**************** Bit definition for OCTOSPI_WIR register *******************/
21165 #define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
21166 #define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos)
21167 #define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk
21169 /**************** Bit definition for OCTOSPI_WABR register ******************/
21170 #define OCTOSPI_WABR_ALTERNATE_Pos (0U)
21171 #define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos)
21172 #define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk
21174 /**************** Bit definition for OCTOSPI_HLCR register ******************/
21175 #define OCTOSPI_HLCR_LM_Pos (0U)
21176 #define OCTOSPI_HLCR_LM_Msk (0x1UL << OCTOSPI_HLCR_LM_Pos)
21177 #define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk
21178 #define OCTOSPI_HLCR_WZL_Pos (1U)
21179 #define OCTOSPI_HLCR_WZL_Msk (0x1UL << OCTOSPI_HLCR_WZL_Pos)
21180 #define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk
21181 #define OCTOSPI_HLCR_TACC_Pos (8U)
21182 #define OCTOSPI_HLCR_TACC_Msk (0xFFUL << OCTOSPI_HLCR_TACC_Pos)
21183 #define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk
21184 #define OCTOSPI_HLCR_TRWR_Pos (16U)
21185 #define OCTOSPI_HLCR_TRWR_Msk (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)
21186 #define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk
21188 /**************** Bit definition for OCTOSPI_VER register *******************/
21189 #define OCTOSPI_VER_VER_Pos (0U)
21190 #define OCTOSPI_VER_VER_Msk (0xFFUL << OCTOSPI_VER_VER_Pos)
21191 #define OCTOSPI_VER_VER OCTOSPI_VER_VER_Msk
21193 /***************** Bit definition for OCTOSPI_ID register *******************/
21194 #define OCTOSPI_ID_ID_Pos (0U)
21195 #define OCTOSPI_ID_ID_Msk (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)
21196 #define OCTOSPI_ID_ID OCTOSPI_ID_ID_Msk
21198 /**************** Bit definition for OCTOSPI_MID register *******************/
21199 #define OCTOSPI_MID_MID_Pos (0U)
21200 #define OCTOSPI_MID_MID_Msk (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)
21201 #define OCTOSPI_MID_MID OCTOSPI_MID_MID_Msk
21203 /******************************************************************************/
21204 /* */
21205 /* OCTOSPIM */
21206 /* */
21207 /******************************************************************************/
21208 
21209 /*************** Bit definition for OCTOSPIM_CR register ********************/
21210 #define OCTOSPIM_CR_MUXEN_Pos (0U)
21211 #define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos)
21212 #define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk
21213 #define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
21214 #define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)
21215 #define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk
21217 /*************** Bit definition for OCTOSPIM_PCR register *******************/
21218 #define OCTOSPIM_PCR_CLKEN_Pos (0U)
21219 #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)
21220 #define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk
21221 #define OCTOSPIM_PCR_CLKSRC_Pos (1U)
21222 #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)
21223 #define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk
21224 #define OCTOSPIM_PCR_DQSEN_Pos (4U)
21225 #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)
21226 #define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk
21227 #define OCTOSPIM_PCR_DQSSRC_Pos (5U)
21228 #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)
21229 #define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk
21230 #define OCTOSPIM_PCR_NCSEN_Pos (8U)
21231 #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)
21232 #define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk
21233 #define OCTOSPIM_PCR_NCSSRC_Pos (9U)
21234 #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)
21235 #define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk
21236 #define OCTOSPIM_PCR_IOLEN_Pos (16U)
21237 #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)
21238 #define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk
21239 #define OCTOSPIM_PCR_IOLSRC_Pos (17U)
21240 #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)
21241 #define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk
21242 #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)
21243 #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)
21244 #define OCTOSPIM_PCR_IOHEN_Pos (24U)
21245 #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)
21246 #define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk
21247 #define OCTOSPIM_PCR_IOHSRC_Pos (25U)
21248 #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)
21249 #define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk
21250 #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)
21251 #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)
21252 /******************************************************************************/
21253 /* */
21254 /* Analog Comparators (COMP) */
21255 /* */
21256 /******************************************************************************/
21257 
21258 /******************* Bit definition for COMP_SR register ********************/
21259 #define COMP_SR_C1VAL_Pos (0U)
21260 #define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos)
21261 #define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
21262 #define COMP_SR_C2VAL_Pos (1U)
21263 #define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos)
21264 #define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
21265 #define COMP_SR_C1IF_Pos (16U)
21266 #define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos)
21267 #define COMP_SR_C1IF COMP_SR_C1IF_Msk
21268 #define COMP_SR_C2IF_Pos (17U)
21269 #define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos)
21270 #define COMP_SR_C2IF COMP_SR_C2IF_Msk
21271 /******************* Bit definition for COMP_ICFR register ********************/
21272 #define COMP_ICFR_C1IF_Pos (16U)
21273 #define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos)
21274 #define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
21275 #define COMP_ICFR_C2IF_Pos (17U)
21276 #define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos)
21277 #define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
21278 /******************* Bit definition for COMP_OR register ********************/
21279 #define COMP_OR_AFOPA6_Pos (0U)
21280 #define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos)
21281 #define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
21282 #define COMP_OR_AFOPA8_Pos (1U)
21283 #define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos)
21284 #define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
21285 #define COMP_OR_AFOPB12_Pos (2U)
21286 #define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos)
21287 #define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
21288 #define COMP_OR_AFOPE6_Pos (3U)
21289 #define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos)
21290 #define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
21291 #define COMP_OR_AFOPE15_Pos (4U)
21292 #define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos)
21293 #define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
21294 #define COMP_OR_AFOPG2_Pos (5U)
21295 #define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos)
21296 #define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
21297 #define COMP_OR_AFOPG3_Pos (6U)
21298 #define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos)
21299 #define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
21300 #define COMP_OR_AFOPG4_Pos (7U)
21301 #define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos)
21302 #define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
21303 #define COMP_OR_AFOPI1_Pos (8U)
21304 #define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos)
21305 #define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
21306 #define COMP_OR_AFOPI4_Pos (9U)
21307 #define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos)
21308 #define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
21309 #define COMP_OR_AFOPK2_Pos (10U)
21310 #define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos)
21311 #define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
21312 
21314 #define COMP_CFGRx_EN_Pos (0U)
21315 #define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos)
21316 #define COMP_CFGRx_EN COMP_CFGRx_EN_Msk
21317 #define COMP_CFGRx_BRGEN_Pos (1U)
21318 #define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos)
21319 #define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk
21320 #define COMP_CFGRx_SCALEN_Pos (2U)
21321 #define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos)
21322 #define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk
21323 #define COMP_CFGRx_POLARITY_Pos (3U)
21324 #define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos)
21325 #define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk
21326 #define COMP_CFGRx_WINMODE_Pos (4U)
21327 #define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos)
21328 #define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk
21329 #define COMP_CFGRx_ITEN_Pos (6U)
21330 #define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos)
21331 #define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk
21332 #define COMP_CFGRx_HYST_Pos (8U)
21333 #define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos)
21334 #define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk
21335 #define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos)
21336 #define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos)
21337 #define COMP_CFGRx_PWRMODE_Pos (12U)
21338 #define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos)
21339 #define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk
21340 #define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos)
21341 #define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos)
21342 #define COMP_CFGRx_INMSEL_Pos (16U)
21343 #define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos)
21344 #define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk
21345 #define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos)
21346 #define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos)
21347 #define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos)
21348 #define COMP_CFGRx_INPSEL_Pos (20U)
21349 #define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos)
21350 #define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk
21351 #define COMP_CFGRx_BLANKING_Pos (24U)
21352 #define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos)
21353 #define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk
21354 #define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos)
21355 #define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos)
21356 #define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos)
21357 #define COMP_CFGRx_LOCK_Pos (31U)
21358 #define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos)
21359 #define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk
21362 /******************************************************************************/
21363 /* */
21364 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
21365 /* */
21366 /******************************************************************************/
21367 /****************** Bit definition for USART_CR1 register *******************/
21368 #define USART_CR1_UE_Pos (0U)
21369 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
21370 #define USART_CR1_UE USART_CR1_UE_Msk
21371 #define USART_CR1_UESM_Pos (1U)
21372 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
21373 #define USART_CR1_UESM USART_CR1_UESM_Msk
21374 #define USART_CR1_RE_Pos (2U)
21375 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
21376 #define USART_CR1_RE USART_CR1_RE_Msk
21377 #define USART_CR1_TE_Pos (3U)
21378 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
21379 #define USART_CR1_TE USART_CR1_TE_Msk
21380 #define USART_CR1_IDLEIE_Pos (4U)
21381 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
21382 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
21383 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
21384 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)
21385 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk
21386 #define USART_CR1_TCIE_Pos (6U)
21387 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
21388 #define USART_CR1_TCIE USART_CR1_TCIE_Msk
21389 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
21390 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)
21391 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk
21392 #define USART_CR1_PEIE_Pos (8U)
21393 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
21394 #define USART_CR1_PEIE USART_CR1_PEIE_Msk
21395 #define USART_CR1_PS_Pos (9U)
21396 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
21397 #define USART_CR1_PS USART_CR1_PS_Msk
21398 #define USART_CR1_PCE_Pos (10U)
21399 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
21400 #define USART_CR1_PCE USART_CR1_PCE_Msk
21401 #define USART_CR1_WAKE_Pos (11U)
21402 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
21403 #define USART_CR1_WAKE USART_CR1_WAKE_Msk
21404 #define USART_CR1_M_Pos (12U)
21405 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
21406 #define USART_CR1_M USART_CR1_M_Msk
21407 #define USART_CR1_M0_Pos (12U)
21408 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
21409 #define USART_CR1_M0 USART_CR1_M0_Msk
21410 #define USART_CR1_MME_Pos (13U)
21411 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
21412 #define USART_CR1_MME USART_CR1_MME_Msk
21413 #define USART_CR1_CMIE_Pos (14U)
21414 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
21415 #define USART_CR1_CMIE USART_CR1_CMIE_Msk
21416 #define USART_CR1_OVER8_Pos (15U)
21417 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
21418 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk
21419 #define USART_CR1_DEDT_Pos (16U)
21420 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
21421 #define USART_CR1_DEDT USART_CR1_DEDT_Msk
21422 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
21423 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
21424 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
21425 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
21426 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
21427 #define USART_CR1_DEAT_Pos (21U)
21428 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
21429 #define USART_CR1_DEAT USART_CR1_DEAT_Msk
21430 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
21431 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
21432 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
21433 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
21434 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
21435 #define USART_CR1_RTOIE_Pos (26U)
21436 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
21437 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
21438 #define USART_CR1_EOBIE_Pos (27U)
21439 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
21440 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
21441 #define USART_CR1_M1_Pos (28U)
21442 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
21443 #define USART_CR1_M1 USART_CR1_M1_Msk
21444 #define USART_CR1_FIFOEN_Pos (29U)
21445 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)
21446 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk
21447 #define USART_CR1_TXFEIE_Pos (30U)
21448 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)
21449 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk
21450 #define USART_CR1_RXFFIE_Pos (31U)
21451 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)
21452 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk
21454 /* Legacy define */
21455 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
21456 #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
21457 
21458 /****************** Bit definition for USART_CR2 register *******************/
21459 #define USART_CR2_SLVEN_Pos (0U)
21460 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)
21461 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk
21462 #define USART_CR2_DIS_NSS_Pos (3U)
21463 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)
21464 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk
21465 #define USART_CR2_ADDM7_Pos (4U)
21466 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
21467 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
21468 #define USART_CR2_LBDL_Pos (5U)
21469 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
21470 #define USART_CR2_LBDL USART_CR2_LBDL_Msk
21471 #define USART_CR2_LBDIE_Pos (6U)
21472 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
21473 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
21474 #define USART_CR2_LBCL_Pos (8U)
21475 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
21476 #define USART_CR2_LBCL USART_CR2_LBCL_Msk
21477 #define USART_CR2_CPHA_Pos (9U)
21478 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
21479 #define USART_CR2_CPHA USART_CR2_CPHA_Msk
21480 #define USART_CR2_CPOL_Pos (10U)
21481 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
21482 #define USART_CR2_CPOL USART_CR2_CPOL_Msk
21483 #define USART_CR2_CLKEN_Pos (11U)
21484 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
21485 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
21486 #define USART_CR2_STOP_Pos (12U)
21487 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
21488 #define USART_CR2_STOP USART_CR2_STOP_Msk
21489 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
21490 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
21491 #define USART_CR2_LINEN_Pos (14U)
21492 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
21493 #define USART_CR2_LINEN USART_CR2_LINEN_Msk
21494 #define USART_CR2_SWAP_Pos (15U)
21495 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
21496 #define USART_CR2_SWAP USART_CR2_SWAP_Msk
21497 #define USART_CR2_RXINV_Pos (16U)
21498 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
21499 #define USART_CR2_RXINV USART_CR2_RXINV_Msk
21500 #define USART_CR2_TXINV_Pos (17U)
21501 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
21502 #define USART_CR2_TXINV USART_CR2_TXINV_Msk
21503 #define USART_CR2_DATAINV_Pos (18U)
21504 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
21505 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
21506 #define USART_CR2_MSBFIRST_Pos (19U)
21507 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
21508 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
21509 #define USART_CR2_ABREN_Pos (20U)
21510 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
21511 #define USART_CR2_ABREN USART_CR2_ABREN_Msk
21512 #define USART_CR2_ABRMODE_Pos (21U)
21513 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
21514 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
21515 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
21516 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
21517 #define USART_CR2_RTOEN_Pos (23U)
21518 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
21519 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
21520 #define USART_CR2_ADD_Pos (24U)
21521 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
21522 #define USART_CR2_ADD USART_CR2_ADD_Msk
21524 /****************** Bit definition for USART_CR3 register *******************/
21525 #define USART_CR3_EIE_Pos (0U)
21526 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
21527 #define USART_CR3_EIE USART_CR3_EIE_Msk
21528 #define USART_CR3_IREN_Pos (1U)
21529 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
21530 #define USART_CR3_IREN USART_CR3_IREN_Msk
21531 #define USART_CR3_IRLP_Pos (2U)
21532 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
21533 #define USART_CR3_IRLP USART_CR3_IRLP_Msk
21534 #define USART_CR3_HDSEL_Pos (3U)
21535 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
21536 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
21537 #define USART_CR3_NACK_Pos (4U)
21538 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
21539 #define USART_CR3_NACK USART_CR3_NACK_Msk
21540 #define USART_CR3_SCEN_Pos (5U)
21541 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
21542 #define USART_CR3_SCEN USART_CR3_SCEN_Msk
21543 #define USART_CR3_DMAR_Pos (6U)
21544 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
21545 #define USART_CR3_DMAR USART_CR3_DMAR_Msk
21546 #define USART_CR3_DMAT_Pos (7U)
21547 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
21548 #define USART_CR3_DMAT USART_CR3_DMAT_Msk
21549 #define USART_CR3_RTSE_Pos (8U)
21550 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
21551 #define USART_CR3_RTSE USART_CR3_RTSE_Msk
21552 #define USART_CR3_CTSE_Pos (9U)
21553 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
21554 #define USART_CR3_CTSE USART_CR3_CTSE_Msk
21555 #define USART_CR3_CTSIE_Pos (10U)
21556 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
21557 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
21558 #define USART_CR3_ONEBIT_Pos (11U)
21559 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
21560 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
21561 #define USART_CR3_OVRDIS_Pos (12U)
21562 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
21563 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
21564 #define USART_CR3_DDRE_Pos (13U)
21565 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
21566 #define USART_CR3_DDRE USART_CR3_DDRE_Msk
21567 #define USART_CR3_DEM_Pos (14U)
21568 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
21569 #define USART_CR3_DEM USART_CR3_DEM_Msk
21570 #define USART_CR3_DEP_Pos (15U)
21571 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
21572 #define USART_CR3_DEP USART_CR3_DEP_Msk
21573 #define USART_CR3_SCARCNT_Pos (17U)
21574 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
21575 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
21576 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
21577 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
21578 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
21579 #define USART_CR3_WUS_Pos (20U)
21580 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
21581 #define USART_CR3_WUS USART_CR3_WUS_Msk
21582 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
21583 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
21584 #define USART_CR3_WUFIE_Pos (22U)
21585 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
21586 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
21587 #define USART_CR3_TXFTIE_Pos (23U)
21588 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)
21589 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk
21590 #define USART_CR3_TCBGTIE_Pos (24U)
21591 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
21592 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
21593 #define USART_CR3_RXFTCFG_Pos (25U)
21594 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)
21595 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk
21596 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)
21597 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)
21598 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)
21599 #define USART_CR3_RXFTIE_Pos (28U)
21600 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)
21601 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk
21602 #define USART_CR3_TXFTCFG_Pos (29U)
21603 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)
21604 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk
21605 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)
21606 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)
21607 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)
21609 /****************** Bit definition for USART_BRR register *******************/
21610 #define USART_BRR_DIV_FRACTION_Pos (0U)
21611 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
21612 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
21613 #define USART_BRR_DIV_MANTISSA_Pos (4U)
21614 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
21615 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
21617 /****************** Bit definition for USART_GTPR register ******************/
21618 #define USART_GTPR_PSC_Pos (0U)
21619 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
21620 #define USART_GTPR_PSC USART_GTPR_PSC_Msk
21621 #define USART_GTPR_GT_Pos (8U)
21622 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
21623 #define USART_GTPR_GT USART_GTPR_GT_Msk
21625 /******************* Bit definition for USART_RTOR register *****************/
21626 #define USART_RTOR_RTO_Pos (0U)
21627 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
21628 #define USART_RTOR_RTO USART_RTOR_RTO_Msk
21629 #define USART_RTOR_BLEN_Pos (24U)
21630 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
21631 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
21633 /******************* Bit definition for USART_RQR register ******************/
21634 #define USART_RQR_ABRRQ_Pos (0U)
21635 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
21636 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
21637 #define USART_RQR_SBKRQ_Pos (1U)
21638 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
21639 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
21640 #define USART_RQR_MMRQ_Pos (2U)
21641 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
21642 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
21643 #define USART_RQR_RXFRQ_Pos (3U)
21644 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
21645 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
21646 #define USART_RQR_TXFRQ_Pos (4U)
21647 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
21648 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
21650 /******************* Bit definition for USART_ISR register ******************/
21651 #define USART_ISR_PE_Pos (0U)
21652 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
21653 #define USART_ISR_PE USART_ISR_PE_Msk
21654 #define USART_ISR_FE_Pos (1U)
21655 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
21656 #define USART_ISR_FE USART_ISR_FE_Msk
21657 #define USART_ISR_NE_Pos (2U)
21658 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
21659 #define USART_ISR_NE USART_ISR_NE_Msk
21660 #define USART_ISR_ORE_Pos (3U)
21661 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
21662 #define USART_ISR_ORE USART_ISR_ORE_Msk
21663 #define USART_ISR_IDLE_Pos (4U)
21664 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
21665 #define USART_ISR_IDLE USART_ISR_IDLE_Msk
21666 #define USART_ISR_RXNE_RXFNE_Pos (5U)
21667 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)
21668 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk
21669 #define USART_ISR_TC_Pos (6U)
21670 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
21671 #define USART_ISR_TC USART_ISR_TC_Msk
21672 #define USART_ISR_TXE_TXFNF_Pos (7U)
21673 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)
21674 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk
21675 #define USART_ISR_LBDF_Pos (8U)
21676 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
21677 #define USART_ISR_LBDF USART_ISR_LBDF_Msk
21678 #define USART_ISR_CTSIF_Pos (9U)
21679 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
21680 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
21681 #define USART_ISR_CTS_Pos (10U)
21682 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
21683 #define USART_ISR_CTS USART_ISR_CTS_Msk
21684 #define USART_ISR_RTOF_Pos (11U)
21685 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
21686 #define USART_ISR_RTOF USART_ISR_RTOF_Msk
21687 #define USART_ISR_EOBF_Pos (12U)
21688 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
21689 #define USART_ISR_EOBF USART_ISR_EOBF_Msk
21690 #define USART_ISR_UDR_Pos (13U)
21691 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)
21692 #define USART_ISR_UDR USART_ISR_UDR_Msk
21693 #define USART_ISR_ABRE_Pos (14U)
21694 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
21695 #define USART_ISR_ABRE USART_ISR_ABRE_Msk
21696 #define USART_ISR_ABRF_Pos (15U)
21697 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
21698 #define USART_ISR_ABRF USART_ISR_ABRF_Msk
21699 #define USART_ISR_BUSY_Pos (16U)
21700 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
21701 #define USART_ISR_BUSY USART_ISR_BUSY_Msk
21702 #define USART_ISR_CMF_Pos (17U)
21703 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
21704 #define USART_ISR_CMF USART_ISR_CMF_Msk
21705 #define USART_ISR_SBKF_Pos (18U)
21706 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
21707 #define USART_ISR_SBKF USART_ISR_SBKF_Msk
21708 #define USART_ISR_RWU_Pos (19U)
21709 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
21710 #define USART_ISR_RWU USART_ISR_RWU_Msk
21711 #define USART_ISR_WUF_Pos (20U)
21712 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
21713 #define USART_ISR_WUF USART_ISR_WUF_Msk
21714 #define USART_ISR_TEACK_Pos (21U)
21715 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
21716 #define USART_ISR_TEACK USART_ISR_TEACK_Msk
21717 #define USART_ISR_REACK_Pos (22U)
21718 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
21719 #define USART_ISR_REACK USART_ISR_REACK_Msk
21720 #define USART_ISR_TXFE_Pos (23U)
21721 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)
21722 #define USART_ISR_TXFE USART_ISR_TXFE_Msk
21723 #define USART_ISR_RXFF_Pos (24U)
21724 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)
21725 #define USART_ISR_RXFF USART_ISR_RXFF_Msk
21726 #define USART_ISR_TCBGT_Pos (25U)
21727 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
21728 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
21729 #define USART_ISR_RXFT_Pos (26U)
21730 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)
21731 #define USART_ISR_RXFT USART_ISR_RXFT_Msk
21732 #define USART_ISR_TXFT_Pos (27U)
21733 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)
21734 #define USART_ISR_TXFT USART_ISR_TXFT_Msk
21736 /******************* Bit definition for USART_ICR register ******************/
21737 #define USART_ICR_PECF_Pos (0U)
21738 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
21739 #define USART_ICR_PECF USART_ICR_PECF_Msk
21740 #define USART_ICR_FECF_Pos (1U)
21741 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
21742 #define USART_ICR_FECF USART_ICR_FECF_Msk
21743 #define USART_ICR_NECF_Pos (2U)
21744 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
21745 #define USART_ICR_NECF USART_ICR_NECF_Msk
21746 #define USART_ICR_ORECF_Pos (3U)
21747 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
21748 #define USART_ICR_ORECF USART_ICR_ORECF_Msk
21749 #define USART_ICR_IDLECF_Pos (4U)
21750 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
21751 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
21752 #define USART_ICR_TXFECF_Pos (5U)
21753 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)
21754 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk
21755 #define USART_ICR_TCCF_Pos (6U)
21756 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
21757 #define USART_ICR_TCCF USART_ICR_TCCF_Msk
21758 #define USART_ICR_TCBGTCF_Pos (7U)
21759 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
21760 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
21761 #define USART_ICR_LBDCF_Pos (8U)
21762 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
21763 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
21764 #define USART_ICR_CTSCF_Pos (9U)
21765 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
21766 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
21767 #define USART_ICR_RTOCF_Pos (11U)
21768 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
21769 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
21770 #define USART_ICR_EOBCF_Pos (12U)
21771 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
21772 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
21773 #define USART_ICR_UDRCF_Pos (13U)
21774 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)
21775 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk
21776 #define USART_ICR_CMCF_Pos (17U)
21777 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
21778 #define USART_ICR_CMCF USART_ICR_CMCF_Msk
21779 #define USART_ICR_WUCF_Pos (20U)
21780 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
21781 #define USART_ICR_WUCF USART_ICR_WUCF_Msk
21783 /******************* Bit definition for USART_RDR register ******************/
21784 #define USART_RDR_RDR_Pos (0U)
21785 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
21786 #define USART_RDR_RDR USART_RDR_RDR_Msk
21788 /******************* Bit definition for USART_TDR register ******************/
21789 #define USART_TDR_TDR_Pos (0U)
21790 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
21791 #define USART_TDR_TDR USART_TDR_TDR_Msk
21793 /******************* Bit definition for USART_PRESC register ******************/
21794 #define USART_PRESC_PRESCALER_Pos (0U)
21795 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)
21796 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk
21797 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)
21798 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)
21799 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)
21800 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)
21802 /******************************************************************************/
21803 /* */
21804 /* Single Wire Protocol Master Interface (SWPMI) */
21805 /* */
21806 /******************************************************************************/
21807 
21808 /******************* Bit definition for SWPMI_CR register ********************/
21809 #define SWPMI_CR_RXDMA_Pos (0U)
21810 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
21811 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
21812 #define SWPMI_CR_TXDMA_Pos (1U)
21813 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
21814 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
21815 #define SWPMI_CR_RXMODE_Pos (2U)
21816 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
21817 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
21818 #define SWPMI_CR_TXMODE_Pos (3U)
21819 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
21820 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
21821 #define SWPMI_CR_LPBK_Pos (4U)
21822 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
21823 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
21824 #define SWPMI_CR_SWPACT_Pos (5U)
21825 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
21826 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
21827 #define SWPMI_CR_DEACT_Pos (10U)
21828 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
21829 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
21830 #define SWPMI_CR_SWPEN_Pos (11U)
21831 #define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos)
21832 #define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk
21834 /******************* Bit definition for SWPMI_BRR register ********************/
21835 #define SWPMI_BRR_BR_Pos (0U)
21836 #define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos)
21837 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
21839 /******************* Bit definition for SWPMI_ISR register ********************/
21840 #define SWPMI_ISR_RXBFF_Pos (0U)
21841 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
21842 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
21843 #define SWPMI_ISR_TXBEF_Pos (1U)
21844 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
21845 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
21846 #define SWPMI_ISR_RXBERF_Pos (2U)
21847 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
21848 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
21849 #define SWPMI_ISR_RXOVRF_Pos (3U)
21850 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
21851 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
21852 #define SWPMI_ISR_TXUNRF_Pos (4U)
21853 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
21854 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
21855 #define SWPMI_ISR_RXNE_Pos (5U)
21856 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
21857 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
21858 #define SWPMI_ISR_TXE_Pos (6U)
21859 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
21860 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
21861 #define SWPMI_ISR_TCF_Pos (7U)
21862 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
21863 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
21864 #define SWPMI_ISR_SRF_Pos (8U)
21865 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
21866 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
21867 #define SWPMI_ISR_SUSP_Pos (9U)
21868 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
21869 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
21870 #define SWPMI_ISR_DEACTF_Pos (10U)
21871 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
21872 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
21873 #define SWPMI_ISR_RDYF_Pos (11U)
21874 #define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos)
21875 #define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk
21877 /******************* Bit definition for SWPMI_ICR register ********************/
21878 #define SWPMI_ICR_CRXBFF_Pos (0U)
21879 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
21880 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
21881 #define SWPMI_ICR_CTXBEF_Pos (1U)
21882 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
21883 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
21884 #define SWPMI_ICR_CRXBERF_Pos (2U)
21885 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
21886 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
21887 #define SWPMI_ICR_CRXOVRF_Pos (3U)
21888 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
21889 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
21890 #define SWPMI_ICR_CTXUNRF_Pos (4U)
21891 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
21892 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
21893 #define SWPMI_ICR_CTCF_Pos (7U)
21894 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
21895 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
21896 #define SWPMI_ICR_CSRF_Pos (8U)
21897 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
21898 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
21899 #define SWPMI_ICR_CRDYF_Pos (11U)
21900 #define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos)
21901 #define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk
21903 /******************* Bit definition for SWPMI_IER register ********************/
21904 #define SWPMI_IER_RXBFIE_Pos (0U)
21905 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
21906 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
21907 #define SWPMI_IER_TXBEIE_Pos (1U)
21908 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
21909 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
21910 #define SWPMI_IER_RXBERIE_Pos (2U)
21911 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
21912 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
21913 #define SWPMI_IER_RXOVRIE_Pos (3U)
21914 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
21915 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
21916 #define SWPMI_IER_TXUNRIE_Pos (4U)
21917 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
21918 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
21919 #define SWPMI_IER_RIE_Pos (5U)
21920 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
21921 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
21922 #define SWPMI_IER_TIE_Pos (6U)
21923 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
21924 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
21925 #define SWPMI_IER_TCIE_Pos (7U)
21926 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
21927 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
21928 #define SWPMI_IER_SRIE_Pos (8U)
21929 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
21930 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
21931 #define SWPMI_IER_RDYIE_Pos (11U)
21932 #define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos)
21933 #define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk
21935 /******************* Bit definition for SWPMI_RFL register ********************/
21936 #define SWPMI_RFL_RFL_Pos (0U)
21937 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
21938 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
21939 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003)
21941 /******************* Bit definition for SWPMI_TDR register ********************/
21942 #define SWPMI_TDR_TD_Pos (0U)
21943 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
21944 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
21946 /******************* Bit definition for SWPMI_RDR register ********************/
21947 #define SWPMI_RDR_RD_Pos (0U)
21948 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
21949 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
21952 /******************* Bit definition for SWPMI_OR register ********************/
21953 #define SWPMI_OR_TBYP_Pos (0U)
21954 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
21955 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
21956 #define SWPMI_OR_CLASS_Pos (1U)
21957 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
21958 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
21960 /******************************************************************************/
21961 /* */
21962 /* Window WATCHDOG */
21963 /* */
21964 /******************************************************************************/
21965 /******************* Bit definition for WWDG_CR register ********************/
21966 #define WWDG_CR_T_Pos (0U)
21967 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
21968 #define WWDG_CR_T WWDG_CR_T_Msk
21969 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
21970 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
21971 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
21972 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
21973 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
21974 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
21975 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
21977 #define WWDG_CR_WDGA_Pos (7U)
21978 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
21979 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
21981 /******************* Bit definition for WWDG_CFR register *******************/
21982 #define WWDG_CFR_W_Pos (0U)
21983 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
21984 #define WWDG_CFR_W WWDG_CFR_W_Msk
21985 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
21986 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
21987 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
21988 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
21989 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
21990 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
21991 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
21993 #define WWDG_CFR_EWI_Pos (9U)
21994 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
21995 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
21997 #define WWDG_CFR_WDGTB_Pos (11U)
21998 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)
21999 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
22000 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
22001 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
22002 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)
22004 /******************* Bit definition for WWDG_SR register ********************/
22005 #define WWDG_SR_EWIF_Pos (0U)
22006 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
22007 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
22010 /******************************************************************************/
22011 /* */
22012 /* DBG */
22013 /* */
22014 /******************************************************************************/
22015 /********************************* DEVICE ID ********************************/
22016 #define STM32H7_DEV_ID 0x483UL
22017 
22018 /******************** Bit definition for DBGMCU_IDCODE register *************/
22019 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
22020 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
22021 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
22022 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
22023 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
22024 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
22025 
22026 /******************** Bit definition for DBGMCU_CR register *****************/
22027 #define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
22028 #define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos)
22029 #define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
22030 #define DBGMCU_CR_DBG_STOPD1_Pos (1U)
22031 #define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)
22032 #define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
22033 #define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
22034 #define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos)
22035 #define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
22036 #define DBGMCU_CR_DBG_STOPD3_Pos (7U)
22037 #define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)
22038 #define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
22039 #define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
22040 #define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos)
22041 #define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
22042 #define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
22043 #define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos)
22044 #define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
22045 #define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
22046 #define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)
22047 #define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
22048 #define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
22049 #define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)
22050 #define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
22051 #define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
22052 #define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)
22053 #define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
22054 
22055 /******************** Bit definition for APB3FZ1 register ************/
22056 #define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
22057 #define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos)
22058 #define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
22059 /******************** Bit definition for APB1LFZ1 register ************/
22060 #define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
22061 #define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos)
22062 #define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
22063 #define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
22064 #define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos)
22065 #define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
22066 #define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
22067 #define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos)
22068 #define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
22069 #define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
22070 #define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos)
22071 #define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
22072 #define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
22073 #define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos)
22074 #define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
22075 #define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
22076 #define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos)
22077 #define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
22078 #define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
22079 #define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos)
22080 #define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
22081 #define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
22082 #define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos)
22083 #define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
22084 #define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
22085 #define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos)
22086 #define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
22087 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
22088 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos)
22089 #define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
22090 #define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
22091 #define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos)
22092 #define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
22093 #define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
22094 #define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos)
22095 #define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
22096 #define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
22097 #define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos)
22098 #define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
22099 #define DBGMCU_APB1LFZ1_DBG_I2C5_Pos (25U)
22100 #define DBGMCU_APB1LFZ1_DBG_I2C5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C5_Pos)
22101 #define DBGMCU_APB1LFZ1_DBG_I2C5 DBGMCU_APB1LFZ1_DBG_I2C5_Msk
22102 
22103 /******************** Bit definition for APB1HFZ1 register ************/
22104 #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U)
22105 #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos)
22106 #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk
22107 #define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U)
22108 #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos)
22109 #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk
22110 /******************** Bit definition for APB2FZ1 register ************/
22111 #define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
22112 #define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos)
22113 #define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
22114 #define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
22115 #define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos)
22116 #define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
22117 #define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
22118 #define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos)
22119 #define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
22120 #define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
22121 #define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos)
22122 #define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
22123 #define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
22124 #define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos)
22125 #define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
22126 /******************** Bit definition for APB4FZ1 register ************/
22127 #define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
22128 #define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos)
22129 #define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
22130 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
22131 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos)
22132 #define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
22133 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
22134 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos)
22135 #define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
22136 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
22137 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos)
22138 #define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
22139 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
22140 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos)
22141 #define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
22142 #define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
22143 #define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos)
22144 #define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
22145 #define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
22146 #define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos)
22147 #define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
22148 /******************** Bit definition for DBGMCU_PIDR4 register ************/
22149 #define DBGMCU_PIDR4_JEP106CON_Pos (0U)
22150 #define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)
22151 #define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk
22152 #define DBGMCU_PIDR4_4KCOUNT_Pos (4U)
22153 #define DBGMCU_PIDR4_4KCOUNT_Msk (0xFUL << DBGMCU_PIDR4_4KCOUNT_Pos)
22154 #define DBGMCU_PIDR4_4KCOUNT DBGMCU_PIDR4_4KCOUNT_Msk
22155 /******************** Bit definition for DBGMCU_PIDR0 register ************/
22156 #define DBGMCU_PIDR0_PARTNUM_Pos (0U)
22157 #define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)
22158 #define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk
22159 /******************** Bit definition for DBGMCU_PIDR1 register ************/
22160 #define DBGMCU_PIDR1_PARTNUM_Pos (0U)
22161 #define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)
22162 #define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk
22163 #define DBGMCU_PIDR1_JEP106ID_Pos (4U)
22164 #define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)
22165 #define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk
22166 /******************** Bit definition for DBGMCU_PIDR2 register ************/
22167 #define DBGMCU_PIDR2_JEP106ID_Pos (0U)
22168 #define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)
22169 #define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk
22170 #define DBGMCU_PIDR2_JEDEC_Pos (3U)
22171 #define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)
22172 #define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk
22173 #define DBGMCU_PIDR2_REVISION_Pos (4U)
22174 #define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos)
22175 #define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk
22176 /******************** Bit definition for DBGMCU_PIDR3 register ************/
22177 #define DBGMCU_PIDR3_CMOD_Pos (0U)
22178 #define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos)
22179 #define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk
22180 #define DBGMCU_PIDR3_REVAND_Pos (4U)
22181 #define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos)
22182 #define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk
22183 /******************** Bit definition for DBGMCU_CIDR0 register ************/
22184 #define DBGMCU_CIR0_PREAMBLE_Pos (0U)
22185 #define DBGMCU_CIR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIR0_PREAMBLE_Pos)
22186 #define DBGMCU_CIR0_PREAMBLE DBGMCU_CIR0_PREAMBLE_Msk
22187 /******************** Bit definition for DBGMCU_CIDR1 register ************/
22188 #define DBGMCU_CIR1_PREAMBLE_Pos (0U)
22189 #define DBGMCU_CIR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIR1_PREAMBLE_Pos)
22190 #define DBGMCU_CIR1_PREAMBLE DBGMCU_CIR1_PREAMBLE_Msk
22191 #define DBGMCU_CIR1_CLASS_Pos (4U)
22192 #define DBGMCU_CIR1_CLASS_Msk (0xFUL << DBGMCU_CIR1_CLASS_Pos)
22193 #define DBGMCU_CIR1_CLASS DBGMCU_CIR1_CLASS_Msk
22194 /******************** Bit definition for DBGMCU_CIDR2 register ************/
22195 #define DBGMCU_CIR2_PREAMBLE_Pos (0U)
22196 #define DBGMCU_CIR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIR2_PREAMBLE_Pos)
22197 #define DBGMCU_CIR2_PREAMBLE DBGMCU_CIR2_PREAMBLE_Msk
22198 /******************** Bit definition for DBGMCU_CIDR3 register ************/
22199 #define DBGMCU_CIR3_PREAMBLE_Pos (0U)
22200 #define DBGMCU_CIR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIR3_PREAMBLE_Pos)
22201 #define DBGMCU_CIR3_PREAMBLE DBGMCU_CIR3_PREAMBLE_Msk
22202 /******************************************************************************/
22203 /* */
22204 /* RAM ECC monitoring */
22205 /* */
22206 /******************************************************************************/
22207 /****************** Bit definition for RAMECC_IER register ******************/
22208 #define RAMECC_IER_GECCDEBWIE_Pos (3U)
22209 #define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)
22210 #define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk
22211 #define RAMECC_IER_GECCDEIE_Pos (2U)
22212 #define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos)
22213 #define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk
22214 #define RAMECC_IER_GECCSEIE_Pos (1U)
22215 #define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos)
22216 #define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk
22217 #define RAMECC_IER_GIE_Pos (0U)
22218 #define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos)
22219 #define RAMECC_IER_GIE RAMECC_IER_GIE_Msk
22221 /******************* Bit definition for RAMECC_CR register ******************/
22222 #define RAMECC_CR_ECCELEN_Pos (5U)
22223 #define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos)
22224 #define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk
22225 #define RAMECC_CR_ECCDEBWIE_Pos (4U)
22226 #define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)
22227 #define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk
22228 #define RAMECC_CR_ECCDEIE_Pos (3U)
22229 #define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos)
22230 #define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk
22231 #define RAMECC_CR_ECCSEIE_Pos (2U)
22232 #define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos)
22233 #define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk
22235 /******************* Bit definition for RAMECC_SR register ******************/
22236 #define RAMECC_SR_DEBWDF_Pos (2U)
22237 #define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos)
22238 #define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk
22239 #define RAMECC_SR_DEDF_Pos (1U)
22240 #define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos)
22241 #define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk
22242 #define RAMECC_SR_SEDCF_Pos (0U)
22243 #define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos)
22244 #define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk
22246 /****************** Bit definition for RAMECC_FAR register ******************/
22247 #define RAMECC_FAR_FADD_Pos (0U)
22248 #define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)
22249 #define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk
22251 /****************** Bit definition for RAMECC_FDRL register *****************/
22252 #define RAMECC_FAR_FDATAL_Pos (0U)
22253 #define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)
22254 #define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk
22256 /****************** Bit definition for RAMECC_FDRH register *****************/
22257 #define RAMECC_FAR_FDATAH_Pos (0U)
22258 #define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)
22259 #define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
22260 
22261 /***************** Bit definition for RAMECC_FECR register ******************/
22262 #define RAMECC_FECR_FEC_Pos (0U)
22263 #define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)
22264 #define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk
22266 /******************************************************************************/
22267 /* */
22268 /* MDIOS */
22269 /* */
22270 /******************************************************************************/
22271 /******************** Bit definition for MDIOS_CR register *******************/
22272 #define MDIOS_CR_EN_Pos (0U)
22273 #define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos)
22274 #define MDIOS_CR_EN MDIOS_CR_EN_Msk
22275 #define MDIOS_CR_WRIE_Pos (1U)
22276 #define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos)
22277 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk
22278 #define MDIOS_CR_RDIE_Pos (2U)
22279 #define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos)
22280 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk
22281 #define MDIOS_CR_EIE_Pos (3U)
22282 #define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos)
22283 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk
22284 #define MDIOS_CR_DPC_Pos (7U)
22285 #define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos)
22286 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk
22287 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
22288 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)
22289 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk
22290 #define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)
22291 #define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)
22292 #define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)
22293 #define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)
22294 #define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)
22296 /******************** Bit definition for MDIOS_SR register *******************/
22297 #define MDIOS_SR_PERF_Pos (0U)
22298 #define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos)
22299 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk
22300 #define MDIOS_SR_SERF_Pos (1U)
22301 #define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos)
22302 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk
22303 #define MDIOS_SR_TERF_Pos (2U)
22304 #define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos)
22305 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk
22307 /******************** Bit definition for MDIOS_CLRFR register *******************/
22308 #define MDIOS_SR_CPERF_Pos (0U)
22309 #define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos)
22310 #define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk
22311 #define MDIOS_SR_CSERF_Pos (1U)
22312 #define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos)
22313 #define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk
22314 #define MDIOS_SR_CTERF_Pos (2U)
22315 #define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos)
22316 #define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk
22318 /******************************************************************************/
22319 /* */
22320 /* USB_OTG */
22321 /* */
22322 /******************************************************************************/
22323 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
22324 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
22325 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
22326 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
22327 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
22328 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
22329 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
22330 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
22331 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
22332 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
22333 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
22334 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
22335 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
22336 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
22337 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
22338 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
22339 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
22340 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
22341 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
22342 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
22343 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
22344 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
22345 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
22346 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
22347 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
22348 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
22349 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
22350 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
22351 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
22352 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
22353 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
22354 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
22355 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
22356 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
22357 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
22358 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
22359 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
22360 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
22361 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
22362 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
22363 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
22364 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
22365 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
22366 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
22367 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
22368 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
22369 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
22370 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
22371 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
22372 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
22373 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
22374 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
22375 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
22376 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
22377 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
22379 /******************** Bit definition forUSB_OTG_HCFG register ********************/
22380 
22381 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
22382 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
22383 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
22384 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
22385 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
22386 #define USB_OTG_HCFG_FSLSS_Pos (2U)
22387 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
22388 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
22390 /******************** Bit definition forUSB_OTG_DCFG register ********************/
22391 
22392 #define USB_OTG_DCFG_DSPD_Pos (0U)
22393 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
22394 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
22395 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
22396 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
22397 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
22398 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
22399 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
22401 #define USB_OTG_DCFG_DAD_Pos (4U)
22402 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
22403 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
22404 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
22405 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
22406 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
22407 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
22408 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
22409 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
22410 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
22412 #define USB_OTG_DCFG_PFIVL_Pos (11U)
22413 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
22414 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
22415 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
22416 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
22418 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
22419 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
22420 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
22421 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
22422 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
22424 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
22425 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
22426 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
22427 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
22428 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
22429 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
22430 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
22431 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
22432 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
22433 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
22435 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
22436 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
22437 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
22438 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
22439 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
22440 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
22441 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
22442 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
22443 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
22444 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
22445 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
22446 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
22447 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
22448 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
22449 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
22450 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
22451 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
22452 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
22453 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
22455 /******************** Bit definition forUSB_OTG_DCTL register ********************/
22456 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
22457 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
22458 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
22459 #define USB_OTG_DCTL_SDIS_Pos (1U)
22460 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
22461 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
22462 #define USB_OTG_DCTL_GINSTS_Pos (2U)
22463 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
22464 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
22465 #define USB_OTG_DCTL_GONSTS_Pos (3U)
22466 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
22467 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
22469 #define USB_OTG_DCTL_TCTL_Pos (4U)
22470 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
22471 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
22472 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
22473 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
22474 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
22475 #define USB_OTG_DCTL_SGINAK_Pos (7U)
22476 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
22477 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
22478 #define USB_OTG_DCTL_CGINAK_Pos (8U)
22479 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
22480 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
22481 #define USB_OTG_DCTL_SGONAK_Pos (9U)
22482 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
22483 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
22484 #define USB_OTG_DCTL_CGONAK_Pos (10U)
22485 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
22486 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
22487 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
22488 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
22489 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
22491 /******************** Bit definition forUSB_OTG_HFIR register ********************/
22492 #define USB_OTG_HFIR_FRIVL_Pos (0U)
22493 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
22494 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
22496 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
22497 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
22498 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
22499 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
22500 #define USB_OTG_HFNUM_FTREM_Pos (16U)
22501 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
22502 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
22504 /******************** Bit definition forUSB_OTG_DSTS register ********************/
22505 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
22506 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
22507 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
22509 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
22510 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
22511 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
22512 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
22513 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
22514 #define USB_OTG_DSTS_EERR_Pos (3U)
22515 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
22516 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
22517 #define USB_OTG_DSTS_FNSOF_Pos (8U)
22518 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
22519 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
22521 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
22522 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
22523 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
22524 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
22526 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
22527 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22528 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
22529 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22530 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22531 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22532 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22533 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22534 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
22535 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
22536 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
22537 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
22538 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
22539 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
22540 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
22541 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
22542 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
22544 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
22545 
22546 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
22547 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
22548 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
22549 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
22550 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
22551 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
22552 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
22553 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
22554 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
22555 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
22556 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
22557 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
22558 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
22559 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
22560 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
22562 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
22563 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
22564 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
22565 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
22566 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
22567 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
22568 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
22569 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
22570 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
22571 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
22572 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
22573 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
22574 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
22575 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
22576 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
22577 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
22578 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
22579 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
22580 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
22581 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
22582 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
22583 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
22584 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
22585 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
22586 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
22587 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
22588 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
22589 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
22590 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
22591 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
22592 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
22593 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
22594 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
22595 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
22596 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
22597 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
22598 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
22599 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
22600 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
22601 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
22602 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
22603 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
22604 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
22605 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
22606 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
22607 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
22609 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
22610 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
22611 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
22612 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
22613 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
22614 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
22615 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
22616 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
22617 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
22618 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
22619 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
22620 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
22621 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
22622 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
22623 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
22624 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
22626 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
22627 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22628 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
22629 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22630 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22631 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22632 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22633 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22634 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
22635 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
22636 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
22637 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
22638 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
22639 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
22641 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
22642 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
22643 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
22644 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
22645 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
22646 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
22647 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
22648 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
22649 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
22650 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
22651 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
22652 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
22653 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
22654 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
22655 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
22656 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
22657 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
22658 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
22659 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
22660 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
22661 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
22662 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
22663 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
22664 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
22665 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
22667 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
22668 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
22669 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
22670 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
22672 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
22673 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22674 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
22675 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22676 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22677 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22678 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22679 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22680 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22681 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22682 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22684 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
22685 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22686 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
22687 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22688 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22689 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22690 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22691 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22692 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22693 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22694 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22696 /******************** Bit definition forUSB_OTG_HAINT register ********************/
22697 #define USB_OTG_HAINT_HAINT_Pos (0U)
22698 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
22699 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
22701 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
22702 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
22703 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
22704 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
22705 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
22706 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
22707 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
22708 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
22709 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
22710 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
22711 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
22712 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
22713 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
22714 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
22715 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
22716 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
22717 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
22718 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
22719 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
22720 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
22721 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
22722 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
22723 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
22724 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
22725 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
22726 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
22727 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
22728 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
22729 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
22730 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
22731 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
22732 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
22733 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
22734 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
22735 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
22736 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
22737 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
22739 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
22740 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
22741 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
22742 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
22743 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
22744 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
22745 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
22746 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
22747 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
22748 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
22749 #define USB_OTG_GINTSTS_SOF_Pos (3U)
22750 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
22751 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
22752 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
22753 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
22754 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
22755 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
22756 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
22757 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
22758 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
22759 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
22760 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
22761 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
22762 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
22763 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
22764 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
22765 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
22766 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
22767 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
22768 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
22769 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
22770 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
22771 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
22772 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
22773 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
22774 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
22775 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
22776 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
22777 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
22778 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
22779 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
22780 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
22781 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
22782 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
22783 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
22784 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
22785 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
22786 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
22787 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
22788 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
22789 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
22790 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
22791 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
22792 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
22793 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
22794 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
22795 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
22796 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
22797 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
22798 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
22799 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
22800 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
22801 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
22802 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
22803 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
22804 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
22805 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
22806 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
22807 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
22808 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
22809 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
22810 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
22811 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
22812 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
22813 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
22814 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
22815 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
22816 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
22817 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
22818 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
22819 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
22820 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
22821 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
22822 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
22823 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
22825 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
22826 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
22827 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
22828 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
22829 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
22830 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
22831 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
22832 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
22833 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
22834 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
22835 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
22836 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
22837 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
22838 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
22839 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
22840 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
22841 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
22842 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
22843 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
22844 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
22845 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
22846 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
22847 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
22848 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
22849 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
22850 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
22851 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
22852 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
22853 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
22854 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
22855 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
22856 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
22857 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
22858 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
22859 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
22860 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
22861 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
22862 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
22863 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
22864 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
22865 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
22866 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
22867 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
22868 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
22869 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
22870 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
22871 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
22872 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
22873 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
22874 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
22875 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
22876 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
22877 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
22878 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
22879 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
22880 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
22881 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
22882 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
22883 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
22884 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
22885 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
22886 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
22887 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
22888 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
22889 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
22890 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
22891 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
22892 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
22893 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
22894 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
22895 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
22896 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
22897 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
22898 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
22899 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
22900 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
22901 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
22902 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
22903 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
22904 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
22905 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
22906 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
22907 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
22908 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
22909 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
22911 /******************** Bit definition forUSB_OTG_DAINT register ********************/
22912 #define USB_OTG_DAINT_IEPINT_Pos (0U)
22913 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
22914 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
22915 #define USB_OTG_DAINT_OEPINT_Pos (16U)
22916 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
22917 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
22919 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
22920 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
22921 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
22922 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
22924 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
22925 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
22926 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
22927 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
22928 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
22929 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
22930 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
22931 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
22932 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
22933 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
22934 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
22935 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
22936 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
22938 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
22939 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
22940 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
22941 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
22942 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
22943 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
22944 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
22946 /******************** Bit definition for OTG register ********************/
22947 
22948 #define USB_OTG_CHNUM_Pos (0U)
22949 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
22950 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
22951 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
22952 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
22953 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
22954 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
22955 #define USB_OTG_BCNT_Pos (4U)
22956 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
22957 #define USB_OTG_BCNT USB_OTG_BCNT_Msk
22959 #define USB_OTG_DPID_Pos (15U)
22960 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
22961 #define USB_OTG_DPID USB_OTG_DPID_Msk
22962 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
22963 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
22965 #define USB_OTG_PKTSTS_Pos (17U)
22966 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
22967 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
22968 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
22969 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
22970 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
22971 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
22973 #define USB_OTG_EPNUM_Pos (0U)
22974 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
22975 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
22976 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
22977 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
22978 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
22979 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
22981 #define USB_OTG_FRMNUM_Pos (21U)
22982 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
22983 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
22984 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
22985 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
22986 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
22987 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
22989 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
22990 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
22991 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
22992 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
22994 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
22995 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
22996 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
22997 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
22999 /******************** Bit definition for OTG register ********************/
23000 #define USB_OTG_NPTXFSA_Pos (0U)
23001 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
23002 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
23003 #define USB_OTG_NPTXFD_Pos (16U)
23004 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
23005 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
23006 #define USB_OTG_TX0FSA_Pos (0U)
23007 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
23008 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
23009 #define USB_OTG_TX0FD_Pos (16U)
23010 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
23011 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
23013 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
23014 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
23015 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
23016 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
23018 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
23019 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
23020 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
23021 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
23023 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
23024 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23025 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
23026 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23027 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23028 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23029 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23030 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23031 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23032 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23033 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23035 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
23036 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23037 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
23038 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23039 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23040 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23041 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23042 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23043 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23044 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23046 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
23047 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
23048 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
23049 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
23050 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
23051 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
23052 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
23054 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
23055 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23056 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
23057 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23058 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23059 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23060 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23061 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23062 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23063 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23064 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23065 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23066 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
23067 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
23068 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
23070 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
23071 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23072 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
23073 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23074 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23075 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23076 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23077 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23078 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23079 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23080 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23081 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23082 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
23083 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
23084 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
23086 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
23087 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
23088 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
23089 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
23091 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
23092 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
23093 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
23094 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
23095 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
23096 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
23097 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
23099 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
23100 #define USB_OTG_GCCFG_DCDET_Pos (0U)
23101 #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
23102 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
23103 #define USB_OTG_GCCFG_PDET_Pos (1U)
23104 #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
23105 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
23106 #define USB_OTG_GCCFG_SDET_Pos (2U)
23107 #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
23108 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
23109 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
23110 #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
23111 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
23112 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
23113 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
23114 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
23115 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
23116 #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
23117 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
23118 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
23119 #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
23120 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
23121 #define USB_OTG_GCCFG_PDEN_Pos (19U)
23122 #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
23123 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
23124 #define USB_OTG_GCCFG_SDEN_Pos (20U)
23125 #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
23126 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
23127 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
23128 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
23129 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
23131 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
23132 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
23133 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos)
23134 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk
23135 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
23136 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos)
23137 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk
23139 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
23140 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
23141 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
23142 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
23143 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
23144 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
23145 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
23147 /******************** Bit definition forUSB_OTG_CID register ********************/
23148 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
23149 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
23150 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
23152 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
23153 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
23154 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
23155 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
23156 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
23157 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
23158 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
23159 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
23160 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
23161 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
23162 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
23163 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
23164 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
23165 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
23166 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
23167 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
23168 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
23169 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
23170 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
23171 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
23172 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
23173 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
23174 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
23175 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
23176 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
23177 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
23178 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
23179 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
23180 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
23181 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
23182 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
23183 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
23184 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
23185 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
23186 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
23187 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
23188 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
23189 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
23190 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
23191 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
23192 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
23193 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
23194 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
23195 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
23196 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
23197 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
23199 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
23200 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
23201 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
23202 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
23203 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
23204 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
23205 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
23206 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
23207 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
23208 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
23209 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
23210 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
23211 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
23212 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
23213 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
23214 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
23215 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
23216 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
23217 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
23218 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
23219 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
23220 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
23221 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
23222 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
23223 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
23224 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
23225 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
23226 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
23228 /******************** Bit definition forUSB_OTG_HPRT register ********************/
23229 #define USB_OTG_HPRT_PCSTS_Pos (0U)
23230 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
23231 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
23232 #define USB_OTG_HPRT_PCDET_Pos (1U)
23233 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
23234 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
23235 #define USB_OTG_HPRT_PENA_Pos (2U)
23236 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
23237 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
23238 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
23239 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
23240 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
23241 #define USB_OTG_HPRT_POCA_Pos (4U)
23242 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
23243 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
23244 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
23245 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
23246 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
23247 #define USB_OTG_HPRT_PRES_Pos (6U)
23248 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
23249 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
23250 #define USB_OTG_HPRT_PSUSP_Pos (7U)
23251 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
23252 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
23253 #define USB_OTG_HPRT_PRST_Pos (8U)
23254 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
23255 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
23257 #define USB_OTG_HPRT_PLSTS_Pos (10U)
23258 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
23259 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
23260 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
23261 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
23262 #define USB_OTG_HPRT_PPWR_Pos (12U)
23263 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
23264 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
23266 #define USB_OTG_HPRT_PTCTL_Pos (13U)
23267 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
23268 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
23269 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
23270 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
23271 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
23272 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
23274 #define USB_OTG_HPRT_PSPD_Pos (17U)
23275 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
23276 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
23277 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
23278 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
23280 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
23281 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
23282 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
23283 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
23284 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
23285 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
23286 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
23287 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
23288 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
23289 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
23290 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
23291 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
23292 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
23293 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
23294 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
23295 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
23296 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
23297 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
23298 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
23299 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
23300 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
23301 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
23302 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
23303 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
23304 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
23305 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
23306 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
23307 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
23308 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
23309 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
23310 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
23311 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
23312 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
23313 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
23315 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
23316 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
23317 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
23318 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
23319 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
23320 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
23321 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
23323 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
23324 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
23325 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
23326 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
23327 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
23328 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
23329 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
23330 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
23331 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
23332 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
23333 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
23334 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
23335 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
23337 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
23338 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
23339 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
23340 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
23341 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
23342 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
23343 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
23344 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
23346 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
23347 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23348 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
23349 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23350 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23351 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23352 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23353 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
23354 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
23355 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
23356 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
23357 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
23358 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
23359 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
23360 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
23361 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
23362 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
23363 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
23364 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
23365 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
23366 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
23367 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
23368 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
23369 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
23370 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
23372 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
23373 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
23374 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
23375 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
23377 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
23378 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
23379 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
23380 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
23381 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
23382 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
23383 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
23384 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
23385 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
23386 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
23387 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
23388 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
23389 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
23391 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
23392 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
23393 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
23394 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
23395 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
23397 #define USB_OTG_HCCHAR_MC_Pos (20U)
23398 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
23399 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
23400 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
23401 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
23403 #define USB_OTG_HCCHAR_DAD_Pos (22U)
23404 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
23405 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
23406 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
23407 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
23408 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
23409 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
23410 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
23411 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
23412 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
23413 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
23414 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
23415 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
23416 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
23417 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
23418 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
23419 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
23420 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
23421 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
23423 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
23424 
23425 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
23426 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
23427 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
23428 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23429 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23430 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23431 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23432 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23433 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23434 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23436 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
23437 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
23438 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
23439 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23440 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23441 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23442 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23443 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23444 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23445 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23447 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
23448 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
23449 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
23450 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
23451 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
23452 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
23453 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
23454 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
23455 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
23456 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
23457 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
23459 /******************** Bit definition forUSB_OTG_HCINT register ********************/
23460 #define USB_OTG_HCINT_XFRC_Pos (0U)
23461 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
23462 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
23463 #define USB_OTG_HCINT_CHH_Pos (1U)
23464 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
23465 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
23466 #define USB_OTG_HCINT_AHBERR_Pos (2U)
23467 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
23468 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
23469 #define USB_OTG_HCINT_STALL_Pos (3U)
23470 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
23471 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
23472 #define USB_OTG_HCINT_NAK_Pos (4U)
23473 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
23474 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
23475 #define USB_OTG_HCINT_ACK_Pos (5U)
23476 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
23477 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
23478 #define USB_OTG_HCINT_NYET_Pos (6U)
23479 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
23480 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
23481 #define USB_OTG_HCINT_TXERR_Pos (7U)
23482 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
23483 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
23484 #define USB_OTG_HCINT_BBERR_Pos (8U)
23485 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
23486 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
23487 #define USB_OTG_HCINT_FRMOR_Pos (9U)
23488 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
23489 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
23490 #define USB_OTG_HCINT_DTERR_Pos (10U)
23491 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
23492 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
23494 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
23495 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
23496 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
23497 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
23498 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
23499 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
23500 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
23501 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
23502 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
23503 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
23504 #define USB_OTG_DIEPINT_TOC_Pos (3U)
23505 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
23506 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
23507 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
23508 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
23509 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
23510 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
23511 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
23512 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
23513 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
23514 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
23515 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
23516 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
23517 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
23518 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
23519 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
23520 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
23521 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
23522 #define USB_OTG_DIEPINT_BNA_Pos (9U)
23523 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
23524 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
23525 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
23526 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
23527 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
23528 #define USB_OTG_DIEPINT_BERR_Pos (12U)
23529 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
23530 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
23531 #define USB_OTG_DIEPINT_NAK_Pos (13U)
23532 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
23533 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
23535 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
23536 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
23537 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
23538 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
23539 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
23540 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
23541 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
23542 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
23543 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
23544 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
23545 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
23546 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
23547 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
23548 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
23549 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
23550 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
23551 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
23552 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
23553 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
23554 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
23555 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
23556 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
23557 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
23558 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
23559 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
23560 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
23561 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
23562 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
23563 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
23564 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
23565 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
23566 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
23567 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
23568 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
23570 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
23571 
23572 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
23573 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
23574 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
23575 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
23576 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
23577 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
23578 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
23579 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
23580 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
23581 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
23582 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
23583 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
23584 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
23585 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
23586 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
23587 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
23588 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
23589 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
23590 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
23591 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
23592 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
23593 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
23594 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
23595 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
23597 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
23598 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
23599 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
23600 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
23602 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
23603 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
23604 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
23605 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
23607 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
23608 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
23609 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
23610 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
23612 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
23613 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
23614 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
23615 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
23616 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
23617 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
23618 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
23620 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
23621 
23622 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
23623 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
23624 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
23625 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
23626 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
23627 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
23628 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
23629 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
23630 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
23631 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
23632 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
23633 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
23634 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
23635 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
23636 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
23637 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
23638 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
23639 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
23640 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
23641 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
23642 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
23643 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
23644 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
23645 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
23646 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
23647 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
23648 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
23649 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
23650 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
23651 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
23652 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
23653 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
23654 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
23655 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
23656 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
23657 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
23658 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
23659 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
23661 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
23662 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
23663 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
23664 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
23665 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
23666 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
23667 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
23668 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
23669 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
23670 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
23671 #define USB_OTG_DOEPINT_STUP_Pos (3U)
23672 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
23673 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
23674 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
23675 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
23676 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
23677 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
23678 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
23679 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
23680 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
23681 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
23682 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
23683 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
23684 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
23685 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
23686 #define USB_OTG_DOEPINT_BNA_Pos (9U)
23687 #define USB_OTG_DOEPINT_BNA_Msk (0x1UL << USB_OTG_DOEPINT_BNA_Pos)
23688 #define USB_OTG_DOEPINT_BNA USB_OTG_DOEPINT_BNA_Msk
23689 #define USB_OTG_DOEPINT_BERR_Pos (12U)
23690 #define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos)
23691 #define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk
23692 #define USB_OTG_DOEPINT_NAK_Pos (13U)
23693 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
23694 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
23695 #define USB_OTG_DOEPINT_NYET_Pos (14U)
23696 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
23697 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
23698 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
23699 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
23700 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
23702 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
23703 
23704 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
23705 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
23706 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
23707 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
23708 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
23709 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
23711 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
23712 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
23713 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
23714 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
23715 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
23717 /******************** Bit definition for PCGCCTL register ********************/
23718 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
23719 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
23720 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
23721 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
23722 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
23723 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
23724 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
23725 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
23726 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
23740 /******************************* ADC Instances ********************************/
23741 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
23742  ((INSTANCE) == ADC2) || \
23743  ((INSTANCE) == ADC3))
23744 
23745 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
23746 
23747 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
23748  ((INSTANCE) == ADC3_COMMON))
23749 
23750 /******************************* CORDIC Instances *****************************/
23751 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
23752 
23753 /******************************** FMAC Instances ******************************/
23754 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
23755 
23756 /******************************** COMP Instances ******************************/
23757 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
23758  ((INSTANCE) == COMP2))
23759 
23760 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
23761 /******************** COMP Instances with window mode capability **************/
23762 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
23763 
23764 /******************************** DTS Instances ******************************/
23765 #define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)
23766 
23767 /******************************* CRC Instances ********************************/
23768 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
23769 
23770 /******************************* DAC Instances ********************************/
23771 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
23772 /******************************* DCMI Instances *******************************/
23773 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
23774 
23775 /******************************* DELAYBLOCK Instances *******************************/
23776 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
23777  ((INSTANCE) == DLYB_SDMMC2) || \
23778  ((INSTANCE) == DLYB_OCTOSPI1) || \
23779  ((INSTANCE) == DLYB_OCTOSPI2) )
23780 /****************************** DFSDM Instances *******************************/
23781 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
23782  ((INSTANCE) == DFSDM1_Filter1) || \
23783  ((INSTANCE) == DFSDM1_Filter2) || \
23784  ((INSTANCE) == DFSDM1_Filter3))
23785 
23786 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
23787  ((INSTANCE) == DFSDM1_Channel1) || \
23788  ((INSTANCE) == DFSDM1_Channel2) || \
23789  ((INSTANCE) == DFSDM1_Channel3) || \
23790  ((INSTANCE) == DFSDM1_Channel4) || \
23791  ((INSTANCE) == DFSDM1_Channel5) || \
23792  ((INSTANCE) == DFSDM1_Channel6) || \
23793  ((INSTANCE) == DFSDM1_Channel7))
23794 /****************************** RAMECC Instances ******************************/
23795 #define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
23796  ((INSTANCE) == RAMECC1_Monitor2) || \
23797  ((INSTANCE) == RAMECC1_Monitor3) || \
23798  ((INSTANCE) == RAMECC1_Monitor4) || \
23799  ((INSTANCE) == RAMECC1_Monitor5) || \
23800  ((INSTANCE) == RAMECC1_Monitor6) || \
23801  ((INSTANCE) == RAMECC2_Monitor1) || \
23802  ((INSTANCE) == RAMECC2_Monitor2) || \
23803  ((INSTANCE) == RAMECC2_Monitor3) || \
23804  ((INSTANCE) == RAMECC3_Monitor1) || \
23805  ((INSTANCE) == RAMECC3_Monitor2))
23806 
23807 /******************************** DMA Instances *******************************/
23808 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
23809  ((INSTANCE) == DMA1_Stream1) || \
23810  ((INSTANCE) == DMA1_Stream2) || \
23811  ((INSTANCE) == DMA1_Stream3) || \
23812  ((INSTANCE) == DMA1_Stream4) || \
23813  ((INSTANCE) == DMA1_Stream5) || \
23814  ((INSTANCE) == DMA1_Stream6) || \
23815  ((INSTANCE) == DMA1_Stream7) || \
23816  ((INSTANCE) == DMA2_Stream0) || \
23817  ((INSTANCE) == DMA2_Stream1) || \
23818  ((INSTANCE) == DMA2_Stream2) || \
23819  ((INSTANCE) == DMA2_Stream3) || \
23820  ((INSTANCE) == DMA2_Stream4) || \
23821  ((INSTANCE) == DMA2_Stream5) || \
23822  ((INSTANCE) == DMA2_Stream6) || \
23823  ((INSTANCE) == DMA2_Stream7) || \
23824  ((INSTANCE) == BDMA_Channel0) || \
23825  ((INSTANCE) == BDMA_Channel1) || \
23826  ((INSTANCE) == BDMA_Channel2) || \
23827  ((INSTANCE) == BDMA_Channel3) || \
23828  ((INSTANCE) == BDMA_Channel4) || \
23829  ((INSTANCE) == BDMA_Channel5) || \
23830  ((INSTANCE) == BDMA_Channel6) || \
23831  ((INSTANCE) == BDMA_Channel7))
23832 
23833 /****************************** BDMA CHANNEL Instances ***************************/
23834 #define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
23835  ((INSTANCE) == BDMA_Channel1) || \
23836  ((INSTANCE) == BDMA_Channel2) || \
23837  ((INSTANCE) == BDMA_Channel3) || \
23838  ((INSTANCE) == BDMA_Channel4) || \
23839  ((INSTANCE) == BDMA_Channel5) || \
23840  ((INSTANCE) == BDMA_Channel6) || \
23841  ((INSTANCE) == BDMA_Channel7))
23842 
23843 /****************************** DMA DMAMUX ALL Instances ***************************/
23844 #define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
23845  ((INSTANCE) == DMA1_Stream1) || \
23846  ((INSTANCE) == DMA1_Stream2) || \
23847  ((INSTANCE) == DMA1_Stream3) || \
23848  ((INSTANCE) == DMA1_Stream4) || \
23849  ((INSTANCE) == DMA1_Stream5) || \
23850  ((INSTANCE) == DMA1_Stream6) || \
23851  ((INSTANCE) == DMA1_Stream7) || \
23852  ((INSTANCE) == DMA2_Stream0) || \
23853  ((INSTANCE) == DMA2_Stream1) || \
23854  ((INSTANCE) == DMA2_Stream2) || \
23855  ((INSTANCE) == DMA2_Stream3) || \
23856  ((INSTANCE) == DMA2_Stream4) || \
23857  ((INSTANCE) == DMA2_Stream5) || \
23858  ((INSTANCE) == DMA2_Stream6) || \
23859  ((INSTANCE) == DMA2_Stream7) || \
23860  ((INSTANCE) == BDMA_Channel0) || \
23861  ((INSTANCE) == BDMA_Channel1) || \
23862  ((INSTANCE) == BDMA_Channel2) || \
23863  ((INSTANCE) == BDMA_Channel3) || \
23864  ((INSTANCE) == BDMA_Channel4) || \
23865  ((INSTANCE) == BDMA_Channel5) || \
23866  ((INSTANCE) == BDMA_Channel6) || \
23867  ((INSTANCE) == BDMA_Channel7))
23868 
23869 /****************************** BDMA DMAMUX Instances ***************************/
23870 #define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
23871  ((INSTANCE) == BDMA_Channel1) || \
23872  ((INSTANCE) == BDMA_Channel2) || \
23873  ((INSTANCE) == BDMA_Channel3) || \
23874  ((INSTANCE) == BDMA_Channel4) || \
23875  ((INSTANCE) == BDMA_Channel5) || \
23876  ((INSTANCE) == BDMA_Channel6) || \
23877  ((INSTANCE) == BDMA_Channel7))
23878 
23879 /****************************** DMA STREAM Instances ***************************/
23880 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
23881  ((INSTANCE) == DMA1_Stream1) || \
23882  ((INSTANCE) == DMA1_Stream2) || \
23883  ((INSTANCE) == DMA1_Stream3) || \
23884  ((INSTANCE) == DMA1_Stream4) || \
23885  ((INSTANCE) == DMA1_Stream5) || \
23886  ((INSTANCE) == DMA1_Stream6) || \
23887  ((INSTANCE) == DMA1_Stream7) || \
23888  ((INSTANCE) == DMA2_Stream0) || \
23889  ((INSTANCE) == DMA2_Stream1) || \
23890  ((INSTANCE) == DMA2_Stream2) || \
23891  ((INSTANCE) == DMA2_Stream3) || \
23892  ((INSTANCE) == DMA2_Stream4) || \
23893  ((INSTANCE) == DMA2_Stream5) || \
23894  ((INSTANCE) == DMA2_Stream6) || \
23895  ((INSTANCE) == DMA2_Stream7))
23896 
23897 /****************************** DMA DMAMUX Instances ***************************/
23898 #define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
23899  ((INSTANCE) == DMA1_Stream1) || \
23900  ((INSTANCE) == DMA1_Stream2) || \
23901  ((INSTANCE) == DMA1_Stream3) || \
23902  ((INSTANCE) == DMA1_Stream4) || \
23903  ((INSTANCE) == DMA1_Stream5) || \
23904  ((INSTANCE) == DMA1_Stream6) || \
23905  ((INSTANCE) == DMA1_Stream7) || \
23906  ((INSTANCE) == DMA2_Stream0) || \
23907  ((INSTANCE) == DMA2_Stream1) || \
23908  ((INSTANCE) == DMA2_Stream2) || \
23909  ((INSTANCE) == DMA2_Stream3) || \
23910  ((INSTANCE) == DMA2_Stream4) || \
23911  ((INSTANCE) == DMA2_Stream5) || \
23912  ((INSTANCE) == DMA2_Stream6) || \
23913  ((INSTANCE) == DMA2_Stream7))
23914 
23915 /******************************** DMA Request Generator Instances **************/
23916 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
23917  ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
23918  ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
23919  ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
23920  ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
23921  ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
23922  ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
23923  ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
23924  ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
23925  ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
23926  ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
23927  ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
23928  ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
23929  ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
23930  ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
23931  ((INSTANCE) == DMAMUX2_RequestGenerator7))
23932 
23933 /******************************* DMA2D Instances *******************************/
23934 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
23935 
23936 /******************************* OTFDEC Instances ******************************/
23937 #define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \
23938  ((__INSTANCE__) == OTFDEC2))
23939 
23940 /****************************** PSSI Instance *********************************/
23941 #define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)
23942 
23943 /******************************** MDMA Request Generator Instances **************/
23944 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
23945  ((INSTANCE) == MDMA_Channel1) || \
23946  ((INSTANCE) == MDMA_Channel2) || \
23947  ((INSTANCE) == MDMA_Channel3) || \
23948  ((INSTANCE) == MDMA_Channel4) || \
23949  ((INSTANCE) == MDMA_Channel5) || \
23950  ((INSTANCE) == MDMA_Channel6) || \
23951  ((INSTANCE) == MDMA_Channel7) || \
23952  ((INSTANCE) == MDMA_Channel8) || \
23953  ((INSTANCE) == MDMA_Channel9) || \
23954  ((INSTANCE) == MDMA_Channel10) || \
23955  ((INSTANCE) == MDMA_Channel11) || \
23956  ((INSTANCE) == MDMA_Channel12) || \
23957  ((INSTANCE) == MDMA_Channel13) || \
23958  ((INSTANCE) == MDMA_Channel14) || \
23959  ((INSTANCE) == MDMA_Channel15))
23960 
23961 
23962 /******************************* FDCAN Instances ******************************/
23963 #define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
23964  ((__INSTANCE__) == FDCAN2) || \
23965  ((__INSTANCE__) == FDCAN3))
23966 
23967 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
23968 
23969 /******************************* GPIO Instances *******************************/
23970 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
23971  ((INSTANCE) == GPIOB) || \
23972  ((INSTANCE) == GPIOC) || \
23973  ((INSTANCE) == GPIOD) || \
23974  ((INSTANCE) == GPIOE) || \
23975  ((INSTANCE) == GPIOF) || \
23976  ((INSTANCE) == GPIOG) || \
23977  ((INSTANCE) == GPIOH) || \
23978  ((INSTANCE) == GPIOJ) || \
23979  ((INSTANCE) == GPIOK))
23980 
23981 /******************************* GPIO AF Instances ****************************/
23982 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
23983 
23984 /**************************** GPIO Lock Instances *****************************/
23985 /* On H7, all GPIO Bank support the Lock mechanism */
23986 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
23987 
23988 /******************************** HSEM Instances *******************************/
23989 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
23990 #define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
23991 #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
23992 #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
23993 
23994 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
23995 #define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
23996 
23997 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
23998 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
23999 
24000 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
24001 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
24002 
24003 /******************************** I2C Instances *******************************/
24004 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
24005  ((INSTANCE) == I2C2) || \
24006  ((INSTANCE) == I2C3) || \
24007  ((INSTANCE) == I2C4) || \
24008  ((INSTANCE) == I2C5))
24009 
24010 /****************************** SMBUS Instances *******************************/
24011 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
24012  ((INSTANCE) == I2C2) || \
24013  ((INSTANCE) == I2C3) || \
24014  ((INSTANCE) == I2C4) || \
24015  ((INSTANCE) == I2C5))
24016 
24017 /************** I2C Instances : wakeup capability from stop modes *************/
24018 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
24019 
24020 /******************************** I2S Instances *******************************/
24021 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
24022  ((INSTANCE) == SPI2) || \
24023  ((INSTANCE) == SPI3))
24024 
24025 /****************************** LTDC Instances ********************************/
24026 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
24027 
24028 /******************************* RNG Instances ********************************/
24029 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
24030 
24031 /****************************** RTC Instances *********************************/
24032 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
24033 
24034 /****************************** SDMMC Instances *********************************/
24035 #define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
24036  ((_INSTANCE_) == SDMMC2))
24037 
24038 /******************************** SPI Instances *******************************/
24039 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
24040  ((INSTANCE) == SPI2) || \
24041  ((INSTANCE) == SPI3) || \
24042  ((INSTANCE) == SPI4) || \
24043  ((INSTANCE) == SPI5) || \
24044  ((INSTANCE) == SPI6))
24045 
24046 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
24047  ((INSTANCE) == SPI2) || \
24048  ((INSTANCE) == SPI3))
24049 
24050 /******************************** SWPMI Instances *****************************/
24051 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
24052 
24053 /****************** LPTIM Instances : All supported instances *****************/
24054 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
24055  ((INSTANCE) == LPTIM2) || \
24056  ((INSTANCE) == LPTIM3) || \
24057  ((INSTANCE) == LPTIM4) || \
24058  ((INSTANCE) == LPTIM5))
24059 
24060 /****************** LPTIM Instances : supporting encoder interface **************/
24061 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
24062  ((INSTANCE) == LPTIM2))
24063 
24064 /****************** TIM Instances : All supported instances *******************/
24065 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24066  ((INSTANCE) == TIM2) || \
24067  ((INSTANCE) == TIM3) || \
24068  ((INSTANCE) == TIM4) || \
24069  ((INSTANCE) == TIM5) || \
24070  ((INSTANCE) == TIM6) || \
24071  ((INSTANCE) == TIM7) || \
24072  ((INSTANCE) == TIM8) || \
24073  ((INSTANCE) == TIM12) || \
24074  ((INSTANCE) == TIM13) || \
24075  ((INSTANCE) == TIM14) || \
24076  ((INSTANCE) == TIM15) || \
24077  ((INSTANCE) == TIM16) || \
24078  ((INSTANCE) == TIM17) || \
24079  ((INSTANCE) == TIM23) || \
24080  ((INSTANCE) == TIM24))
24081 
24082 /************* TIM Instances : at least 1 capture/compare channel *************/
24083 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24084  ((INSTANCE) == TIM2) || \
24085  ((INSTANCE) == TIM3) || \
24086  ((INSTANCE) == TIM4) || \
24087  ((INSTANCE) == TIM5) || \
24088  ((INSTANCE) == TIM8) || \
24089  ((INSTANCE) == TIM12) || \
24090  ((INSTANCE) == TIM13) || \
24091  ((INSTANCE) == TIM14) || \
24092  ((INSTANCE) == TIM15) || \
24093  ((INSTANCE) == TIM16) || \
24094  ((INSTANCE) == TIM17) || \
24095  ((INSTANCE) == TIM23) || \
24096  ((INSTANCE) == TIM24))
24097 
24098 /************ TIM Instances : at least 2 capture/compare channels *************/
24099 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24100  ((INSTANCE) == TIM2) || \
24101  ((INSTANCE) == TIM3) || \
24102  ((INSTANCE) == TIM4) || \
24103  ((INSTANCE) == TIM5) || \
24104  ((INSTANCE) == TIM8) || \
24105  ((INSTANCE) == TIM12) || \
24106  ((INSTANCE) == TIM15) || \
24107  ((INSTANCE) == TIM23) || \
24108  ((INSTANCE) == TIM24))
24109 
24110 /************ TIM Instances : at least 3 capture/compare channels *************/
24111 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24112  ((INSTANCE) == TIM2) || \
24113  ((INSTANCE) == TIM3) || \
24114  ((INSTANCE) == TIM4) || \
24115  ((INSTANCE) == TIM5) || \
24116  ((INSTANCE) == TIM8) || \
24117  ((INSTANCE) == TIM23) || \
24118  ((INSTANCE) == TIM24))
24119 
24120 /************ TIM Instances : at least 4 capture/compare channels *************/
24121 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24122  ((INSTANCE) == TIM2) || \
24123  ((INSTANCE) == TIM3) || \
24124  ((INSTANCE) == TIM4) || \
24125  ((INSTANCE) == TIM5) || \
24126  ((INSTANCE) == TIM8) || \
24127  ((INSTANCE) == TIM23) || \
24128  ((INSTANCE) == TIM24))
24129 
24130 /************ TIM Instances : at least 5 capture/compare channels *************/
24131 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24132  ((INSTANCE) == TIM8))
24133 /************ TIM Instances : at least 6 capture/compare channels *************/
24134 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24135  ((INSTANCE) == TIM8))
24136 
24137 /******************** TIM Instances : Advanced-control timers *****************/
24138 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
24139  ((__INSTANCE__) == TIM8))
24140 
24141 /******************** TIM Instances : Advanced-control timers *****************/
24142 
24143 /******************* TIM Instances : Timer input XOR function *****************/
24144 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24145  ((INSTANCE) == TIM2) || \
24146  ((INSTANCE) == TIM3) || \
24147  ((INSTANCE) == TIM4) || \
24148  ((INSTANCE) == TIM5) || \
24149  ((INSTANCE) == TIM8) || \
24150  ((INSTANCE) == TIM15) || \
24151  ((INSTANCE) == TIM23) || \
24152  ((INSTANCE) == TIM24))
24153 
24154 /****************** TIM Instances : DMA requests generation (UDE) *************/
24155 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24156  ((INSTANCE) == TIM2) || \
24157  ((INSTANCE) == TIM3) || \
24158  ((INSTANCE) == TIM4) || \
24159  ((INSTANCE) == TIM5) || \
24160  ((INSTANCE) == TIM6) || \
24161  ((INSTANCE) == TIM7) || \
24162  ((INSTANCE) == TIM8) || \
24163  ((INSTANCE) == TIM15) || \
24164  ((INSTANCE) == TIM16) || \
24165  ((INSTANCE) == TIM17) || \
24166  ((INSTANCE) == TIM23) || \
24167  ((INSTANCE) == TIM24))
24168 
24169 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
24170 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24171  ((INSTANCE) == TIM2) || \
24172  ((INSTANCE) == TIM3) || \
24173  ((INSTANCE) == TIM4) || \
24174  ((INSTANCE) == TIM5) || \
24175  ((INSTANCE) == TIM8) || \
24176  ((INSTANCE) == TIM15) || \
24177  ((INSTANCE) == TIM16) || \
24178  ((INSTANCE) == TIM17) || \
24179  ((INSTANCE) == TIM23) || \
24180  ((INSTANCE) == TIM24))
24181 
24182 /************ TIM Instances : DMA requests generation (COMDE) *****************/
24183 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24184  ((INSTANCE) == TIM2) || \
24185  ((INSTANCE) == TIM3) || \
24186  ((INSTANCE) == TIM4) || \
24187  ((INSTANCE) == TIM5) || \
24188  ((INSTANCE) == TIM8) || \
24189  ((INSTANCE) == TIM15))
24190 
24191 /******************** TIM Instances : DMA burst feature ***********************/
24192 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24193  ((INSTANCE) == TIM2) || \
24194  ((INSTANCE) == TIM3) || \
24195  ((INSTANCE) == TIM4) || \
24196  ((INSTANCE) == TIM5) || \
24197  ((INSTANCE) == TIM8))
24198 
24199 /*************** TIM Instances : external trigger reamp input available *******/
24200 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24201  ((INSTANCE) == TIM2) || \
24202  ((INSTANCE) == TIM3) || \
24203  ((INSTANCE) == TIM4) || \
24204  ((INSTANCE) == TIM5) || \
24205  ((INSTANCE) == TIM8) || \
24206  ((INSTANCE) == TIM23) || \
24207  ((INSTANCE) == TIM24))
24208 
24209 /****************** TIM Instances : remapping capability **********************/
24210 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24211  ((INSTANCE) == TIM2) || \
24212  ((INSTANCE) == TIM3) || \
24213  ((INSTANCE) == TIM5) || \
24214  ((INSTANCE) == TIM8) || \
24215  ((INSTANCE) == TIM16) || \
24216  ((INSTANCE) == TIM17) || \
24217  ((INSTANCE) == TIM23) || \
24218  ((INSTANCE) == TIM24))
24219 
24220 /*************** TIM Instances : external trigger reamp input available *******/
24221 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24222  ((INSTANCE) == TIM2) || \
24223  ((INSTANCE) == TIM3) || \
24224  ((INSTANCE) == TIM5) || \
24225  ((INSTANCE) == TIM8) || \
24226  ((INSTANCE) == TIM23) || \
24227  ((INSTANCE) == TIM24)))
24228 
24229 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
24230 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24231  ((INSTANCE) == TIM2) || \
24232  ((INSTANCE) == TIM3) || \
24233  ((INSTANCE) == TIM4) || \
24234  ((INSTANCE) == TIM5) || \
24235  ((INSTANCE) == TIM6) || \
24236  ((INSTANCE) == TIM7) || \
24237  ((INSTANCE) == TIM8) || \
24238  ((INSTANCE) == TIM12) || \
24239  ((INSTANCE) == TIM15) || \
24240  ((INSTANCE) == TIM23) || \
24241  ((INSTANCE) == TIM24))
24242 
24243 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
24244 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24245  ((INSTANCE) == TIM2) || \
24246  ((INSTANCE) == TIM3) || \
24247  ((INSTANCE) == TIM4) || \
24248  ((INSTANCE) == TIM5) || \
24249  ((INSTANCE) == TIM8) || \
24250  ((INSTANCE) == TIM12) || \
24251  ((INSTANCE) == TIM15) || \
24252  ((INSTANCE) == TIM23) || \
24253  ((INSTANCE) == TIM24))
24254 
24255 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
24256 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24257  ((INSTANCE) == TIM8))
24258 
24259 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
24260 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24261  ((INSTANCE) == TIM2) || \
24262  ((INSTANCE) == TIM3) || \
24263  ((INSTANCE) == TIM4) || \
24264  ((INSTANCE) == TIM5) || \
24265  ((INSTANCE) == TIM8) || \
24266  ((INSTANCE) == TIM15) || \
24267  ((INSTANCE) == TIM16) || \
24268  ((INSTANCE) == TIM17) || \
24269  ((INSTANCE) == TIM23) || \
24270  ((INSTANCE) == TIM24))
24271 
24272 /****************** TIM Instances : supporting commutation event *************/
24273 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24274  ((INSTANCE) == TIM8) || \
24275  ((INSTANCE) == TIM15) || \
24276  ((INSTANCE) == TIM16) || \
24277  ((INSTANCE) == TIM17))
24278 
24279 /****************** TIM Instances : supporting encoder interface **************/
24280 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
24281  ((__INSTANCE__) == TIM2) || \
24282  ((__INSTANCE__) == TIM3) || \
24283  ((__INSTANCE__) == TIM4) || \
24284  ((__INSTANCE__) == TIM5) || \
24285  ((__INSTANCE__) == TIM8) || \
24286  ((__INSTANCE__) == TIM23) || \
24287  ((__INSTANCE__) == TIM24))
24288 
24289 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
24290 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24291  ((INSTANCE) == TIM8))
24292 /******************* TIM Instances : output(s) available **********************/
24293 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
24294  ((((INSTANCE) == TIM1) && \
24295  (((CHANNEL) == TIM_CHANNEL_1) || \
24296  ((CHANNEL) == TIM_CHANNEL_2) || \
24297  ((CHANNEL) == TIM_CHANNEL_3) || \
24298  ((CHANNEL) == TIM_CHANNEL_4) || \
24299  ((CHANNEL) == TIM_CHANNEL_5) || \
24300  ((CHANNEL) == TIM_CHANNEL_6))) \
24301  || \
24302  (((INSTANCE) == TIM2) && \
24303  (((CHANNEL) == TIM_CHANNEL_1) || \
24304  ((CHANNEL) == TIM_CHANNEL_2) || \
24305  ((CHANNEL) == TIM_CHANNEL_3) || \
24306  ((CHANNEL) == TIM_CHANNEL_4))) \
24307  || \
24308  (((INSTANCE) == TIM3) && \
24309  (((CHANNEL) == TIM_CHANNEL_1)|| \
24310  ((CHANNEL) == TIM_CHANNEL_2) || \
24311  ((CHANNEL) == TIM_CHANNEL_3) || \
24312  ((CHANNEL) == TIM_CHANNEL_4))) \
24313  || \
24314  (((INSTANCE) == TIM4) && \
24315  (((CHANNEL) == TIM_CHANNEL_1) || \
24316  ((CHANNEL) == TIM_CHANNEL_2) || \
24317  ((CHANNEL) == TIM_CHANNEL_3) || \
24318  ((CHANNEL) == TIM_CHANNEL_4))) \
24319  || \
24320  (((INSTANCE) == TIM5) && \
24321  (((CHANNEL) == TIM_CHANNEL_1) || \
24322  ((CHANNEL) == TIM_CHANNEL_2) || \
24323  ((CHANNEL) == TIM_CHANNEL_3) || \
24324  ((CHANNEL) == TIM_CHANNEL_4))) \
24325  || \
24326  (((INSTANCE) == TIM8) && \
24327  (((CHANNEL) == TIM_CHANNEL_1) || \
24328  ((CHANNEL) == TIM_CHANNEL_2) || \
24329  ((CHANNEL) == TIM_CHANNEL_3) || \
24330  ((CHANNEL) == TIM_CHANNEL_4) || \
24331  ((CHANNEL) == TIM_CHANNEL_5) || \
24332  ((CHANNEL) == TIM_CHANNEL_6))) \
24333  || \
24334  (((INSTANCE) == TIM12) && \
24335  (((CHANNEL) == TIM_CHANNEL_1) || \
24336  ((CHANNEL) == TIM_CHANNEL_2))) \
24337  || \
24338  (((INSTANCE) == TIM13) && \
24339  (((CHANNEL) == TIM_CHANNEL_1))) \
24340  || \
24341  (((INSTANCE) == TIM14) && \
24342  (((CHANNEL) == TIM_CHANNEL_1))) \
24343  || \
24344  (((INSTANCE) == TIM15) && \
24345  (((CHANNEL) == TIM_CHANNEL_1) || \
24346  ((CHANNEL) == TIM_CHANNEL_2))) \
24347  || \
24348  (((INSTANCE) == TIM16) && \
24349  (((CHANNEL) == TIM_CHANNEL_1))) \
24350  || \
24351  (((INSTANCE) == TIM17) && \
24352  (((CHANNEL) == TIM_CHANNEL_1))) \
24353  || \
24354  (((INSTANCE) == TIM23) && \
24355  (((CHANNEL) == TIM_CHANNEL_1) || \
24356  ((CHANNEL) == TIM_CHANNEL_2) || \
24357  ((CHANNEL) == TIM_CHANNEL_3) || \
24358  ((CHANNEL) == TIM_CHANNEL_4))) \
24359  || \
24360  (((INSTANCE) == TIM24) && \
24361  (((CHANNEL) == TIM_CHANNEL_1) || \
24362  ((CHANNEL) == TIM_CHANNEL_2) || \
24363  ((CHANNEL) == TIM_CHANNEL_3) || \
24364  ((CHANNEL) == TIM_CHANNEL_4))))
24365 
24366 /****************** TIM Instances : supporting the break function *************/
24367 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
24368  (((INSTANCE) == TIM1) || \
24369  ((INSTANCE) == TIM8) || \
24370  ((INSTANCE) == TIM15) || \
24371  ((INSTANCE) == TIM16) || \
24372  ((INSTANCE) == TIM17))
24373 
24374 /************** TIM Instances : supporting Break source selection *************/
24375 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24376  ((INSTANCE) == TIM8))
24377 
24378 /****************** TIM Instances : supporting complementary output(s) ********/
24379 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
24380  ((((INSTANCE) == TIM1) && \
24381  (((CHANNEL) == TIM_CHANNEL_1) || \
24382  ((CHANNEL) == TIM_CHANNEL_2) || \
24383  ((CHANNEL) == TIM_CHANNEL_3))) \
24384  || \
24385  (((INSTANCE) == TIM8) && \
24386  (((CHANNEL) == TIM_CHANNEL_1) || \
24387  ((CHANNEL) == TIM_CHANNEL_2) || \
24388  ((CHANNEL) == TIM_CHANNEL_3))) \
24389  || \
24390  (((INSTANCE) == TIM15) && \
24391  ((CHANNEL) == TIM_CHANNEL_1)) \
24392  || \
24393  (((INSTANCE) == TIM16) && \
24394  ((CHANNEL) == TIM_CHANNEL_1)) \
24395  || \
24396  (((INSTANCE) == TIM17) && \
24397  ((CHANNEL) == TIM_CHANNEL_1)))
24398 
24399 /****************** TIM Instances : supporting counting mode selection ********/
24400 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
24401  (((INSTANCE) == TIM1) || \
24402  ((INSTANCE) == TIM2) || \
24403  ((INSTANCE) == TIM3) || \
24404  ((INSTANCE) == TIM4) || \
24405  ((INSTANCE) == TIM5) || \
24406  ((INSTANCE) == TIM8))
24407 
24408 /****************** TIM Instances : supporting repetition counter *************/
24409 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
24410  (((INSTANCE) == TIM1) || \
24411  ((INSTANCE) == TIM8) || \
24412  ((INSTANCE) == TIM15) || \
24413  ((INSTANCE) == TIM16) || \
24414  ((INSTANCE) == TIM17))
24415 
24416 /****************** TIM Instances : supporting synchronization ****************/
24417 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
24418  (((__INSTANCE__) == TIM1) || \
24419  ((__INSTANCE__) == TIM2) || \
24420  ((__INSTANCE__) == TIM3) || \
24421  ((__INSTANCE__) == TIM4) || \
24422  ((__INSTANCE__) == TIM5) || \
24423  ((__INSTANCE__) == TIM6) || \
24424  ((__INSTANCE__) == TIM8) || \
24425  ((__INSTANCE__) == TIM12) || \
24426  ((__INSTANCE__) == TIM15) || \
24427  ((__INSTANCE__) == TIM23) || \
24428  ((__INSTANCE__) == TIM24))
24429 
24430 /****************** TIM Instances : supporting clock division *****************/
24431 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
24432  (((INSTANCE) == TIM1) || \
24433  ((INSTANCE) == TIM2) || \
24434  ((INSTANCE) == TIM3) || \
24435  ((INSTANCE) == TIM4) || \
24436  ((INSTANCE) == TIM5) || \
24437  ((INSTANCE) == TIM8) || \
24438  ((INSTANCE) == TIM15) || \
24439  ((INSTANCE) == TIM16) || \
24440  ((INSTANCE) == TIM17) || \
24441  ((INSTANCE) == TIM23) || \
24442  ((INSTANCE) == TIM24))
24443 
24444 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
24445 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
24446  (((INSTANCE) == TIM1) || \
24447  ((INSTANCE) == TIM2) || \
24448  ((INSTANCE) == TIM3) || \
24449  ((INSTANCE) == TIM4) || \
24450  ((INSTANCE) == TIM5) || \
24451  ((INSTANCE) == TIM8) || \
24452  ((INSTANCE) == TIM23) || \
24453  ((INSTANCE) == TIM24))
24454 
24455 /****************** TIM Instances : supporting external clock mode 2 **********/
24456 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
24457  (((INSTANCE) == TIM1) || \
24458  ((INSTANCE) == TIM2) || \
24459  ((INSTANCE) == TIM3) || \
24460  ((INSTANCE) == TIM4) || \
24461  ((INSTANCE) == TIM5) || \
24462  ((INSTANCE) == TIM8) || \
24463  ((INSTANCE) == TIM23) || \
24464  ((INSTANCE) == TIM24))
24465 
24466 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
24467 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
24468  (((INSTANCE) == TIM1) || \
24469  ((INSTANCE) == TIM2) || \
24470  ((INSTANCE) == TIM3) || \
24471  ((INSTANCE) == TIM4) || \
24472  ((INSTANCE) == TIM5) || \
24473  ((INSTANCE) == TIM8) || \
24474  ((INSTANCE) == TIM15) || \
24475  ((INSTANCE) == TIM23) || \
24476  ((INSTANCE) == TIM24))
24477 
24478 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
24479 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
24480  (((INSTANCE) == TIM1) || \
24481  ((INSTANCE) == TIM2) || \
24482  ((INSTANCE) == TIM3) || \
24483  ((INSTANCE) == TIM4) || \
24484  ((INSTANCE) == TIM5) || \
24485  ((INSTANCE) == TIM8) || \
24486  ((INSTANCE) == TIM15) || \
24487  ((INSTANCE) == TIM23) || \
24488  ((INSTANCE) == TIM24))
24489 
24490 /****************** TIM Instances : supporting OCxREF clear *******************/
24491 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
24492  (((INSTANCE) == TIM1) || \
24493  ((INSTANCE) == TIM2) || \
24494  ((INSTANCE) == TIM3))
24495 
24496 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
24497 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
24498  (((INSTANCE) == TIM2) || \
24499  ((INSTANCE) == TIM5) || \
24500  ((INSTANCE) == TIM23) || \
24501  ((INSTANCE) == TIM24))
24502 
24503 /****************** TIM Instances : TIM_BKIN2 ***************************/
24504 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
24505  (((INSTANCE) == TIM1) || \
24506  ((INSTANCE) == TIM8))
24507 
24508 /****************** TIM Instances : supporting Hall sensor interface **********/
24509 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
24510  ((__INSTANCE__) == TIM2) || \
24511  ((__INSTANCE__) == TIM3) || \
24512  ((__INSTANCE__) == TIM4) || \
24513  ((__INSTANCE__) == TIM5) || \
24514  ((__INSTANCE__) == TIM15) || \
24515  ((__INSTANCE__) == TIM8) || \
24516  ((__INSTANCE__) == TIM23) || \
24517  ((__INSTANCE__) == TIM24))
24518 
24519 /******************** USART Instances : Synchronous mode **********************/
24520 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24521  ((INSTANCE) == USART2) || \
24522  ((INSTANCE) == USART3) || \
24523  ((INSTANCE) == USART6) || \
24524  ((INSTANCE) == USART10))
24525 
24526 /******************** USART Instances : SPI slave mode ************************/
24527 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24528  ((INSTANCE) == USART2) || \
24529  ((INSTANCE) == USART3) || \
24530  ((INSTANCE) == USART6) || \
24531  ((INSTANCE) == USART10))
24532 
24533 /******************** UART Instances : Asynchronous mode **********************/
24534 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24535  ((INSTANCE) == USART2) || \
24536  ((INSTANCE) == USART3) || \
24537  ((INSTANCE) == UART4) || \
24538  ((INSTANCE) == UART5) || \
24539  ((INSTANCE) == USART6) || \
24540  ((INSTANCE) == UART7) || \
24541  ((INSTANCE) == UART8) || \
24542  ((INSTANCE) == UART9) || \
24543  ((INSTANCE) == USART10))
24544 
24545 /******************** UART Instances : FIFO mode.******************************/
24546 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24547  ((INSTANCE) == USART2) || \
24548  ((INSTANCE) == USART3) || \
24549  ((INSTANCE) == UART4) || \
24550  ((INSTANCE) == UART5) || \
24551  ((INSTANCE) == USART6) || \
24552  ((INSTANCE) == UART7) || \
24553  ((INSTANCE) == UART8) || \
24554  ((INSTANCE) == UART9) || \
24555  ((INSTANCE) == USART10)|| \
24556  ((INSTANCE) == LPUART1))
24557 
24558 /****************** UART Instances : Auto Baud Rate detection *****************/
24559 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24560  ((INSTANCE) == USART2) || \
24561  ((INSTANCE) == USART3) || \
24562  ((INSTANCE) == UART4) || \
24563  ((INSTANCE) == UART5) || \
24564  ((INSTANCE) == USART6) || \
24565  ((INSTANCE) == UART7) || \
24566  ((INSTANCE) == UART8) || \
24567  ((INSTANCE) == UART9) || \
24568  ((INSTANCE) == USART10))
24569 
24570 /*********************** UART Instances : Driver Enable ***********************/
24571 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24572  ((INSTANCE) == USART2) || \
24573  ((INSTANCE) == USART3) || \
24574  ((INSTANCE) == UART4) || \
24575  ((INSTANCE) == UART5) || \
24576  ((INSTANCE) == USART6) || \
24577  ((INSTANCE) == UART7) || \
24578  ((INSTANCE) == UART8) || \
24579  ((INSTANCE) == UART9) || \
24580  ((INSTANCE) == USART10)|| \
24581  ((INSTANCE) == LPUART1))
24582 
24583 /********************* UART Instances : Half-Duplex mode **********************/
24584 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24585  ((INSTANCE) == USART2) || \
24586  ((INSTANCE) == USART3) || \
24587  ((INSTANCE) == UART4) || \
24588  ((INSTANCE) == UART5) || \
24589  ((INSTANCE) == USART6) || \
24590  ((INSTANCE) == UART7) || \
24591  ((INSTANCE) == UART8) || \
24592  ((INSTANCE) == UART9) || \
24593  ((INSTANCE) == USART10)|| \
24594  ((INSTANCE) == LPUART1))
24595 
24596 /******************* UART Instances : Hardware Flow control *******************/
24597 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24598  ((INSTANCE) == USART2) || \
24599  ((INSTANCE) == USART3) || \
24600  ((INSTANCE) == UART4) || \
24601  ((INSTANCE) == UART5) || \
24602  ((INSTANCE) == USART6) || \
24603  ((INSTANCE) == UART7) || \
24604  ((INSTANCE) == UART8) || \
24605  ((INSTANCE) == UART9) || \
24606  ((INSTANCE) == USART10)|| \
24607  ((INSTANCE) == LPUART1))
24608 
24609 /************************* UART Instances : LIN mode **************************/
24610 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24611  ((INSTANCE) == USART2) || \
24612  ((INSTANCE) == USART3) || \
24613  ((INSTANCE) == UART4) || \
24614  ((INSTANCE) == UART5) || \
24615  ((INSTANCE) == USART6) || \
24616  ((INSTANCE) == UART7) || \
24617  ((INSTANCE) == UART8) || \
24618  ((INSTANCE) == UART9) || \
24619  ((INSTANCE) == USART10))
24620 
24621 /****************** UART Instances : Wake-up from Stop mode *******************/
24622 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24623  ((INSTANCE) == USART2) || \
24624  ((INSTANCE) == USART3) || \
24625  ((INSTANCE) == UART4) || \
24626  ((INSTANCE) == UART5) || \
24627  ((INSTANCE) == USART6) || \
24628  ((INSTANCE) == UART7) || \
24629  ((INSTANCE) == UART8) || \
24630  ((INSTANCE) == UART9) || \
24631  ((INSTANCE) == USART10)|| \
24632  ((INSTANCE) == LPUART1))
24633 
24634 /************************* UART Instances : IRDA mode *************************/
24635 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24636  ((INSTANCE) == USART2) || \
24637  ((INSTANCE) == USART3) || \
24638  ((INSTANCE) == UART4) || \
24639  ((INSTANCE) == UART5) || \
24640  ((INSTANCE) == USART6) || \
24641  ((INSTANCE) == UART7) || \
24642  ((INSTANCE) == UART8) || \
24643  ((INSTANCE) == UART9) || \
24644  ((INSTANCE) == USART10))
24645 
24646 /********************* USART Instances : Smard card mode **********************/
24647 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24648  ((INSTANCE) == USART2) || \
24649  ((INSTANCE) == USART3) || \
24650  ((INSTANCE) == USART6) ||\
24651  ((INSTANCE) == USART10))
24652 
24653 /****************************** LPUART Instance *******************************/
24654 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
24655 
24656 /****************************** IWDG Instances ********************************/
24657 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
24658 /****************************** USB Instances ********************************/
24659 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
24660 
24661 /****************************** WWDG Instances ********************************/
24662 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
24663 /****************************** MDIOS Instances ********************************/
24664 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
24665 
24666 /****************************** CEC Instances *********************************/
24667 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
24668 
24669 /****************************** SAI Instances ********************************/
24670 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
24671  ((INSTANCE) == SAI1_Block_B) || \
24672  ((INSTANCE) == SAI4_Block_A) || \
24673  ((INSTANCE) == SAI4_Block_B))
24674 
24675 /****************************** SPDIFRX Instances ********************************/
24676 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
24677 
24678 /****************************** OPAMP Instances *******************************/
24679 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
24680  ((INSTANCE) == OPAMP2))
24681 
24682 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
24683 
24684 /*********************** USB OTG PCD Instances ********************************/
24685 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
24686 
24687 /*********************** USB OTG HCD Instances ********************************/
24688 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
24689 
24690 /******************************************************************************/
24691 /* For a painless codes migration between the STM32H7xx device product */
24692 /* lines, or with STM32F7xx devices the aliases defined below are put */
24693 /* in place to overcome the differences in the interrupt handlers and IRQn */
24694 /* definitions. No need to update developed interrupt code when moving */
24695 /* across product lines within the same STM32H7 Family */
24696 /******************************************************************************/
24697 
24698 /* Aliases for __IRQn */
24699 #define RNG_IRQn HASH_RNG_IRQn
24700 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
24701 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
24702 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
24703 #define PVD_IRQn PVD_AVD_IRQn
24704 
24705 
24706 /* Aliases for DCMI/PSSI __IRQn */
24707 #define DCMI_IRQn DCMI_PSSI_IRQn
24708 
24709 /* Aliases for __IRQHandler */
24710 #define RNG_IRQHandler HASH_RNG_IRQHandler
24711 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
24712 #define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
24713 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
24714 #define PVD_IRQHandler PVD_AVD_IRQHandler
24715 
24716 /* Aliases for COMP __IRQHandler */
24717 #define COMP_IRQHandler COMP1_IRQHandler
24718 
24731 #ifdef __cplusplus
24732 }
24733 #endif /* __cplusplus */
24734 
24735 #endif /* STM32H735xx_H */
24736 
24737 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
OTFDEC_TypeDef::IER
__IO uint32_t IER
Definition: stm32h735xx.h:2057
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition: stm32h735xx.h:179
COMP_IRQn
@ COMP_IRQn
Definition: stm32h735xx.h:178
R
#define R
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:5104
FDCAN_ClockCalibrationUnit_TypeDef::CSTAT
__IO uint32_t CSTAT
Definition: stm32h735xx.h:411
RCC_TypeDef::APB1HENR
__IO uint32_t APB1HENR
Definition: stm32h735xx.h:1290
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32h735xx.h:64
EXTI_TypeDef::RTSR1
__IO uint32_t RTSR1
Definition: stm32h735xx.h:897
GPV_TypeDef::AXI_TARG2_FN_MOD
__IO uint32_t AXI_TARG2_FN_MOD
Definition: stm32h735xx.h:2103
FDCAN_GlobalTypeDef::SIDFC
__IO uint32_t SIDFC
Definition: stm32h735xx.h:344
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition: stm32h735xx.h:123
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f407xx.h:711
FLASH_TypeDef::BOOT_PRG
__IO uint32_t BOOT_PRG
Definition: stm32h735xx.h:979
PSSI_TypeDef::IER
__IO uint32_t IER
Definition: stm32h735xx.h:589
OCTOSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32h735xx.h:1978
FLASH_TypeDef::PRAR_CUR1
__IO uint32_t PRAR_CUR1
Definition: stm32h735xx.h:972
ETH_TypeDef::MACL3A0R0R
__IO uint32_t MACL3A0R0R
Definition: stm32h735xx.h:798
GPV_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32h735xx.h:2100
RCC_TypeDef::D3CFGR
__IO uint32_t D3CFGR
Definition: stm32h735xx.h:1247
FDCAN_GlobalTypeDef::TXBCIE
__IO uint32_t TXBCIE
Definition: stm32h735xx.h:368
EXTI_TypeDef::D3PMR3
__IO uint32_t D3PMR3
Definition: stm32h735xx.h:914
USB_OTG_GlobalTypeDef::GHWCFG1
__IO uint32_t GHWCFG1
Definition: stm32h735xx.h:1852
OCTOSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32h735xx.h:1969
RCC_TypeDef::CSICFGR
__IO uint32_t CSICFGR
Definition: stm32h735xx.h:1242
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
OTFDEC_Region_TypeDef::REG_NONCER1
__IO uint32_t REG_NONCER1
Definition: stm32h735xx.h:2044
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32h735xx.h:1731
GPV_TypeDef::AXI_PERIPH_ID_7
uint32_t AXI_PERIPH_ID_7
Definition: stm32h735xx.h:2079
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition: stm32h735xx.h:88
SPI_TypeDef::CFG1
__IO uint32_t CFG1
Definition: stm32h735xx.h:1487
FDCAN_GlobalTypeDef::RESERVED1
__IO uint32_t RESERVED1
Definition: stm32h735xx.h:323
FDCAN3_IT0_IRQn
@ FDCAN3_IT0_IRQn
Definition: stm32h735xx.h:198
FLASH_TypeDef::OPTSR_CUR
__IO uint32_t OPTSR_CUR
Definition: stm32h735xx.h:969
FDCAN2_IT0_IRQn
@ FDCAN2_IT0_IRQn
Definition: stm32h735xx.h:82
FDCAN_CAL_IRQn
@ FDCAN_CAL_IRQn
Definition: stm32h735xx.h:124
ETH_TypeDef::MACATSSR
__IO uint32_t MACATSSR
Definition: stm32h735xx.h:827
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32h735xx.h:118
HSEM_Common_TypeDef
Definition: stm32h735xx.h:1471
DMAMUX_ChannelStatus_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32h735xx.h:646
GPV_TypeDef::AXI_TARG8_FN_MOD_ISS_BM
__IO uint32_t AXI_TARG8_FN_MOD_ISS_BM
Definition: stm32h735xx.h:2121
SDMMC_TypeDef::IDMABSIZE
__IO uint32_t IDMABSIZE
Definition: stm32h735xx.h:1433
DLYB_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32h735xx.h:1450
TTCAN_TypeDef::TTOCN
__IO uint32_t TTOCN
Definition: stm32h735xx.h:387
DBGMCU_TypeDef::APB4FZ1
__IO uint32_t APB4FZ1
Definition: stm32h735xx.h:548
SYSCFG_TypeDef::UR12
__IO uint32_t UR12
Definition: stm32h735xx.h:1123
GPV_TypeDef::AXI_INI3_FN_MOD
__IO uint32_t AXI_INI3_FN_MOD
Definition: stm32h735xx.h:2143
RCC_TypeDef::D3AMR
__IO uint32_t D3AMR
Definition: stm32h735xx.h:1281
ETH_TypeDef::DMACCATDR
__IO uint32_t DMACCATDR
Definition: stm32h735xx.h:880
GPV_TypeDef::AXI_INI1_FN_MOD_AHB
__IO uint32_t AXI_INI1_FN_MOD_AHB
Definition: stm32h735xx.h:2128
ETH_TypeDef::MMCTMCGPR
__IO uint32_t MMCTMCGPR
Definition: stm32h735xx.h:781
PWR_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32h735xx.h:1225
HSEM_TypeDef::C1ICR
__IO uint32_t C1ICR
Definition: stm32h735xx.h:1462
EXTI_TypeDef::FTSR2
__IO uint32_t FTSR2
Definition: stm32h735xx.h:905
FMAC_TypeDef::X1BUFCFG
__IO uint32_t X1BUFCFG
Definition: stm32h735xx.h:996
SPI_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32h735xx.h:1495
DMAMUX2_OVR_IRQn
@ DMAMUX2_OVR_IRQn
Definition: stm32h735xx.h:169
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f407xx.h:758
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f469xx.h:698
DBGMCU_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32h735xx.h:545
DAC_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h735xx.h:489
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f407xx.h:346
I2C5_EV_IRQn
@ I2C5_EV_IRQn
Definition: stm32h735xx.h:196
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32h735xx.h:66
GPV_TypeDef::AXI_INI5_WRITE_QOS
__IO uint32_t AXI_INI5_WRITE_QOS
Definition: stm32h735xx.h:2150
OTFDEC2_IRQn
@ OTFDEC2_IRQn
Definition: stm32h735xx.h:191
FDCAN_GlobalTypeDef::RESERVED3
__IO uint32_t RESERVED3
Definition: stm32h735xx.h:337
COMPOPT_TypeDef::SR
__IO uint32_t SR
Definition: stm32h735xx.h:1582
RCC_TypeDef::APB4LPENR
__IO uint32_t APB4LPENR
Definition: stm32h735xx.h:1302
ETH_TypeDef::DMACCARBR
__IO uint32_t DMACCARBR
Definition: stm32h735xx.h:886
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32h735xx.h:75
PSSI_TypeDef::VERR
__IO uint32_t VERR
Definition: stm32h735xx.h:596
FMC_IRQn
@ FMC_IRQn
Definition: stm32h735xx.h:109
ETH_TypeDef::MACATSNR
__IO uint32_t MACATSNR
Definition: stm32h735xx.h:826
OTFDEC_Region_TypeDef::REG_END_ADDR
__IO uint32_t REG_END_ADDR
Definition: stm32h735xx.h:2042
EXTI_TypeDef::IMR2
__IO uint32_t IMR2
Definition: stm32h735xx.h:922
ETH_TypeDef::MACL3A2R1R
__IO uint32_t MACL3A2R1R
Definition: stm32h735xx.h:808
ETH_TypeDef::MACVTR
__IO uint32_t MACVTR
Definition: stm32h735xx.h:730
RCC_TypeDef::APB4ENR
__IO uint32_t APB4ENR
Definition: stm32h735xx.h:1292
FDCAN_GlobalTypeDef::RESERVED7
__IO uint32_t RESERVED7
Definition: stm32h735xx.h:373
__I
#define __I
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:234
FLASH_TypeDef::SCAR_PRG1
__IO uint32_t SCAR_PRG1
Definition: stm32h735xx.h:975
OCTOSPI_TypeDef::WPTCR
__IO uint32_t WPTCR
Definition: stm32h735xx.h:1996
BDMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32h735xx.h:635
ETH_TypeDef::RESERVED41
uint32_t RESERVED41
Definition: stm32h735xx.h:879
DMAMUX_ChannelStatus_TypeDef
Definition: stm32h735xx.h:643
MDMA_Channel_TypeDef::CMDR
__IO uint32_t CMDR
Definition: stm32h735xx.h:683
SYSCFG_TypeDef::CCVR
__IO uint32_t CCVR
Definition: stm32h735xx.h:1106
BDMA_Channel0_IRQn
@ BDMA_Channel0_IRQn
Definition: stm32h735xx.h:170
EXTI_Core_TypeDef::IMR3
__IO uint32_t IMR3
Definition: stm32h735xx.h:950
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32h735xx.h:144
SAI_TypeDef::PDMCR
__IO uint32_t PDMCR
Definition: stm32h735xx.h:1375
SYSCFG_TypeDef::UR0
__IO uint32_t UR0
Definition: stm32h735xx.h:1113
SWPMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:1621
GPV_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32h735xx.h:2092
BDMA_Channel_TypeDef::CM0AR
__IO uint32_t CM0AR
Definition: stm32h735xx.h:628
OTFDEC_Region_TypeDef::REG_KEYR1
__IO uint32_t REG_KEYR1
Definition: stm32h735xx.h:2046
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition: stm32h735xx.h:151
GPV_TypeDef::AXI_TARG7_FN_MOD_ISS_BM
__IO uint32_t AXI_TARG7_FN_MOD_ISS_BM
Definition: stm32h735xx.h:2113
ADC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32h735xx.h:281
FMAC_IRQn
@ FMAC_IRQn
Definition: stm32h735xx.h:192
CRYP_TypeDef::CSGCMCCM3R
__IO uint32_t CSGCMCCM3R
Definition: stm32h735xx.h:1696
DMA_TypeDef
Definition: stm32f407xx.h:356
EXTI_TypeDef::EMR2
__IO uint32_t EMR2
Definition: stm32h735xx.h:923
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32h735xx.h:53
OCTOSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32h735xx.h:1990
DBGMCU_TypeDef::APB1LFZ1
__IO uint32_t APB1LFZ1
Definition: stm32h735xx.h:542
FMAC_TypeDef::PARAM
__IO uint32_t PARAM
Definition: stm32h735xx.h:999
ETH_TypeDef::DMACIER
__IO uint32_t DMACIER
Definition: stm32h735xx.h:876
MDMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h735xx.h:673
FDCAN_GlobalTypeDef::TXESC
__IO uint32_t TXESC
Definition: stm32h735xx.h:361
ETH_TypeDef::DMACRDLAR
__IO uint32_t DMACRDLAR
Definition: stm32h735xx.h:870
GPV_TypeDef::AXI_INI4_WRITE_QOS
__IO uint32_t AXI_INI4_WRITE_QOS
Definition: stm32h735xx.h:2146
ETH_TypeDef::DMACRIWTR
__IO uint32_t DMACRIWTR
Definition: stm32h735xx.h:877
FDCAN_GlobalTypeDef::PSR
__IO uint32_t PSR
Definition: stm32h735xx.h:335
USART10_IRQn
@ USART10_IRQn
Definition: stm32h735xx.h:195
MDMA_Channel_TypeDef::CESR
__IO uint32_t CESR
Definition: stm32h735xx.h:672
CEC_IRQn
@ CEC_IRQn
Definition: stm32h735xx.h:150
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f469xx.h:593
PSSI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32h735xx.h:591
CRS_IRQn
@ CRS_IRQn
Definition: stm32h735xx.h:184
USB_OTG_GlobalTypeDef::GADPCTL
__IO uint32_t GADPCTL
Definition: stm32h735xx.h:1859
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32h735xx.h:106
OCTOSPI2_IRQn
@ OCTOSPI2_IRQn
Definition: stm32h735xx.h:189
ETH_TypeDef::MACSTSUR
__IO uint32_t MACSTSUR
Definition: stm32h735xx.h:815
DTS_TypeDef::SR
__IO uint32_t SR
Definition: stm32h735xx.h:1518
ETH_TypeDef::RESERVED25
uint32_t RESERVED25
Definition: stm32h735xx.h:818
ETH_TypeDef::MTLTQDR
__IO uint32_t MTLTQDR
Definition: stm32h735xx.h:852
CRYP_TypeDef::CSGCMCCM0R
__IO uint32_t CSGCMCCM0R
Definition: stm32h735xx.h:1693
SPI_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32h735xx.h:1493
ADC_Common_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32h735xx.h:296
CRYP_TypeDef::CSGCM1R
__IO uint32_t CSGCM1R
Definition: stm32h735xx.h:1702
ADC_Common_TypeDef::CDR2
__IO uint32_t CDR2
Definition: stm32h735xx.h:299
OCTOSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:1962
CORDIC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32h735xx.h:437
TTCAN_TypeDef::TTTMK
__IO uint32_t TTTMK
Definition: stm32h735xx.h:389
BDMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition: stm32h735xx.h:626
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32h735xx.h:69
TTCAN_TypeDef::TTILS
__IO uint32_t TTILS
Definition: stm32h735xx.h:392
PSSI_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:586
TTCAN_TypeDef::TTCPT
__IO uint32_t TTCPT
Definition: stm32h735xx.h:397
FLASH_TypeDef::CRCSADD1
__IO uint32_t CRCSADD1
Definition: stm32h735xx.h:982
ETH_TypeDef::DMACCATBR
__IO uint32_t DMACCATBR
Definition: stm32h735xx.h:884
VREFBUF_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32h735xx.h:310
FDCAN_GlobalTypeDef::TXEFS
__IO uint32_t TXEFS
Definition: stm32h735xx.h:371
DLYB_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:1449
OCTOSPI1_IRQn
@ OCTOSPI1_IRQn
Definition: stm32h735xx.h:148
SDMMC_TypeDef::ACKTIME
__IO uint32_t ACKTIME
Definition: stm32h735xx.h:1430
OTFDEC_Region_TypeDef::REG_KEYR0
__IO uint32_t REG_KEYR0
Definition: stm32h735xx.h:2045
PWR_TypeDef::CPUCR
__IO uint32_t CPUCR
Definition: stm32h735xx.h:1224
CRS_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:462
HSEM_TypeDef
HW Semaphore HSEM.
Definition: stm32h735xx.h:1457
CRYP_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32h735xx.h:1679
FDCAN2_IT1_IRQn
@ FDCAN2_IT1_IRQn
Definition: stm32h735xx.h:84
TTCAN_TypeDef::TTGTP
__IO uint32_t TTGTP
Definition: stm32h735xx.h:388
ETH_TypeDef::MMCRLPIMSTR
__IO uint32_t MMCRLPIMSTR
Definition: stm32h735xx.h:792
CRYP_TypeDef::CSGCMCCM2R
__IO uint32_t CSGCMCCM2R
Definition: stm32h735xx.h:1695
ETH_TypeDef::MACTSIACR
__IO uint32_t MACTSIACR
Definition: stm32h735xx.h:828
GPV_TypeDef::AXI_INI1_FN_MOD
__IO uint32_t AXI_INI1_FN_MOD
Definition: stm32h735xx.h:2132
FLASH_TypeDef::CRCCR1
__IO uint32_t CRCCR1
Definition: stm32h735xx.h:981
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32h735xx.h:130
CRS_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32h735xx.h:463
OCTOSPI_TypeDef::RESERVED15
uint32_t RESERVED15
Definition: stm32h735xx.h:1997
RAMECC_TypeDef::IER
__IO uint32_t IER
Definition: stm32h735xx.h:1660
RNG_TypeDef::HTCR
__IO uint32_t HTCR
Definition: stm32h735xx.h:1747
OCTOSPI_TypeDef::WPIR
__IO uint32_t WPIR
Definition: stm32h735xx.h:1998
MDIOS_TypeDef
MDIOS.
Definition: stm32f769xx.h:1212
USB_OTG_GlobalTypeDef::GSNPSID
__IO uint32_t GSNPSID
Definition: stm32h735xx.h:1851
PSSI_TypeDef::SIDR
__IO uint32_t SIDR
Definition: stm32h735xx.h:598
HASH_RNG_IRQn
@ HASH_RNG_IRQn
Definition: stm32h735xx.h:137
CORDIC_TypeDef::WDATA
__IO uint32_t WDATA
Definition: stm32h735xx.h:438
FLASH_TypeDef::OPTSR2_CUR
__IO uint32_t OPTSR2_CUR
Definition: stm32h735xx.h:987
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32h735xx.h:94
CRYP_TypeDef::DMACR
__IO uint32_t DMACR
Definition: stm32h735xx.h:1677
ADC_TypeDef::HTR1_TR2
__IO uint32_t HTR1_TR2
Definition: stm32h735xx.h:257
FDCAN_GlobalTypeDef::TXBC
__IO uint32_t TXBC
Definition: stm32h735xx.h:359
RCC_TypeDef::AHB4RSTR
__IO uint32_t AHB4RSTR
Definition: stm32h735xx.h:1273
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32h735xx.h:141
ETH_TypeDef::RESERVED40
uint32_t RESERVED40
Definition: stm32h735xx.h:872
ETH_TypeDef::MMCRCRCEPR
__IO uint32_t MMCRCRCEPR
Definition: stm32h735xx.h:785
FMC_Bank2_TypeDef::PMEM2
__IO uint32_t PMEM2
Definition: stm32h735xx.h:1032
DBGMCU_TypeDef::PIDR1
__IO uint32_t PIDR1
Definition: stm32h735xx.h:553
CRYP_TypeDef::CSGCM2R
__IO uint32_t CSGCM2R
Definition: stm32h735xx.h:1703
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32h735xx.h:58
ETH_TypeDef::MACSSIR
__IO uint32_t MACSSIR
Definition: stm32h735xx.h:812
GPV_TypeDef::AXI_TARG2_FN_MOD_ISS_BM
__IO uint32_t AXI_TARG2_FN_MOD_ISS_BM
Definition: stm32h735xx.h:2097
ETH_TypeDef::MACSTNR
__IO uint32_t MACSTNR
Definition: stm32h735xx.h:814
BDMA_Channel6_IRQn
@ BDMA_Channel6_IRQn
Definition: stm32h735xx.h:176
TTCAN_TypeDef
TTFD Controller Area Network.
Definition: stm32h735xx.h:380
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32h735xx.h:126
OTFDEC_TypeDef::HWCFGR2
__IO uint32_t HWCFGR2
Definition: stm32h735xx.h:2059
OCTOSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32h735xx.h:1974
OCTOSPIM_TypeDef
OCTO Serial Peripheral Interface IO Manager.
Definition: stm32h735xx.h:2025
RCC_TypeDef::APB4RSTR
__IO uint32_t APB4RSTR
Definition: stm32h735xx.h:1278
FLASH_TypeDef::OPTSR_PRG
__IO uint32_t OPTSR_PRG
Definition: stm32h735xx.h:970
HSEM_Common_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32h735xx.h:1474
FDCAN_GlobalTypeDef::TEST
__IO uint32_t TEST
Definition: stm32h735xx.h:325
RCC_TypeDef::PLL1DIVR
__IO uint32_t PLL1DIVR
Definition: stm32h735xx.h:1251
OCTOSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h735xx.h:1984
FLASH_TypeDef::WPSN_PRG1
__IO uint32_t WPSN_PRG1
Definition: stm32h735xx.h:977
HASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:1717
RCC_TypeDef::PLL3FRACR
__IO uint32_t PLL3FRACR
Definition: stm32h735xx.h:1256
DTS_IRQn
@ DTS_IRQn
Definition: stm32h735xx.h:187
RAMECC_MonitorTypeDef
RAM_ECC_Specific_Registers.
Definition: stm32h735xx.h:1648
LPTIM_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32h735xx.h:1574
MDMA_TypeDef::GISR0
__IO uint32_t GISR0
Definition: stm32h735xx.h:665
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f407xx.h:557
EXTI_TypeDef::D3PCR3L
__IO uint32_t D3PCR3L
Definition: stm32h735xx.h:915
CRYP_TypeDef::K0RR
__IO uint32_t K0RR
Definition: stm32h735xx.h:1682
OCTOSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32h735xx.h:1970
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32h735xx.h:91
FLASH_TypeDef::SR1
__IO uint32_t SR1
Definition: stm32h735xx.h:966
DMAMUX_RequestGen_TypeDef::RGCR
__IO uint32_t RGCR
Definition: stm32h735xx.h:651
FDCAN_GlobalTypeDef::ILE
__IO uint32_t ILE
Definition: stm32h735xx.h:341
GPV_TypeDef::AXI_PERIPH_ID_5
uint32_t AXI_PERIPH_ID_5
Definition: stm32h735xx.h:2077
ADC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32h735xx.h:259
ADC_TypeDef::HTR2_CALFACT
__IO uint32_t HTR2_CALFACT
Definition: stm32h735xx.h:284
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f407xx.h:315
SPI6_IRQn
@ SPI6_IRQn
Definition: stm32h735xx.h:143
OCTOSPI_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32h735xx.h:1963
PVD_AVD_IRQn
@ PVD_AVD_IRQn
Definition: stm32h735xx.h:63
CRYP_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32h735xx.h:1680
ETH_TypeDef::MACHWF2R
__IO uint32_t MACHWF2R
Definition: stm32h735xx.h:758
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f407xx.h:875
COMP_Common_TypeDef
Definition: stm32h735xx.h:1592
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32h735xx.h:70
ETH_TypeDef::MACTSEACR
__IO uint32_t MACTSEACR
Definition: stm32h735xx.h:829
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32h735xx.h:108
ETH_TypeDef::MACSPI2R
__IO uint32_t MACSPI2R
Definition: stm32h735xx.h:843
ADC_TypeDef::OFR3
__IO uint32_t OFR3
Definition: stm32h735xx.h:271
SYSCFG_TypeDef::UR18
__IO uint32_t UR18
Definition: stm32h735xx.h:1129
ETH_TypeDef::MACSPI1R
__IO uint32_t MACSPI1R
Definition: stm32h735xx.h:842
RCC_TypeDef::CICR
__IO uint32_t CICR
Definition: stm32h735xx.h:1265
OCTOSPI_TypeDef::WTCR
__IO uint32_t WTCR
Definition: stm32h735xx.h:2004
RCC_TypeDef::HSICFGR
__IO uint32_t HSICFGR
Definition: stm32h735xx.h:1240
ETH_TypeDef::MACL3A0R1R
__IO uint32_t MACL3A0R1R
Definition: stm32h735xx.h:806
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32h735xx.h:251
ETH_TypeDef::MACISR
__IO uint32_t MACISR
Definition: stm32h735xx.h:741
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f469xx.h:625
CRYP_TypeDef::CSGCMCCM5R
__IO uint32_t CSGCMCCM5R
Definition: stm32h735xx.h:1698
DBGMCU_TypeDef::APB2FZ1
__IO uint32_t APB2FZ1
Definition: stm32h735xx.h:546
OCTOSPI_TypeDef::TCR
__IO uint32_t TCR
Definition: stm32h735xx.h:1986
FLASH_TypeDef::SCAR_CUR1
__IO uint32_t SCAR_CUR1
Definition: stm32h735xx.h:974
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f407xx.h:846
ETH_TypeDef::MACSTSR
__IO uint32_t MACSTSR
Definition: stm32h735xx.h:813
COMPOPT_TypeDef
Comparator.
Definition: stm32h735xx.h:1580
TTCAN_TypeDef::TTOCF
__IO uint32_t TTOCF
Definition: stm32h735xx.h:384
CRYP_TypeDef::CSGCM3R
__IO uint32_t CSGCM3R
Definition: stm32h735xx.h:1704
GPV_TypeDef::AXI_TARG4_FN_MOD_ISS_BM
__IO uint32_t AXI_TARG4_FN_MOD_ISS_BM
Definition: stm32h735xx.h:2107
FLASH_TypeDef::CRCDATA
__IO uint32_t CRCDATA
Definition: stm32h735xx.h:984
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f469xx.h:611
OCTOSPI_TypeDef::DCR2
__IO uint32_t DCR2
Definition: stm32h735xx.h:1965
SPI_TypeDef::IER
__IO uint32_t IER
Definition: stm32h735xx.h:1489
ETH_TypeDef::MACARPAR
__IO uint32_t MACARPAR
Definition: stm32h735xx.h:763
ADC_TypeDef::OFR4
__IO uint32_t OFR4
Definition: stm32h735xx.h:272
RTC_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32h735xx.h:1319
FLASH_TypeDef::OPTCCR
__IO uint32_t OPTCCR
Definition: stm32h735xx.h:971
PWR_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32h735xx.h:1227
SYSCFG_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32h735xx.h:1103
RCC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32h735xx.h:1280
SWPMI_TypeDef::RFL
__IO uint32_t RFL
Definition: stm32h735xx.h:1627
RAMECC_MonitorTypeDef::SR
__IO uint32_t SR
Definition: stm32h735xx.h:1651
DTS_TypeDef::ITENR
__IO uint32_t ITENR
Definition: stm32h735xx.h:1519
SPDIFRX_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32h735xx.h:1404
ETH_TypeDef::MACPPSWR
__IO uint32_t MACPPSWR
Definition: stm32h735xx.h:838
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32h735xx.h:71
SYSCFG_TypeDef::PMCR
__IO uint32_t PMCR
Definition: stm32h735xx.h:1101
CORDIC_IRQn
@ CORDIC_IRQn
Definition: stm32h735xx.h:193
HASH_TypeDef
HASH.
Definition: stm32h735xx.h:1715
SPI_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32h735xx.h:1491
ETH_TypeDef::MACPPSTTSR
__IO uint32_t MACPPSTTSR
Definition: stm32h735xx.h:835
TTCAN_TypeDef::TTCTC
__IO uint32_t TTCTC
Definition: stm32h735xx.h:396
ETH_TypeDef::DMACRDRLR
__IO uint32_t DMACRDRLR
Definition: stm32h735xx.h:875
CRYP_TypeDef::CSGCM4R
__IO uint32_t CSGCM4R
Definition: stm32h735xx.h:1705
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32f769xx.h:874
GPV_TypeDef::AXI_TARG1_FN_MOD
__IO uint32_t AXI_TARG1_FN_MOD
Definition: stm32h735xx.h:2095
FMC_Bank2_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32h735xx.h:1028
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32h735xx.h:85
TTCAN_TypeDef::TTRMC
__IO uint32_t TTRMC
Definition: stm32h735xx.h:383
COMPOPT_TypeDef::OR
__IO uint32_t OR
Definition: stm32h735xx.h:1584
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32h735xx.h:56
OCTOSPI_TypeDef::HWCFGR
__IO uint32_t HWCFGR
Definition: stm32h735xx.h:2012
GPV_TypeDef::AXI_INI1_READ_QOS
__IO uint32_t AXI_INI1_READ_QOS
Definition: stm32h735xx.h:2130
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32h735xx.h:654
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32h735xx.h:183
CRYP_TypeDef::K2RR
__IO uint32_t K2RR
Definition: stm32h735xx.h:1686
ETH_TypeDef::MMCRUPGR
__IO uint32_t MMCRUPGR
Definition: stm32h735xx.h:788
VREFBUF_TypeDef
VREFBUF.
Definition: stm32h735xx.h:308
EXTI_Core_TypeDef::IMR2
__IO uint32_t IMR2
Definition: stm32h735xx.h:946
CRYP_TypeDef::DOUT
__IO uint32_t DOUT
Definition: stm32h735xx.h:1676
HASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32h735xx.h:1722
FDCAN_GlobalTypeDef::TXBRP
__IO uint32_t TXBRP
Definition: stm32h735xx.h:362
FDCAN_GlobalTypeDef::CCCR
__IO uint32_t CCCR
Definition: stm32h735xx.h:327
EXTI_TypeDef::D3PMR1
__IO uint32_t D3PMR1
Definition: stm32h735xx.h:900
TTCAN_TypeDef::TTLGT
__IO uint32_t TTLGT
Definition: stm32h735xx.h:395
GPV_TypeDef::AXI_COMP_ID_0
__IO uint32_t AXI_COMP_ID_0
Definition: stm32h735xx.h:2084
FDCAN_GlobalTypeDef::RXF1C
__IO uint32_t RXF1C
Definition: stm32h735xx.h:355
DBGMCU_TypeDef::RESERVED6
uint32_t RESERVED6
Definition: stm32h735xx.h:543
RCC_TypeDef::RESERVED12
uint32_t RESERVED12
Definition: stm32h735xx.h:1293
FDCAN_GlobalTypeDef::RXF1S
__IO uint32_t RXF1S
Definition: stm32h735xx.h:356
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition: stm32h735xx.h:146
PWR_TypeDef::D3CR
__IO uint32_t D3CR
Definition: stm32h735xx.h:1226
ETH_TypeDef::MACL3L4C1R
__IO uint32_t MACL3L4C1R
Definition: stm32h735xx.h:803
FDCAN_GlobalTypeDef::TOCV
__IO uint32_t TOCV
Definition: stm32h735xx.h:332
ETH_TypeDef::MACRWKPFR
__IO uint32_t MACRWKPFR
Definition: stm32h735xx.h:746
RCC_TypeDef::PLLCKSELR
__IO uint32_t PLLCKSELR
Definition: stm32h735xx.h:1249
FDCAN_ClockCalibrationUnit_TypeDef::CWD
__IO uint32_t CWD
Definition: stm32h735xx.h:412
GPV_TypeDef::AXI_INI3_READ_QOS
__IO uint32_t AXI_INI3_READ_QOS
Definition: stm32h735xx.h:2141
GPV_TypeDef::AXI_PERIPH_ID_1
__IO uint32_t AXI_PERIPH_ID_1
Definition: stm32h735xx.h:2081
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32h735xx.h:149
ETH_TypeDef::MACVHTR
__IO uint32_t MACVHTR
Definition: stm32h735xx.h:732
ADC_TypeDef::OFR2
__IO uint32_t OFR2
Definition: stm32h735xx.h:270
MDMA_Channel_TypeDef::CLAR
__IO uint32_t CLAR
Definition: stm32h735xx.h:679
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32h735xx.h:129
RCC_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32h735xx.h:1279
FLASH_TypeDef::BOOT_CUR
__IO uint32_t BOOT_CUR
Definition: stm32h735xx.h:978
GPV_TypeDef::AXI_INI3_FN_MOD_AHB
__IO uint32_t AXI_INI3_FN_MOD_AHB
Definition: stm32h735xx.h:2139
TTCAN_TypeDef::TURNA
__IO uint32_t TURNA
Definition: stm32h735xx.h:394
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition: stm32h735xx.h:269
ECC_IRQn
@ ECC_IRQn
Definition: stm32h735xx.h:185
OPAMP_TypeDef::HSOTR
__IO uint32_t HSOTR
Definition: stm32h735xx.h:1091
FDCAN_GlobalTypeDef::TXBTIE
__IO uint32_t TXBTIE
Definition: stm32h735xx.h:367
SYSCFG_TypeDef::UR14
__IO uint32_t UR14
Definition: stm32h735xx.h:1125
OCTOSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32h735xx.h:1980
RCC_TypeDef::D2CCIP1R
__IO uint32_t D2CCIP1R
Definition: stm32h735xx.h:1259
FLASH_TypeDef::PRAR_PRG1
__IO uint32_t PRAR_PRG1
Definition: stm32h735xx.h:973
USART3_IRQn
@ USART3_IRQn
Definition: stm32h735xx.h:101
DTS_TypeDef::ITR1
__IO uint32_t ITR1
Definition: stm32h735xx.h:1515
MDMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition: stm32h735xx.h:682
DBGMCU_TypeDef::PIDR3
__IO uint32_t PIDR3
Definition: stm32h735xx.h:555
FDCAN_GlobalTypeDef::RXF0C
__IO uint32_t RXF0C
Definition: stm32h735xx.h:351
DMAMUX_ChannelStatus_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32h735xx.h:645
TIM24_IRQn
@ TIM24_IRQn
Definition: stm32h735xx.h:201
GPV_TypeDef::AXI_TARG5_FN_MOD_ISS_BM
__IO uint32_t AXI_TARG5_FN_MOD_ISS_BM
Definition: stm32h735xx.h:2109
DBGMCU_TypeDef::CIDR1
__IO uint32_t CIDR1
Definition: stm32h735xx.h:557
OTFDEC_TypeDef
Definition: stm32h735xx.h:2051
TIM1_BRK_IRQn
@ TIM1_BRK_IRQn
Definition: stm32h735xx.h:86
GPV_TypeDef::AXI_TARG3_FN_MOD_ISS_BM
__IO uint32_t AXI_TARG3_FN_MOD_ISS_BM
Definition: stm32h735xx.h:2105
UART4_IRQn
@ UART4_IRQn
Definition: stm32h735xx.h:113
CRS_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32h735xx.h:465
FDCAN_ClockCalibrationUnit_TypeDef::IR
__IO uint32_t IR
Definition: stm32h735xx.h:413
ETH_TypeDef::MACTSCR
__IO uint32_t MACTSCR
Definition: stm32h735xx.h:811
SPI_TypeDef::UDRDR
__IO uint32_t UDRDR
Definition: stm32h735xx.h:1500
TIM_TypeDef
TIM.
Definition: stm32f407xx.h:729
FLASH_TypeDef::ECC_FA1
__IO uint32_t ECC_FA1
Definition: stm32h735xx.h:985
RCC_TypeDef::D3CCIPR
__IO uint32_t D3CCIPR
Definition: stm32h735xx.h:1261
ETH_TypeDef::DMASBMR
__IO uint32_t DMASBMR
Definition: stm32h735xx.h:860
BDMA_Channel_TypeDef
Definition: stm32h735xx.h:623
ETH_TypeDef::MACTSICNR
__IO uint32_t MACTSICNR
Definition: stm32h735xx.h:830
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f407xx.h:574
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f407xx.h:794
USART6_IRQn
@ USART6_IRQn
Definition: stm32h735xx.h:128
FDCAN_GlobalTypeDef::GFC
__IO uint32_t GFC
Definition: stm32h735xx.h:343
FDCAN_GlobalTypeDef::IE
__IO uint32_t IE
Definition: stm32h735xx.h:339
SAI4_IRQn
@ SAI4_IRQn
Definition: stm32h735xx.h:186
ETH_TypeDef::MTLQICSR
__IO uint32_t MTLQICSR
Definition: stm32h735xx.h:854
DAC_TypeDef::SHHR
__IO uint32_t SHHR
Definition: stm32h735xx.h:493
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f407xx.h:861
FMAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:1000
OTFDEC1_IRQn
@ OTFDEC1_IRQn
Definition: stm32h735xx.h:190
OTFDEC_Region_TypeDef::REG_START_ADDR
__IO uint32_t REG_START_ADDR
Definition: stm32h735xx.h:2041
EXTI_TypeDef::SWIER1
__IO uint32_t SWIER1
Definition: stm32h735xx.h:899
FDCAN_GlobalTypeDef::DBTP
__IO uint32_t DBTP
Definition: stm32h735xx.h:324
ETH_TypeDef::MACRXTXSR
__IO uint32_t MACRXTXSR
Definition: stm32h735xx.h:743
SYSCFG_TypeDef::UR15
__IO uint32_t UR15
Definition: stm32h735xx.h:1126
PSSI_TypeDef::IPIDR
__IO uint32_t IPIDR
Definition: stm32h735xx.h:597
FDCAN_GlobalTypeDef::ILS
__IO uint32_t ILS
Definition: stm32h735xx.h:340
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32h735xx.h:97
CRS_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h735xx.h:464
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition: stm32h735xx.h:152
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32h735xx.h:121
OCTOSPI_TypeDef::VER
__IO uint32_t VER
Definition: stm32h735xx.h:2013
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32h735xx.h:89
ADC_TypeDef::SQR4
__IO uint32_t SQR4
Definition: stm32h735xx.h:263
USART_TypeDef::PRESC
__IO uint32_t PRESC
Definition: stm32h735xx.h:1613
CRC_TypeDef
CRC calculation unit.
Definition: stm32f407xx.h:280
SDMMC_TypeDef::IDMABASE0
__IO uint32_t IDMABASE0
Definition: stm32h735xx.h:1434
GPV_TypeDef::AXI_INI4_READ_QOS
__IO uint32_t AXI_INI4_READ_QOS
Definition: stm32h735xx.h:2145
BDMA_Channel1_IRQn
@ BDMA_Channel1_IRQn
Definition: stm32h735xx.h:171
HSEM_Common_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h735xx.h:1475
PWR_TypeDef
Power Control.
Definition: stm32f407xx.h:587
ADC_TypeDef::IER
__IO uint32_t IER
Definition: stm32h735xx.h:249
EXTI_TypeDef::D3PCR1H
__IO uint32_t D3PCR1H
Definition: stm32h735xx.h:902
RCC_TypeDef::APB1HRSTR
__IO uint32_t APB1HRSTR
Definition: stm32h735xx.h:1276
MDMA_Channel_TypeDef::CBRUR
__IO uint32_t CBRUR
Definition: stm32h735xx.h:678
BDMA_Channel5_IRQn
@ BDMA_Channel5_IRQn
Definition: stm32h735xx.h:175
ADC_TypeDef::HTR3_RES11
__IO uint32_t HTR3_RES11
Definition: stm32h735xx.h:286
GPV_TypeDef::AXI_PERIPH_ID_0
__IO uint32_t AXI_PERIPH_ID_0
Definition: stm32h735xx.h:2080
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32f769xx.h:989
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f407xx.h:597
EXTI_TypeDef::FTSR3
__IO uint32_t FTSR3
Definition: stm32h735xx.h:912
FDCAN_GlobalTypeDef::TXBAR
__IO uint32_t TXBAR
Definition: stm32h735xx.h:363
HSEM_TypeDef::C1IER
__IO uint32_t C1IER
Definition: stm32h735xx.h:1461
ETH_TypeDef::MACTSAR
__IO uint32_t MACTSAR
Definition: stm32h735xx.h:817
SDMMC_TypeDef::IDMABASE1
__IO uint32_t IDMABASE1
Definition: stm32h735xx.h:1435
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32h735xx.h:54
ETH_TypeDef::MACL3A3R1R
__IO uint32_t MACL3A3R1R
Definition: stm32h735xx.h:809
RCC_TypeDef::APB3RSTR
__IO uint32_t APB3RSTR
Definition: stm32h735xx.h:1274
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32h735xx.h:111
OTFDEC_TypeDef::SIDR
__IO uint32_t SIDR
Definition: stm32h735xx.h:2063
RAMECC_TypeDef
Definition: stm32h735xx.h:1658
ETH_TypeDef::DMACMFCR
__IO uint32_t DMACMFCR
Definition: stm32h735xx.h:889
FLASH_TypeDef::CRCEADD1
__IO uint32_t CRCEADD1
Definition: stm32h735xx.h:983
SYSCFG_TypeDef::UR3
__IO uint32_t UR3
Definition: stm32h735xx.h:1116
DBGMCU_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32h735xx.h:547
ETH_TypeDef::MMCTLPITCR
__IO uint32_t MMCTLPITCR
Definition: stm32h735xx.h:791
HSEM1_IRQn
@ HSEM1_IRQn
Definition: stm32h735xx.h:167
PSSI_TypeDef::RIS
__IO uint32_t RIS
Definition: stm32h735xx.h:588
FDCAN_GlobalTypeDef::TXEFC
__IO uint32_t TXEFC
Definition: stm32h735xx.h:370
RCC_TypeDef::CRRCR
__IO uint32_t CRRCR
Definition: stm32h735xx.h:1241
FDCAN1_IT0_IRQn
@ FDCAN1_IT0_IRQn
Definition: stm32h735xx.h:81
FDCAN_GlobalTypeDef::NDAT2
__IO uint32_t NDAT2
Definition: stm32h735xx.h:350
GPV_TypeDef::AXI_COMP_ID_2
__IO uint32_t AXI_COMP_ID_2
Definition: stm32h735xx.h:2086
FMAC_TypeDef::WDATA
__IO uint32_t WDATA
Definition: stm32h735xx.h:1002
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32h735xx.h:90
ADC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32h735xx.h:266
TIM_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32h735xx.h:1551
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32f769xx.h:374
ADC_TypeDef::RES1_TR3
__IO uint32_t RES1_TR3
Definition: stm32h735xx.h:258
FDCAN3_IT1_IRQn
@ FDCAN3_IT1_IRQn
Definition: stm32h735xx.h:199
GPV_TypeDef::AXI_TARG7_FN_MOD
__IO uint32_t AXI_TARG7_FN_MOD
Definition: stm32h735xx.h:2119
DBGMCU_TypeDef::PIDR2
__IO uint32_t PIDR2
Definition: stm32h735xx.h:554
DAC_TypeDef::SHSR1
__IO uint32_t SHSR1
Definition: stm32h735xx.h:491
CRYP_TypeDef::K2LR
__IO uint32_t K2LR
Definition: stm32h735xx.h:1685
ETH_TypeDef::MACVR
__IO uint32_t MACVR
Definition: stm32h735xx.h:753
SWPMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32h735xx.h:1625
TTCAN_TypeDef::TTOST
__IO uint32_t TTOST
Definition: stm32h735xx.h:393
FMAC_TypeDef
Filter and Mathematical ACcelerator.
Definition: stm32h735xx.h:994
FDCAN_GlobalTypeDef::TSCC
__IO uint32_t TSCC
Definition: stm32h735xx.h:329
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32h735xx.h:60
CRYP_TypeDef::SR
__IO uint32_t SR
Definition: stm32h735xx.h:1674
RCC_TypeDef::APB1LENR
__IO uint32_t APB1LENR
Definition: stm32h735xx.h:1289
ETH_TypeDef::DMACSR
__IO uint32_t DMACSR
Definition: stm32h735xx.h:887
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32h735xx.h:115
SWPMI_TypeDef::TDR
__IO uint32_t TDR
Definition: stm32h735xx.h:1628
ETH_TypeDef::DMACCARDR
__IO uint32_t DMACCARDR
Definition: stm32h735xx.h:882
EXTI_Core_TypeDef::PR1
__IO uint32_t PR1
Definition: stm32h735xx.h:944
DTS_TypeDef::DR
__IO uint32_t DR
Definition: stm32h735xx.h:1517
CRYP_TypeDef::CSGCMCCM6R
__IO uint32_t CSGCMCCM6R
Definition: stm32h735xx.h:1699
ETH_TypeDef::MACTSSR
__IO uint32_t MACTSSR
Definition: stm32h735xx.h:819
FMC_Bank2_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32h735xx.h:1034
DTS_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32h735xx.h:1511
MDMA_Channel_TypeDef::CDAR
__IO uint32_t CDAR
Definition: stm32h735xx.h:677
EXTI_TypeDef::FTSR1
__IO uint32_t FTSR1
Definition: stm32h735xx.h:898
MDMA_IRQn
@ MDMA_IRQn
Definition: stm32h735xx.h:165
EXTI_TypeDef::D3PCR3H
__IO uint32_t D3PCR3H
Definition: stm32h735xx.h:916
GPV_TypeDef::AXI_TARG7_FN_MOD2
__IO uint32_t AXI_TARG7_FN_MOD2
Definition: stm32h735xx.h:2115
GPV_TypeDef::AXI_INI4_FN_MOD
__IO uint32_t AXI_INI4_FN_MOD
Definition: stm32h735xx.h:2147
FDCAN_GlobalTypeDef::NBTP
__IO uint32_t NBTP
Definition: stm32h735xx.h:328
EXTI_Core_TypeDef::EMR1
__IO uint32_t EMR1
Definition: stm32h735xx.h:943
FDCAN_ClockCalibrationUnit_TypeDef::CCFG
__IO uint32_t CCFG
Definition: stm32h735xx.h:410
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h735xx.h:49
RCC_IRQn
@ RCC_IRQn
Definition: stm32h735xx.h:67
DTS_TypeDef::CFGR1
__IO uint32_t CFGR1
Definition: stm32h735xx.h:1510
SAI_Block_TypeDef
Definition: stm32f469xx.h:848
CRYP_TypeDef::CSGCM7R
__IO uint32_t CSGCM7R
Definition: stm32h735xx.h:1708
DBGMCU_TypeDef::APB3FZ1
__IO uint32_t APB3FZ1
Definition: stm32h735xx.h:540
DLYB_TypeDef
Delay Block DLYB.
Definition: stm32h735xx.h:1447
WAKEUP_PIN_IRQn
@ WAKEUP_PIN_IRQn
Definition: stm32h735xx.h:188
SDMMC_TypeDef::IPVR
__IO uint32_t IPVR
Definition: stm32h735xx.h:1439
MDIOS_IRQn
@ MDIOS_IRQn
Definition: stm32h735xx.h:164
ETH_TypeDef::DMACTDRLR
__IO uint32_t DMACTDRLR
Definition: stm32h735xx.h:874
EXTI_TypeDef::EMR1
__IO uint32_t EMR1
Definition: stm32h735xx.h:919
FDCAN_GlobalTypeDef::CREL
__IO uint32_t CREL
Definition: stm32h735xx.h:321
SAI_TypeDef::PDMDLY
__IO uint32_t PDMDLY
Definition: stm32h735xx.h:1376
FDCAN_GlobalTypeDef::TXFQS
__IO uint32_t TXFQS
Definition: stm32h735xx.h:360
OCTOSPI_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32h735xx.h:1985
GPV_TypeDef::AXI_COMP_ID_3
__IO uint32_t AXI_COMP_ID_3
Definition: stm32h735xx.h:2087
CRYP_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:1673
GPV_TypeDef::AXI_TARG8_FN_MOD
__IO uint32_t AXI_TARG8_FN_MOD
Definition: stm32h735xx.h:2125
ADC_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32h735xx.h:282
CRYP_TypeDef::K1RR
__IO uint32_t K1RR
Definition: stm32h735xx.h:1684
DBGMCU_TypeDef::PIDR0
__IO uint32_t PIDR0
Definition: stm32h735xx.h:552
ETH_TypeDef::MACHT0R
__IO uint32_t MACHT0R
Definition: stm32h735xx.h:727
PSSI_TypeDef::MIS
__IO uint32_t MIS
Definition: stm32h735xx.h:590
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32h735xx.h:131
BDMA_Channel7_IRQn
@ BDMA_Channel7_IRQn
Definition: stm32h735xx.h:177
OTFDEC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32h735xx.h:2056
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition: stm32h735xx.h:153
MDMA_Channel_TypeDef::CBNDTR
__IO uint32_t CBNDTR
Definition: stm32h735xx.h:675
MDMA_Channel_TypeDef::CTBR
__IO uint32_t CTBR
Definition: stm32h735xx.h:680
CRYP_TypeDef::K3RR
__IO uint32_t K3RR
Definition: stm32h735xx.h:1688
FDCAN_GlobalTypeDef::TXEFA
__IO uint32_t TXEFA
Definition: stm32h735xx.h:372
COMP_Common_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32h735xx.h:1594
FPU_IRQn
@ FPU_IRQn
Definition: stm32h735xx.h:138
ADC_TypeDef
Analog to Digital Converter
Definition: stm32f407xx.h:179
PWR_TypeDef::WKUPEPR
__IO uint32_t WKUPEPR
Definition: stm32h735xx.h:1230
FDCAN_GlobalTypeDef::TXBCR
__IO uint32_t TXBCR
Definition: stm32h735xx.h:364
OCTOSPI_TypeDef::RESERVED19
uint32_t RESERVED19
Definition: stm32h735xx.h:2005
ETH_TypeDef::MMCTSCGPR
__IO uint32_t MMCTSCGPR
Definition: stm32h735xx.h:780
ETH_TypeDef::RESERVED44
uint32_t RESERVED44
Definition: stm32h735xx.h:885
ETH_TypeDef::MACL3L4C0R
__IO uint32_t MACL3L4C0R
Definition: stm32h735xx.h:795
OTFDEC_Region_TypeDef::REG_KEYR2
__IO uint32_t REG_KEYR2
Definition: stm32h735xx.h:2047
RCC_TypeDef::AHB4LPENR
__IO uint32_t AHB4LPENR
Definition: stm32h735xx.h:1297
GPV_TypeDef::AXI_INI6_FN_MOD
__IO uint32_t AXI_INI6_FN_MOD
Definition: stm32h735xx.h:2155
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition: stm32h735xx.h:157
OCTOSPI_TypeDef::DCR4
__IO uint32_t DCR4
Definition: stm32h735xx.h:1967
SYSCFG_TypeDef::UR16
__IO uint32_t UR16
Definition: stm32h735xx.h:1127
RAMECC_MonitorTypeDef::FDRH
__IO uint32_t FDRH
Definition: stm32h735xx.h:1654
USART1_IRQn
@ USART1_IRQn
Definition: stm32h735xx.h:99
ETH_TypeDef::MMCRAEPR
__IO uint32_t MMCRAEPR
Definition: stm32h735xx.h:786
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32h735xx.h:102
EXTI_Core_TypeDef
This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx,...
Definition: stm32h735xx.h:940
ADC_TypeDef::AWD3CR
__IO uint32_t AWD3CR
Definition: stm32h735xx.h:280
EXTI_TypeDef::RTSR2
__IO uint32_t RTSR2
Definition: stm32h735xx.h:904
FDCAN_GlobalTypeDef::TDCR
__IO uint32_t TDCR
Definition: stm32h735xx.h:336
ETH_TypeDef::MACIER
__IO uint32_t MACIER
Definition: stm32h735xx.h:742
FDCAN_GlobalTypeDef::IR
__IO uint32_t IR
Definition: stm32h735xx.h:338
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f407xx.h:443
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32h735xx.h:73
ETH_TypeDef::MTLTQUR
__IO uint32_t MTLTQUR
Definition: stm32h735xx.h:851
COMPOPT_TypeDef::ICFR
__IO uint32_t ICFR
Definition: stm32h735xx.h:1583
ADC_TypeDef::LTR2_DIFSEL
__IO uint32_t LTR2_DIFSEL
Definition: stm32h735xx.h:283
DMA2D_IRQn
@ DMA2D_IRQn
Definition: stm32h735xx.h:147
EXTI_TypeDef::D3PCR1L
__IO uint32_t D3PCR1L
Definition: stm32h735xx.h:901
ETH_TypeDef::MACIVIR
__IO uint32_t MACIVIR
Definition: stm32h735xx.h:735
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32h735xx.h:93
ETH_TypeDef::MACL4A1R
__IO uint32_t MACL4A1R
Definition: stm32h735xx.h:804
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32h735xx.h:116
EXTI_Core_TypeDef::PR2
__IO uint32_t PR2
Definition: stm32h735xx.h:948
ETH_TypeDef::MACDR
__IO uint32_t MACDR
Definition: stm32h735xx.h:754
DAC_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32h735xx.h:490
FMAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32h735xx.h:1001
CRYP_TypeDef::K1LR
__IO uint32_t K1LR
Definition: stm32h735xx.h:1683
ETH_TypeDef::DMAISR
__IO uint32_t DMAISR
Definition: stm32h735xx.h:861
FMC_Bank2_TypeDef::PCR2
__IO uint32_t PCR2
Definition: stm32h735xx.h:1030
ETH_TypeDef::DMADSR
__IO uint32_t DMADSR
Definition: stm32h735xx.h:862
OTFDEC_TypeDef::HWCFGR1
__IO uint32_t HWCFGR1
Definition: stm32h735xx.h:2060
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f407xx.h:889
CRYP_TypeDef::K3LR
__IO uint32_t K3LR
Definition: stm32h735xx.h:1687
FDCAN_GlobalTypeDef::TSCV
__IO uint32_t TSCV
Definition: stm32h735xx.h:330
GPV_TypeDef::AXI_PERIPH_ID_2
__IO uint32_t AXI_PERIPH_ID_2
Definition: stm32h735xx.h:2082
EXTI_Core_TypeDef::IMR1
__IO uint32_t IMR1
Definition: stm32h735xx.h:942
PWR_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32h735xx.h:1223
SYSCFG_TypeDef::CCCSR
__IO uint32_t CCCSR
Definition: stm32h735xx.h:1105
ETH_TypeDef::MACLCSR
__IO uint32_t MACLCSR
Definition: stm32h735xx.h:748
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32h735xx.h:107
ETH_TypeDef::MACLTCR
__IO uint32_t MACLTCR
Definition: stm32h735xx.h:749
RCC_TypeDef::APB1LLPENR
__IO uint32_t APB1LLPENR
Definition: stm32h735xx.h:1299
BDMA_Channel4_IRQn
@ BDMA_Channel4_IRQn
Definition: stm32h735xx.h:174
OCTOSPI_TypeDef::MID
__IO uint32_t MID
Definition: stm32h735xx.h:2015
OCTOSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32h735xx.h:1972
TIM23_IRQn
@ TIM23_IRQn
Definition: stm32h735xx.h:200
TTCAN_TypeDef::TTMLM
__IO uint32_t TTMLM
Definition: stm32h735xx.h:385
GPV_TypeDef::AXI_TARG1_FN_MOD_LB
__IO uint32_t AXI_TARG1_FN_MOD_LB
Definition: stm32h735xx.h:2093
ETH_IRQn
@ ETH_IRQn
Definition: stm32h735xx.h:122
MDMA_TypeDef
MDMA Controller.
Definition: stm32h735xx.h:663
CRYP_TypeDef::IV1LR
__IO uint32_t IV1LR
Definition: stm32h735xx.h:1691
CORDIC_TypeDef
COordincate Rotation DIgital Computer.
Definition: stm32h735xx.h:435
EXTI_TypeDef::PR3
__IO uint32_t PR3
Definition: stm32h735xx.h:928
DMAMUX_RequestGenStatus_TypeDef::RGSR
__IO uint32_t RGSR
Definition: stm32h735xx.h:656
MDIOS_WKUP_IRQn
@ MDIOS_WKUP_IRQn
Definition: stm32h735xx.h:163
GPV_TypeDef::AXI_PERIPH_ID_4
__IO uint32_t AXI_PERIPH_ID_4
Definition: stm32h735xx.h:2076
OCTOSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32h735xx.h:1976
ETH_TypeDef::DMACRDTPR
__IO uint32_t DMACRDTPR
Definition: stm32h735xx.h:873
MDMA_Channel_TypeDef::CSAR
__IO uint32_t CSAR
Definition: stm32h735xx.h:676
EXTI_TypeDef::RTSR3
__IO uint32_t RTSR3
Definition: stm32h735xx.h:911
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f469xx.h:377
CRYP_TypeDef::CSGCMCCM7R
__IO uint32_t CSGCMCCM7R
Definition: stm32h735xx.h:1700
GPV_TypeDef::AXI_TARG2_FN_MOD_LB
__IO uint32_t AXI_TARG2_FN_MOD_LB
Definition: stm32h735xx.h:2101
SWPMI_TypeDef::OR
__IO uint32_t OR
Definition: stm32h735xx.h:1630
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32h735xx.h:127
ETH_TypeDef::MTLRQMPOCR
__IO uint32_t MTLRQMPOCR
Definition: stm32h735xx.h:856
FDCAN_GlobalTypeDef::XIDAM
__IO uint32_t XIDAM
Definition: stm32h735xx.h:347
OPAMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32h735xx.h:1089
FDCAN_ClockCalibrationUnit_TypeDef::IE
__IO uint32_t IE
Definition: stm32h735xx.h:414
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32h735xx.h:105
ETH_TypeDef::MMCTLPIMSTR
__IO uint32_t MMCTLPIMSTR
Definition: stm32h735xx.h:790
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32h735xx.h:96
TIM_TypeDef::TISEL
__IO uint32_t TISEL
Definition: stm32h735xx.h:1557
ETH_TypeDef::DMACRCR
__IO uint32_t DMACRCR
Definition: stm32h735xx.h:866
OCTOSPI_TypeDef::HLCR
__IO uint32_t HLCR
Definition: stm32h735xx.h:2010
FLASH_TypeDef::WPSN_CUR1
__IO uint32_t WPSN_CUR1
Definition: stm32h735xx.h:976
OCTOSPIM_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:2027
ETH_TypeDef::MACPOCR
__IO uint32_t MACPOCR
Definition: stm32h735xx.h:840
GPV_TypeDef::AXI_INI2_WRITE_QOS
__IO uint32_t AXI_INI2_WRITE_QOS
Definition: stm32h735xx.h:2135
FDCAN_GlobalTypeDef::ENDN
__IO uint32_t ENDN
Definition: stm32h735xx.h:322
CRYP_TypeDef::K0LR
__IO uint32_t K0LR
Definition: stm32h735xx.h:1681
RCC_TypeDef::PLL2DIVR
__IO uint32_t PLL2DIVR
Definition: stm32h735xx.h:1253
FDCAN_GlobalTypeDef::ECR
__IO uint32_t ECR
Definition: stm32h735xx.h:334
CRYP_TypeDef::CSGCMCCM1R
__IO uint32_t CSGCMCCM1R
Definition: stm32h735xx.h:1694
RCC_TypeDef::APB1HLPENR
__IO uint32_t APB1HLPENR
Definition: stm32h735xx.h:1300
ETH_TypeDef::MACACR
__IO uint32_t MACACR
Definition: stm32h735xx.h:824
SYSCFG_TypeDef::UR13
__IO uint32_t UR13
Definition: stm32h735xx.h:1124
TTCAN_TypeDef::TTIE
__IO uint32_t TTIE
Definition: stm32h735xx.h:391
USB_OTG_GlobalTypeDef::GHWCFG2
__IO uint32_t GHWCFG2
Definition: stm32h735xx.h:1853
DMAMUX_RequestGen_TypeDef
Definition: stm32h735xx.h:649
CRYP_TypeDef::CSGCM5R
__IO uint32_t CSGCM5R
Definition: stm32h735xx.h:1706
ETH_TypeDef::MMCRLPITCR
__IO uint32_t MMCRLPITCR
Definition: stm32h735xx.h:793
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32h735xx.h:55
ETH_TypeDef::RESERVED28
uint32_t RESERVED28
Definition: stm32h735xx.h:825
FDCAN_GlobalTypeDef::RXF1A
__IO uint32_t RXF1A
Definition: stm32h735xx.h:357
GPV_TypeDef
Global Programmer View.
Definition: stm32h735xx.h:2073
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32h735xx.h:92
PWR_TypeDef::WKUPCR
__IO uint32_t WKUPCR
Definition: stm32h735xx.h:1228
FDCAN_ClockCalibrationUnit_TypeDef
FD Controller Area Network.
Definition: stm32h735xx.h:407
CRYP_TypeDef::IV0RR
__IO uint32_t IV0RR
Definition: stm32h735xx.h:1690
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32h735xx.h:133
OCTOSPI_TypeDef::RESERVED6
uint32_t RESERVED6
Definition: stm32h735xx.h:1979
FDCAN_GlobalTypeDef::XIDFC
__IO uint32_t XIDFC
Definition: stm32h735xx.h:345
RCC_TypeDef::PLL3DIVR
__IO uint32_t PLL3DIVR
Definition: stm32h735xx.h:1255
OTFDEC_Region_TypeDef
OTFD register.
Definition: stm32h735xx.h:2038
OCTOSPI_TypeDef
OCTO Serial Peripheral Interface.
Definition: stm32h735xx.h:1960
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f407xx.h:527
MDMA_Channel_TypeDef
Definition: stm32h735xx.h:668
EXTI_TypeDef::PR2
__IO uint32_t PR2
Definition: stm32h735xx.h:924
TIM1_UP_IRQn
@ TIM1_UP_IRQn
Definition: stm32h735xx.h:87
TIM16_IRQn
@ TIM16_IRQn
Definition: stm32h735xx.h:161
OCTOSPI_TypeDef::ID
__IO uint32_t ID
Definition: stm32h735xx.h:2014
MDMA_Channel_TypeDef::CISR
__IO uint32_t CISR
Definition: stm32h735xx.h:670
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f407xx.h:293
GPV_TypeDef::AXI_INI1_WRITE_QOS
__IO uint32_t AXI_INI1_WRITE_QOS
Definition: stm32h735xx.h:2131
ETH_TypeDef::DMACTDTPR
__IO uint32_t DMACTDTPR
Definition: stm32h735xx.h:871
GPV_TypeDef::AXI_COMP_ID_1
__IO uint32_t AXI_COMP_ID_1
Definition: stm32h735xx.h:2085
GPV_TypeDef::AXI_INI6_WRITE_QOS
__IO uint32_t AXI_INI6_WRITE_QOS
Definition: stm32h735xx.h:2154
HASH_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32h735xx.h:1721
BDMA_TypeDef
Definition: stm32h735xx.h:632
LPTIM_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32h735xx.h:1573
ETH_TypeDef::MTLRQOMR
__IO uint32_t MTLRQOMR
Definition: stm32h735xx.h:855
FMAC_TypeDef::YBUFCFG
__IO uint32_t YBUFCFG
Definition: stm32h735xx.h:998
DBGMCU_TypeDef::CIDR2
__IO uint32_t CIDR2
Definition: stm32h735xx.h:558
LPTIM4_IRQn
@ LPTIM4_IRQn
Definition: stm32h735xx.h:181
SYSCFG_TypeDef::UR5
__IO uint32_t UR5
Definition: stm32h735xx.h:1118
OCTOSPI_TypeDef::WCCR
__IO uint32_t WCCR
Definition: stm32h735xx.h:2002
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32h735xx.h:98
ETH_TypeDef::MACTTSSNR
__IO uint32_t MACTTSSNR
Definition: stm32h735xx.h:821
ADC_IRQn
@ ADC_IRQn
Definition: stm32h735xx.h:80
ETH_TypeDef::DMACSFCSR
__IO uint32_t DMACSFCSR
Definition: stm32h735xx.h:878
SWPMI_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32h735xx.h:1622
EXTI_Core_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32h735xx.h:945
RAMECC_MonitorTypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:1650
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32h735xx.h:110
RCC_TypeDef::APB1LRSTR
__IO uint32_t APB1LRSTR
Definition: stm32h735xx.h:1275
SPI_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32h735xx.h:1492
FDCAN_GlobalTypeDef::RESERVED5
__IO uint32_t RESERVED5
Definition: stm32h735xx.h:346
DTS_TypeDef::RAMPVALR
__IO uint32_t RAMPVALR
Definition: stm32h735xx.h:1514
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f469xx.h:723
FDCAN_GlobalTypeDef::TOCC
__IO uint32_t TOCC
Definition: stm32h735xx.h:331
EXTI_TypeDef::EMR3
__IO uint32_t EMR3
Definition: stm32h735xx.h:927
SPI_TypeDef::CFG2
__IO uint32_t CFG2
Definition: stm32h735xx.h:1488
ETH_TypeDef::MACL3A2R0R
__IO uint32_t MACL3A2R0R
Definition: stm32h735xx.h:800
EXTI_TypeDef::D3PCR2L
__IO uint32_t D3PCR2L
Definition: stm32h735xx.h:908
FDCAN_GlobalTypeDef::TXBTO
__IO uint32_t TXBTO
Definition: stm32h735xx.h:365
ETH_TypeDef::DMACTCR
__IO uint32_t DMACTCR
Definition: stm32h735xx.h:865
DTS_TypeDef::T0VALR1
__IO uint32_t T0VALR1
Definition: stm32h735xx.h:1512
BDMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition: stm32h735xx.h:627
ADC_TypeDef::LTR3_RES10
__IO uint32_t LTR3_RES10
Definition: stm32h735xx.h:285
ETH_TypeDef::MACECR
__IO uint32_t MACECR
Definition: stm32h735xx.h:724
OCTOSPI_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32h735xx.h:1981
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f407xx.h:773
CRYP_TypeDef::IV0LR
__IO uint32_t IV0LR
Definition: stm32h735xx.h:1689
ADC_Common_TypeDef
Definition: stm32f407xx.h:203
RCC_TypeDef::D2CFGR
__IO uint32_t D2CFGR
Definition: stm32h735xx.h:1246
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32h735xx.h:117
ETH_TypeDef::MACLMIR
__IO uint32_t MACLMIR
Definition: stm32h735xx.h:844
SDMMC_TypeDef::IDMACTRL
__IO uint32_t IDMACTRL
Definition: stm32h735xx.h:1432
TTCAN_TypeDef::TTTMC
__IO uint32_t TTTMC
Definition: stm32h735xx.h:382
SDMMC2_IRQn
@ SDMMC2_IRQn
Definition: stm32h735xx.h:166
FLASH_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32h735xx.h:967
EXTI_TypeDef::IMR3
__IO uint32_t IMR3
Definition: stm32h735xx.h:926
DMAMUX_RequestGenStatus_TypeDef::RGCFR
__IO uint32_t RGCFR
Definition: stm32h735xx.h:657
ETH_TypeDef::MACL3A1R0R
__IO uint32_t MACL3A1R0R
Definition: stm32h735xx.h:799
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32h735xx.h:79
FLASH_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32h735xx.h:965
OTFDEC_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:2053
OTFDEC_TypeDef::VERR
__IO uint32_t VERR
Definition: stm32h735xx.h:2061
DBGMCU_TypeDef::RESERVED5
uint32_t RESERVED5
Definition: stm32h735xx.h:541
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32h735xx.h:72
ETH_TypeDef::MACPFR
__IO uint32_t MACPFR
Definition: stm32h735xx.h:725
ETH_TypeDef::MACWTR
__IO uint32_t MACWTR
Definition: stm32h735xx.h:726
HASH_TypeDef::STR
__IO uint32_t STR
Definition: stm32h735xx.h:1719
DMAMUX1_OVR_IRQn
@ DMAMUX1_OVR_IRQn
Definition: stm32h735xx.h:154
HSEM_TypeDef::C1MISR
__IO uint32_t C1MISR
Definition: stm32h735xx.h:1464
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32h735xx.h:57
OCTOSPI_TypeDef::WIR
__IO uint32_t WIR
Definition: stm32h735xx.h:2006
OTFDEC_Region_TypeDef::REG_CONFIGR
__IO uint32_t REG_CONFIGR
Definition: stm32h735xx.h:2040
ETH_TypeDef::MACL3A3R0R
__IO uint32_t MACL3A3R0R
Definition: stm32h735xx.h:801
BDMA_Channel3_IRQn
@ BDMA_Channel3_IRQn
Definition: stm32h735xx.h:173
DTS_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32h735xx.h:1516
FDCAN_GlobalTypeDef::NDAT1
__IO uint32_t NDAT1
Definition: stm32h735xx.h:349
ADC_TypeDef::CALFACT2_RES14
__IO uint32_t CALFACT2_RES14
Definition: stm32h735xx.h:289
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32f769xx.h:352
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:327
MDMA_Channel_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32h735xx.h:681
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32h735xx.h:119
GPV_TypeDef::AXI_TARG8_FN_MOD2
__IO uint32_t AXI_TARG8_FN_MOD2
Definition: stm32h735xx.h:2123
DAC_TypeDef::SHSR2
__IO uint32_t SHSR2
Definition: stm32h735xx.h:492
ETH_TypeDef::MACL3A1R1R
__IO uint32_t MACL3A1R1R
Definition: stm32h735xx.h:807
RCC_TypeDef::PLL1FRACR
__IO uint32_t PLL1FRACR
Definition: stm32h735xx.h:1252
RNG_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32h735xx.h:1746
ETH_TypeDef::MTLOMR
__IO uint32_t MTLOMR
Definition: stm32h735xx.h:846
PSSI_TypeDef
PSSI.
Definition: stm32h735xx.h:584
BDMA_Channel2_IRQn
@ BDMA_Channel2_IRQn
Definition: stm32h735xx.h:172
SWPMI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32h735xx.h:1623
HASH_TypeDef::DIN
__IO uint32_t DIN
Definition: stm32h735xx.h:1718
DTS_TypeDef
DTS.
Definition: stm32h735xx.h:1508
PSSI_TypeDef::DR
__IO uint32_t DR
Definition: stm32h735xx.h:593
EXTI_TypeDef::SWIER2
__IO uint32_t SWIER2
Definition: stm32h735xx.h:906
DBGMCU_TypeDef::CIDR3
__IO uint32_t CIDR3
Definition: stm32h735xx.h:559
RCC_TypeDef::APB3ENR
__IO uint32_t APB3ENR
Definition: stm32h735xx.h:1288
ETH_TypeDef::DMACTDLAR
__IO uint32_t DMACTDLAR
Definition: stm32h735xx.h:868
FDCAN_GlobalTypeDef::HPMS
__IO uint32_t HPMS
Definition: stm32h735xx.h:348
OCTOSPI_TypeDef::DCR1
__IO uint32_t DCR1
Definition: stm32h735xx.h:1964
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32h735xx.h:132
ETH_TypeDef::MACL4A0R
__IO uint32_t MACL4A0R
Definition: stm32h735xx.h:796
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32h735xx.h:74
SYSCFG_TypeDef::UR6
__IO uint32_t UR6
Definition: stm32h735xx.h:1119
OTFDEC_TypeDef::IPIDR
__IO uint32_t IPIDR
Definition: stm32h735xx.h:2062
ADC_TypeDef::AWD2CR
__IO uint32_t AWD2CR
Definition: stm32h735xx.h:279
RCC_TypeDef::AHB4ENR
__IO uint32_t AHB4ENR
Definition: stm32h735xx.h:1287
DTS_TypeDef::ICIFR
__IO uint32_t ICIFR
Definition: stm32h735xx.h:1520
EXTI_Core_TypeDef::EMR3
__IO uint32_t EMR3
Definition: stm32h735xx.h:951
ETH_TypeDef::MACTTSSSR
__IO uint32_t MACTTSSSR
Definition: stm32h735xx.h:822
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32h735xx.h:134
SWPMI_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h735xx.h:1624
SWPMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32h735xx.h:1626
DTS_TypeDef::OR
__IO uint32_t OR
Definition: stm32h735xx.h:1521
ETH_TypeDef::MACPPSCR
__IO uint32_t MACPPSCR
Definition: stm32h735xx.h:833
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f407xx.h:819
ETH_TypeDef::RESERVED42
uint32_t RESERVED42
Definition: stm32h735xx.h:881
FDCAN1_IT1_IRQn
@ FDCAN1_IT1_IRQn
Definition: stm32h735xx.h:83
EXTI_TypeDef::RESERVED5
uint32_t RESERVED5
Definition: stm32h735xx.h:925
GPV_TypeDef::AXI_TARG7_FN_MOD_LB
__IO uint32_t AXI_TARG7_FN_MOD_LB
Definition: stm32h735xx.h:2117
OCTOSPI_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32h735xx.h:1975
CRYP_TypeDef
Crypto Processor.
Definition: stm32h735xx.h:1671
EXTI_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32h735xx.h:921
FLASH_TypeDef::OPTSR2_PRG
__IO uint32_t OPTSR2_PRG
Definition: stm32h735xx.h:988
RCC_TypeDef::APB3LPENR
__IO uint32_t APB3LPENR
Definition: stm32h735xx.h:1298
RCC_TypeDef::D1CCIPR
__IO uint32_t D1CCIPR
Definition: stm32h735xx.h:1258
FDCAN_GlobalTypeDef::RXBC
__IO uint32_t RXBC
Definition: stm32h735xx.h:354
MDMA_Channel_TypeDef::CTCR
__IO uint32_t CTCR
Definition: stm32h735xx.h:674
DBGMCU_TypeDef::CIDR0
__IO uint32_t CIDR0
Definition: stm32h735xx.h:556
EXTI_TypeDef::IMR1
__IO uint32_t IMR1
Definition: stm32h735xx.h:918
EXTI_TypeDef::PR1
__IO uint32_t PR1
Definition: stm32h735xx.h:920
FMC_Bank2_TypeDef::PATT2
__IO uint32_t PATT2
Definition: stm32h735xx.h:1033
GPV_TypeDef::AXI_PERIPH_ID_3
__IO uint32_t AXI_PERIPH_ID_3
Definition: stm32h735xx.h:2083
LPTIM3_IRQn
@ LPTIM3_IRQn
Definition: stm32h735xx.h:180
SYSCFG_TypeDef::UR1
__IO uint32_t UR1
Definition: stm32h735xx.h:1114
SYSCFG_TypeDef::UR17
__IO uint32_t UR17
Definition: stm32h735xx.h:1128
SPI_TypeDef::CRCPOLY
__IO uint32_t CRCPOLY
Definition: stm32h735xx.h:1497
EXTI_Core_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32h735xx.h:949
CORDIC_TypeDef::RDATA
__IO uint32_t RDATA
Definition: stm32h735xx.h:439
PSSI_TypeDef::HWCFGR
__IO uint32_t HWCFGR
Definition: stm32h735xx.h:595
ETH_TypeDef::MACVIR
__IO uint32_t MACVIR
Definition: stm32h735xx.h:734
EXTI_TypeDef::SWIER3
__IO uint32_t SWIER3
Definition: stm32h735xx.h:913
SYSCFG_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32h735xx.h:1104
FDCAN_GlobalTypeDef::RWD
__IO uint32_t RWD
Definition: stm32h735xx.h:326
GPV_TypeDef::AXI_INI1_FN_MOD2
__IO uint32_t AXI_INI1_FN_MOD2
Definition: stm32h735xx.h:2127
UART9_IRQn
@ UART9_IRQn
Definition: stm32h735xx.h:194
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32h735xx.h:68
ETH_TypeDef::MACLETR
__IO uint32_t MACLETR
Definition: stm32h735xx.h:750
ETH_TypeDef::MACTFCR
__IO uint32_t MACTFCR
Definition: stm32h735xx.h:737
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32h735xx.h:77
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition: stm32h735xx.h:158
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition: stm32h735xx.h:155
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f469xx.h:602
UART7_IRQn
@ UART7_IRQn
Definition: stm32h735xx.h:139
GPV_TypeDef::AXI_INI2_FN_MOD
__IO uint32_t AXI_INI2_FN_MOD
Definition: stm32h735xx.h:2136
ETH_TypeDef::MACSTNUR
__IO uint32_t MACSTNUR
Definition: stm32h735xx.h:816
CRYP_IRQn
@ CRYP_IRQn
Definition: stm32h735xx.h:136
COMP_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32h735xx.h:1589
CRYP_TypeDef::IMSCR
__IO uint32_t IMSCR
Definition: stm32h735xx.h:1678
ADC_TypeDef::CALFACT_RES13
__IO uint32_t CALFACT_RES13
Definition: stm32h735xx.h:288
GPV_TypeDef::RESERVED15
uint32_t RESERVED15
Definition: stm32h735xx.h:2116
ETH_TypeDef::MACPPSIR
__IO uint32_t MACPPSIR
Definition: stm32h735xx.h:837
ETH_TypeDef::MACMDIODR
__IO uint32_t MACMDIODR
Definition: stm32h735xx.h:761
PWR_TypeDef::WKUPFR
__IO uint32_t WKUPFR
Definition: stm32h735xx.h:1229
TTCAN_TypeDef::TURCF
__IO uint32_t TURCF
Definition: stm32h735xx.h:386
RAMECC_MonitorTypeDef::FDRL
__IO uint32_t FDRL
Definition: stm32h735xx.h:1653
SYSCFG_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32h735xx.h:1100
CRS_TypeDef
Clock Recovery System.
Definition: stm32h735xx.h:460
SYSCFG_TypeDef::CCCR
__IO uint32_t CCCR
Definition: stm32h735xx.h:1107
FDCAN_GlobalTypeDef::RXF0S
__IO uint32_t RXF0S
Definition: stm32h735xx.h:352
DBGMCU_TypeDef::PIDR4
__IO uint32_t PIDR4
Definition: stm32h735xx.h:550
ETH_TypeDef::MACPCSR
__IO uint32_t MACPCSR
Definition: stm32h735xx.h:745
TIM17_IRQn
@ TIM17_IRQn
Definition: stm32h735xx.h:162
CEC_TypeDef
HDMI-CEC.
Definition: stm32f769xx.h:301
PSSI_TypeDef::SR
__IO uint32_t SR
Definition: stm32h735xx.h:587
BDMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h735xx.h:634
ETH_TypeDef::MACHT1R
__IO uint32_t MACHT1R
Definition: stm32h735xx.h:728
DMAMUX_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h735xx.h:640
ETH_TypeDef::RESERVED39
uint32_t RESERVED39
Definition: stm32h735xx.h:869
GPV_TypeDef::AXI_INI3_FN_MOD2
__IO uint32_t AXI_INI3_FN_MOD2
Definition: stm32h735xx.h:2138
EXTI_Core_TypeDef::PR3
__IO uint32_t PR3
Definition: stm32h735xx.h:952
OCTOSPI_TypeDef::RESERVED14
uint32_t RESERVED14
Definition: stm32h735xx.h:1995
LTDC_IRQn
@ LTDC_IRQn
Definition: stm32h735xx.h:145
ETH_TypeDef::MACPPSTTNR
__IO uint32_t MACPPSTTNR
Definition: stm32h735xx.h:836
MDMA_Channel_TypeDef::CIFCR
__IO uint32_t CIFCR
Definition: stm32h735xx.h:671
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32h735xx.h:62
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32h735xx.h:59
HSEM_Common_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32h735xx.h:1476
OTFDEC_Region_TypeDef::REG_KEYR3
__IO uint32_t REG_KEYR3
Definition: stm32h735xx.h:2048
SPI_TypeDef::TXCRC
__IO uint32_t TXCRC
Definition: stm32h735xx.h:1498
ETH_TypeDef::MACSPI0R
__IO uint32_t MACSPI0R
Definition: stm32h735xx.h:841
EXTI_Core_TypeDef::EMR2
__IO uint32_t EMR2
Definition: stm32h735xx.h:947
OCTOSPI_TypeDef::WABR
__IO uint32_t WABR
Definition: stm32h735xx.h:2008
SYSCFG_TypeDef::ADC2ALT
__IO uint32_t ADC2ALT
Definition: stm32h735xx.h:1109
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32h735xx.h:103
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32h735xx.h:78
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32h735xx.h:52
FDCAN_GlobalTypeDef::RXESC
__IO uint32_t RXESC
Definition: stm32h735xx.h:358
ADC_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:250
ADC_TypeDef::LTR1_TR1
__IO uint32_t LTR1_TR1
Definition: stm32h735xx.h:256
OCTOSPI_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32h735xx.h:1973
GPV_TypeDef::AXI_INI5_READ_QOS
__IO uint32_t AXI_INI5_READ_QOS
Definition: stm32h735xx.h:2149
TTCAN_TypeDef::TTIR
__IO uint32_t TTIR
Definition: stm32h735xx.h:390
USB_OTG_GlobalTypeDef::GPWRDN
__IO uint32_t GPWRDN
Definition: stm32h735xx.h:1857
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h735xx.h:248
LPTIM5_IRQn
@ LPTIM5_IRQn
Definition: stm32h735xx.h:182
HSEM_TypeDef::CR
__IO uint32_t CR
Definition: stm32h735xx.h:1466
ETH_TypeDef::MMCTPCGR
__IO uint32_t MMCTPCGR
Definition: stm32h735xx.h:783
OCTOSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32h735xx.h:1982
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32h735xx.h:125
RAMECC_MonitorTypeDef::FECR
__IO uint32_t FECR
Definition: stm32h735xx.h:1655
HSEM_Common_TypeDef::IER
__IO uint32_t IER
Definition: stm32h735xx.h:1473
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32h735xx.h:76
I2C5_ER_IRQn
@ I2C5_ER_IRQn
Definition: stm32h735xx.h:197
FMC_Bank2_TypeDef::ECCR2
__IO uint32_t ECCR2
Definition: stm32h735xx.h:1035
ADC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32h735xx.h:265
OCTOSPI_TypeDef::DCR3
__IO uint32_t DCR3
Definition: stm32h735xx.h:1966
BDMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h735xx.h:625
SYSCFG_TypeDef::UR4
__IO uint32_t UR4
Definition: stm32h735xx.h:1117
GPV_TypeDef::AXI_INI6_READ_QOS
__IO uint32_t AXI_INI6_READ_QOS
Definition: stm32h735xx.h:2153
SYSCFG_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32h735xx.h:1108
ETH_TypeDef::DMACCR
__IO uint32_t DMACCR
Definition: stm32h735xx.h:864
ETH_TypeDef::MTLTQOMR
__IO uint32_t MTLTQOMR
Definition: stm32h735xx.h:850
OPAMP_TypeDef::OTR
__IO uint32_t OTR
Definition: stm32h735xx.h:1090
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32h735xx.h:65
FMAC_TypeDef::X2BUFCFG
__IO uint32_t X2BUFCFG
Definition: stm32h735xx.h:997
FDCAN_GlobalTypeDef::TXBCF
__IO uint32_t TXBCF
Definition: stm32h735xx.h:366
GPV_TypeDef::AXI_TARG1_FN_MOD_ISS_BM
__IO uint32_t AXI_TARG1_FN_MOD_ISS_BM
Definition: stm32h735xx.h:2089
RCC_TypeDef::RSR
__IO uint32_t RSR
Definition: stm32h735xx.h:1283
FMAC_TypeDef::RDATA
__IO uint32_t RDATA
Definition: stm32h735xx.h:1003
ETH_TypeDef::MACMDIOAR
__IO uint32_t MACMDIOAR
Definition: stm32h735xx.h:760
ETH_TypeDef::DMAMR
__IO uint32_t DMAMR
Definition: stm32h735xx.h:859
FLASH_TypeDef
FLASH Registers.
Definition: stm32f407xx.h:457
GPV_TypeDef::AXI_PERIPH_ID_6
uint32_t AXI_PERIPH_ID_6
Definition: stm32h735xx.h:2078
CRYP_TypeDef::IV1RR
__IO uint32_t IV1RR
Definition: stm32h735xx.h:1692
OCTOSPI_TypeDef::RESERVED18
uint32_t RESERVED18
Definition: stm32h735xx.h:2003
ETH_TypeDef::RESERVED43
uint32_t RESERVED43
Definition: stm32h735xx.h:883
GPV_TypeDef::AXI_INI5_FN_MOD
__IO uint32_t AXI_INI5_FN_MOD
Definition: stm32h735xx.h:2151
ETH_TypeDef::MACRFCR
__IO uint32_t MACRFCR
Definition: stm32h735xx.h:739
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32h735xx.h:112
HSEM_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32h735xx.h:1467
ETH_TypeDef::MACHWF0R
__IO uint32_t MACHWF0R
Definition: stm32h735xx.h:756
SPI5_IRQn
@ SPI5_IRQn
Definition: stm32h735xx.h:142
USART2_IRQn
@ USART2_IRQn
Definition: stm32h735xx.h:100
ETH_TypeDef::MACTSECNR
__IO uint32_t MACTSECNR
Definition: stm32h735xx.h:831
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f407xx.h:544
ADC_TypeDef::PCSEL_RES0
__IO uint32_t PCSEL_RES0
Definition: stm32h735xx.h:255
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32h735xx.h:168
ADC_TypeDef::DIFSEL_RES12
__IO uint32_t DIFSEL_RES12
Definition: stm32h735xx.h:287
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:368
VREFBUF_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h735xx.h:311
RCC_TypeDef::D2CCIP2R
__IO uint32_t D2CCIP2R
Definition: stm32h735xx.h:1260
FLASH_TypeDef::KEYR1
__IO uint32_t KEYR1
Definition: stm32h735xx.h:963
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition: stm32h735xx.h:1619
DAC_TypeDef::SHRR
__IO uint32_t SHRR
Definition: stm32h735xx.h:494
CRC_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32h735xx.h:449
OCTOSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32h735xx.h:1992
UART5_IRQn
@ UART5_IRQn
Definition: stm32h735xx.h:114
SWPMI_TypeDef::RDR
__IO uint32_t RDR
Definition: stm32h735xx.h:1629
COMP_TypeDef
Definition: stm32h735xx.h:1587
DTS_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32h735xx.h:1513
GPV_TypeDef::AXI_TARG1_FN_MOD2
__IO uint32_t AXI_TARG1_FN_MOD2
Definition: stm32h735xx.h:2091
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32h735xx.h:120
UART8_IRQn
@ UART8_IRQn
Definition: stm32h735xx.h:140
OCTOSPI_TypeDef::RESERVED10
uint32_t RESERVED10
Definition: stm32h735xx.h:1987
SYSCFG_TypeDef::UR7
__IO uint32_t UR7
Definition: stm32h735xx.h:1120
SPI_TypeDef::RXCRC
__IO uint32_t RXCRC
Definition: stm32h735xx.h:1499
FDCAN_ClockCalibrationUnit_TypeDef::CREL
__IO uint32_t CREL
Definition: stm32h735xx.h:409
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32h735xx.h:95
OCTOSPI_TypeDef::IR
__IO uint32_t IR
Definition: stm32h735xx.h:1988
CRYP_TypeDef::CSGCM0R
__IO uint32_t CSGCM0R
Definition: stm32h735xx.h:1701
SYSCFG_TypeDef::PKGR
__IO uint32_t PKGR
Definition: stm32h735xx.h:1111
SYSCFG_TypeDef::UR11
__IO uint32_t UR11
Definition: stm32h735xx.h:1122
CRYP_TypeDef::CSGCM6R
__IO uint32_t CSGCM6R
Definition: stm32h735xx.h:1707
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32h735xx.h:104
OCTOSPI_TypeDef::WPCCR
__IO uint32_t WPCCR
Definition: stm32h735xx.h:1994
RTC_TypeDef
Real-Time Clock.
Definition: stm32f407xx.h:635
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition: stm32h735xx.h:159
DMAMUX_Channel_TypeDef
Definition: stm32h735xx.h:638
ETH_TypeDef::MAC1USTCR
__IO uint32_t MAC1USTCR
Definition: stm32h735xx.h:751
RCC_TypeDef::PLL2FRACR
__IO uint32_t PLL2FRACR
Definition: stm32h735xx.h:1254
GPV_TypeDef::AXI_TARG6_FN_MOD_ISS_BM
__IO uint32_t AXI_TARG6_FN_MOD_ISS_BM
Definition: stm32h735xx.h:2111
RNG_TypeDef
RNG.
Definition: stm32f407xx.h:784
GPV_TypeDef::AXI_TARG2_FN_MOD2
__IO uint32_t AXI_TARG2_FN_MOD2
Definition: stm32h735xx.h:2099
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition: stm32h735xx.h:156
RCC_TypeDef::CIFR
__IO uint32_t CIFR
Definition: stm32h735xx.h:1264
CRYP_TypeDef::CSGCMCCM4R
__IO uint32_t CSGCMCCM4R
Definition: stm32h735xx.h:1697
BDMA_Channel_TypeDef::CM1AR
__IO uint32_t CM1AR
Definition: stm32h735xx.h:629
GPV_TypeDef::AXI_INI2_READ_QOS
__IO uint32_t AXI_INI2_READ_QOS
Definition: stm32h735xx.h:2134
HSEM_TypeDef::C1ISR
__IO uint32_t C1ISR
Definition: stm32h735xx.h:1463
FDCAN_GlobalTypeDef
FD Controller Area Network.
Definition: stm32h735xx.h:319
DCMI_PSSI_IRQn
@ DCMI_PSSI_IRQn
Definition: stm32h735xx.h:135
RAMECC_MonitorTypeDef::FAR
__IO uint32_t FAR
Definition: stm32h735xx.h:1652
DBGMCU_TypeDef::APB1HFZ1
__IO uint32_t APB1HFZ1
Definition: stm32h735xx.h:544
CRYP_TypeDef::DIN
__IO uint32_t DIN
Definition: stm32h735xx.h:1675
ETH_TypeDef::MTLISR
__IO uint32_t MTLISR
Definition: stm32h735xx.h:848
FDCAN_GlobalTypeDef::RXF0A
__IO uint32_t RXF0A
Definition: stm32h735xx.h:353
TTCAN_TypeDef::TTCSM
__IO uint32_t TTCSM
Definition: stm32h735xx.h:398
ETH_TypeDef::MTLRQDR
__IO uint32_t MTLRQDR
Definition: stm32h735xx.h:857
SDMMC_TypeDef
SD host Interface.
Definition: stm32f769xx.h:889
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32h735xx.h:252
OCTOSPI_TypeDef::WPABR
__IO uint32_t WPABR
Definition: stm32h735xx.h:2000
OTFDEC_Region_TypeDef::REG_NONCER0
__IO uint32_t REG_NONCER0
Definition: stm32h735xx.h:2043
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f469xx.h:843
FMC_Bank2_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32h735xx.h:1031
TTCAN_TypeDef::TTTS
__IO uint32_t TTTS
Definition: stm32h735xx.h:400
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32h735xx.h:1087
ETH_TypeDef::MACHWF1R
__IO uint32_t MACHWF1R
Definition: stm32h735xx.h:757
EXTI_TypeDef::D3PCR2H
__IO uint32_t D3PCR2H
Definition: stm32h735xx.h:909
OTFDEC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h735xx.h:2055
RCC_TypeDef::D1CFGR
__IO uint32_t D1CFGR
Definition: stm32h735xx.h:1245
GPV_TypeDef::AXI_INI3_WRITE_QOS
__IO uint32_t AXI_INI3_WRITE_QOS
Definition: stm32h735xx.h:2142
RCC_TypeDef::CIER
__IO uint32_t CIER
Definition: stm32h735xx.h:1263
SYSCFG_TypeDef::UR2
__IO uint32_t UR2
Definition: stm32h735xx.h:1115
EXTI_TypeDef::D3PMR2
__IO uint32_t D3PMR2
Definition: stm32h735xx.h:907
TIM15_IRQn
@ TIM15_IRQn
Definition: stm32h735xx.h:160

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:54