drivers/twihs/twihs.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef TWIHS_H_INCLUDED
38 #define TWIHS_H_INCLUDED
39 
40 #include "compiler.h"
41 
43 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47 
48 
51 #define TWIHS_TIMEOUT 30000
52 
57 #define TWIHS_SUCCESS 0
58 #define TWIHS_INVALID_ARGUMENT 1
59 #define TWIHS_ARBITRATION_LOST 2
60 #define TWIHS_NO_CHIP_FOUND 3
61 #define TWIHS_RECEIVE_OVERRUN 4
62 #define TWIHS_RECEIVE_NACK 5
63 #define TWIHS_SEND_OVERRUN 6
64 #define TWIHS_SEND_NACK 7
65 #define TWIHS_BUSY 8
66 #define TWIHS_ERROR_TIMEOUT 9
67 
74 typedef struct twihs_options {
76  uint32_t master_clk;
78  uint32_t speed;
80  uint8_t chip;
82  uint8_t smbus;
84 
88 typedef struct twihs_packet {
90  uint8_t addr[3];
92  uint32_t addr_length;
94  void *buffer;
96  uint32_t length;
98  uint8_t chip;
100 
106 static inline void twihs_enable_smbus_quick_command(Twihs *p_twihs)
107 {
108  p_twihs->TWIHS_CR = TWIHS_CR_QUICK;
109 }
110 
116 static inline void twihs_enable_highspeed(Twihs *p_twihs)
117 {
118  p_twihs->TWIHS_CR = TWIHS_CR_HSEN;
119 }
120 
126 static inline void twihs_disable_highspeed(Twihs *p_twihs)
127 {
128  p_twihs->TWIHS_CR = TWIHS_CR_HSDIS;
129 }
130 
136 static inline void twihs_enable_smbus(Twihs *p_twihs)
137 {
138  p_twihs->TWIHS_CR = TWIHS_CR_SMBEN;
139 }
140 
146 static inline void twihs_disable_smbus(Twihs *p_twihs)
147 {
148  p_twihs->TWIHS_CR = TWIHS_CR_SMBDIS;
149 }
150 
156 static inline void twihs_enable_pec(Twihs *p_twihs)
157 {
158  p_twihs->TWIHS_CR = TWIHS_CR_PECEN;
159 }
160 
166 static inline void twihs_disable_pec(Twihs *p_twihs)
167 {
168  p_twihs->TWIHS_CR = TWIHS_CR_PECDIS;
169 }
170 
176 static inline void twihs_request_pec(Twihs *p_twihs)
177 {
178  p_twihs->TWIHS_CR = TWIHS_CR_PECRQ;
179 }
180 
186 static inline void twihs_send_clear(Twihs *p_twihs)
187 {
188  p_twihs->TWIHS_CR = TWIHS_CR_CLEAR;
189 }
190 
191 #if !(SAMV70 || SAMV71 || SAME70 || SAMS70)
192 
197 static inline void twihs_enable_alternative_command(Twihs *p_twihs)
198 {
199  p_twihs->TWIHS_CR = TWIHS_CR_ACMEN;
200 }
201 
207 static inline void twihs_disable_alternative_command(Twihs *p_twihs)
208 {
209  p_twihs->TWIHS_CR = TWIHS_CR_ACMDIS;
210 }
211 #endif
212 
218 static inline void twihs_disable_slave_nack(Twihs *p_twihs)
219 {
220  p_twihs->TWIHS_SMR &= ~TWIHS_SMR_NACKEN;
221 }
222 
228 static inline void twihs_enable_slave_nack(Twihs *p_twihs)
229 {
230  p_twihs->TWIHS_SMR |= TWIHS_SMR_NACKEN;
231 }
232 
238 static inline void twihs_disable_slave_default_addr(Twihs *p_twihs)
239 {
240  p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SMDA;
241 }
242 
248 static inline void twihs_enable_slave_default_addr(Twihs *p_twihs)
249 {
250  p_twihs->TWIHS_SMR |= TWIHS_SMR_SMDA;
251 }
252 
258 static inline void twihs_disable_smbus_host_header(Twihs *p_twihs)
259 {
260  p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SMHH;
261 }
262 
268 static inline void twihs_enable_smbus_host_header(Twihs *p_twihs)
269 {
270  p_twihs->TWIHS_SMR |= TWIHS_SMR_SMHH;
271 }
272 
278 static inline void twihs_disable_clock_wait_state(Twihs *p_twihs)
279 {
280  p_twihs->TWIHS_SMR |= TWIHS_SMR_SCLWSDIS;
281 }
282 
288 static inline void twihs_clear_disable_clock_wait_state(Twihs *p_twihs)
289 {
290  p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SCLWSDIS;
291 }
292 
293 #if (SAMG53 || SAMG54 || SAMV70 || SAMV71 || SAME70 || SAMS70)
294 
299 static inline void twihs_disable_slave_addr1_matching(Twihs *p_twihs)
300 {
301  p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SADR1EN;
302 }
303 
309 static inline void twihs_enable_slave_addr1_matching(Twihs *p_twihs)
310 {
311  p_twihs->TWIHS_SMR |= TWIHS_SMR_SADR1EN;
312 }
313 
319 static inline void twihs_disable_slave_addr2_matching(Twihs *p_twihs)
320 {
321  p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SADR2EN;
322 }
323 
329 static inline void twihs_enable_slave_addr2_matching(Twihs *p_twihs)
330 {
331  p_twihs->TWIHS_SMR |= TWIHS_SMR_SADR2EN;
332 }
333 
339 static inline void twihs_disable_slave_addr3_matching(Twihs *p_twihs)
340 {
341  p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SADR3EN;
342 }
343 
349 static inline void twihs_enable_slave_addr3_matching(Twihs *p_twihs)
350 {
351  p_twihs->TWIHS_SMR |= TWIHS_SMR_SADR3EN;
352 }
353 
359 static inline void twihs_disable_slave_data_matching(Twihs *p_twihs)
360 {
361  p_twihs->TWIHS_SMR &= ~TWIHS_SMR_DATAMEN;
362 }
363 
369 static inline void twihs_enable_slave_data_matching(Twihs *p_twihs)
370 {
371  p_twihs->TWIHS_SMR |= TWIHS_SMR_DATAMEN;
372 }
373 
374 void twihs_set_sleepwalking(Twihs *p_twihs,
375  uint32_t ul_matching_addr1, bool flag1,
376  uint32_t ul_matching_addr2, bool flag2,
377  uint32_t ul_matching_addr3, bool flag3,
378  uint32_t ul_matching_data, bool flag);
379 #endif
380 
381 void twihs_enable_master_mode(Twihs *p_twihs);
382 void twihs_disable_master_mode(Twihs *p_twihs);
383 uint32_t twihs_master_init(Twihs *p_twihs, const twihs_options_t *p_opt);
384 uint32_t twihs_set_speed(Twihs *p_twihs, uint32_t ul_speed, uint32_t ul_mck);
385 uint32_t twihs_probe(Twihs *p_twihs, uint8_t uc_slave_addr);
386 uint32_t twihs_master_read(Twihs *p_twihs, twihs_packet_t *p_packet);
387 uint32_t twihs_master_write(Twihs *p_twihs, twihs_packet_t *p_packet);
388 void twihs_enable_interrupt(Twihs *p_twihs, uint32_t ul_sources);
389 void twihs_disable_interrupt(Twihs *p_twihs, uint32_t ul_sources);
390 uint32_t twihs_get_interrupt_status(Twihs *p_twihs);
391 uint32_t twihs_get_interrupt_mask(Twihs *p_twihs);
392 uint8_t twihs_read_byte(Twihs *p_twihs);
393 void twihs_write_byte(Twihs *p_twihs, uint8_t uc_byte);
394 void twihs_enable_slave_mode(Twihs *p_twihs);
395 void twihs_disable_slave_mode(Twihs *p_twihs);
396 void twihs_slave_init(Twihs *p_twihs, uint32_t ul_device_addr);
397 void twihs_set_slave_addr(Twihs *p_twihs, uint32_t ul_device_addr);
398 uint32_t twihs_slave_read(Twihs *p_twihs, uint8_t *p_data);
399 uint32_t twihs_slave_write(Twihs *p_twihs, uint8_t *p_data);
400 void twihs_reset(Twihs *p_twihs);
401 #if !(SAMV70 || SAMV71 || SAME70 || SAMS70)
402 Pdc *twihs_get_pdc_base(Twihs *p_twihs);
403 #endif
404 void twihs_set_write_protection(Twihs *p_twihs, bool flag);
405 void twihs_read_write_protection_status(Twihs *p_twihs, uint32_t *p_status);
406 void twihs_smbus_set_timing(Twihs *p_twihs, uint32_t ul_timing);
407 #if !(SAMV70 || SAMV71 || SAME70 || SAMS70)
408 void twihs_set_alternative_command(Twihs *p_twihs, uint32_t ul_alt_cmd);
409 #endif
410 void twihs_set_filter(Twihs *p_twihs, uint32_t ul_filter);
411 void twihs_mask_slave_addr(Twihs *p_twihs, uint32_t ul_mask);
412 
413 
415 
416 #ifdef __cplusplus
417 }
418 #endif
419 
420 
422 #endif /* TWIHS_H_INCLUDED */
#define TWIHS_CR_PECDIS
(TWIHS_CR) Packet Error Checking Disable
void * buffer
Where to find the data to be transferred.
void twihs_write_byte(Twihs *p_twihs, uint8_t uc_byte)
Sends a byte of data to one of the TWIHS slaves on the bus.
Definition: twihs.c:456
uint8_t twihs_read_byte(Twihs *p_twihs)
Reads a byte from the TWIHS bus.
Definition: twihs.c:445
void twihs_set_filter(Twihs *p_twihs, uint32_t ul_filter)
Set the filter for TWIHS.
Definition: twihs.c:674
void twihs_read_write_protection_status(Twihs *p_twihs, uint32_t *p_status)
Read the write protection status.
Definition: twihs.c:639
static void twihs_disable_smbus(Twihs *p_twihs)
Disable SMBus mode.
static void twihs_disable_slave_nack(Twihs *p_twihs)
Normal value to be returned in the ACK cycle of the data phase in slave receiver mode.
#define TWIHS_CR_SMBDIS
(TWIHS_CR) SMBus Mode Disabled
#define TWIHS_SMR_DATAMEN
(TWIHS_SMR) Data Matching Enable
Information concerning the data transmission.
#define TWIHS_SMR_SADR1EN
(TWIHS_SMR) Slave Address 1 Enable
#define TWIHS_CR_HSEN
(TWIHS_CR) TWIHS High-Speed Mode Enabled
#define TWIHS_CR_SMBEN
(TWIHS_CR) SMBus Mode Enabled
struct twihs_options twihs_options_t
Input parameters when initializing the TWIHS module mode.
#define TWIHS_CR_CLEAR
(TWIHS_CR) Bus CLEAR Command
void twihs_slave_init(Twihs *p_twihs, uint32_t ul_device_addr)
Initialize TWIHS slave mode.
Definition: twihs.c:493
#define TWIHS_SMR_SMDA
(TWIHS_SMR) SMBus Default Address
void twihs_set_write_protection(Twihs *p_twihs, bool flag)
Enables/Disables write protection mode.
Definition: twihs.c:624
uint32_t master_clk
MCK for TWIHS.
void twihs_set_slave_addr(Twihs *p_twihs, uint32_t ul_device_addr)
Set TWIHS slave address.
Definition: twihs.c:515
uint32_t addr_length
Length of the TWIHS data address segment (1-3 bytes).
#define TWIHS_SMR_SCLWSDIS
(TWIHS_SMR) Clock Wait State Disable
__O uint32_t TWIHS_CR
(Twihs Offset: 0x00) Control Register
#define TWIHS_CR_PECRQ
(TWIHS_CR) PEC Request
static void twihs_clear_disable_clock_wait_state(Twihs *p_twihs)
Clear clock wait state disable mode.
static void twihs_disable_smbus_host_header(Twihs *p_twihs)
Acknowledge of the SMBus Host Header disabled.
static void twihs_enable_smbus_quick_command(Twihs *p_twihs)
If Master mode is enabled, a SMBUS Quick Command is sent.
uint32_t twihs_probe(Twihs *p_twihs, uint8_t uc_slave_addr)
Test if a chip answers a given I2C address.
Definition: twihs.c:211
static void twihs_send_clear(Twihs *p_twihs)
If master mode is enabled, send a bus clear command.
uint32_t twihs_set_speed(Twihs *p_twihs, uint32_t ul_speed, uint32_t ul_mck)
Set the I2C bus speed in conjunction with the clock frequency.
Definition: twihs.c:147
uint8_t chip
The desired address.
uint32_t twihs_master_init(Twihs *p_twihs, const twihs_options_t *p_opt)
Initialize TWIHS master mode.
Definition: twihs.c:113
Commonly used includes, types and macros.
__IO uint32_t TWIHS_SMR
(Twihs Offset: 0x08) Slave Mode Register
#define TWIHS_CR_QUICK
(TWIHS_CR) SMBus Quick Command
void twihs_enable_interrupt(Twihs *p_twihs, uint32_t ul_sources)
Enable TWIHS interrupts.
Definition: twihs.c:394
uint32_t twihs_get_interrupt_mask(Twihs *p_twihs)
Read TWIHS interrupt mask.
Definition: twihs.c:433
static void twihs_enable_highspeed(Twihs *p_twihs)
Enable high speed mode.
static void twihs_enable_smbus(Twihs *p_twihs)
Enable SMBus mode.
static void twihs_request_pec(Twihs *p_twihs)
Request a packet error checking.
static void twihs_enable_slave_nack(Twihs *p_twihs)
NACK value to be returned in the ACK cycle of the data phase in slave receiver mode.
void twihs_reset(Twihs *p_twihs)
Reset TWIHS.
Definition: twihs.c:589
uint32_t twihs_get_interrupt_status(Twihs *p_twihs)
Get TWIHS interrupt status.
Definition: twihs.c:421
#define TWIHS_CR_ACMEN
(TWIHS_CR) Alternative Command Mode Enable
static void twihs_enable_smbus_host_header(Twihs *p_twihs)
Acknowledge of the SMBus Host Header enabled.
uint32_t twihs_slave_read(Twihs *p_twihs, uint8_t *p_data)
Read data from master.
Definition: twihs.c:531
static void twihs_enable_pec(Twihs *p_twihs)
Enable packet error checking.
static void twihs_disable_clock_wait_state(Twihs *p_twihs)
Clock stretching disabled in slave mode, OVRE and UNRE will indicate overrun and underrun.
#define TWIHS_SMR_SMHH
(TWIHS_SMR) SMBus Host Header
static void twihs_disable_pec(Twihs *p_twihs)
Disable packet error checking.
static void twihs_enable_alternative_command(Twihs *p_twihs)
Enable alternative command mode.
Twihs hardware registers.
static void twihs_enable_slave_default_addr(Twihs *p_twihs)
Acknowledge of the SMBus Default Address enabled.
uint32_t length
How many bytes do we want to transfer.
#define TWIHS_CR_PECEN
(TWIHS_CR) Packet Error Checking Enable
#define TWIHS_CR_ACMDIS
(TWIHS_CR) Alternative Command Mode Disable
#define TWIHS_SMR_SADR2EN
(TWIHS_SMR) Slave Address 2 Enable
void twihs_smbus_set_timing(Twihs *p_twihs, uint32_t ul_timing)
Set the prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles for SMBUS mode. ...
Definition: twihs.c:650
struct twihs_packet twihs_packet_t
Information concerning the data transmission.
uint32_t twihs_master_read(Twihs *p_twihs, twihs_packet_t *p_packet)
Read multiple bytes from a TWIHS compatible slave device.
Definition: twihs.c:270
static void twihs_disable_slave_default_addr(Twihs *p_twihs)
Acknowledge of the SMBus Default Address disabled.
uint8_t smbus
SMBUS mode (set 1 to use SMBUS quick command, otherwise don&#39;t).
uint32_t twihs_slave_write(Twihs *p_twihs, uint8_t *p_data)
Write data to TWIHS bus.
Definition: twihs.c:562
void twihs_set_alternative_command(Twihs *p_twihs, uint32_t ul_alt_cmd)
Set length/direction/PEC for alternative command mode.
Definition: twihs.c:662
#define TWIHS_SMR_NACKEN
(TWIHS_SMR) Slave Receiver Data Phase NACK enable
uint8_t chip
TWIHS chip address to communicate with.
void twihs_disable_slave_mode(Twihs *p_twihs)
Disable TWIHS slave mode.
Definition: twihs.c:481
uint32_t speed
The baud rate of the TWIHS bus.
void twihs_disable_interrupt(Twihs *p_twihs, uint32_t ul_sources)
Disable TWIHS interrupts.
Definition: twihs.c:406
void twihs_enable_slave_mode(Twihs *p_twihs)
Enable TWIHS slave mode.
Definition: twihs.c:466
Input parameters when initializing the TWIHS module mode.
static void twihs_disable_alternative_command(Twihs *p_twihs)
Enable alternative command mode.
uint32_t twihs_master_write(Twihs *p_twihs, twihs_packet_t *p_packet)
Write multiple bytes to a TWIHS compatible slave device.
Definition: twihs.c:334
Pdc * twihs_get_pdc_base(Twihs *p_twihs)
Get TWIHS PDC base address.
Definition: twihs.c:604
static void twihs_disable_highspeed(Twihs *p_twihs)
Disable high speed mode.
void twihs_disable_master_mode(Twihs *p_twihs)
Disable TWIHS master mode.
Definition: twihs.c:99
#define TWIHS_CR_HSDIS
(TWIHS_CR) TWIHS High-Speed Mode Disabled
void twihs_enable_master_mode(Twihs *p_twihs)
Enable TWIHS master mode.
Definition: twihs.c:84
void twihs_mask_slave_addr(Twihs *p_twihs, uint32_t ul_mask)
A mask can be applied on the slave device address in slave mode in order to allow multiple address an...
Definition: twihs.c:686
#define TWIHS_SMR_SADR3EN
(TWIHS_SMR) Slave Address 3 Enable


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autogenerated on Sat Sep 19 2020 03:19:05