utils/cmsis/same70/include/component/twihs.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_TWIHS_COMPONENT_
36 #define _SAME70_TWIHS_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t TWIHS_CR;
48  __IO uint32_t TWIHS_MMR;
49  __IO uint32_t TWIHS_SMR;
50  __IO uint32_t TWIHS_IADR;
51  __IO uint32_t TWIHS_CWGR;
52  __I uint32_t Reserved1[3];
53  __I uint32_t TWIHS_SR;
54  __O uint32_t TWIHS_IER;
55  __O uint32_t TWIHS_IDR;
56  __I uint32_t TWIHS_IMR;
57  __I uint32_t TWIHS_RHR;
58  __O uint32_t TWIHS_THR;
59  __IO uint32_t TWIHS_SMBTR;
60  __I uint32_t Reserved2[2];
61  __IO uint32_t TWIHS_FILTR;
62  __I uint32_t Reserved3[1];
63  __IO uint32_t TWIHS_SWMR;
64  __I uint32_t Reserved4[32];
65  __I uint32_t TWIHS_DR;
66  __I uint32_t Reserved5[4];
67  __IO uint32_t TWIHS_WPMR;
68  __I uint32_t TWIHS_WPSR;
69  __I uint32_t Reserved6[4];
70  __I uint32_t TWIHS_VER;
71 } Twihs;
72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
73 /* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */
74 #define TWIHS_CR_START (0x1u << 0)
75 #define TWIHS_CR_STOP (0x1u << 1)
76 #define TWIHS_CR_MSEN (0x1u << 2)
77 #define TWIHS_CR_MSDIS (0x1u << 3)
78 #define TWIHS_CR_SVEN (0x1u << 4)
79 #define TWIHS_CR_SVDIS (0x1u << 5)
80 #define TWIHS_CR_QUICK (0x1u << 6)
81 #define TWIHS_CR_SWRST (0x1u << 7)
82 #define TWIHS_CR_HSEN (0x1u << 8)
83 #define TWIHS_CR_HSDIS (0x1u << 9)
84 #define TWIHS_CR_SMBEN (0x1u << 10)
85 #define TWIHS_CR_SMBDIS (0x1u << 11)
86 #define TWIHS_CR_PECEN (0x1u << 12)
87 #define TWIHS_CR_PECDIS (0x1u << 13)
88 #define TWIHS_CR_PECRQ (0x1u << 14)
89 #define TWIHS_CR_CLEAR (0x1u << 15)
90 #define TWIHS_CR_ACMEN (0x1u << 16)
91 #define TWIHS_CR_ACMDIS (0x1u << 17)
92 #define TWIHS_CR_THRCLR (0x1u << 24)
93 #define TWIHS_CR_LOCKCLR (0x1u << 26)
94 #define TWIHS_CR_FIFOEN (0x1u << 28)
95 #define TWIHS_CR_FIFODIS (0x1u << 29)
96 /* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */
97 #define TWIHS_MMR_IADRSZ_Pos 8
98 #define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos)
99 #define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)))
100 #define TWIHS_MMR_IADRSZ_NONE (0x0u << 8)
101 #define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8)
102 #define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8)
103 #define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8)
104 #define TWIHS_MMR_MREAD (0x1u << 12)
105 #define TWIHS_MMR_DADR_Pos 16
106 #define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos)
107 #define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)))
108 /* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */
109 #define TWIHS_SMR_NACKEN (0x1u << 0)
110 #define TWIHS_SMR_SMDA (0x1u << 2)
111 #define TWIHS_SMR_SMHH (0x1u << 3)
112 #define TWIHS_SMR_SCLWSDIS (0x1u << 6)
113 #define TWIHS_SMR_MASK_Pos 8
114 #define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos)
115 #define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)))
116 #define TWIHS_SMR_SADR_Pos 16
117 #define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos)
118 #define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)))
119 #define TWIHS_SMR_SADR1EN (0x1u << 28)
120 #define TWIHS_SMR_SADR2EN (0x1u << 29)
121 #define TWIHS_SMR_SADR3EN (0x1u << 30)
122 #define TWIHS_SMR_DATAMEN (0x1u << 31)
123 /* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */
124 #define TWIHS_IADR_IADR_Pos 0
125 #define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos)
126 #define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)))
127 /* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */
128 #define TWIHS_CWGR_CLDIV_Pos 0
129 #define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos)
130 #define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)))
131 #define TWIHS_CWGR_CHDIV_Pos 8
132 #define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos)
133 #define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)))
134 #define TWIHS_CWGR_CKDIV_Pos 16
135 #define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos)
136 #define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)))
137 #define TWIHS_CWGR_HOLD_Pos 24
138 #define TWIHS_CWGR_HOLD_Msk (0x3fu << TWIHS_CWGR_HOLD_Pos)
139 #define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)))
140 /* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */
141 #define TWIHS_SR_TXCOMP (0x1u << 0)
142 #define TWIHS_SR_RXRDY (0x1u << 1)
143 #define TWIHS_SR_TXRDY (0x1u << 2)
144 #define TWIHS_SR_SVREAD (0x1u << 3)
145 #define TWIHS_SR_SVACC (0x1u << 4)
146 #define TWIHS_SR_GACC (0x1u << 5)
147 #define TWIHS_SR_OVRE (0x1u << 6)
148 #define TWIHS_SR_UNRE (0x1u << 7)
149 #define TWIHS_SR_NACK (0x1u << 8)
150 #define TWIHS_SR_ARBLST (0x1u << 9)
151 #define TWIHS_SR_SCLWS (0x1u << 10)
152 #define TWIHS_SR_EOSACC (0x1u << 11)
153 #define TWIHS_SR_MCACK (0x1u << 16)
154 #define TWIHS_SR_TOUT (0x1u << 18)
155 #define TWIHS_SR_PECERR (0x1u << 19)
156 #define TWIHS_SR_SMBDAM (0x1u << 20)
157 #define TWIHS_SR_SMBHHM (0x1u << 21)
158 #define TWIHS_SR_SCL (0x1u << 24)
159 #define TWIHS_SR_SDA (0x1u << 25)
160 /* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */
161 #define TWIHS_IER_TXCOMP (0x1u << 0)
162 #define TWIHS_IER_RXRDY (0x1u << 1)
163 #define TWIHS_IER_TXRDY (0x1u << 2)
164 #define TWIHS_IER_SVACC (0x1u << 4)
165 #define TWIHS_IER_GACC (0x1u << 5)
166 #define TWIHS_IER_OVRE (0x1u << 6)
167 #define TWIHS_IER_UNRE (0x1u << 7)
168 #define TWIHS_IER_NACK (0x1u << 8)
169 #define TWIHS_IER_ARBLST (0x1u << 9)
170 #define TWIHS_IER_SCL_WS (0x1u << 10)
171 #define TWIHS_IER_EOSACC (0x1u << 11)
172 #define TWIHS_IER_MCACK (0x1u << 16)
173 #define TWIHS_IER_TOUT (0x1u << 18)
174 #define TWIHS_IER_PECERR (0x1u << 19)
175 #define TWIHS_IER_SMBDAM (0x1u << 20)
176 #define TWIHS_IER_SMBHHM (0x1u << 21)
177 /* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */
178 #define TWIHS_IDR_TXCOMP (0x1u << 0)
179 #define TWIHS_IDR_RXRDY (0x1u << 1)
180 #define TWIHS_IDR_TXRDY (0x1u << 2)
181 #define TWIHS_IDR_SVACC (0x1u << 4)
182 #define TWIHS_IDR_GACC (0x1u << 5)
183 #define TWIHS_IDR_OVRE (0x1u << 6)
184 #define TWIHS_IDR_UNRE (0x1u << 7)
185 #define TWIHS_IDR_NACK (0x1u << 8)
186 #define TWIHS_IDR_ARBLST (0x1u << 9)
187 #define TWIHS_IDR_SCL_WS (0x1u << 10)
188 #define TWIHS_IDR_EOSACC (0x1u << 11)
189 #define TWIHS_IDR_MCACK (0x1u << 16)
190 #define TWIHS_IDR_TOUT (0x1u << 18)
191 #define TWIHS_IDR_PECERR (0x1u << 19)
192 #define TWIHS_IDR_SMBDAM (0x1u << 20)
193 #define TWIHS_IDR_SMBHHM (0x1u << 21)
194 /* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */
195 #define TWIHS_IMR_TXCOMP (0x1u << 0)
196 #define TWIHS_IMR_RXRDY (0x1u << 1)
197 #define TWIHS_IMR_TXRDY (0x1u << 2)
198 #define TWIHS_IMR_SVACC (0x1u << 4)
199 #define TWIHS_IMR_GACC (0x1u << 5)
200 #define TWIHS_IMR_OVRE (0x1u << 6)
201 #define TWIHS_IMR_UNRE (0x1u << 7)
202 #define TWIHS_IMR_NACK (0x1u << 8)
203 #define TWIHS_IMR_ARBLST (0x1u << 9)
204 #define TWIHS_IMR_SCL_WS (0x1u << 10)
205 #define TWIHS_IMR_EOSACC (0x1u << 11)
206 #define TWIHS_IMR_MCACK (0x1u << 16)
207 #define TWIHS_IMR_TOUT (0x1u << 18)
208 #define TWIHS_IMR_PECERR (0x1u << 19)
209 #define TWIHS_IMR_SMBDAM (0x1u << 20)
210 #define TWIHS_IMR_SMBHHM (0x1u << 21)
211 /* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */
212 #define TWIHS_RHR_RXDATA_Pos 0
213 #define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos)
214 /* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */
215 #define TWIHS_THR_TXDATA_Pos 0
216 #define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos)
217 #define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)))
218 /* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */
219 #define TWIHS_SMBTR_PRESC_Pos 0
220 #define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos)
221 #define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)))
222 #define TWIHS_SMBTR_TLOWS_Pos 8
223 #define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos)
224 #define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)))
225 #define TWIHS_SMBTR_TLOWM_Pos 16
226 #define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos)
227 #define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)))
228 #define TWIHS_SMBTR_THMAX_Pos 24
229 #define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos)
230 #define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)))
231 /* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */
232 #define TWIHS_FILTR_FILT (0x1u << 0)
233 #define TWIHS_FILTR_PADFEN (0x1u << 1)
234 #define TWIHS_FILTR_PADFCFG (0x1u << 2)
235 #define TWIHS_FILTR_THRES_Pos 8
236 #define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos)
237 #define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)))
238 /* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */
239 #define TWIHS_SWMR_SADR1_Pos 0
240 #define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos)
241 #define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)))
242 #define TWIHS_SWMR_SADR2_Pos 8
243 #define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos)
244 #define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)))
245 #define TWIHS_SWMR_SADR3_Pos 16
246 #define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos)
247 #define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)))
248 #define TWIHS_SWMR_DATAM_Pos 24
249 #define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos)
250 #define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)))
251 /* -------- TWIHS_DR : (TWIHS Offset: 0xD0) Debug Register -------- */
252 #define TWIHS_DR_SWEN (0x1u << 0)
253 #define TWIHS_DR_CLKRQ (0x1u << 1)
254 #define TWIHS_DR_SWMATCH (0x1u << 2)
255 #define TWIHS_DR_TRP (0x1u << 3)
256 /* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */
257 #define TWIHS_WPMR_WPEN (0x1u << 0)
258 #define TWIHS_WPMR_WPKEY_Pos 8
259 #define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos)
260 #define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)))
261 #define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8)
262 /* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */
263 #define TWIHS_WPSR_WPVS (0x1u << 0)
264 #define TWIHS_WPSR_WPVSRC_Pos 8
265 #define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos)
266 /* -------- TWIHS_VER : (TWIHS Offset: 0xFC) Version Register -------- */
267 #define TWIHS_VER_VERSION_Pos 0
268 #define TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos)
269 #define TWIHS_VER_MFN_Pos 16
270 #define TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos)
273 
274 
275 #endif /* _SAME70_TWIHS_COMPONENT_ */
__IO uint32_t TWIHS_SMBTR
(Twihs Offset: 0x38) SMBus Timing Register
__I uint32_t TWIHS_SR
(Twihs Offset: 0x20) Status Register
__I uint32_t TWIHS_RHR
(Twihs Offset: 0x30) Receive Holding Register
__I uint32_t TWIHS_IMR
(Twihs Offset: 0x2C) Interrupt Mask Register
__O uint32_t TWIHS_IER
(Twihs Offset: 0x24) Interrupt Enable Register
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__O uint32_t TWIHS_CR
(Twihs Offset: 0x00) Control Register
__IO uint32_t TWIHS_CWGR
(Twihs Offset: 0x10) Clock Waveform Generator Register
__IO uint32_t TWIHS_SWMR
(Twihs Offset: 0x4C) SleepWalking Matching Register
__IO uint32_t TWIHS_SMR
(Twihs Offset: 0x08) Slave Mode Register
__O uint32_t TWIHS_THR
(Twihs Offset: 0x34) Transmit Holding Register
__IO uint32_t TWIHS_MMR
(Twihs Offset: 0x04) Master Mode Register
__I uint32_t TWIHS_WPSR
(Twihs Offset: 0xE8) Write Protection Status Register
__IO uint32_t TWIHS_WPMR
(Twihs Offset: 0xE4) Write Protection Mode Register
Twihs hardware registers.
__I uint32_t TWIHS_DR
(Twihs Offset: 0xD0) Debug Register
__I uint32_t TWIHS_VER
(Twihs Offset: 0xFC) Version Register
__IO uint32_t TWIHS_IADR
(Twihs Offset: 0x0C) Internal Address Register
__O uint32_t TWIHS_IDR
(Twihs Offset: 0x28) Interrupt Disable Register
__IO uint32_t TWIHS_FILTR
(Twihs Offset: 0x44) Filter Register
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:05