system_stm32f10x.c
Go to the documentation of this file.
1 #include <stdbool.h>
2 #include "stm32f10x.h"
3 
4 #define SYSCLK_FREQ_72MHz 72000000
5 
8 __I uint8_t AHBPrescTable[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 };
9 
10 uint32_t hse_value = 8000000;
11 
12 void SystemInit(void)
13 {
14  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
15  /* Set HSION bit */
16  RCC->CR |= (uint32_t) 0x00000001;
17 
18  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
19  RCC->CFGR &= (uint32_t) 0xF8FF0000;
20 
21  /* Reset HSEON, CSSON and PLLON bits */
22  RCC->CR &= (uint32_t) 0xFEF6FFFF;
23 
24  /* Reset HSEBYP bit */
25  RCC->CR &= (uint32_t) 0xFFFBFFFF;
26 
27  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
28  RCC->CFGR &= (uint32_t) 0xFF80FFFF;
29 
30  /* Disable all interrupts and clear pending bits */
31  RCC->CIR = 0x009F0000;
32 
33  SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
34 }
35 
37 {
38  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
39 
40  /* Get SYSCLK source ------------------------------------------------------- */
41  tmp = RCC->CFGR & RCC_CFGR_SWS;
42 
43  switch (tmp) {
44  case 0x00: /* HSI used as system clock */
46  break;
47  case 0x04: /* HSE used as system clock */
49  break;
50  case 0x08: /* PLL used as system clock */
51 
52  /* Get PLL clock source and multiplication factor ---------------------- */
53  pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
54  pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
55 
56  pllmull = (pllmull >> 18) + 2;
57 
58  if (pllsource == 0x00) {
59  /* HSI oscillator clock divided by 2 selected as PLL clock entry */
60  SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
61  } else {
62  /* HSE selected as PLL clock entry */
63  if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t) RESET) { /* HSE oscillator clock divided by 2 */
64  SystemCoreClock = (hse_value >> 1) * pllmull;
65  } else {
66  SystemCoreClock = hse_value * pllmull;
67  }
68  }
69  break;
70 
71  default:
73  break;
74  }
75 
76  /* Compute HCLK clock frequency ---------------- */
77  /* Get HCLK prescaler */
78  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
79  /* HCLK clock frequency */
80  SystemCoreClock >>= tmp;
81 }
82 
83 enum {
84  SRC_NONE = 0,
87 };
88 
89 // Set system clock to 72 (HSE) or 64 (HSI) MHz
90 void SetSysClock(bool overclock)
91 {
92  __IO uint32_t StartUpCounter = 0, status = 0, clocksrc = SRC_NONE;
93  __IO uint32_t *RCC_CRH = &GPIOC->CRH;
94  __IO uint32_t RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL9;
95 
96  // First, try running off HSE
97  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
98  RCC->APB2ENR |= RCC_CFGR_HPRE_0;
99 
100  // Wait till HSE is ready
101  do {
102  status = RCC->CR & RCC_CR_HSERDY;
103  StartUpCounter++;
104  } while ((status == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
105 
106  if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
107  // external xtal started up, we're good to go
108  clocksrc = SRC_HSE;
109  } else {
110  // If HSE fails to start-up, try to enable HSI and configure for 64MHz operation
111  RCC->CR |= ((uint32_t)RCC_CR_HSION);
112  StartUpCounter = 0;
113  do {
114  status = RCC->CR & RCC_CR_HSIRDY;
115  StartUpCounter++;
116  } while ((status == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
117  if ((RCC->CR & RCC_CR_HSIRDY) != RESET) {
118  // we're on internal RC
119  clocksrc = SRC_HSI;
120  } else {
121  // We're fucked
122  while(1);
123  }
124  }
125 
126  // Enable Prefetch Buffer
127  FLASH->ACR |= FLASH_ACR_PRFTBE;
128  // Flash 2 wait state
129  FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
130  FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
131  // HCLK = SYSCLK
132  RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
133  // PCLK2 = HCLK
134  RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
135  // PCLK1 = HCLK
136  RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
137  *RCC_CRH &= (uint32_t)~((uint32_t)0xF << (RCC_CFGR_PLLMULL9 >> 16));
138 
139  // Configure PLL
140  hse_value = 8000000;
141  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
142  *RCC_CRH |= (uint32_t)0x8 << (RCC_CFGR_PLLMULL9 >> 16);
143  GPIOC->ODR &= (uint32_t)~(CAN_MCR_RESET);
144 
145  RCC_CFGR_PLLMUL = GPIOC->IDR & CAN_MCR_RESET ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
146  switch (clocksrc) {
147  case SRC_HSE:
148  if (overclock) {
149  if (RCC_CFGR_PLLMUL == RCC_CFGR_PLLMULL6)
150  RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL7;
151  else if (RCC_CFGR_PLLMUL == RCC_CFGR_PLLMULL9)
152  RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL10;
153  }
154  // overclock=false : PLL configuration: PLLCLK = HSE * 9 = 72 MHz || HSE * 6 = 72 MHz
155  // overclock=true : PLL configuration: PLLCLK = HSE * 10 = 80 MHz || HSE * 7 = 84 MHz
156  RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL);
157  break;
158  case SRC_HSI:
159  // PLL configuration: PLLCLK = HSI / 2 * 16 = 64 MHz
160  RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL16);
161  break;
162  }
163 
164  // Enable PLL
165  RCC->CR |= RCC_CR_PLLON;
166  // Wait till PLL is ready
167  while ((RCC->CR & RCC_CR_PLLRDY) == 0);
168  // Select PLL as system clock source
169  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
170  RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
171  // Wait till PLL is used as system clock source
172  while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08);
173 
175 }
#define RCC_CFGR_PLLMULL6
Definition: stm32f10x.h:1858
#define FLASH_BASE
Definition: stm32f4xx.h:1843
void SystemCoreClockUpdate(void)
Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable cont...
#define RCC_CFGR_PLLMULL
Definition: stm32f10x.h:1774
#define RCC_CFGR_PPRE2_DIV1
Definition: stm32f4xx.h:8696
#define CAN_MCR_RESET
Definition: stm32f4xx.h:2561
#define RCC_CFGR_HPRE
Definition: stm32f4xx.h:8656
#define RCC_CR_HSEON
Definition: stm32f4xx.h:8578
#define RCC_CFGR_PLLMULL10
Definition: stm32f10x.h:1862
#define RCC_CFGR_PLLMULL7
Definition: stm32f10x.h:1859
uint32_t SystemCoreClock
#define RCC_CFGR_PLLSRC_HSI_Div2
Definition: stm32f10x.h:1848
void SystemInit(void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the Syst...
#define RCC_CFGR_SW_PLL
Definition: stm32f4xx.h:8638
#define GPIOC
Definition: stm32f4xx.h:2112
#define __I
Definition: core_cm0.h:195
#define RCC_CFGR_PLLMULL16
Definition: stm32f10x.h:1868
#define FLASH
Definition: stm32f4xx.h:2123
static volatile uint8_t * status
Definition: drv_i2c.c:102
#define HSE_STARTUP_TIMEOUT
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
Definition: stm32f4xx.h:146
#define RCC_CR_PLLRDY
Definition: stm32f4xx.h:8583
#define RCC_CR_PLLON
Definition: stm32f4xx.h:8582
#define HSI_VALUE
Definition: stm32f4xx.h:150
#define SCB
Definition: core_cm0.h:503
#define RCC_CFGR_PLLSRC_HSE
Definition: stm32f10x.h:1849
#define RCC_CFGR_HPRE_DIV1
Definition: stm32f4xx.h:8662
#define __IO
Definition: core_cm0.h:198
uint32_t hse_value
#define RCC_CFGR_PLLMULL9
Definition: stm32f10x.h:1861
__I uint8_t AHBPrescTable[16]
#define RCC
Definition: stm32f4xx.h:2122
#define RCC_CR_HSION
Definition: stm32f4xx.h:8558
#define FLASH_ACR_LATENCY_2
Definition: stm32f10x.h:7794
#define RCC_CFGR_PLLSRC
Definition: stm32f10x.h:1769
#define RCC_CFGR_SWS
Definition: stm32f4xx.h:8644
#define FLASH_ACR_LATENCY
Definition: stm32f4xx.h:4534
#define RCC_CFGR_PLLXTPRE
Definition: stm32f10x.h:1771
#define FLASH_ACR_PRFTBE
Definition: stm32f10x.h:7797
#define RCC_CFGR_SW
Definition: stm32f4xx.h:8632
#define RCC_CFGR_HPRE_0
Definition: stm32f4xx.h:8657
void SetSysClock(bool overclock)
CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
#define RCC_CR_HSIRDY
Definition: stm32f4xx.h:8559
#define SYSCLK_FREQ_72MHz
#define RCC_CR_HSERDY
Definition: stm32f4xx.h:8579
#define RCC_CFGR_PPRE1_DIV2
Definition: stm32f4xx.h:8685


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19