stm32f4xx_tim.c
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1 
118 /* Includes ------------------------------------------------------------------*/
119 #include "stm32f4xx_tim.h"
120 #include "stm32f4xx_rcc.h"
121 
131 /* Private typedef -----------------------------------------------------------*/
132 /* Private define ------------------------------------------------------------*/
133 
134 /* ---------------------- TIM registers bit mask ------------------------ */
135 #define SMCR_ETR_MASK ((uint16_t)0x00FF)
136 #define CCMR_OFFSET ((uint16_t)0x0018)
137 #define CCER_CCE_SET ((uint16_t)0x0001)
138 #define CCER_CCNE_SET ((uint16_t)0x0004)
139 #define CCMR_OC13M_MASK ((uint16_t)0xFF8F)
140 #define CCMR_OC24M_MASK ((uint16_t)0x8FFF)
141 
142 /* Private macro -------------------------------------------------------------*/
143 /* Private variables ---------------------------------------------------------*/
144 /* Private function prototypes -----------------------------------------------*/
145 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
146  uint16_t TIM_ICFilter);
147 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
148  uint16_t TIM_ICFilter);
149 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
150  uint16_t TIM_ICFilter);
151 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
152  uint16_t TIM_ICFilter);
153 
154 /* Private functions ---------------------------------------------------------*/
155 
201 {
202  /* Check the parameters */
204 
205  if (TIMx == TIM1)
206  {
209  }
210  else if (TIMx == TIM2)
211  {
214  }
215  else if (TIMx == TIM3)
216  {
219  }
220  else if (TIMx == TIM4)
221  {
224  }
225  else if (TIMx == TIM5)
226  {
229  }
230  else if (TIMx == TIM6)
231  {
234  }
235  else if (TIMx == TIM7)
236  {
239  }
240  else if (TIMx == TIM8)
241  {
244  }
245  else if (TIMx == TIM9)
246  {
249  }
250  else if (TIMx == TIM10)
251  {
254  }
255  else if (TIMx == TIM11)
256  {
259  }
260  else if (TIMx == TIM12)
261  {
264  }
265  else if (TIMx == TIM13)
266  {
269  }
270  else
271  {
272  if (TIMx == TIM14)
273  {
276  }
277  }
278 }
279 
288 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
289 {
290  uint16_t tmpcr1 = 0;
291 
292  /* Check the parameters */
294  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
295  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
296 
297  tmpcr1 = TIMx->CR1;
298 
299  if((TIMx == TIM1) || (TIMx == TIM8)||
300  (TIMx == TIM2) || (TIMx == TIM3)||
301  (TIMx == TIM4) || (TIMx == TIM5))
302  {
303  /* Select the Counter Mode */
304  tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
305  tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
306  }
307 
308  if((TIMx != TIM6) && (TIMx != TIM7))
309  {
310  /* Set the clock division */
311  tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
312  tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
313  }
314 
315  TIMx->CR1 = tmpcr1;
316 
317  /* Set the Autoreload value */
318  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
319 
320  /* Set the Prescaler value */
321  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
322 
323  if ((TIMx == TIM1) || (TIMx == TIM8))
324  {
325  /* Set the Repetition Counter value */
326  TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
327  }
328 
329  /* Generate an update event to reload the Prescaler
330  and the repetition counter(only for TIM1 and TIM8) value immediatly */
332 }
333 
340 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
341 {
342  /* Set the default configuration */
343  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
344  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
345  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
346  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
347  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
348 }
349 
360 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
361 {
362  /* Check the parameters */
364  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
365  /* Set the Prescaler value */
366  TIMx->PSC = Prescaler;
367  /* Set or reset the UG Bit */
368  TIMx->EGR = TIM_PSCReloadMode;
369 }
370 
383 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
384 {
385  uint16_t tmpcr1 = 0;
386 
387  /* Check the parameters */
389  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
390 
391  tmpcr1 = TIMx->CR1;
392 
393  /* Reset the CMS and DIR Bits */
394  tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
395 
396  /* Set the Counter Mode */
397  tmpcr1 |= TIM_CounterMode;
398 
399  /* Write to TIMx CR1 register */
400  TIMx->CR1 = tmpcr1;
401 }
402 
409 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
410 {
411  /* Check the parameters */
413 
414  /* Set the Counter Register value */
415  TIMx->CNT = Counter;
416 }
417 
424 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
425 {
426  /* Check the parameters */
428 
429  /* Set the Autoreload Register value */
430  TIMx->ARR = Autoreload;
431 }
432 
439 {
440  /* Check the parameters */
442 
443  /* Get the Counter Register value */
444  return TIMx->CNT;
445 }
446 
453 {
454  /* Check the parameters */
456 
457  /* Get the Prescaler Register value */
458  return TIMx->PSC;
459 }
460 
469 {
470  /* Check the parameters */
473 
474  if (NewState != DISABLE)
475  {
476  /* Set the Update Disable Bit */
477  TIMx->CR1 |= TIM_CR1_UDIS;
478  }
479  else
480  {
481  /* Reset the Update Disable Bit */
482  TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
483  }
484 }
485 
497 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
498 {
499  /* Check the parameters */
501  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
502 
503  if (TIM_UpdateSource != TIM_UpdateSource_Global)
504  {
505  /* Set the URS Bit */
506  TIMx->CR1 |= TIM_CR1_URS;
507  }
508  else
509  {
510  /* Reset the URS Bit */
511  TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
512  }
513 }
514 
523 {
524  /* Check the parameters */
527 
528  if (NewState != DISABLE)
529  {
530  /* Set the ARR Preload Bit */
531  TIMx->CR1 |= TIM_CR1_ARPE;
532  }
533  else
534  {
535  /* Reset the ARR Preload Bit */
536  TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
537  }
538 }
539 
549 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
550 {
551  /* Check the parameters */
553  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
554 
555  /* Reset the OPM Bit */
556  TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
557 
558  /* Configure the OPM Mode */
559  TIMx->CR1 |= TIM_OPMode;
560 }
561 
572 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
573 {
574  /* Check the parameters */
576  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
577 
578  /* Reset the CKD Bits */
579  TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
580 
581  /* Set the CKD value */
582  TIMx->CR1 |= TIM_CKD;
583 }
584 
592 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
593 {
594  /* Check the parameters */
597 
598  if (NewState != DISABLE)
599  {
600  /* Enable the TIM Counter */
601  TIMx->CR1 |= TIM_CR1_CEN;
602  }
603  else
604  {
605  /* Disable the TIM Counter */
606  TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
607  }
608 }
673 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
674 {
675  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
676 
677  /* Check the parameters */
679  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
681  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
682 
683  /* Disable the Channel 1: Reset the CC1E Bit */
684  TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
685 
686  /* Get the TIMx CCER register value */
687  tmpccer = TIMx->CCER;
688  /* Get the TIMx CR2 register value */
689  tmpcr2 = TIMx->CR2;
690 
691  /* Get the TIMx CCMR1 register value */
692  tmpccmrx = TIMx->CCMR1;
693 
694  /* Reset the Output Compare Mode Bits */
695  tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
696  tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
697  /* Select the Output Compare Mode */
698  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
699 
700  /* Reset the Output Polarity level */
701  tmpccer &= (uint16_t)~TIM_CCER_CC1P;
702  /* Set the Output Compare Polarity */
703  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
704 
705  /* Set the Output State */
706  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
707 
708  if((TIMx == TIM1) || (TIMx == TIM8))
709  {
714 
715  /* Reset the Output N Polarity level */
716  tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
717  /* Set the Output N Polarity */
718  tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
719  /* Reset the Output N State */
720  tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
721 
722  /* Set the Output N State */
723  tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
724  /* Reset the Output Compare and Output Compare N IDLE State */
725  tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
726  tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
727  /* Set the Output Idle state */
728  tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
729  /* Set the Output N Idle state */
730  tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
731  }
732  /* Write to TIMx CR2 */
733  TIMx->CR2 = tmpcr2;
734 
735  /* Write to TIMx CCMR1 */
736  TIMx->CCMR1 = tmpccmrx;
737 
738  /* Set the Capture Compare Register value */
739  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
740 
741  /* Write to TIMx CCER */
742  TIMx->CCER = tmpccer;
743 }
744 
754 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
755 {
756  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
757 
758  /* Check the parameters */
760  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
762  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
763 
764  /* Disable the Channel 2: Reset the CC2E Bit */
765  TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
766 
767  /* Get the TIMx CCER register value */
768  tmpccer = TIMx->CCER;
769  /* Get the TIMx CR2 register value */
770  tmpcr2 = TIMx->CR2;
771 
772  /* Get the TIMx CCMR1 register value */
773  tmpccmrx = TIMx->CCMR1;
774 
775  /* Reset the Output Compare mode and Capture/Compare selection Bits */
776  tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
777  tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
778 
779  /* Select the Output Compare Mode */
780  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
781 
782  /* Reset the Output Polarity level */
783  tmpccer &= (uint16_t)~TIM_CCER_CC2P;
784  /* Set the Output Compare Polarity */
785  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
786 
787  /* Set the Output State */
788  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
789 
790  if((TIMx == TIM1) || (TIMx == TIM8))
791  {
796 
797  /* Reset the Output N Polarity level */
798  tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
799  /* Set the Output N Polarity */
800  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
801  /* Reset the Output N State */
802  tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
803 
804  /* Set the Output N State */
805  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
806  /* Reset the Output Compare and Output Compare N IDLE State */
807  tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
808  tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
809  /* Set the Output Idle state */
810  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
811  /* Set the Output N Idle state */
812  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
813  }
814  /* Write to TIMx CR2 */
815  TIMx->CR2 = tmpcr2;
816 
817  /* Write to TIMx CCMR1 */
818  TIMx->CCMR1 = tmpccmrx;
819 
820  /* Set the Capture Compare Register value */
821  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
822 
823  /* Write to TIMx CCER */
824  TIMx->CCER = tmpccer;
825 }
826 
835 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
836 {
837  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
838 
839  /* Check the parameters */
841  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
843  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
844 
845  /* Disable the Channel 3: Reset the CC2E Bit */
846  TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
847 
848  /* Get the TIMx CCER register value */
849  tmpccer = TIMx->CCER;
850  /* Get the TIMx CR2 register value */
851  tmpcr2 = TIMx->CR2;
852 
853  /* Get the TIMx CCMR2 register value */
854  tmpccmrx = TIMx->CCMR2;
855 
856  /* Reset the Output Compare mode and Capture/Compare selection Bits */
857  tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
858  tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;
859  /* Select the Output Compare Mode */
860  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
861 
862  /* Reset the Output Polarity level */
863  tmpccer &= (uint16_t)~TIM_CCER_CC3P;
864  /* Set the Output Compare Polarity */
865  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
866 
867  /* Set the Output State */
868  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
869 
870  if((TIMx == TIM1) || (TIMx == TIM8))
871  {
876 
877  /* Reset the Output N Polarity level */
878  tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
879  /* Set the Output N Polarity */
880  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
881  /* Reset the Output N State */
882  tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
883 
884  /* Set the Output N State */
885  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
886  /* Reset the Output Compare and Output Compare N IDLE State */
887  tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
888  tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
889  /* Set the Output Idle state */
890  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
891  /* Set the Output N Idle state */
892  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
893  }
894  /* Write to TIMx CR2 */
895  TIMx->CR2 = tmpcr2;
896 
897  /* Write to TIMx CCMR2 */
898  TIMx->CCMR2 = tmpccmrx;
899 
900  /* Set the Capture Compare Register value */
901  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
902 
903  /* Write to TIMx CCER */
904  TIMx->CCER = tmpccer;
905 }
906 
915 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
916 {
917  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
918 
919  /* Check the parameters */
921  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
923  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
924 
925  /* Disable the Channel 4: Reset the CC4E Bit */
926  TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
927 
928  /* Get the TIMx CCER register value */
929  tmpccer = TIMx->CCER;
930  /* Get the TIMx CR2 register value */
931  tmpcr2 = TIMx->CR2;
932 
933  /* Get the TIMx CCMR2 register value */
934  tmpccmrx = TIMx->CCMR2;
935 
936  /* Reset the Output Compare mode and Capture/Compare selection Bits */
937  tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
938  tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
939 
940  /* Select the Output Compare Mode */
941  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
942 
943  /* Reset the Output Polarity level */
944  tmpccer &= (uint16_t)~TIM_CCER_CC4P;
945  /* Set the Output Compare Polarity */
946  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
947 
948  /* Set the Output State */
949  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
950 
951  if((TIMx == TIM1) || (TIMx == TIM8))
952  {
954  /* Reset the Output Compare IDLE State */
955  tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
956  /* Set the Output Idle state */
957  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
958  }
959  /* Write to TIMx CR2 */
960  TIMx->CR2 = tmpcr2;
961 
962  /* Write to TIMx CCMR2 */
963  TIMx->CCMR2 = tmpccmrx;
964 
965  /* Set the Capture Compare Register value */
966  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
967 
968  /* Write to TIMx CCER */
969  TIMx->CCER = tmpccer;
970 }
971 
978 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
979 {
980  /* Set the default configuration */
981  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
982  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
983  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
984  TIM_OCInitStruct->TIM_Pulse = 0x00000000;
985  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
986  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
987  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
988  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
989 }
990 
1014 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
1015 {
1016  uint32_t tmp = 0;
1017  uint16_t tmp1 = 0;
1018 
1019  /* Check the parameters */
1021  assert_param(IS_TIM_CHANNEL(TIM_Channel));
1022  assert_param(IS_TIM_OCM(TIM_OCMode));
1023 
1024  tmp = (uint32_t) TIMx;
1025  tmp += CCMR_OFFSET;
1026 
1027  tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
1028 
1029  /* Disable the Channel: Reset the CCxE Bit */
1030  TIMx->CCER &= (uint16_t) ~tmp1;
1031 
1032  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
1033  {
1034  tmp += (TIM_Channel>>1);
1035 
1036  /* Reset the OCxM bits in the CCMRx register */
1037  *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
1038 
1039  /* Configure the OCxM bits in the CCMRx register */
1040  *(__IO uint32_t *) tmp |= TIM_OCMode;
1041  }
1042  else
1043  {
1044  tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
1045 
1046  /* Reset the OCxM bits in the CCMRx register */
1047  *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
1048 
1049  /* Configure the OCxM bits in the CCMRx register */
1050  *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
1051  }
1052 }
1053 
1060 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
1061 {
1062  /* Check the parameters */
1064 
1065  /* Set the Capture Compare1 Register value */
1066  TIMx->CCR1 = Compare1;
1067 }
1068 
1076 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
1077 {
1078  /* Check the parameters */
1080 
1081  /* Set the Capture Compare2 Register value */
1082  TIMx->CCR2 = Compare2;
1083 }
1084 
1091 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
1092 {
1093  /* Check the parameters */
1095 
1096  /* Set the Capture Compare3 Register value */
1097  TIMx->CCR3 = Compare3;
1098 }
1099 
1106 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
1107 {
1108  /* Check the parameters */
1110 
1111  /* Set the Capture Compare4 Register value */
1112  TIMx->CCR4 = Compare4;
1113 }
1114 
1124 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1125 {
1126  uint16_t tmpccmr1 = 0;
1127 
1128  /* Check the parameters */
1130  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1131  tmpccmr1 = TIMx->CCMR1;
1132 
1133  /* Reset the OC1M Bits */
1134  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
1135 
1136  /* Configure The Forced output Mode */
1137  tmpccmr1 |= TIM_ForcedAction;
1138 
1139  /* Write to TIMx CCMR1 register */
1140  TIMx->CCMR1 = tmpccmr1;
1141 }
1142 
1153 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1154 {
1155  uint16_t tmpccmr1 = 0;
1156 
1157  /* Check the parameters */
1159  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1160  tmpccmr1 = TIMx->CCMR1;
1161 
1162  /* Reset the OC2M Bits */
1163  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
1164 
1165  /* Configure The Forced output Mode */
1166  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
1167 
1168  /* Write to TIMx CCMR1 register */
1169  TIMx->CCMR1 = tmpccmr1;
1170 }
1171 
1181 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1182 {
1183  uint16_t tmpccmr2 = 0;
1184 
1185  /* Check the parameters */
1187  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1188 
1189  tmpccmr2 = TIMx->CCMR2;
1190 
1191  /* Reset the OC1M Bits */
1192  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
1193 
1194  /* Configure The Forced output Mode */
1195  tmpccmr2 |= TIM_ForcedAction;
1196 
1197  /* Write to TIMx CCMR2 register */
1198  TIMx->CCMR2 = tmpccmr2;
1199 }
1200 
1210 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1211 {
1212  uint16_t tmpccmr2 = 0;
1213 
1214  /* Check the parameters */
1216  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1217  tmpccmr2 = TIMx->CCMR2;
1218 
1219  /* Reset the OC2M Bits */
1220  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
1221 
1222  /* Configure The Forced output Mode */
1223  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
1224 
1225  /* Write to TIMx CCMR2 register */
1226  TIMx->CCMR2 = tmpccmr2;
1227 }
1228 
1238 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1239 {
1240  uint16_t tmpccmr1 = 0;
1241 
1242  /* Check the parameters */
1244  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1245 
1246  tmpccmr1 = TIMx->CCMR1;
1247 
1248  /* Reset the OC1PE Bit */
1249  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
1250 
1251  /* Enable or Disable the Output Compare Preload feature */
1252  tmpccmr1 |= TIM_OCPreload;
1253 
1254  /* Write to TIMx CCMR1 register */
1255  TIMx->CCMR1 = tmpccmr1;
1256 }
1257 
1268 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1269 {
1270  uint16_t tmpccmr1 = 0;
1271 
1272  /* Check the parameters */
1274  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1275 
1276  tmpccmr1 = TIMx->CCMR1;
1277 
1278  /* Reset the OC2PE Bit */
1279  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
1280 
1281  /* Enable or Disable the Output Compare Preload feature */
1282  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
1283 
1284  /* Write to TIMx CCMR1 register */
1285  TIMx->CCMR1 = tmpccmr1;
1286 }
1287 
1297 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1298 {
1299  uint16_t tmpccmr2 = 0;
1300 
1301  /* Check the parameters */
1303  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1304 
1305  tmpccmr2 = TIMx->CCMR2;
1306 
1307  /* Reset the OC3PE Bit */
1308  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
1309 
1310  /* Enable or Disable the Output Compare Preload feature */
1311  tmpccmr2 |= TIM_OCPreload;
1312 
1313  /* Write to TIMx CCMR2 register */
1314  TIMx->CCMR2 = tmpccmr2;
1315 }
1316 
1326 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1327 {
1328  uint16_t tmpccmr2 = 0;
1329 
1330  /* Check the parameters */
1332  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1333 
1334  tmpccmr2 = TIMx->CCMR2;
1335 
1336  /* Reset the OC4PE Bit */
1337  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
1338 
1339  /* Enable or Disable the Output Compare Preload feature */
1340  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
1341 
1342  /* Write to TIMx CCMR2 register */
1343  TIMx->CCMR2 = tmpccmr2;
1344 }
1345 
1355 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1356 {
1357  uint16_t tmpccmr1 = 0;
1358 
1359  /* Check the parameters */
1361  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1362 
1363  /* Get the TIMx CCMR1 register value */
1364  tmpccmr1 = TIMx->CCMR1;
1365 
1366  /* Reset the OC1FE Bit */
1367  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
1368 
1369  /* Enable or Disable the Output Compare Fast Bit */
1370  tmpccmr1 |= TIM_OCFast;
1371 
1372  /* Write to TIMx CCMR1 */
1373  TIMx->CCMR1 = tmpccmr1;
1374 }
1375 
1386 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1387 {
1388  uint16_t tmpccmr1 = 0;
1389 
1390  /* Check the parameters */
1392  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1393 
1394  /* Get the TIMx CCMR1 register value */
1395  tmpccmr1 = TIMx->CCMR1;
1396 
1397  /* Reset the OC2FE Bit */
1398  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
1399 
1400  /* Enable or Disable the Output Compare Fast Bit */
1401  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
1402 
1403  /* Write to TIMx CCMR1 */
1404  TIMx->CCMR1 = tmpccmr1;
1405 }
1406 
1416 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1417 {
1418  uint16_t tmpccmr2 = 0;
1419 
1420  /* Check the parameters */
1422  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1423 
1424  /* Get the TIMx CCMR2 register value */
1425  tmpccmr2 = TIMx->CCMR2;
1426 
1427  /* Reset the OC3FE Bit */
1428  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
1429 
1430  /* Enable or Disable the Output Compare Fast Bit */
1431  tmpccmr2 |= TIM_OCFast;
1432 
1433  /* Write to TIMx CCMR2 */
1434  TIMx->CCMR2 = tmpccmr2;
1435 }
1436 
1446 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1447 {
1448  uint16_t tmpccmr2 = 0;
1449 
1450  /* Check the parameters */
1452  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1453 
1454  /* Get the TIMx CCMR2 register value */
1455  tmpccmr2 = TIMx->CCMR2;
1456 
1457  /* Reset the OC4FE Bit */
1458  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
1459 
1460  /* Enable or Disable the Output Compare Fast Bit */
1461  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
1462 
1463  /* Write to TIMx CCMR2 */
1464  TIMx->CCMR2 = tmpccmr2;
1465 }
1466 
1476 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1477 {
1478  uint16_t tmpccmr1 = 0;
1479 
1480  /* Check the parameters */
1482  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1483 
1484  tmpccmr1 = TIMx->CCMR1;
1485 
1486  /* Reset the OC1CE Bit */
1487  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
1488 
1489  /* Enable or Disable the Output Compare Clear Bit */
1490  tmpccmr1 |= TIM_OCClear;
1491 
1492  /* Write to TIMx CCMR1 register */
1493  TIMx->CCMR1 = tmpccmr1;
1494 }
1495 
1506 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1507 {
1508  uint16_t tmpccmr1 = 0;
1509 
1510  /* Check the parameters */
1512  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1513 
1514  tmpccmr1 = TIMx->CCMR1;
1515 
1516  /* Reset the OC2CE Bit */
1517  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
1518 
1519  /* Enable or Disable the Output Compare Clear Bit */
1520  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
1521 
1522  /* Write to TIMx CCMR1 register */
1523  TIMx->CCMR1 = tmpccmr1;
1524 }
1525 
1535 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1536 {
1537  uint16_t tmpccmr2 = 0;
1538 
1539  /* Check the parameters */
1541  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1542 
1543  tmpccmr2 = TIMx->CCMR2;
1544 
1545  /* Reset the OC3CE Bit */
1546  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
1547 
1548  /* Enable or Disable the Output Compare Clear Bit */
1549  tmpccmr2 |= TIM_OCClear;
1550 
1551  /* Write to TIMx CCMR2 register */
1552  TIMx->CCMR2 = tmpccmr2;
1553 }
1554 
1564 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1565 {
1566  uint16_t tmpccmr2 = 0;
1567 
1568  /* Check the parameters */
1570  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1571 
1572  tmpccmr2 = TIMx->CCMR2;
1573 
1574  /* Reset the OC4CE Bit */
1575  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
1576 
1577  /* Enable or Disable the Output Compare Clear Bit */
1578  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
1579 
1580  /* Write to TIMx CCMR2 register */
1581  TIMx->CCMR2 = tmpccmr2;
1582 }
1583 
1593 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1594 {
1595  uint16_t tmpccer = 0;
1596 
1597  /* Check the parameters */
1599  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1600 
1601  tmpccer = TIMx->CCER;
1602 
1603  /* Set or Reset the CC1P Bit */
1604  tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
1605  tmpccer |= TIM_OCPolarity;
1606 
1607  /* Write to TIMx CCER register */
1608  TIMx->CCER = tmpccer;
1609 }
1610 
1620 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1621 {
1622  uint16_t tmpccer = 0;
1623  /* Check the parameters */
1625  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1626 
1627  tmpccer = TIMx->CCER;
1628 
1629  /* Set or Reset the CC1NP Bit */
1630  tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
1631  tmpccer |= TIM_OCNPolarity;
1632 
1633  /* Write to TIMx CCER register */
1634  TIMx->CCER = tmpccer;
1635 }
1636 
1647 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1648 {
1649  uint16_t tmpccer = 0;
1650 
1651  /* Check the parameters */
1653  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1654 
1655  tmpccer = TIMx->CCER;
1656 
1657  /* Set or Reset the CC2P Bit */
1658  tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
1659  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
1660 
1661  /* Write to TIMx CCER register */
1662  TIMx->CCER = tmpccer;
1663 }
1664 
1674 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1675 {
1676  uint16_t tmpccer = 0;
1677 
1678  /* Check the parameters */
1680  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1681 
1682  tmpccer = TIMx->CCER;
1683 
1684  /* Set or Reset the CC2NP Bit */
1685  tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
1686  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
1687 
1688  /* Write to TIMx CCER register */
1689  TIMx->CCER = tmpccer;
1690 }
1691 
1701 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1702 {
1703  uint16_t tmpccer = 0;
1704 
1705  /* Check the parameters */
1707  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1708 
1709  tmpccer = TIMx->CCER;
1710 
1711  /* Set or Reset the CC3P Bit */
1712  tmpccer &= (uint16_t)~TIM_CCER_CC3P;
1713  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
1714 
1715  /* Write to TIMx CCER register */
1716  TIMx->CCER = tmpccer;
1717 }
1718 
1728 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1729 {
1730  uint16_t tmpccer = 0;
1731 
1732  /* Check the parameters */
1734  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1735 
1736  tmpccer = TIMx->CCER;
1737 
1738  /* Set or Reset the CC3NP Bit */
1739  tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
1740  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
1741 
1742  /* Write to TIMx CCER register */
1743  TIMx->CCER = tmpccer;
1744 }
1745 
1755 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1756 {
1757  uint16_t tmpccer = 0;
1758 
1759  /* Check the parameters */
1761  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1762 
1763  tmpccer = TIMx->CCER;
1764 
1765  /* Set or Reset the CC4P Bit */
1766  tmpccer &= (uint16_t)~TIM_CCER_CC4P;
1767  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
1768 
1769  /* Write to TIMx CCER register */
1770  TIMx->CCER = tmpccer;
1771 }
1772 
1786 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
1787 {
1788  uint16_t tmp = 0;
1789 
1790  /* Check the parameters */
1792  assert_param(IS_TIM_CHANNEL(TIM_Channel));
1793  assert_param(IS_TIM_CCX(TIM_CCx));
1794 
1795  tmp = CCER_CCE_SET << TIM_Channel;
1796 
1797  /* Reset the CCxE Bit */
1798  TIMx->CCER &= (uint16_t)~ tmp;
1799 
1800  /* Set or reset the CCxE Bit */
1801  TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
1802 }
1803 
1816 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
1817 {
1818  uint16_t tmp = 0;
1819 
1820  /* Check the parameters */
1823  assert_param(IS_TIM_CCXN(TIM_CCxN));
1824 
1825  tmp = CCER_CCNE_SET << TIM_Channel;
1826 
1827  /* Reset the CCxNE Bit */
1828  TIMx->CCER &= (uint16_t) ~tmp;
1829 
1830  /* Set or reset the CCxNE Bit */
1831  TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
1832 }
1900 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
1901 {
1902  /* Check the parameters */
1904  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
1905  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
1906  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
1907  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
1908 
1909  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
1910  {
1911  /* TI1 Configuration */
1912  TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
1913  TIM_ICInitStruct->TIM_ICSelection,
1914  TIM_ICInitStruct->TIM_ICFilter);
1915  /* Set the Input Capture Prescaler value */
1916  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1917  }
1918  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
1919  {
1920  /* TI2 Configuration */
1922  TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
1923  TIM_ICInitStruct->TIM_ICSelection,
1924  TIM_ICInitStruct->TIM_ICFilter);
1925  /* Set the Input Capture Prescaler value */
1926  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1927  }
1928  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
1929  {
1930  /* TI3 Configuration */
1932  TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
1933  TIM_ICInitStruct->TIM_ICSelection,
1934  TIM_ICInitStruct->TIM_ICFilter);
1935  /* Set the Input Capture Prescaler value */
1936  TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1937  }
1938  else
1939  {
1940  /* TI4 Configuration */
1942  TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
1943  TIM_ICInitStruct->TIM_ICSelection,
1944  TIM_ICInitStruct->TIM_ICFilter);
1945  /* Set the Input Capture Prescaler value */
1946  TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1947  }
1948 }
1949 
1956 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
1957 {
1958  /* Set the default configuration */
1959  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
1960  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
1961  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
1962  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
1963  TIM_ICInitStruct->TIM_ICFilter = 0x00;
1964 }
1965 
1975 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
1976 {
1977  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
1978  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
1979 
1980  /* Check the parameters */
1982 
1983  /* Select the Opposite Input Polarity */
1984  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
1985  {
1986  icoppositepolarity = TIM_ICPolarity_Falling;
1987  }
1988  else
1989  {
1990  icoppositepolarity = TIM_ICPolarity_Rising;
1991  }
1992  /* Select the Opposite Input */
1993  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
1994  {
1995  icoppositeselection = TIM_ICSelection_IndirectTI;
1996  }
1997  else
1998  {
1999  icoppositeselection = TIM_ICSelection_DirectTI;
2000  }
2001  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
2002  {
2003  /* TI1 Configuration */
2004  TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
2005  TIM_ICInitStruct->TIM_ICFilter);
2006  /* Set the Input Capture Prescaler value */
2007  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2008  /* TI2 Configuration */
2009  TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
2010  /* Set the Input Capture Prescaler value */
2011  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2012  }
2013  else
2014  {
2015  /* TI2 Configuration */
2016  TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
2017  TIM_ICInitStruct->TIM_ICFilter);
2018  /* Set the Input Capture Prescaler value */
2019  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2020  /* TI1 Configuration */
2021  TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
2022  /* Set the Input Capture Prescaler value */
2023  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2024  }
2025 }
2026 
2033 {
2034  /* Check the parameters */
2036 
2037  /* Get the Capture 1 Register value */
2038  return TIMx->CCR1;
2039 }
2040 
2048 {
2049  /* Check the parameters */
2051 
2052  /* Get the Capture 2 Register value */
2053  return TIMx->CCR2;
2054 }
2055 
2062 {
2063  /* Check the parameters */
2065 
2066  /* Get the Capture 3 Register value */
2067  return TIMx->CCR3;
2068 }
2069 
2076 {
2077  /* Check the parameters */
2079 
2080  /* Get the Capture 4 Register value */
2081  return TIMx->CCR4;
2082 }
2083 
2095 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2096 {
2097  /* Check the parameters */
2099  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2100 
2101  /* Reset the IC1PSC Bits */
2102  TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
2103 
2104  /* Set the IC1PSC value */
2105  TIMx->CCMR1 |= TIM_ICPSC;
2106 }
2107 
2120 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2121 {
2122  /* Check the parameters */
2124  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2125 
2126  /* Reset the IC2PSC Bits */
2127  TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
2128 
2129  /* Set the IC2PSC value */
2130  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
2131 }
2132 
2144 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2145 {
2146  /* Check the parameters */
2148  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2149 
2150  /* Reset the IC3PSC Bits */
2151  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
2152 
2153  /* Set the IC3PSC value */
2154  TIMx->CCMR2 |= TIM_ICPSC;
2155 }
2156 
2168 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2169 {
2170  /* Check the parameters */
2172  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2173 
2174  /* Reset the IC4PSC Bits */
2175  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
2176 
2177  /* Set the IC4PSC value */
2178  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
2179 }
2221 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
2222 {
2223  /* Check the parameters */
2225  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
2226  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
2227  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
2228  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
2231 
2232  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2233  the OSSI State, the dead time value and the Automatic Output Enable Bit */
2234  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
2235  TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
2236  TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
2237  TIM_BDTRInitStruct->TIM_AutomaticOutput;
2238 }
2239 
2246 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
2247 {
2248  /* Set the default configuration */
2249  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
2250  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
2251  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
2252  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
2253  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
2254  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
2255  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
2256 }
2257 
2266 {
2267  /* Check the parameters */
2269  assert_param(IS_FUNCTIONAL_STATE(NewState));
2270 
2271  if (NewState != DISABLE)
2272  {
2273  /* Enable the TIM Main Output */
2274  TIMx->BDTR |= TIM_BDTR_MOE;
2275  }
2276  else
2277  {
2278  /* Disable the TIM Main Output */
2279  TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
2280  }
2281 }
2282 
2291 {
2292  /* Check the parameters */
2294  assert_param(IS_FUNCTIONAL_STATE(NewState));
2295 
2296  if (NewState != DISABLE)
2297  {
2298  /* Set the COM Bit */
2299  TIMx->CR2 |= TIM_CR2_CCUS;
2300  }
2301  else
2302  {
2303  /* Reset the COM Bit */
2304  TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
2305  }
2306 }
2307 
2316 {
2317  /* Check the parameters */
2319  assert_param(IS_FUNCTIONAL_STATE(NewState));
2320  if (NewState != DISABLE)
2321  {
2322  /* Set the CCPC Bit */
2323  TIMx->CR2 |= TIM_CR2_CCPC;
2324  }
2325  else
2326  {
2327  /* Reset the CCPC Bit */
2328  TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
2329  }
2330 }
2372 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
2373 {
2374  /* Check the parameters */
2376  assert_param(IS_TIM_IT(TIM_IT));
2377  assert_param(IS_FUNCTIONAL_STATE(NewState));
2378 
2379  if (NewState != DISABLE)
2380  {
2381  /* Enable the Interrupt sources */
2382  TIMx->DIER |= TIM_IT;
2383  }
2384  else
2385  {
2386  /* Disable the Interrupt sources */
2387  TIMx->DIER &= (uint16_t)~TIM_IT;
2388  }
2389 }
2390 
2410 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
2411 {
2412  /* Check the parameters */
2414  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
2415 
2416  /* Set the event sources */
2417  TIMx->EGR = TIM_EventSource;
2418 }
2419 
2443 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
2444 {
2445  ITStatus bitstatus = RESET;
2446  /* Check the parameters */
2448  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
2449 
2450 
2451  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
2452  {
2453  bitstatus = SET;
2454  }
2455  else
2456  {
2457  bitstatus = RESET;
2458  }
2459  return bitstatus;
2460 }
2461 
2485 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
2486 {
2487  /* Check the parameters */
2489 
2490  /* Clear the flags */
2491  TIMx->SR = (uint16_t)~TIM_FLAG;
2492 }
2493 
2513 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
2514 {
2515  ITStatus bitstatus = RESET;
2516  uint16_t itstatus = 0x0, itenable = 0x0;
2517  /* Check the parameters */
2519  assert_param(IS_TIM_GET_IT(TIM_IT));
2520 
2521  itstatus = TIMx->SR & TIM_IT;
2522 
2523  itenable = TIMx->DIER & TIM_IT;
2524  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
2525  {
2526  bitstatus = SET;
2527  }
2528  else
2529  {
2530  bitstatus = RESET;
2531  }
2532  return bitstatus;
2533 }
2534 
2554 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
2555 {
2556  /* Check the parameters */
2558 
2559  /* Clear the IT pending Bit */
2560  TIMx->SR = (uint16_t)~TIM_IT;
2561 }
2562 
2591 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
2592 {
2593  /* Check the parameters */
2595  assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
2596  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
2597 
2598  /* Set the DMA Base and the DMA Burst Length */
2599  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
2600 }
2601 
2618 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
2619 {
2620  /* Check the parameters */
2622  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
2623  assert_param(IS_FUNCTIONAL_STATE(NewState));
2624 
2625  if (NewState != DISABLE)
2626  {
2627  /* Enable the DMA sources */
2628  TIMx->DIER |= TIM_DMASource;
2629  }
2630  else
2631  {
2632  /* Disable the DMA sources */
2633  TIMx->DIER &= (uint16_t)~TIM_DMASource;
2634  }
2635 }
2636 
2645 {
2646  /* Check the parameters */
2648  assert_param(IS_FUNCTIONAL_STATE(NewState));
2649 
2650  if (NewState != DISABLE)
2651  {
2652  /* Set the CCDS Bit */
2653  TIMx->CR2 |= TIM_CR2_CCDS;
2654  }
2655  else
2656  {
2657  /* Reset the CCDS Bit */
2658  TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
2659  }
2660 }
2684 {
2685  /* Check the parameters */
2687 
2688  /* Disable slave mode to clock the prescaler directly with the internal clock */
2689  TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
2690 }
2691 
2704 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
2705 {
2706  /* Check the parameters */
2708  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
2709 
2710  /* Select the Internal Trigger */
2711  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
2712 
2713  /* Select the External clock mode1 */
2714  TIMx->SMCR |= TIM_SlaveMode_External1;
2715 }
2716 
2734 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
2735  uint16_t TIM_ICPolarity, uint16_t ICFilter)
2736 {
2737  /* Check the parameters */
2739  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
2740  assert_param(IS_TIM_IC_FILTER(ICFilter));
2741 
2742  /* Configure the Timer Input Clock Source */
2743  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
2744  {
2745  TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
2746  }
2747  else
2748  {
2749  TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
2750  }
2751  /* Select the Trigger source */
2752  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
2753  /* Select the External clock mode1 */
2754  TIMx->SMCR |= TIM_SlaveMode_External1;
2755 }
2756 
2774 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
2775  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
2776 {
2777  uint16_t tmpsmcr = 0;
2778 
2779  /* Check the parameters */
2781  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
2782  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
2783  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
2784  /* Configure the ETR Clock source */
2785  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
2786 
2787  /* Get the TIMx SMCR register value */
2788  tmpsmcr = TIMx->SMCR;
2789 
2790  /* Reset the SMS Bits */
2791  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
2792 
2793  /* Select the External clock mode1 */
2794  tmpsmcr |= TIM_SlaveMode_External1;
2795 
2796  /* Select the Trigger selection : ETRF */
2797  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
2798  tmpsmcr |= TIM_TS_ETRF;
2799 
2800  /* Write to TIMx SMCR */
2801  TIMx->SMCR = tmpsmcr;
2802 }
2803 
2821 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
2822  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
2823 {
2824  /* Check the parameters */
2826  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
2827  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
2828  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
2829 
2830  /* Configure the ETR Clock source */
2831  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
2832 
2833  /* Enable the External clock mode2 */
2834  TIMx->SMCR |= TIM_SMCR_ECE;
2835 }
2892 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
2893 {
2894  uint16_t tmpsmcr = 0;
2895 
2896  /* Check the parameters */
2898  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
2899 
2900  /* Get the TIMx SMCR register value */
2901  tmpsmcr = TIMx->SMCR;
2902 
2903  /* Reset the TS Bits */
2904  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
2905 
2906  /* Set the Input Trigger source */
2907  tmpsmcr |= TIM_InputTriggerSource;
2908 
2909  /* Write to TIMx SMCR */
2910  TIMx->SMCR = tmpsmcr;
2911 }
2912 
2935 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
2936 {
2937  /* Check the parameters */
2939  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
2940 
2941  /* Reset the MMS Bits */
2942  TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
2943  /* Select the TRGO source */
2944  TIMx->CR2 |= TIM_TRGOSource;
2945 }
2946 
2959 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
2960 {
2961  /* Check the parameters */
2963  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
2964 
2965  /* Reset the SMS Bits */
2966  TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
2967 
2968  /* Select the Slave Mode */
2969  TIMx->SMCR |= TIM_SlaveMode;
2970 }
2971 
2982 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
2983 {
2984  /* Check the parameters */
2986  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
2987 
2988  /* Reset the MSM Bit */
2989  TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
2990 
2991  /* Set or Reset the MSM Bit */
2992  TIMx->SMCR |= TIM_MasterSlaveMode;
2993 }
2994 
3012 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
3013  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
3014 {
3015  uint16_t tmpsmcr = 0;
3016 
3017  /* Check the parameters */
3019  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
3020  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
3021  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
3022 
3023  tmpsmcr = TIMx->SMCR;
3024 
3025  /* Reset the ETR Bits */
3026  tmpsmcr &= SMCR_ETR_MASK;
3027 
3028  /* Set the Prescaler, the Filter value and the Polarity */
3029  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
3030 
3031  /* Write to TIMx SMCR */
3032  TIMx->SMCR = tmpsmcr;
3033 }
3070 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
3071  uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
3072 {
3073  uint16_t tmpsmcr = 0;
3074  uint16_t tmpccmr1 = 0;
3075  uint16_t tmpccer = 0;
3076 
3077  /* Check the parameters */
3079  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
3080  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
3081  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
3082 
3083  /* Get the TIMx SMCR register value */
3084  tmpsmcr = TIMx->SMCR;
3085 
3086  /* Get the TIMx CCMR1 register value */
3087  tmpccmr1 = TIMx->CCMR1;
3088 
3089  /* Get the TIMx CCER register value */
3090  tmpccer = TIMx->CCER;
3091 
3092  /* Set the encoder Mode */
3093  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
3094  tmpsmcr |= TIM_EncoderMode;
3095 
3096  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3097  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
3098  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
3099 
3100  /* Set the TI1 and the TI2 Polarities */
3101  tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
3102  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
3103 
3104  /* Write to TIMx SMCR */
3105  TIMx->SMCR = tmpsmcr;
3106 
3107  /* Write to TIMx CCMR1 */
3108  TIMx->CCMR1 = tmpccmr1;
3109 
3110  /* Write to TIMx CCER */
3111  TIMx->CCER = tmpccer;
3112 }
3113 
3123 {
3124  /* Check the parameters */
3126  assert_param(IS_FUNCTIONAL_STATE(NewState));
3127 
3128  if (NewState != DISABLE)
3129  {
3130  /* Set the TI1S Bit */
3131  TIMx->CR2 |= TIM_CR2_TI1S;
3132  }
3133  else
3134  {
3135  /* Reset the TI1S Bit */
3136  TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
3137  }
3138 }
3173 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
3174 {
3175  /* Check the parameters */
3177  assert_param(IS_TIM_REMAP(TIM_Remap));
3178 
3179  /* Set the Timer remapping configuration */
3180  TIMx->OR = TIM_Remap;
3181 }
3204 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3205  uint16_t TIM_ICFilter)
3206 {
3207  uint16_t tmpccmr1 = 0, tmpccer = 0;
3208 
3209  /* Disable the Channel 1: Reset the CC1E Bit */
3210  TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
3211  tmpccmr1 = TIMx->CCMR1;
3212  tmpccer = TIMx->CCER;
3213 
3214  /* Select the Input and set the filter */
3215  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
3216  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
3217 
3218  /* Select the Polarity and set the CC1E Bit */
3219  tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
3220  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
3221 
3222  /* Write to TIMx CCMR1 and CCER registers */
3223  TIMx->CCMR1 = tmpccmr1;
3224  TIMx->CCER = tmpccer;
3225 }
3226 
3245 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3246  uint16_t TIM_ICFilter)
3247 {
3248  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
3249 
3250  /* Disable the Channel 2: Reset the CC2E Bit */
3251  TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
3252  tmpccmr1 = TIMx->CCMR1;
3253  tmpccer = TIMx->CCER;
3254  tmp = (uint16_t)(TIM_ICPolarity << 4);
3255 
3256  /* Select the Input and set the filter */
3257  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
3258  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
3259  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
3260 
3261  /* Select the Polarity and set the CC2E Bit */
3262  tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
3263  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
3264 
3265  /* Write to TIMx CCMR1 and CCER registers */
3266  TIMx->CCMR1 = tmpccmr1 ;
3267  TIMx->CCER = tmpccer;
3268 }
3269 
3287 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3288  uint16_t TIM_ICFilter)
3289 {
3290  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
3291 
3292  /* Disable the Channel 3: Reset the CC3E Bit */
3293  TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
3294  tmpccmr2 = TIMx->CCMR2;
3295  tmpccer = TIMx->CCER;
3296  tmp = (uint16_t)(TIM_ICPolarity << 8);
3297 
3298  /* Select the Input and set the filter */
3299  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
3300  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
3301 
3302  /* Select the Polarity and set the CC3E Bit */
3303  tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
3304  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
3305 
3306  /* Write to TIMx CCMR2 and CCER registers */
3307  TIMx->CCMR2 = tmpccmr2;
3308  TIMx->CCER = tmpccer;
3309 }
3310 
3328 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3329  uint16_t TIM_ICFilter)
3330 {
3331  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
3332 
3333  /* Disable the Channel 4: Reset the CC4E Bit */
3334  TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
3335  tmpccmr2 = TIMx->CCMR2;
3336  tmpccer = TIMx->CCER;
3337  tmp = (uint16_t)(TIM_ICPolarity << 12);
3338 
3339  /* Select the Input and set the filter */
3340  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
3341  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
3342  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
3343 
3344  /* Select the Polarity and set the CC4E Bit */
3345  tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
3346  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
3347 
3348  /* Write to TIMx CCMR2 and CCER registers */
3349  TIMx->CCMR2 = tmpccmr2;
3350  TIMx->CCER = tmpccer ;
3351 }
3352 
3365 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
#define TIM_CCMR1_OC1FE
Definition: stm32f4xx.h:10528
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
#define IS_TIM_COUNTER_MODE(MODE)
uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
FlagStatus
Definition: stm32f4xx.h:706
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
#define IS_TIM_CKD_DIV(DIV)
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
#define TIM_PSCReloadMode_Immediate
#define IS_TIM_OC_MODE(MODE)
#define TIM_TS_ETRF
#define TIM_CCER_CC3NE
Definition: stm32f4xx.h:10636
uint16_t TIM_OutputNState
Definition: stm32f4xx_tim.h:92
#define TIM4
Definition: stm32f4xx.h:2039
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.
#define IS_TIM_EVENT_SOURCE(SOURCE)
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
#define IS_TIM_SLAVE_MODE(MODE)
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx&#39;s One Pulse Mode.
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
#define IS_TIM_LIST3_PERIPH(PERIPH)
#define TIM_OSSIState_Disable
#define TIM_AutomaticOutput_Disable
#define TIM_ICSelection_DirectTI
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx&#39;s DMA Requests.
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
#define TIM_LOCKLevel_OFF
#define TIM_CCER_CC4P
Definition: stm32f4xx.h:10639
FunctionalState
Definition: stm32f4xx.h:708
#define TIM1
Definition: stm32f4xx.h:2078
#define TIM_CCMR1_OC1M
Definition: stm32f4xx.h:10531
#define TIM_CR2_CCDS
Definition: stm32f4xx.h:10440
#define IS_TIM_TRGO_SOURCE(SOURCE)
#define IS_TIM_EXT_POLARITY(POLARITY)
__IO uint16_t CCER
Definition: stm32f4xx.h:1684
uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI4 as Input.
#define TIM_CCMR2_CC4S
Definition: stm32f4xx.h:10589
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
#define TIM_Channel_3
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
#define TIM_CCER_CC1NP
Definition: stm32f4xx.h:10629
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
#define TIM3
Definition: stm32f4xx.h:2038
#define TIM_CR2_OIS3N
Definition: stm32f4xx.h:10453
#define TIM12
Definition: stm32f4xx.h:2043
#define IS_TIM_OUTPUTN_STATE(STATE)
#define IS_TIM_BREAK_STATE(STATE)
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
#define TIM_CCMR1_OC2FE
Definition: stm32f4xx.h:10542
#define TIM9
Definition: stm32f4xx.h:2091
#define TIM_OCNIdleState_Reset
#define TIM2
Definition: stm32f4xx.h:2037
#define TIM_OutputNState_Disable
#define TIM8
Definition: stm32f4xx.h:2079
#define CCMR_OFFSET
#define TIM_CCMR1_CC1S
Definition: stm32f4xx.h:10524
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
#define IS_TIM_PRESCALER_RELOAD(RELOAD)
uint16_t TIM_AutomaticOutput
This file contains all the functions prototypes for the TIM firmware library.
#define TIM_ICSelection_IndirectTI
#define TIM_CR1_CEN
Definition: stm32f4xx.h:10421
#define TIM_CCER_CC3P
Definition: stm32f4xx.h:10635
#define IS_TIM_GET_IT(IT)
__IO uint16_t PSC
Definition: stm32f4xx.h:1687
void TIM_DeInit(TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
#define TIM_ICPolarity_Falling
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx&#39;s Hall sensor interface.
#define TIM_CCMR2_IC3F
Definition: stm32f4xx.h:10609
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output ena...
#define IS_TIM_UPDATE_SOURCE(SOURCE)
static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI2 as Input.
#define TIM_CCMR2_CC3S
Definition: stm32f4xx.h:10575
#define TIM_SlaveMode_External1
#define TIM_CCER_CC1E
Definition: stm32f4xx.h:10626
#define IS_TIM_LIST5_PERIPH(PERIPH)
__IO uint16_t CCMR1
Definition: stm32f4xx.h:1680
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define TIM_CR1_CMS
Definition: stm32f4xx.h:10427
#define TIM_Channel_2
#define CCMR_OC13M_MASK
#define TIM_CR2_OIS1N
Definition: stm32f4xx.h:10449
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
#define IS_TIM_ENCODER_MODE(MODE)
void assert_param(int val)
#define TIM_CR2_OIS3
Definition: stm32f4xx.h:10452
#define IS_TIM_OCFAST_STATE(STATE)
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
#define IS_TIM_IC_PRESCALER(PRESCALER)
#define IS_TIM_OCM(MODE)
#define IS_TIM_CCX(CCX)
#define IS_TIM_GET_FLAG(FLAG)
#define TIM_CCMR2_OC4FE
Definition: stm32f4xx.h:10593
#define TIM_CCMR2_OC3FE
Definition: stm32f4xx.h:10579
#define TIM_CCMR2_OC3CE
Definition: stm32f4xx.h:10587
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
uint16_t TIM_ICPolarity
__IO uint32_t CCR3
Definition: stm32f4xx.h:1694
#define TIM_CCMR1_OC2PE
Definition: stm32f4xx.h:10543
#define IS_TIM_BREAK_POLARITY(POLARITY)
#define SMCR_ETR_MASK
#define TIM_CR2_OIS2N
Definition: stm32f4xx.h:10451
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx&#39;s DMA interface.
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
#define IS_TIM_OSSI_STATE(STATE)
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
__IO uint32_t CCR1
Definition: stm32f4xx.h:1692
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL)
Definition: stm32f4xx.h:706
#define TIM_OSSRState_Disable
#define TIM_CR1_UDIS
Definition: stm32f4xx.h:10422
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
#define IS_TIM_LIST1_PERIPH(PERIPH)
uint16_t TIM_ICPrescaler
static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI3 as Input.
#define TIM_CR1_URS
Definition: stm32f4xx.h:10423
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
enum FlagStatus ITStatus
#define IS_TIM_LOCK_LEVEL(LEVEL)
uint16_t TIM_OCPolarity
Definition: stm32f4xx_tim.h:99
#define TIM_CCER_CC4NP
Definition: stm32f4xx.h:10640
#define TIM_CCMR1_IC1F
Definition: stm32f4xx.h:10558
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
__IO uint16_t DCR
Definition: stm32f4xx.h:1698
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
#define TIM_CCMR2_OC4CE
Definition: stm32f4xx.h:10601
#define TIM_TIxExternalCLK1Source_TI2
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
#define TIM6
Definition: stm32f4xx.h:2041
#define TIM_CCMR1_CC2S_0
Definition: stm32f4xx.h:10539
#define IS_TIM_REMAP(TIM_REMAP)
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx&#39;s interrupt pending bits.
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx&#39;s pending flags.
#define __IO
Definition: core_cm0.h:198
#define TIM_CCER_CC3E
Definition: stm32f4xx.h:10634
#define IS_TIM_OSSR_STATE(STATE)
#define TIM_CCMR1_OC2CE
Definition: stm32f4xx.h:10550
#define TIM5
Definition: stm32f4xx.h:2040
void TIM_RemapConfig(TIM_TypeDef *TIMx, uint16_t TIM_Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
#define TIM_CKD_DIV1
#define IS_TIM_LIST2_PERIPH(PERIPH)
#define TIM_CR2_CCPC
Definition: stm32f4xx.h:10438
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measur...
#define IS_TIM_CHANNEL(CHANNEL)
#define TIM_SMCR_ECE
Definition: stm32f4xx.h:10479
#define CCER_CCE_SET
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
#define TIM_CR2_MMS
Definition: stm32f4xx.h:10442
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
#define TIM_CCMR2_OC4PE
Definition: stm32f4xx.h:10594
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
#define IS_TIM_EXT_FILTER(EXTFILTER)
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
#define TIM_Channel_1
#define TIM_CCMR2_OC3M
Definition: stm32f4xx.h:10582
#define TIM_ICPolarity_Rising
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
#define TIM_CR1_DIR
Definition: stm32f4xx.h:10425
#define TIM_CCER_CC2NP
Definition: stm32f4xx.h:10633
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
#define IS_TIM_OCCLEAR_STATE(STATE)
#define IS_TIM_CCXN(CCXN)
#define TIM10
Definition: stm32f4xx.h:2092
#define IS_TIM_IC_POLARITY(POLARITY)
void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
#define IS_TIM_DMA_SOURCE(SOURCE)
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
__IO uint32_t ARR
Definition: stm32f4xx.h:1689
#define TIM_CCER_CC2P
Definition: stm32f4xx.h:10631
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
#define TIM_CCER_CC3NP
Definition: stm32f4xx.h:10637
#define TIM_CCER_CC2E
Definition: stm32f4xx.h:10630
#define IS_TIM_DMA_LENGTH(LENGTH)
#define IS_TIM_ALL_PERIPH(PERIPH)
TIM Time Base Init structure definition.
Definition: stm32f4xx_tim.h:55
#define TIM_ICPSC_DIV1
#define TIM_OutputState_Disable
#define TIM_CCER_CC4E
Definition: stm32f4xx.h:10638
#define TIM_OCMode_Timing
uint16_t TIM_OCNPolarity
#define TIM_BDTR_MOE
Definition: stm32f4xx.h:10686
#define TIM_CR1_ARPE
Definition: stm32f4xx.h:10431
#define TIM_SMCR_TS
Definition: stm32f4xx.h:10462
#define TIM_SMCR_MSM
Definition: stm32f4xx.h:10467
#define TIM_CR1_OPM
Definition: stm32f4xx.h:10424
TIM Input Capture Init structure definition.
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
__IO uint16_t BDTR
Definition: stm32f4xx.h:1696
static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI1 as Input.
uint16_t TIM_BreakPolarity
__IO uint32_t CCR4
Definition: stm32f4xx.h:1695
#define TIM_CCMR2_OC4M
Definition: stm32f4xx.h:10596
uint16_t TIM_OutputState
Definition: stm32f4xx_tim.h:89
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
#define IS_TIM_IC_SELECTION(SELECTION)
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
#define TIM13
Definition: stm32f4xx.h:2044
#define TIM_CCMR1_OC1CE
Definition: stm32f4xx.h:10536
#define TIM_CCER_CC1NE
Definition: stm32f4xx.h:10628
#define TIM_CCER_CC2NE
Definition: stm32f4xx.h:10632
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
__IO uint16_t OR
Definition: stm32f4xx.h:1702
uint16_t TIM_ICSelection
#define TIM_CCMR1_IC2F
Definition: stm32f4xx.h:10568
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
#define TIM11
Definition: stm32f4xx.h:2093
uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
#define TIM_CCMR1_CC2S
Definition: stm32f4xx.h:10538
#define TIM_CR2_TI1S
Definition: stm32f4xx.h:10447
#define IS_TIM_OCNIDLE_STATE(STATE)
__IO uint16_t SR
Definition: stm32f4xx.h:1676
uint16_t TIM_OCNIdleState
#define TIM_CCMR2_IC3PSC
Definition: stm32f4xx.h:10605
#define TIM_CCMR2_OC3PE
Definition: stm32f4xx.h:10580
#define IS_TIM_TRIGGER_SELECTION(SELECTION)
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
#define TIM_CR2_OIS2
Definition: stm32f4xx.h:10450
#define TIM_OCPolarity_High
#define IS_TIM_IC_FILTER(ICFILTER)
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
#define TIM_BreakPolarity_Low
#define IS_TIM_IT(IT)
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeB...
#define CCMR_OC24M_MASK
#define TIM_SMCR_SMS
Definition: stm32f4xx.h:10457
__IO uint16_t CCMR2
Definition: stm32f4xx.h:1682
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
__IO uint16_t CR2
Definition: stm32f4xx.h:1670
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
#define IS_TIM_LIST4_PERIPH(PERIPH)
#define TIM_CCMR1_IC1PSC
Definition: stm32f4xx.h:10554
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
#define TIM_OCIdleState_Reset
#define TIM_UpdateSource_Global
#define IS_TIM_LIST6_PERIPH(TIMx)
__IO uint16_t CR1
Definition: stm32f4xx.h:1668
#define TIM_Break_Disable
#define IS_TIM_OC_POLARITY(POLARITY)
#define IS_TIM_OUTPUT_STATE(STATE)
#define IS_TIM_DMA_BASE(BASE)
#define TIM_CR2_CCUS
Definition: stm32f4xx.h:10439
uint32_t TIM_GetCounter(TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
__IO uint16_t DIER
Definition: stm32f4xx.h:1674
#define TIM_CR2_OIS1
Definition: stm32f4xx.h:10448
TIM Output Compare Init structure definition.
Definition: stm32f4xx_tim.h:84
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
#define TIM_CR2_OIS4
Definition: stm32f4xx.h:10454
#define TIM_CR1_CKD
Definition: stm32f4xx.h:10433
#define IS_TIM_MSM_STATE(STATE)
#define TIM_CCMR1_OC1PE
Definition: stm32f4xx.h:10529
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
#define TIM_CCMR2_IC4PSC
Definition: stm32f4xx.h:10615
#define CCER_CCNE_SET
#define TIM_CCER_CC1P
Definition: stm32f4xx.h:10627
BDTR structure definition.
__IO uint16_t SMCR
Definition: stm32f4xx.h:1672
#define IS_TIM_OCIDLE_STATE(STATE)
#define TIM14
Definition: stm32f4xx.h:2045
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
#define TIM_CounterMode_Up
__IO uint32_t CNT
Definition: stm32f4xx.h:1686
#define IS_TIM_OPM_MODE(MODE)
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
__IO uint32_t CCR2
Definition: stm32f4xx.h:1693
#define IS_TIM_OCPRELOAD_STATE(STATE)
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
#define TIM_CCMR1_CC1S_0
Definition: stm32f4xx.h:10525
#define IS_TIM_OCN_POLARITY(POLARITY)
#define IS_TIM_FORCED_ACTION(ACTION)
__IO uint16_t EGR
Definition: stm32f4xx.h:1678
#define TIM_CCMR1_OC2M
Definition: stm32f4xx.h:10545
uint16_t TIM_OCIdleState
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
#define TIM_CCMR1_IC2PSC
Definition: stm32f4xx.h:10564
void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
#define IS_TIM_EXT_PRESCALER(PRESCALER)
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
#define TIM7
Definition: stm32f4xx.h:2042
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
__IO uint16_t RCR
Definition: stm32f4xx.h:1690


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19