stm32f4xx_fsmc.c
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1 
34 /* Includes ------------------------------------------------------------------*/
35 #include "stm32f4xx_fsmc.h"
36 #include "stm32f4xx_rcc.h"
37 
47 /* Private typedef -----------------------------------------------------------*/
48 /* Private define ------------------------------------------------------------*/
49 
50 /* --------------------- FSMC registers bit mask ---------------------------- */
51 /* FSMC BCRx Mask */
52 #define BCR_MBKEN_SET ((uint32_t)0x00000001)
53 #define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
54 #define BCR_FACCEN_SET ((uint32_t)0x00000040)
55 
56 /* FSMC PCRx Mask */
57 #define PCR_PBKEN_SET ((uint32_t)0x00000004)
58 #define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
59 #define PCR_ECCEN_SET ((uint32_t)0x00000040)
60 #define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
61 #define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
62 
63 /* Private macro -------------------------------------------------------------*/
64 /* Private variables ---------------------------------------------------------*/
65 /* Private function prototypes -----------------------------------------------*/
66 /* Private functions ---------------------------------------------------------*/
67 
121 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
122 {
123  /* Check the parameter */
125 
126  /* FSMC_Bank1_NORSRAM1 */
127  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
128  {
129  FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
130  }
131  /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
132  else
133  {
134  FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
135  }
136  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
137  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
138 }
139 
148 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
149 {
150  /* Check the parameters */
151  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
152  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
153  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
154  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
155  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
156  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
158  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
160  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
161  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
162  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
163  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
171 
172  /* Bank1 NOR/SRAM control register configuration */
173  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
174  (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
175  FSMC_NORSRAMInitStruct->FSMC_MemoryType |
176  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
177  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
178  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
179  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
180  FSMC_NORSRAMInitStruct->FSMC_WrapMode |
181  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
182  FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
183  FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
184  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
185  FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
186  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
187  {
188  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
189  }
190  /* Bank1 NOR/SRAM timing register configuration */
191  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
192  (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
193  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
194  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
195  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
196  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
197  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
198  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
199 
200 
201  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
202  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
203  {
210  FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
211  (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
212  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
213  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
214  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
215  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
216  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
217  }
218  else
219  {
220  FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
221  }
222 }
223 
230 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
231 {
232  /* Reset NOR/SRAM Init structure parameters values */
233  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
234  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
235  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
236  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
237  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
238  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
239  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
240  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
242  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
243  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
244  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
245  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
246  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
247  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
248  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
249  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
250  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
251  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
253  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
254  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
255  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
256  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
257  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
258  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
259  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
260 }
261 
273 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
274 {
277 
278  if (NewState != DISABLE)
279  {
280  /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
281  FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
282  }
283  else
284  {
285  /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
286  FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
287  }
288 }
346 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
347 {
348  /* Check the parameter */
349  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
350 
351  if(FSMC_Bank == FSMC_Bank2_NAND)
352  {
353  /* Set the FSMC_Bank2 registers to their reset values */
354  FSMC_Bank2->PCR2 = 0x00000018;
355  FSMC_Bank2->SR2 = 0x00000040;
356  FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
357  FSMC_Bank2->PATT2 = 0xFCFCFCFC;
358  }
359  /* FSMC_Bank3_NAND */
360  else
361  {
362  /* Set the FSMC_Bank3 registers to their reset values */
363  FSMC_Bank3->PCR3 = 0x00000018;
364  FSMC_Bank3->SR3 = 0x00000040;
365  FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
366  FSMC_Bank3->PATT3 = 0xFCFCFCFC;
367  }
368 }
369 
377 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
378 {
379  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
380 
381  /* Check the parameters */
382  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
383  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
385  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
386  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
387  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
388  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
397 
398  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
399  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
401  FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
402  FSMC_NANDInitStruct->FSMC_ECC |
403  FSMC_NANDInitStruct->FSMC_ECCPageSize |
404  (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
405  (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
406 
407  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
408  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
409  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
410  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
411  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
412 
413  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
414  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
415  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
416  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
417  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
418 
419  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
420  {
421  /* FSMC_Bank2_NAND registers configuration */
422  FSMC_Bank2->PCR2 = tmppcr;
423  FSMC_Bank2->PMEM2 = tmppmem;
424  FSMC_Bank2->PATT2 = tmppatt;
425  }
426  else
427  {
428  /* FSMC_Bank3_NAND registers configuration */
429  FSMC_Bank3->PCR3 = tmppcr;
430  FSMC_Bank3->PMEM3 = tmppmem;
431  FSMC_Bank3->PATT3 = tmppatt;
432  }
433 }
434 
435 
442 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
443 {
444  /* Reset NAND Init structure parameters values */
445  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
446  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
447  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
448  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
449  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
450  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
451  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
452  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
453  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
454  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
455  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
456  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
457  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
458  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
459  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
460 }
461 
471 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
472 {
473  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
475 
476  if (NewState != DISABLE)
477  {
478  /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
479  if(FSMC_Bank == FSMC_Bank2_NAND)
480  {
481  FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
482  }
483  else
484  {
485  FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
486  }
487  }
488  else
489  {
490  /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
491  if(FSMC_Bank == FSMC_Bank2_NAND)
492  {
493  FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
494  }
495  else
496  {
497  FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
498  }
499  }
500 }
511 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
512 {
513  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
515 
516  if (NewState != DISABLE)
517  {
518  /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
519  if(FSMC_Bank == FSMC_Bank2_NAND)
520  {
521  FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
522  }
523  else
524  {
525  FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
526  }
527  }
528  else
529  {
530  /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
531  if(FSMC_Bank == FSMC_Bank2_NAND)
532  {
533  FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
534  }
535  else
536  {
537  FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
538  }
539  }
540 }
541 
550 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
551 {
552  uint32_t eccval = 0x00000000;
553 
554  if(FSMC_Bank == FSMC_Bank2_NAND)
555  {
556  /* Get the ECCR2 register value */
557  eccval = FSMC_Bank2->ECCR2;
558  }
559  else
560  {
561  /* Get the ECCR3 register value */
562  eccval = FSMC_Bank3->ECCR3;
563  }
564  /* Return the error correction code value */
565  return(eccval);
566 }
615 {
616  /* Set the FSMC_Bank4 registers to their reset values */
617  FSMC_Bank4->PCR4 = 0x00000018;
618  FSMC_Bank4->SR4 = 0x00000000;
619  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
620  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
621  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
622 }
623 
631 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
632 {
633  /* Check the parameters */
634  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
635  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
636  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
637 
642 
651 
652  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
653  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
655  (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
656  (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
657 
658  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
659  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
660  (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
661  (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
662  (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
663 
664  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
665  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
666  (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
667  (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
668  (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
669 
670  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
671  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
672  (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
673  (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
674  (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
675 }
676 
683 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
684 {
685  /* Reset PCCARD Init structure parameters values */
686  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
687  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
688  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
689  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
690  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
691  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
692  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
693  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
694  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
695  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
696  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
697  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
698  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
699  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
700  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
701 }
702 
710 {
712 
713  if (NewState != DISABLE)
714  {
715  /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
716  FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
717  }
718  else
719  {
720  /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
721  FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
722  }
723 }
756 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
757 {
758  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
759  assert_param(IS_FSMC_IT(FSMC_IT));
761 
762  if (NewState != DISABLE)
763  {
764  /* Enable the selected FSMC_Bank2 interrupts */
765  if(FSMC_Bank == FSMC_Bank2_NAND)
766  {
767  FSMC_Bank2->SR2 |= FSMC_IT;
768  }
769  /* Enable the selected FSMC_Bank3 interrupts */
770  else if (FSMC_Bank == FSMC_Bank3_NAND)
771  {
772  FSMC_Bank3->SR3 |= FSMC_IT;
773  }
774  /* Enable the selected FSMC_Bank4 interrupts */
775  else
776  {
777  FSMC_Bank4->SR4 |= FSMC_IT;
778  }
779  }
780  else
781  {
782  /* Disable the selected FSMC_Bank2 interrupts */
783  if(FSMC_Bank == FSMC_Bank2_NAND)
784  {
785 
786  FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
787  }
788  /* Disable the selected FSMC_Bank3 interrupts */
789  else if (FSMC_Bank == FSMC_Bank3_NAND)
790  {
791  FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
792  }
793  /* Disable the selected FSMC_Bank4 interrupts */
794  else
795  {
796  FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
797  }
798  }
799 }
800 
816 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
817 {
818  FlagStatus bitstatus = RESET;
819  uint32_t tmpsr = 0x00000000;
820 
821  /* Check the parameters */
823  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
824 
825  if(FSMC_Bank == FSMC_Bank2_NAND)
826  {
827  tmpsr = FSMC_Bank2->SR2;
828  }
829  else if(FSMC_Bank == FSMC_Bank3_NAND)
830  {
831  tmpsr = FSMC_Bank3->SR3;
832  }
833  /* FSMC_Bank4_PCCARD*/
834  else
835  {
836  tmpsr = FSMC_Bank4->SR4;
837  }
838 
839  /* Get the flag status */
840  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
841  {
842  bitstatus = SET;
843  }
844  else
845  {
846  bitstatus = RESET;
847  }
848  /* Return the flag status */
849  return bitstatus;
850 }
851 
866 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
867 {
868  /* Check the parameters */
870  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
871 
872  if(FSMC_Bank == FSMC_Bank2_NAND)
873  {
874  FSMC_Bank2->SR2 &= ~FSMC_FLAG;
875  }
876  else if(FSMC_Bank == FSMC_Bank3_NAND)
877  {
878  FSMC_Bank3->SR3 &= ~FSMC_FLAG;
879  }
880  /* FSMC_Bank4_PCCARD*/
881  else
882  {
883  FSMC_Bank4->SR4 &= ~FSMC_FLAG;
884  }
885 }
886 
901 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
902 {
903  ITStatus bitstatus = RESET;
904  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
905 
906  /* Check the parameters */
907  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
908  assert_param(IS_FSMC_GET_IT(FSMC_IT));
909 
910  if(FSMC_Bank == FSMC_Bank2_NAND)
911  {
912  tmpsr = FSMC_Bank2->SR2;
913  }
914  else if(FSMC_Bank == FSMC_Bank3_NAND)
915  {
916  tmpsr = FSMC_Bank3->SR3;
917  }
918  /* FSMC_Bank4_PCCARD*/
919  else
920  {
921  tmpsr = FSMC_Bank4->SR4;
922  }
923 
924  itstatus = tmpsr & FSMC_IT;
925 
926  itenable = tmpsr & (FSMC_IT >> 3);
927  if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
928  {
929  bitstatus = SET;
930  }
931  else
932  {
933  bitstatus = RESET;
934  }
935  return bitstatus;
936 }
937 
952 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
953 {
954  /* Check the parameters */
955  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
956  assert_param(IS_FSMC_IT(FSMC_IT));
957 
958  if(FSMC_Bank == FSMC_Bank2_NAND)
959  {
960  FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
961  }
962  else if(FSMC_Bank == FSMC_Bank3_NAND)
963  {
964  FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
965  }
966  /* FSMC_Bank4_PCCARD*/
967  else
968  {
969  FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
970  }
971 }
972 
989 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
De-initializes the FSMC NOR/SRAM Banks registers to their default reset values.
#define IS_FSMC_DATA_LATENCY(LATENCY)
FlagStatus
Definition: stm32f4xx.h:706
#define IS_FSMC_MUX(MUX)
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_IOSpaceTimingStruct
#define IS_FSMC_WAIT_TIME(TIME)
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
void FSMC_PCCARDCmd(FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
#define FSMC_WrapMode_Disable
#define FSMC_Bank4
Definition: stm32f10x.h:1452
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
#define FSMC_Bank3
Definition: stm32f10x.h:1451
FunctionalState
Definition: stm32f4xx.h:708
#define IS_FSMC_HOLD_TIME(TIME)
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStru...
#define FSMC_DataAddressMux_Enable
#define FSMC_MemoryType_NOR
#define FSMC_Bank1
Definition: stm32f10x.h:1448
#define IS_FSMC_WRITE_OPERATION(OPERATION)
#define IS_FSMC_CLEAR_FLAG(FLAG)
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
#define IS_FSMC_DATASETUP_TIME(TIME)
#define BCR_MBKEN_SET
#define IS_FSMC_WRITE_BURST(BURST)
#define FSMC_AsynchronousWait_Disable
#define BCR_FACCEN_SET
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
#define IS_FSMC_TCLR_TIME(TIME)
FSMC NOR/SRAM Init structure definition.
#define IS_FSMC_GET_FLAG(FLAG)
#define IS_FSMC_MEMORY_WIDTH(WIDTH)
FSMC_NORSRAMTimingInitTypeDef * FSMC_WriteTimingStruct
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
void assert_param(int val)
#define IS_FSMC_HIZ_TIME(TIME)
#define PCR_ECCEN_RESET
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
#define IS_FSMC_ASYNWAIT(STATE)
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE)
#define IS_FSMC_WRAP_MODE(MODE)
#define FSMC_Waitfeature_Disable
#define FSMC_ExtendedMode_Enable
FSMC NAND Init structure definition.
Definition: stm32f4xx.h:706
#define IS_FSMC_ACCESS_MODE(MODE)
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
enum FlagStatus ITStatus
#define IS_FSMC_IT_BANK(BANK)
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
#define IS_FSMC_TURNAROUND_TIME(TIME)
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
#define IS_FSMC_WAIT_FEATURE(FEATURE)
#define IS_FSMC_WAIT_POLARITY(POLARITY)
#define IS_FSMC_BURSTMODE(STATE)
FSMC PCCARD Init structure definition.
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
#define FSMC_ECCPageSize_256Bytes
#define FSMC_Bank2
Definition: stm32f10x.h:1450
#define IS_FSMC_IT(IT)
FSMC_NORSRAMTimingInitTypeDef * FSMC_ReadWriteTimingStruct
#define FSMC_ECC_Disable
#define FSMC_Bank1_NORSRAM1
#define FSMC_ExtendedMode_Disable
#define FSMC_WaitSignalPolarity_Low
#define FSMC_WriteOperation_Enable
#define FSMC_MemoryType_SRAM
#define FSMC_WaitSignalActive_BeforeWaitState
#define IS_FSMC_ECC_STATE(STATE)
#define IS_FSMC_NORSRAM_BANK(BANK)
#define PCR_ECCEN_SET
#define IS_FSMC_GETFLAG_BANK(BANK)
#define FSMC_MemoryDataWidth_16b
This file contains all the functions prototypes for the FSMC firmware library.
#define FSMC_WriteBurst_Disable
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME)
#define FSMC_AccessMode_A
#define FSMC_WaitSignal_Enable
#define FSMC_Bank3_NAND
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC&#39;s pending flags.
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
De-initializes the FSMC NAND Banks registers to their default reset values.
#define FSMC_Bank2_NAND
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
#define IS_FSMC_TAR_TIME(TIME)
#define FSMC_BurstAccessMode_Disable
#define IS_FSMC_WAITE_SIGNAL(SIGNAL)
#define PCR_PBKEN_RESET
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC&#39;s interrupt pending bits.
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME)
#define FSMC_Bank1E
Definition: stm32f10x.h:1449
#define BCR_MBKEN_RESET
#define IS_FSMC_EXTENDED_MODE(MODE)
#define IS_FSMC_NAND_BANK(BANK)
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
Returns the error correction code register value.
#define IS_FSMC_MEMORY(MEMORY)
#define IS_FSMC_CLK_DIV(DIV)
#define IS_FSMC_SETUP_TIME(TIME)
void FSMC_PCCARDDeInit(void)
De-initializes the FSMC PCCARD Bank registers to their default reset values.
#define IS_FSMC_GET_IT(IT)
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.
#define PCR_MEMORYTYPE_NAND
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
#define PCR_PBKEN_SET
#define IS_FSMC_ECCPAGE_SIZE(SIZE)
#define FSMC_MemoryDataWidth_8b


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19