stm32f4xx_fsmc.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F4xx_FSMC_H
31 #define __STM32F4xx_FSMC_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
53 typedef struct
54 {
65  uint32_t FSMC_DataSetupTime;
75  uint32_t FSMC_CLKDivision;
79  uint32_t FSMC_DataLatency;
87  uint32_t FSMC_AccessMode;
90 
94 typedef struct
95 {
96  uint32_t FSMC_Bank;
103  uint32_t FSMC_MemoryType;
122  uint32_t FSMC_WrapMode;
134  uint32_t FSMC_WaitSignal;
138  uint32_t FSMC_ExtendedMode;
141  uint32_t FSMC_WriteBurst;
148 
152 typedef struct
153 {
154  uint32_t FSMC_SetupTime;
173  uint32_t FSMC_HiZSetupTime;
179 
183 typedef struct
184 {
185  uint32_t FSMC_Bank;
188  uint32_t FSMC_Waitfeature;
194  uint32_t FSMC_ECC;
197  uint32_t FSMC_ECCPageSize;
204  uint32_t FSMC_TARSetupTime;
212 
217 typedef struct
218 {
219  uint32_t FSMC_Waitfeature;
226  uint32_t FSMC_TARSetupTime;
237 
238 /* Exported constants --------------------------------------------------------*/
239 
247 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
248 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
249 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
250 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
251 
258 #define FSMC_Bank2_NAND ((uint32_t)0x00000010)
259 #define FSMC_Bank3_NAND ((uint32_t)0x00000100)
260 
267 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
268 
272 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
273  ((BANK) == FSMC_Bank1_NORSRAM2) || \
274  ((BANK) == FSMC_Bank1_NORSRAM3) || \
275  ((BANK) == FSMC_Bank1_NORSRAM4))
276 
277 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
278  ((BANK) == FSMC_Bank3_NAND))
279 
280 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
281  ((BANK) == FSMC_Bank3_NAND) || \
282  ((BANK) == FSMC_Bank4_PCCARD))
283 
284 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
285  ((BANK) == FSMC_Bank3_NAND) || \
286  ((BANK) == FSMC_Bank4_PCCARD))
287 
296 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
297 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
298 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
299  ((MUX) == FSMC_DataAddressMux_Enable))
300 
308 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
309 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
310 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
311 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
312  ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
313  ((MEMORY) == FSMC_MemoryType_NOR))
314 
322 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
323 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
324 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
325  ((WIDTH) == FSMC_MemoryDataWidth_16b))
326 
334 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
335 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
336 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
337  ((STATE) == FSMC_BurstAccessMode_Enable))
338 
345 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
346 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
347 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
348  ((STATE) == FSMC_AsynchronousWait_Enable))
349 
356 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
357 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
358 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
359  ((POLARITY) == FSMC_WaitSignalPolarity_High))
360 
367 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
368 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
369 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
370  ((MODE) == FSMC_WrapMode_Enable))
371 
378 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
379 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
380 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
381  ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
382 
389 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
390 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
391 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
392  ((OPERATION) == FSMC_WriteOperation_Enable))
393 
400 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
401 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
402 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
403  ((SIGNAL) == FSMC_WaitSignal_Enable))
404 
411 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
412 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
413 
414 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
415  ((MODE) == FSMC_ExtendedMode_Enable))
416 
424 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
425 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
426 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
427  ((BURST) == FSMC_WriteBurst_Enable))
428 
435 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
436 
443 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
444 
451 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
452 
459 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
460 
467 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
468 
475 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
476 
483 #define FSMC_AccessMode_A ((uint32_t)0x00000000)
484 #define FSMC_AccessMode_B ((uint32_t)0x10000000)
485 #define FSMC_AccessMode_C ((uint32_t)0x20000000)
486 #define FSMC_AccessMode_D ((uint32_t)0x30000000)
487 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
488  ((MODE) == FSMC_AccessMode_B) || \
489  ((MODE) == FSMC_AccessMode_C) || \
490  ((MODE) == FSMC_AccessMode_D))
491 
506 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
507 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
508 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
509  ((FEATURE) == FSMC_Waitfeature_Enable))
510 
518 #define FSMC_ECC_Disable ((uint32_t)0x00000000)
519 #define FSMC_ECC_Enable ((uint32_t)0x00000040)
520 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
521  ((STATE) == FSMC_ECC_Enable))
522 
529 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
530 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
531 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
532 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
533 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
534 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
535 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
536  ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
537  ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
538  ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
539  ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
540  ((SIZE) == FSMC_ECCPageSize_8192Bytes))
541 
548 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
549 
556 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
557 
564 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
565 
572 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
573 
580 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
581 
588 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
589 
596 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
597 #define FSMC_IT_Level ((uint32_t)0x00000010)
598 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
599 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
600 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
601  ((IT) == FSMC_IT_Level) || \
602  ((IT) == FSMC_IT_FallingEdge))
603 
610 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
611 #define FSMC_FLAG_Level ((uint32_t)0x00000002)
612 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
613 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
614 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
615  ((FLAG) == FSMC_FLAG_Level) || \
616  ((FLAG) == FSMC_FLAG_FallingEdge) || \
617  ((FLAG) == FSMC_FLAG_FEMPT))
618 
619 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
620 
632 /* Exported macro ------------------------------------------------------------*/
633 /* Exported functions --------------------------------------------------------*/
634 
635 /* NOR/SRAM Controller functions **********************************************/
636 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
637 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
638 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
639 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
640 
641 /* NAND Controller functions **************************************************/
642 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
643 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
644 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
645 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
646 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
647 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
648 
649 /* PCCARD Controller functions ************************************************/
650 void FSMC_PCCARDDeInit(void);
651 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
652 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
653 void FSMC_PCCARDCmd(FunctionalState NewState);
654 
655 /* Interrupts and flags management functions **********************************/
656 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
657 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
658 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
659 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
660 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
661 
662 #ifdef __cplusplus
663 }
664 #endif
665 
666 #endif /*__STM32F4xx_FSMC_H */
667 
675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
FlagStatus
Definition: stm32f4xx.h:706
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_IOSpaceTimingStruct
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStru...
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
FunctionalState
Definition: stm32f4xx.h:708
Timing parameters For NOR/SRAM Banks.
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC&#39;s pending flags.
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
FSMC NOR/SRAM Init structure definition.
FSMC_NORSRAMTimingInitTypeDef * FSMC_WriteTimingStruct
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
FSMC NAND Init structure definition.
Timing parameters For FSMC NAND and PCCARD Banks.
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
De-initializes the FSMC NOR/SRAM Banks registers to their default reset values.
enum FlagStatus ITStatus
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
void FSMC_PCCARDDeInit(void)
De-initializes the FSMC PCCARD Bank registers to their default reset values.
void FSMC_PCCARDCmd(FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC&#39;s interrupt pending bits.
FSMC PCCARD Init structure definition.
FSMC_NORSRAMTimingInitTypeDef * FSMC_ReadWriteTimingStruct
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
Returns the error correction code register value.
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
De-initializes the FSMC NAND Banks registers to their default reset values.
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19