stm32f30x_syscfg.c
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1 
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f30x_syscfg.h"
50 
60 /* Private typedef -----------------------------------------------------------*/
61 /* Private define ------------------------------------------------------------*/
62 /* Reset value od SYSCFG_CFGR1 register */
63 #define CFGR1_CLEAR_MASK ((uint32_t)0x7C000000)
64 
65 /* ------------ SYSCFG registers bit address in the alias region -------------*/
66 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
67 
68 /* --- CFGR1 Register ---*/
69 /* Alias word address of USB_IT_RMP bit */
70 #define CFGR1_OFFSET (SYSCFG_OFFSET + 0x00)
71 #define USBITRMP_BitNumber 0x05
72 #define CFGR1_USBITRMP_BB (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4))
73 
74 /* --- CFGR2 Register ---*/
75 /* Alias word address of BYP_ADDR_PAR bit */
76 #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
77 #define BYPADDRPAR_BitNumber 0x04
78 #define CFGR1_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
79 
80 /* Private macro -------------------------------------------------------------*/
81 /* Private variables ---------------------------------------------------------*/
82 /* Private function prototypes -----------------------------------------------*/
83 /* Private functions ---------------------------------------------------------*/
84 
108 void SYSCFG_DeInit(void)
109 {
110  /* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
111  SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
112  /* Set FPU Interrupt Enable bits to default value */
113  SYSCFG->CFGR1 |= 0x7C000000;
114  /* Reset RAM Write protection bits to default value */
115  SYSCFG->RCR = 0x00000000;
116  /* Set EXTICRx registers to reset value */
117  SYSCFG->EXTICR[0] = 0;
118  SYSCFG->EXTICR[1] = 0;
119  SYSCFG->EXTICR[2] = 0;
120  SYSCFG->EXTICR[3] = 0;
121  /* Set CFGR2 register to reset value */
122  SYSCFG->CFGR2 = 0;
123  /* Set CFGR3 register to reset value */
124  SYSCFG->CFGR3 = 0;
125 }
126 
136 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
137 {
138  uint32_t tmpcfgr1 = 0;
139 
140  /* Check the parameter */
141  assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
142 
143  /* Get CFGR1 register value */
144  tmpcfgr1 = SYSCFG->CFGR1;
145 
146  /* Clear MEM_MODE bits */
147  tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
148 
149  /* Set the new MEM_MODE bits value */
150  tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap;
151 
152  /* Set CFGR1 register with the new memory remap configuration */
153  SYSCFG->CFGR1 = tmpcfgr1;
154 }
155 
192 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
193 {
194  /* Check the parameters */
195  assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
197 
198  if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000)
199  {
200  if (NewState != DISABLE)
201  {
202  /* Remap the DMA channel */
203  SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
204  }
205  else
206  {
207  /* use the default DMA channel mapping */
208  SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
209  }
210  }
211  else
212  {
213  if (NewState != DISABLE)
214  {
215  /* Remap the DMA channel */
216  SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap;
217  }
218  else
219  {
220  /* use the default DMA channel mapping */
221  SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap);
222  }
223  }
224 }
225 
240 void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
241 {
242  /* Check the parameters */
243  assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap));
245 
246  if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000)
247  {
248  if (NewState != DISABLE)
249  {
250  /* Remap the trigger */
251  SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap;
252  }
253  else
254  {
255  /* Use the default trigger mapping */
256  SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap);
257  }
258  }
259  else
260  {
261  if (NewState != DISABLE)
262  {
263  /* Remap the trigger */
264  SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap;
265  }
266  else
267  {
268  /* Use the default trigger mapping */
269  SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap);
270  }
271  }
272 }
273 
286 void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
287 {
288  /* Check the parameter */
289  assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap));
290 
291  /* Reset the encoder mode remapping bits */
292  SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE);
293 
294  /* Set the selected configuration */
295  SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap);
296 }
297 
313 {
314  /* Check the parameter */
316 
317  /* Remap the USB interupt lines */
318  *(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState;
319 }
320 
344 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
345 {
346  /* Check the parameters */
347  assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
349 
350  if (NewState != DISABLE)
351  {
352  /* Enable fast mode plus driving capability for selected I2C pin */
353  SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
354  }
355  else
356  {
357  /* Disable fast mode plus driving capability for selected I2C pin */
358  SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
359  }
360 }
361 
376 void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)
377 {
378  /* Check the parameters */
380  assert_param(IS_SYSCFG_IT(SYSCFG_IT));
381 
382  if (NewState != DISABLE)
383  {
384  /* Enable the selected SYSCFG interrupts */
385  SYSCFG->CFGR1 |= SYSCFG_IT;
386  }
387  else
388  {
389  /* Disable the selected SYSCFG interrupts */
390  SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
391  }
392 }
393 
402 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
403 {
404  uint32_t tmp = 0x00;
405 
406  /* Check the parameters */
407  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
408  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
409 
410  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
411  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
412  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
413 }
414 
426 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
427 {
428  /* Check the parameter */
429  assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
430 
431  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
432 }
433 
442 {
443  /* Disable the adddress parity check on RAM */
444  *(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001;
445 }
446 
454 void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
455 {
456  /* Check the parameter */
457  assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP));
458 
459  /* Enable the write-protection on the selected ICODE SRAM page */
460  SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP;
461 }
462 
470 #ifdef __GNUC__
471 # pragma GCC diagnostic push
472 # pragma GCC diagnostic ignored "-Wunused-parameter"
473 #endif
474 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
475 {
476  FlagStatus bitstatus = RESET;
477 
478  /* Check the parameter */
479  assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
480 
481  /* Check the status of the specified SPI flag */
482  if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
483  {
484  /* SYSCFG_Flag is set */
485  bitstatus = SET;
486  }
487  else
488  {
489  /* SYSCFG_Flag is reset */
490  bitstatus = RESET;
491  }
492  /* Return the SYSCFG_Flag status */
493  return bitstatus;
494 }
495 #ifdef __GNUC__
496 # pragma GCC diagnostic pop
497 #endif
498 
506 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
507 {
508  /* Check the parameter */
509  assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
510 
511  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
512 }
513 
529 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
530 
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
Checks whether the specified SYSCFG flag is set or not.
FlagStatus
Definition: stm32f4xx.h:706
#define IS_SYSCFG_IT(IT)
void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)
Enables or disables the selected SYSCFG interrupts.
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
Configures the I2C fast mode plus driving capability.
FunctionalState
Definition: stm32f4xx.h:708
#define IS_SYSCFG_PAGE(PAGE)
#define IS_EXTI_PIN_SOURCE(PINSOURCE)
void assert_param(int val)
void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
Configures the remapping capabilities of encoder mode. @ note This feature implement the so-called M/...
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
Connects the selected parameter to the break input of TIM1.
#define IS_SYSCFG_DMA_REMAP(REMAP)
void SYSCFG_BypassParityCheckDisable(void)
Disables the parity check on RAM.
#define CFGR1_BYPADDRPAR_BB
void SYSCFG_DeInit(void)
Deinitializes the SYSCFG registers to their default reset values.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define IS_SYSCFG_ENCODER_REMAP(REMAP)
#define IS_SYSCFG_TRIGGER_REMAP(REMAP)
Definition: stm32f4xx.h:706
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
Configures the memory mapping at address 0x00000000.
#define SYSCFG
Definition: stm32f4xx.h:2089
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
Clears the selected SYSCFG flag.
#define __IO
Definition: core_cm0.h:198
#define IS_EXTI_PORT_SOURCE(PORTSOURCE)
This file contains all the functions prototypes for the SYSCFG firmware library.
#define IS_SYSCFG_LOCK_CONFIG(CONFIG)
#define IS_SYSCFG_I2C_FMP(PIN)
void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
Enables the ICODE SRAM write protection.
#define IS_SYSCFG_MEMORY_REMAP(REMAP)
#define CFGR1_USBITRMP_BB
void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
Configures the remapping capabilities of DAC/TIM triggers.
#define IS_SYSCFG_FLAG(FLAG)
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
Selects the GPIO pin used as EXTI Line.
void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState)
Remaps the USB interrupt lines.
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
Configures the DMA channels remapping.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19