stm32f10x_fsmc.c
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1 
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x_fsmc.h"
24 #include "stm32f10x_rcc.h"
25 
46 /* --------------------- FSMC registers bit mask ---------------------------- */
47 
48 /* FSMC BCRx Mask */
49 #define BCR_MBKEN_Set ((uint32_t)0x00000001)
50 #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
51 #define BCR_FACCEN_Set ((uint32_t)0x00000040)
52 
53 /* FSMC PCRx Mask */
54 #define PCR_PBKEN_Set ((uint32_t)0x00000004)
55 #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
56 #define PCR_ECCEN_Set ((uint32_t)0x00000040)
57 #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
58 #define PCR_MemoryType_NAND ((uint32_t)0x00000008)
59 
102 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
103 {
104  /* Check the parameter */
106 
107  /* FSMC_Bank1_NORSRAM1 */
108  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
109  {
110  FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
111  }
112  /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
113  else
114  {
115  FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
116  }
117  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
118  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
119 }
120 
129 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
130 {
131  /* Check the parameter */
132  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
133 
134  if(FSMC_Bank == FSMC_Bank2_NAND)
135  {
136  /* Set the FSMC_Bank2 registers to their reset values */
137  FSMC_Bank2->PCR2 = 0x00000018;
138  FSMC_Bank2->SR2 = 0x00000040;
139  FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
140  FSMC_Bank2->PATT2 = 0xFCFCFCFC;
141  }
142  /* FSMC_Bank3_NAND */
143  else
144  {
145  /* Set the FSMC_Bank3 registers to their reset values */
146  FSMC_Bank3->PCR3 = 0x00000018;
147  FSMC_Bank3->SR3 = 0x00000040;
148  FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
149  FSMC_Bank3->PATT3 = 0xFCFCFCFC;
150  }
151 }
152 
159 {
160  /* Set the FSMC_Bank4 registers to their reset values */
161  FSMC_Bank4->PCR4 = 0x00000018;
162  FSMC_Bank4->SR4 = 0x00000000;
163  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
164  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
165  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
166 }
167 
176 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
177 {
178  /* Check the parameters */
179  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
180  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
181  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
182  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
183  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
184  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
186  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
188  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
189  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
190  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
191  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
199 
200  /* Bank1 NOR/SRAM control register configuration */
201  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
202  (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
203  FSMC_NORSRAMInitStruct->FSMC_MemoryType |
204  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
205  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
206  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
207  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
208  FSMC_NORSRAMInitStruct->FSMC_WrapMode |
209  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
210  FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
211  FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
212  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
213  FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
214 
215  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
216  {
217  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
218  }
219 
220  /* Bank1 NOR/SRAM timing register configuration */
221  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
222  (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
223  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
224  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
225  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
226  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
227  (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
228  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
229 
230 
231  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
232  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
233  {
240  FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
241  (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
242  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
243  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
244  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
245  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
246  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
247  }
248  else
249  {
250  FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
251  }
252 }
253 
262 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
263 {
264  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
265 
266  /* Check the parameters */
267  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
268  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
270  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
271  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
272  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
273  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
282 
283  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
284  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
286  FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
287  FSMC_NANDInitStruct->FSMC_ECC |
288  FSMC_NANDInitStruct->FSMC_ECCPageSize |
289  (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
290  (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
291 
292  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
293  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
294  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
295  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
296  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
297 
298  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
299  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
300  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
301  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
302  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
303 
304  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
305  {
306  /* FSMC_Bank2_NAND registers configuration */
307  FSMC_Bank2->PCR2 = tmppcr;
308  FSMC_Bank2->PMEM2 = tmppmem;
309  FSMC_Bank2->PATT2 = tmppatt;
310  }
311  else
312  {
313  /* FSMC_Bank3_NAND registers configuration */
314  FSMC_Bank3->PCR3 = tmppcr;
315  FSMC_Bank3->PMEM3 = tmppmem;
316  FSMC_Bank3->PATT3 = tmppatt;
317  }
318 }
319 
328 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
329 {
330  /* Check the parameters */
331  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
332  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
333  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
334 
339 
348 
349  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
350  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
352  (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
353  (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
354 
355  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
356  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
357  (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
358  (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
359  (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
360 
361  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
362  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
363  (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
364  (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
365  (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
366 
367  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
368  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
369  (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
370  (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
371  (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
372 }
373 
380 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
381 {
382  /* Reset NOR/SRAM Init structure parameters values */
383  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
384  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
385  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
386  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
387  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
388  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
389  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
390  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
392  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
393  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
394  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
395  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
396  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
397  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
398  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
399  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
400  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
401  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
403  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
404  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
405  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
406  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
407  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
408  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
409  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
410 }
411 
418 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
419 {
420  /* Reset NAND Init structure parameters values */
421  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
422  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
423  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
424  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
425  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
426  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
427  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
428  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
429  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
430  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
431  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
432  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
433  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
434  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
435  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
436 }
437 
444 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
445 {
446  /* Reset PCCARD Init structure parameters values */
447  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
448  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
449  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
450  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
451  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
452  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
453  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
454  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
455  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
456  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
457  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
458  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
459  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
460  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
461  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
462 }
463 
475 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
476 {
479 
480  if (NewState != DISABLE)
481  {
482  /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
483  FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
484  }
485  else
486  {
487  /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
488  FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
489  }
490 }
491 
501 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
502 {
503  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
505 
506  if (NewState != DISABLE)
507  {
508  /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
509  if(FSMC_Bank == FSMC_Bank2_NAND)
510  {
511  FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
512  }
513  else
514  {
515  FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
516  }
517  }
518  else
519  {
520  /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
521  if(FSMC_Bank == FSMC_Bank2_NAND)
522  {
523  FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
524  }
525  else
526  {
527  FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
528  }
529  }
530 }
531 
539 {
541 
542  if (NewState != DISABLE)
543  {
544  /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
545  FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
546  }
547  else
548  {
549  /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
550  FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
551  }
552 }
553 
564 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
565 {
566  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
568 
569  if (NewState != DISABLE)
570  {
571  /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
572  if(FSMC_Bank == FSMC_Bank2_NAND)
573  {
574  FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
575  }
576  else
577  {
578  FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
579  }
580  }
581  else
582  {
583  /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
584  if(FSMC_Bank == FSMC_Bank2_NAND)
585  {
586  FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
587  }
588  else
589  {
590  FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
591  }
592  }
593 }
594 
603 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
604 {
605  uint32_t eccval = 0x00000000;
606 
607  if(FSMC_Bank == FSMC_Bank2_NAND)
608  {
609  /* Get the ECCR2 register value */
610  eccval = FSMC_Bank2->ECCR2;
611  }
612  else
613  {
614  /* Get the ECCR3 register value */
615  eccval = FSMC_Bank3->ECCR3;
616  }
617  /* Return the error correction code value */
618  return(eccval);
619 }
620 
637 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
638 {
639  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
640  assert_param(IS_FSMC_IT(FSMC_IT));
642 
643  if (NewState != DISABLE)
644  {
645  /* Enable the selected FSMC_Bank2 interrupts */
646  if(FSMC_Bank == FSMC_Bank2_NAND)
647  {
648  FSMC_Bank2->SR2 |= FSMC_IT;
649  }
650  /* Enable the selected FSMC_Bank3 interrupts */
651  else if (FSMC_Bank == FSMC_Bank3_NAND)
652  {
653  FSMC_Bank3->SR3 |= FSMC_IT;
654  }
655  /* Enable the selected FSMC_Bank4 interrupts */
656  else
657  {
658  FSMC_Bank4->SR4 |= FSMC_IT;
659  }
660  }
661  else
662  {
663  /* Disable the selected FSMC_Bank2 interrupts */
664  if(FSMC_Bank == FSMC_Bank2_NAND)
665  {
666 
667  FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
668  }
669  /* Disable the selected FSMC_Bank3 interrupts */
670  else if (FSMC_Bank == FSMC_Bank3_NAND)
671  {
672  FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
673  }
674  /* Disable the selected FSMC_Bank4 interrupts */
675  else
676  {
677  FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
678  }
679  }
680 }
681 
697 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
698 {
699  FlagStatus bitstatus = RESET;
700  uint32_t tmpsr = 0x00000000;
701 
702  /* Check the parameters */
704  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
705 
706  if(FSMC_Bank == FSMC_Bank2_NAND)
707  {
708  tmpsr = FSMC_Bank2->SR2;
709  }
710  else if(FSMC_Bank == FSMC_Bank3_NAND)
711  {
712  tmpsr = FSMC_Bank3->SR3;
713  }
714  /* FSMC_Bank4_PCCARD*/
715  else
716  {
717  tmpsr = FSMC_Bank4->SR4;
718  }
719 
720  /* Get the flag status */
721  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
722  {
723  bitstatus = SET;
724  }
725  else
726  {
727  bitstatus = RESET;
728  }
729  /* Return the flag status */
730  return bitstatus;
731 }
732 
747 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
748 {
749  /* Check the parameters */
751  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
752 
753  if(FSMC_Bank == FSMC_Bank2_NAND)
754  {
755  FSMC_Bank2->SR2 &= ~FSMC_FLAG;
756  }
757  else if(FSMC_Bank == FSMC_Bank3_NAND)
758  {
759  FSMC_Bank3->SR3 &= ~FSMC_FLAG;
760  }
761  /* FSMC_Bank4_PCCARD*/
762  else
763  {
764  FSMC_Bank4->SR4 &= ~FSMC_FLAG;
765  }
766 }
767 
782 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
783 {
784  ITStatus bitstatus = RESET;
785  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
786 
787  /* Check the parameters */
788  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
789  assert_param(IS_FSMC_GET_IT(FSMC_IT));
790 
791  if(FSMC_Bank == FSMC_Bank2_NAND)
792  {
793  tmpsr = FSMC_Bank2->SR2;
794  }
795  else if(FSMC_Bank == FSMC_Bank3_NAND)
796  {
797  tmpsr = FSMC_Bank3->SR3;
798  }
799  /* FSMC_Bank4_PCCARD*/
800  else
801  {
802  tmpsr = FSMC_Bank4->SR4;
803  }
804 
805  itstatus = tmpsr & FSMC_IT;
806 
807  itenable = tmpsr & (FSMC_IT >> 3);
808  if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
809  {
810  bitstatus = SET;
811  }
812  else
813  {
814  bitstatus = RESET;
815  }
816  return bitstatus;
817 }
818 
833 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
834 {
835  /* Check the parameters */
836  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
837  assert_param(IS_FSMC_IT(FSMC_IT));
838 
839  if(FSMC_Bank == FSMC_Bank2_NAND)
840  {
841  FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
842  }
843  else if(FSMC_Bank == FSMC_Bank3_NAND)
844  {
845  FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
846  }
847  /* FSMC_Bank4_PCCARD*/
848  else
849  {
850  FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
851  }
852 }
853 
866 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
#define IS_FSMC_DATA_LATENCY(LATENCY)
FlagStatus
Definition: stm32f4xx.h:706
#define IS_FSMC_MUX(MUX)
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_IOSpaceTimingStruct
#define IS_FSMC_WAIT_TIME(TIME)
#define FSMC_WrapMode_Disable
#define FSMC_Bank4
Definition: stm32f10x.h:1452
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
#define FSMC_Bank3
Definition: stm32f10x.h:1451
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC&#39;s pending flags.
FunctionalState
Definition: stm32f4xx.h:708
#define IS_FSMC_HOLD_TIME(TIME)
#define FSMC_DataAddressMux_Enable
#define FSMC_MemoryType_NOR
#define FSMC_Bank1
Definition: stm32f10x.h:1448
#define IS_FSMC_WRITE_OPERATION(OPERATION)
#define IS_FSMC_CLEAR_FLAG(FLAG)
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC&#39;s interrupt pending bits.
#define IS_FSMC_DATASETUP_TIME(TIME)
#define IS_FSMC_WRITE_BURST(BURST)
#define FSMC_AsynchronousWait_Disable
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
#define IS_FSMC_TCLR_TIME(TIME)
FSMC NOR/SRAM Init structure definition.
#define IS_FSMC_GET_FLAG(FLAG)
#define IS_FSMC_MEMORY_WIDTH(WIDTH)
FSMC_NORSRAMTimingInitTypeDef * FSMC_WriteTimingStruct
void assert_param(int val)
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
#define IS_FSMC_HIZ_TIME(TIME)
#define IS_FSMC_ASYNWAIT(STATE)
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE)
#define IS_FSMC_WRAP_MODE(MODE)
#define FSMC_Waitfeature_Disable
#define FSMC_ExtendedMode_Enable
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
Returns the error correction code register value.
FSMC NAND Init structure definition.
Definition: stm32f4xx.h:706
#define IS_FSMC_ACCESS_MODE(MODE)
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
enum FlagStatus ITStatus
#define IS_FSMC_IT_BANK(BANK)
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
#define IS_FSMC_TURNAROUND_TIME(TIME)
#define PCR_PBKEN_Reset
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
#define IS_FSMC_WAIT_FEATURE(FEATURE)
#define IS_FSMC_WAIT_POLARITY(POLARITY)
#define IS_FSMC_BURSTMODE(STATE)
FSMC PCCARD Init structure definition.
#define PCR_ECCEN_Reset
#define BCR_MBKEN_Set
#define FSMC_ECCPageSize_256Bytes
#define FSMC_Bank2
Definition: stm32f10x.h:1450
#define IS_FSMC_IT(IT)
FSMC_NORSRAMTimingInitTypeDef * FSMC_ReadWriteTimingStruct
#define FSMC_ECC_Disable
#define FSMC_Bank1_NORSRAM1
#define FSMC_ExtendedMode_Disable
#define FSMC_WaitSignalPolarity_Low
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
#define PCR_ECCEN_Set
#define FSMC_WriteOperation_Enable
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
#define FSMC_MemoryType_SRAM
#define FSMC_WaitSignalActive_BeforeWaitState
This file contains all the functions prototypes for the RCC firmware library.
#define IS_FSMC_ECC_STATE(STATE)
#define IS_FSMC_NORSRAM_BANK(BANK)
#define IS_FSMC_GETFLAG_BANK(BANK)
#define FSMC_MemoryDataWidth_16b
#define PCR_MemoryType_NAND
#define FSMC_WriteBurst_Disable
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
Deinitializes the FSMC NAND Banks registers to their default reset values.
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME)
#define FSMC_AccessMode_A
#define FSMC_WaitSignal_Enable
#define FSMC_Bank3_NAND
void FSMC_PCCARDCmd(FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStru...
void FSMC_PCCARDDeInit(void)
Deinitializes the FSMC PCCARD Bank registers to their default reset values.
#define FSMC_Bank2_NAND
#define IS_FSMC_TAR_TIME(TIME)
#define BCR_FACCEN_Set
#define FSMC_BurstAccessMode_Disable
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
#define IS_FSMC_WAITE_SIGNAL(SIGNAL)
#define PCR_PBKEN_Set
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME)
#define FSMC_Bank1E
Definition: stm32f10x.h:1449
This file contains all the functions prototypes for the FSMC firmware library.
#define IS_FSMC_EXTENDED_MODE(MODE)
#define IS_FSMC_NAND_BANK(BANK)
#define BCR_MBKEN_Reset
#define IS_FSMC_MEMORY(MEMORY)
#define IS_FSMC_CLK_DIV(DIV)
#define IS_FSMC_SETUP_TIME(TIME)
#define IS_FSMC_GET_IT(IT)
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
#define IS_FSMC_ECCPAGE_SIZE(SIZE)
#define FSMC_MemoryDataWidth_8b


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19