drv_gpio.c
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1 /*
2  drv_gpio.c : GPIO support for STM32F103CB
3 
4  Adapted from https://github.com/multiwii/baseflight/blob/master/src/drv_gpio.c
5 
6  This file is part of BreezySTM32.
7 
8  BreezySTM32 is free software: you can redistribute it and/or modify
9  it under the terms of the GNU General Public License as published by
10  the Free Software Foundation, either version 3 of the License, or
11  (at your option) any later version.
12 
13  BreezySTM32 is distributed in the hope that it will be useful,
14  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  GNU General Public License for more details.
17 
18  You should have received a copy of the GNU General Public License
19  along with BreezySTM32. If not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #include <stdint.h>
23 #include <stdbool.h>
24 #include <stdlib.h>
25 #include <stdint.h>
26 #include <math.h>
27 #include <ctype.h>
28 #include <string.h>
29 #include <stdio.h>
30 
31 #include "stm32f10x_conf.h"
32 #include "core_cm3.h"
33 #include "breezyprintf.h"
34 #include "drv_system.h" // timers, delays, etc
35 #include "drv_gpio.h"
36 
37 #define I2C_DEVICE (I2CDEV_2)
38 
39 #define GYRO
40 #define ACC
41 #define BUZZER
42 #define LED0
43 #define LED1
44 #define INVERTER
45 
46 #define I2C_DEVICE (I2CDEV_2)
47 
48 #include "drv_adc.h"
49 #include "drv_i2c.h"
50 #include "drv_pwm.h"
51 #include "drv_spi.h"
52 #include "drv_timer.h"
53 #include "drv_serial.h"
54 #include "drv_uart.h"
55 
56 void gpioInit(GPIO_TypeDef *gpio, gpio_config_t *config)
57 {
58  uint32_t pinpos;
59  for (pinpos = 0; pinpos < 16; pinpos++) {
60  // are we doing this pin?
61  if (config->pin & (0x1 << pinpos)) {
62  // reference CRL or CRH, depending whether pin number is 0..7 or 8..15
63  __IO uint32_t *cr = &gpio->CRL + (pinpos / 8);
64  // mask out extra bits from pinmode, leaving just CNF+MODE
65  uint32_t currentmode = config->mode & 0x0F;
66  // offset to CNF and MODE portions of CRx register
67  uint32_t shift = (pinpos % 8) * 4;
68  // Read out current CRx value
69  uint32_t tmp = *cr;
70  // if we're in output mode, add speed too.
71  if (config->mode & 0x10)
72  currentmode |= config->speed;
73  // Mask out 4 bits
74  tmp &= ~(0xF << shift);
75  // apply current pinmode
76  tmp |= currentmode << shift;
77  *cr = tmp;
78  // Special handling for IPD/IPU
79  if (config->mode == Mode_IPD) {
80  gpio->ODR &= ~(1U << pinpos);
81  } else if (config->mode == Mode_IPU) {
82  gpio->ODR |= (1U << pinpos);
83  }
84  }
85  }
86 }
87 
88 void gpioExtiLineConfig(uint8_t portsrc, uint8_t pinsrc)
89 {
90  uint32_t tmp = 0x00;
91 
92  tmp = ((uint32_t)0x0F) << (0x04 * (pinsrc & (uint8_t)0x03));
93  AFIO->EXTICR[pinsrc >> 0x02] &= ~tmp;
94  AFIO->EXTICR[pinsrc >> 0x02] |= (((uint32_t)portsrc) << (0x04 * (pinsrc & (uint8_t)0x03)));
95 }
96 
97 #define LSB_MASK ((uint16_t)0xFFFF)
98 #define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
99 #define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
100 #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
101 #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
102 
103 void gpioPinRemapConfig(uint32_t remap, bool enable)
104 {
105  uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
106  if ((remap & 0x80000000) == 0x80000000)
107  tmpreg = AFIO->MAPR2;
108  else
109  tmpreg = AFIO->MAPR;
110 
111  tmpmask = (remap & DBGAFR_POSITION_MASK) >> 0x10;
112  tmp = remap & LSB_MASK;
113 
115  tmpreg &= DBGAFR_SWJCFG_MASK;
116  AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
117  } else if ((remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) {
118  tmp1 = ((uint32_t)0x03) << tmpmask;
119  tmpreg &= ~tmp1;
120  tmpreg |= ~DBGAFR_SWJCFG_MASK;
121  } else {
122  tmpreg &= ~(tmp << ((remap >> 0x15) * 0x10));
123  tmpreg |= ~DBGAFR_SWJCFG_MASK;
124  }
125 
126  if (enable)
127  tmpreg |= (tmp << ((remap >> 0x15) * 0x10));
128 
129  if ((remap & 0x80000000) == 0x80000000)
130  AFIO->MAPR2 = tmpreg;
131  else
132  AFIO->MAPR = tmpreg;
133 }
GPIO_Mode mode
Definition: drv_gpio.h:63
#define LSB_MASK
Definition: drv_gpio.c:97
__IO uint32_t ODR
Definition: stm32f4xx.h:1288
GPIO_Speed speed
Definition: drv_gpio.h:64
__IO uint32_t CRL
Definition: stm32f10x.h:1003
#define DBGAFR_LOCATION_MASK
Definition: drv_gpio.c:100
void gpioPinRemapConfig(uint32_t remap, bool enable)
Definition: drv_gpio.c:103
void gpioInit(GPIO_TypeDef *gpio, gpio_config_t *config)
Definition: drv_gpio.c:56
#define DBGAFR_SWJCFG_MASK
Definition: drv_gpio.c:99
uint16_t pin
Definition: drv_gpio.h:62
General Purpose I/O.
Definition: stm32f4xx.h:1281
#define DBGAFR_NUMBITS_MASK
Definition: drv_gpio.c:101
#define __IO
Definition: core_cm0.h:198
#define DBGAFR_POSITION_MASK
Definition: drv_gpio.c:98
void gpioExtiLineConfig(uint8_t portsrc, uint8_t pinsrc)
Definition: drv_gpio.c:88
#define AFIO
Definition: stm32f10x.h:1406


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:18