ssp_11xx.h

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/*
 * @brief LPC11xx SSP Registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */
 
#ifndef __SSP_11XX_H_
#define __SSP_11XX_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef struct {                        
        __IO uint32_t CR0;              
        __IO uint32_t CR1;              
        __IO uint32_t DR;               
        __I  uint32_t SR;               
        __IO uint32_t CPSR;             
        __IO uint32_t IMSC;             
        __I  uint32_t RIS;              
        __I  uint32_t MIS;              
        __O  uint32_t ICR;              
} LPC_SSP_T;
 
#define SSP_CR0_DSS(n)          ((uint32_t) ((n) & 0xF))
 
#define SSP_CR0_FRF_SPI         ((uint32_t) (0 << 4))
 
#define SSP_CR0_FRF_TI          ((uint32_t) (1 << 4))
 
#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))
 
#define SSP_CR0_CPOL_LO     ((uint32_t) (0))
#define SSP_CR0_CPOL_HI     ((uint32_t) (1 << 6))
 
#define SSP_CR0_CPHA_FIRST  ((uint32_t) (0))
#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
 
#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
 
#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
 
#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
 
#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
 
#define SSP_CR1_LBM_EN      ((uint32_t) (1 << 0))
 
#define SSP_CR1_SSP_EN      ((uint32_t) (1 << 1))
 
#define SSP_CR1_SLAVE_EN    ((uint32_t) (1 << 2))
#define SSP_CR1_MASTER_EN   ((uint32_t) (0))
 
#define SSP_CR1_SO_DISABLE  ((uint32_t) (1 << 3))
 
#define SSP_CR1_BITMASK     ((uint32_t) (0x0F))
 
#define SSP_CPSR_BITMASK    ((uint32_t) (0xFF))
 
#define SSP_DR_BITMASK(n)   ((n) & 0xFFFF)
 
#define SSP_SR_BITMASK  ((uint32_t) (0x1F))
 
#define SSP_ICR_BITMASK ((uint32_t) (0x03))
 
typedef enum _SSP_STATUS {
        SSP_STAT_TFE = ((uint32_t)(1 << 0)),
        SSP_STAT_TNF = ((uint32_t)(1 << 1)),
        SSP_STAT_RNE = ((uint32_t)(1 << 2)),
        SSP_STAT_RFF = ((uint32_t)(1 << 3)),
        SSP_STAT_BSY = ((uint32_t)(1 << 4)),
} SSP_STATUS_T;
 
typedef enum _SSP_INTMASK {
        SSP_RORIM = ((uint32_t)(1 << 0)),       
        SSP_RTIM = ((uint32_t)(1 << 1)),
        SSP_RXIM = ((uint32_t)(1 << 2)),
        SSP_TXIM = ((uint32_t)(1 << 3)),
        SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
} SSP_INTMASK_T;
 
typedef enum _SSP_MASKINTSTATUS {
        SSP_RORMIS = ((uint32_t)(1 << 0)),      
        SSP_RTMIS = ((uint32_t)(1 << 1)),       
        SSP_RXMIS = ((uint32_t)(1 << 2)),       
        SSP_TXMIS = ((uint32_t)(1 << 3)),       
        SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} SSP_MASKINTSTATUS_T;
 
typedef enum _SSP_RAWINTSTATUS {
        SSP_RORRIS = ((uint32_t)(1 << 0)),      
        SSP_RTRIS = ((uint32_t)(1 << 1)),       
        SSP_RXRIS = ((uint32_t)(1 << 2)),       
        SSP_TXRIS = ((uint32_t)(1 << 3)),       
        SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} SSP_RAWINTSTATUS_T;
 
typedef enum _SSP_INTCLEAR {
        SSP_RORIC = 0x0,
        SSP_RTIC = 0x1,
        SSP_INT_CLEAR_BITMASK = 0x3,
} SSP_INTCLEAR_T;
 
/*
 * @brief SSP clock format
 */
typedef enum CHIP_SSP_CLOCK_FORMAT {
        SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),               
        SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),              
        SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),              
        SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),              
        SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,
        SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,
        SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,
        SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,
} CHIP_SSP_CLOCK_MODE_T;
 
/*
 * @brief SSP frame format
 */
typedef enum CHIP_SSP_FRAME_FORMAT {
        SSP_FRAMEFORMAT_SPI = (0 << 4),                 
        CHIP_SSP_FRAME_FORMAT_TI = (1u << 4),                   
        SSP_FRAMEFORMAT_MICROWIRE = (2u << 4),  
} CHIP_SSP_FRAME_FORMAT_T;
 
/*
 * @brief Number of bits per frame
 */
typedef enum CHIP_SSP_BITS {
        SSP_BITS_4 = (3u << 0),         
        SSP_BITS_5 = (4u << 0),         
        SSP_BITS_6 = (5u << 0),         
        SSP_BITS_7 = (6u << 0),         
        SSP_BITS_8 = (7u << 0),         
        SSP_BITS_9 = (8u << 0),         
        SSP_BITS_10 = (9u << 0),        
        SSP_BITS_11 = (10u << 0),       
        SSP_BITS_12 = (11u << 0),       
        SSP_BITS_13 = (12u << 0),       
        SSP_BITS_14 = (13u << 0),       
        SSP_BITS_15 = (14u << 0),       
        SSP_BITS_16 = (15u << 0),       
} CHIP_SSP_BITS_T;
 
/*
 * @brief SSP config format
 */
typedef struct SSP_ConfigFormat {
        CHIP_SSP_BITS_T bits;                                   
        CHIP_SSP_CLOCK_MODE_T clockMode;        
        CHIP_SSP_FRAME_FORMAT_T frameFormat;    
} SSP_ConfigFormat;
 
STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
{
        pSSP->CR1 |= SSP_CR1_SSP_EN;
}
 
STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
{
        pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}
 
STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
{
        pSSP->CR1 |= SSP_CR1_LBM_EN;
}
 
STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
{
        pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
}
 
STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, SSP_STATUS_T Stat)
{
        return (pSSP->SR & Stat) ? SET : RESET;
}
 
STATIC INLINE uint32_t Chip_SSP_GetIntStatus(LPC_SSP_T *pSSP)
{
        return pSSP->MIS;
}
 
STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus(LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
{
        return (pSSP->RIS & RawInt) ? SET : RESET;
}
 
STATIC INLINE uint8_t Chip_SSP_GetDataSize(LPC_SSP_T *pSSP)
{
        return SSP_CR0_DSS(pSSP->CR0);
}
 
STATIC INLINE void Chip_SSP_ClearIntPending(LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
{
        pSSP->ICR = IntClear;
}
 
STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
{
        pSSP->IMSC |= SSP_TXIM;
}
 
STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
{
        pSSP->IMSC &= (~SSP_TXIM);
}
 
STATIC INLINE uint16_t Chip_SSP_ReceiveFrame(LPC_SSP_T *pSSP)
{
        return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
}
 
STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
{
        pSSP->DR = SSP_DR_BITMASK(tx_data);
}
 
void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
 
STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
{
        pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
}
 
STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
{
        pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
}
 
/*
 * @brief SSP mode
 */
typedef enum CHIP_SSP_MODE {
        SSP_MODE_MASTER = (0 << 2),     
        SSP_MODE_SLAVE = (1u << 2),     
} CHIP_SSP_MODE_T;
 
/*
 * @brief SPI address
 */
typedef struct {
        uint8_t port;   
        uint8_t pin;    
} SPI_Address_t;
 
/*
 * @brief SSP data setup structure
 */
typedef struct {
        void      *tx_data;     
        uint32_t  tx_cnt;       
        void      *rx_data;     
        uint32_t  rx_cnt;       
        uint32_t  length;       
} Chip_SSP_DATA_SETUP_T;
 
#define SSP_CPHA_FIRST          SSP_CR0_CPHA_FIRST
#define SSP_CPHA_SECOND         SSP_CR0_CPHA_SECOND
 
/* There's no bug here!!!
 * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
 * That means the active clock is in HI state.
 * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
 * high between frames. That means the active clock is in LO state.
 */
#define SSP_CPOL_HI             SSP_CR0_CPOL_LO
#define SSP_CPOL_LO             SSP_CR0_CPOL_HI
 
#define SSP_SLAVE_MODE          SSP_CR1_SLAVE_EN
#define SSP_MASTER_MODE         SSP_CR1_MASTER_EN
 
void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
 
Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
 
Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
 
uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
 
uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
 
uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
 
void Chip_SSP_Init(LPC_SSP_T *pSSP);
 
void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
 
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
 
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
 
#ifdef __cplusplus
}
#endif
 
#endif /* __SSP_11XX_H_ */