chip.h
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1 /*
2  * @brief LPC11xx basic chip inclusion file
3  *
4  * Copyright(C) NXP Semiconductors, 2012
5  * All rights reserved.
6  *
7  * Software that is described herein is for illustrative purposes only
8  * which provides customers with programming information regarding the
9  * LPC products. This software is supplied "AS IS" without any warranties of
10  * any kind, and NXP Semiconductors and its licensor disclaim any and
11  * all warranties, express or implied, including all implied warranties of
12  * merchantability, fitness for a particular purpose and non-infringement of
13  * intellectual property rights. NXP Semiconductors assumes no responsibility
14  * or liability for the use of the software, conveys no license or rights under any
15  * patent, copyright, mask work right, or any other intellectual property rights in
16  * or to any products. NXP Semiconductors reserves the right to make changes
17  * in the software without notification. NXP Semiconductors also makes no
18  * representation or warranty that such application will be suitable for the
19  * specified use without further testing or modification.
20  *
21  * Permission to use, copy, modify, and distribute this software and its
22  * documentation is hereby granted, under NXP Semiconductors' and its
23  * licensor's relevant copyrights in the software, without fee, provided that it
24  * is used in conjunction with NXP Semiconductors microcontrollers. This
25  * copyright, permission, and disclaimer notice must appear in all copies of
26  * this code.
27  */
28 
29 #ifndef __CHIP_H_
30 #define __CHIP_H_
31 
32 #include "lpc_types.h"
33 #include "sys_config.h"
34 #include "cmsis.h"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 #ifndef CORE_M0
41 #error CORE_M0 is not defined for the LPC11xx architecture
42 #error CORE_M0 should be defined as part of your compiler define list
43 #endif
44 
45 #if !defined(ENABLE_UNTESTED_CODE)
46 #if defined(CHIP_LPC110X)
47 #warning The LCP110X code has not been tested with a platform. This code should \
48 build without errors but may not work correctly for the device. To disable this \
49 #warning message, define ENABLE_UNTESTED_CODE.
50 #endif
51 #if defined(CHIP_LPC11XXLV)
52 #warning The LPC11XXLV code has not been tested with a platform. This code should \
53 build without errors but may not work correctly for the device. To disable this \
54 #warning message, define ENABLE_UNTESTED_CODE.
55 #endif
56 #if defined(CHIP_LPC11AXX)
57 #warning The LPC11AXX code has not been tested with a platform. This code should \
58 build without errors but may not work correctly for the device. To disable this \
59 #warning message, define ENABLE_UNTESTED_CODE.
60 #endif
61 #if defined(CHIP_LPC11EXX)
62 #warning The LPC11EXX code has not been tested with a platform. This code should \
63 build without errors but may not work correctly for the device. To disable this \
64 warning message, define ENABLE_UNTESTED_CODE.
65 #endif
66 #endif
67 
68 #if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
69  !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX) && \
70  !defined(CHIP_LPC1125)
71 #error CHIP_LPC110x/CHIP_LPC11XXLV/CHIP_LPC11AXX/CHIP_LPC11CXX/CHIP_LPC11EXX/CHIP_LPC11UXX/CHIP_LPC1125 is not defined!
72 #endif
73 
74 /* Peripheral mapping per device
75  Peripheral Device(s)
76  ---------------------------- -------------------------------------------------------------------------------------------------------------
77  I2C(40000000) CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
78  WDT(40004000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
79  UART0(40008000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
80  UART1(40020000) CHIP_LPC1125
81  UART2(40024000) CHIP_LPC1125
82  USART/SMARTCARD(40008000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
83  TIMER0_16(4000C000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
84  TIMER1_16(40010000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
85  TIMER0_32(40014000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
86  TIMER1_32(40018000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
87  ADC(4001C000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
88  DAC(40024000) CHIP_LPC11AXX
89  ACMP(40028000) CHIP_LPC11AXX
90  PMU(40038000) CHIP_LPC110x/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX CHIP_LPC1125
91  FLASH_CTRL(4003C000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX CHIP_LPC1125
92  FLASH_EEPROM(4003C000) CHIP_LPC11EXX/ CHIP_LPC11AXX
93  SPI0(40040000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX
94  SSP0(40040000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
95  IOCONF(40044000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
96  SYSCON(40048000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
97  GPIOINTS(4004C000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
98  USB(40080000) CHIP_LPC11UXX
99  CCAN(40050000) CHIP_LPC11CXX
100  SPI1(40058000) CHIP_LPC11CXX
101  SSP1(40058000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
102  GPIO_GRP0_INT(4005C000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
103  GPIO_GRP1_INT(40060000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
104  GPIO_PORT(50000000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
105  GPIO_PIO0(50000000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
106  GPIO_PIO1(50010000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
107  GPIO_PIO2(50020000) CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
108  GPIO_PIO3(50030000) CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
109  */
110 
116 #define LPC_I2C_BASE 0x40000000
117 #define LPC_WWDT_BASE 0x40004000
118 #define LPC_USART_BASE 0x40008000
119 #define LPC_TIMER16_0_BASE 0x4000C000
120 #define LPC_TIMER16_1_BASE 0x40010000
121 #define LPC_TIMER32_0_BASE 0x40014000
122 #define LPC_TIMER32_1_BASE 0x40018000
123 #define LPC_ADC_BASE 0x4001C000
124 #define LPC_DAC_BASE 0x40024000
125 #define LPC_ACMP_BASE 0x40028000
126 #define LPC_PMU_BASE 0x40038000
127 #define LPC_FLASH_BASE 0x4003C000
128 #define LPC_SSP0_BASE 0x40040000
129 #define LPC_IOCON_BASE 0x40044000
130 #define LPC_SYSCTL_BASE 0x40048000
131 #define LPC_USB0_BASE 0x40080000
132 #define LPC_CAN0_BASE 0x40050000
133 #define LPC_SSP1_BASE 0x40058000
134 #if defined(CHIP_LPC1125)
135 #define LPC_USART1_BASE 0x40020000
136 #define LPC_USART2_BASE 0x40024000
137 #endif
138 #if defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX)
139 #define LPC_GPIO_PIN_INT_BASE 0x4004C000
140 #define LPC_GPIO_GROUP_INT0_BASE 0x4005C000
141 #define LPC_GPIO_GROUP_INT1_BASE 0x40060000
142 #define LPC_GPIO_PORT_BASE 0x50000000
143 #else
144 #define LPC_GPIO_PORT0_BASE 0x50000000
145 #define LPC_GPIO_PORT1_BASE 0x50010000
146 #if defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC1125)
147 #define LPC_GPIO_PORT2_BASE 0x50020000
148 #define LPC_GPIO_PORT3_BASE 0x50030000
149 #endif /* defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC1125) */
150 #endif /* defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) */
151 #define IAP_ENTRY_LOCATION 0X1FFF1FF1
152 #define LPC_ROM_API_BASE_LOC 0x1FFF1FF8
153 
154 #if !defined(CHIP_LPC110x)
155 #define LPC_I2C ((LPC_I2C_T *) LPC_I2C_BASE)
156 #endif
157 
158 #define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
159 #define LPC_USART ((LPC_USART_T *) LPC_USART_BASE)
160 #define LPC_TIMER16_0 ((LPC_TIMER_T *) LPC_TIMER16_0_BASE)
161 #define LPC_TIMER16_1 ((LPC_TIMER_T *) LPC_TIMER16_1_BASE)
162 #define LPC_TIMER32_0 ((LPC_TIMER_T *) LPC_TIMER32_0_BASE)
163 #define LPC_TIMER32_1 ((LPC_TIMER_T *) LPC_TIMER32_1_BASE)
164 #define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
165 
166 #if defined(CHIP_LPC1125)
167 #define LPC_USART0 LPC_USART
168 #define LPC_USART1 ((LPC_USART_T *) LPC_USART1_BASE)
169 #define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
170 #endif
171 
172 #if defined(CHIP_LPC11AXX)
173 #define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
174 #define LPC_CMP ((LPC_CMP_T *) LPC_ACMP_BASE)
175 #endif
176 
177 #define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
178 #define LPC_FMC ((LPC_FMC_T *) LPC_FLASH_BASE)
179 #define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
180 #define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
181 #define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
182 #if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC1125)
183 #define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
184 #endif
185 #define LPC_USB ((LPC_USB_T *) LPC_USB0_BASE)
186 
187 #if defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX)
188 #define LPC_PININT ((LPC_PIN_INT_T *) LPC_GPIO_PIN_INT_BASE)
189 #define LPC_GPIOGROUP ((LPC_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
190 #define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
191 #else
192 #define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO_PORT0_BASE)
193 #endif
194 
195 #define LPC_ROM_API (*((LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC))
196 
197 
211 extern const uint32_t OscRateIn;
212 
226 extern const uint32_t ExtRateIn;
227 
232 #include "pmu_11xx.h"
233 #include "fmc_11xx.h"
234 #include "sysctl_11xx.h"
235 #include "clock_11xx.h"
236 #include "iocon_11xx.h"
237 #include "timer_11xx.h"
238 #include "uart_11xx.h"
239 #include "wwdt_11xx.h"
240 #include "ssp_11xx.h"
241 #include "romapi_11xx.h"
242 
243 #if !defined(CHIP_LPC1125)
244 /* All LPC1xx devices except the LPC1125 */
245 #include "adc_11xx.h"
246 
247 #else
248 /* LPC1125 has different IP than other LPC11xx devices */
249 #include "adc_1125.h"
250 #endif
251 
252 /* Different GPIO/GPIOGROUP/PININT blocks for parts with similar numbers */
253 #if defined(CHIP_LPC11CXX) || defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC1125)
254 #include "gpio_11xx_2.h"
255 #else
256 #include "gpio_11xx_1.h"
257 #include "gpiogroup_11xx.h"
258 #include "pinint_11xx.h"
259 #endif
260 
261 /* Family specific drivers */
262 #if defined(CHIP_LPC11AXX)
263 #include "acmp_11xx.h"
264 #include "dac_11xx.h"
265 #endif
266 #if !defined(CHIP_LPC110X)
267 #include "i2c_11xx.h"
268 #endif
269 #if defined(CHIP_LPC11CXX)
270 #include "ccand_11xx.h"
271 #endif
272 #if defined(CHIP_LPC11UXX)
273 #include "usbd_11xx.h"
274 #endif
275 
284 extern uint32_t SystemCoreClock;
285 
291 void SystemCoreClockUpdate(void);
292 
299 void Chip_SystemInit(void);
300 
305 #ifdef __cplusplus
306 }
307 #endif
308 
309 #endif /* __CHIP_H_ */
gpiogroup_11xx.h
pinint_11xx.h
SystemCoreClock
uint32_t SystemCoreClock
Current system clock rate, mainly used for sysTick.
Definition: board.cpp:18
gpio_11xx_2.h
wwdt_11xx.h
uart_11xx.h
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Update system core clock rate, should be called if the system has a clock rate change.
uavcan::uint32_t
std::uint32_t uint32_t
Definition: std.hpp:26
timer_11xx.h
ssp_11xx.h
lpc_types.h
adc_11xx.h
iocon_11xx.h
sys_config.h
ExtRateIn
const uint32_t ExtRateIn
Clock rate on the CLKIN pin This value is defined externally to the chip layer and contains the value...
Definition: board.cpp:16
Chip_SystemInit
void Chip_SystemInit(void)
Set up and initialize hardware prior to call to main()
ccand_11xx.h
clock_11xx.h
i2c_11xx.h
pmu_11xx.h
cmsis.h
OscRateIn
const uint32_t OscRateIn
System oscillator rate This value is defined externally to the chip layer and contains the value in H...
Definition: board.cpp:15
sysctl_11xx.h
fmc_11xx.h
romapi_11xx.h

uavcan_communicator
Author(s):
autogenerated on Fri Dec 13 2024 03:10:02