stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c

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/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
 
#ifdef HAL_PWR_MODULE_ENABLED
 
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
 
#if !defined (DUAL_CORE)
#define PVD_MODE_IT              (0x00010000U)
#define PVD_MODE_EVT             (0x00020000U)
#endif /* !defined (DUAL_CORE) */
 
#define PVD_RISING_EDGE          (0x00000001U)
#define PVD_FALLING_EDGE         (0x00000002U)
#define PVD_RISING_FALLING_EDGE  (0x00000003U)
 
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
 
void HAL_PWR_DeInit (void)
{
}
 
void HAL_PWR_EnableBkUpAccess (void)
{
  /* Enable access to RTC and backup registers */
  SET_BIT (PWR->CR1, PWR_CR1_DBP);
}
 
void HAL_PWR_DisableBkUpAccess (void)
{
  /* Disable access to RTC and backup registers */
  CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
}
void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
{
  /* Check the PVD configuration parameter */
  if (sConfigPVD == NULL)
  {
    return;
  }
 
  /* Check the parameters */
  assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
  assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
 
  /* Set PLS[7:5] bits according to PVDLevel value */
  MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
 
  /* Clear previous config */
#if !defined (DUAL_CORE)
  __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
  __HAL_PWR_PVD_EXTI_DISABLE_IT ();
#endif /* !defined (DUAL_CORE) */
 
  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
 
#if !defined (DUAL_CORE)
  /* Interrupt mode configuration */
  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
  {
    __HAL_PWR_PVD_EXTI_ENABLE_IT ();
  }
 
  /* Event mode configuration */
  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
  {
    __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
  }
#endif /* !defined (DUAL_CORE) */
 
  /* Rising edge configuration */
  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
  {
    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
  }
 
  /* Falling edge configuration */
  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
  {
    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
  }
}
 
void HAL_PWR_EnablePVD (void)
{
  /* Enable the power voltage detector */
  SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
}
 
void HAL_PWR_DisablePVD (void)
{
  /* Disable the power voltage detector */
  CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
}
 
void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
{
  /* Check the parameters */
  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
 
  /*
     Enable and Specify the Wake-Up pin polarity and the pull configuration
     for the event detection (rising or falling edge).
  */
  MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
}
 
void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
{
  /* Check the parameters */
  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
 
  /* Disable the wake up pin selected */
  CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
}
 
void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
{
  /* Check the parameters */
  assert_param (IS_PWR_REGULATOR (Regulator));
  assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
 
  /* Clear SLEEPDEEP bit of Cortex System Control Register */
  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 
  /* Select SLEEP mode entry */
  if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
  {
    /* Request Wait For Interrupt */
    __WFI ();
  }
  else
  {
    /* Request Wait For Event */
    __WFE ();
  }
}
 
void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
{
  /* Check the parameters */
  assert_param (IS_PWR_REGULATOR (Regulator));
  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
 
  /* Select the regulator state in STOP mode */
  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
 
  /* Configure the PWR mode for the different Domains */
#if defined (DUAL_CORE)
  /* Check CPU ID */
  if (HAL_GetCurrentCPUID () == CM7_CPUID)
  {
    /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
  }
  else
  {
    /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
  }
#else /* Single core devices */
  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
  CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
 
#if defined (PWR_CPUCR_PDDS_D2)
  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
#endif /* PWR_CPUCR_PDDS_D2 */
#endif /* defined (DUAL_CORE) */
 
  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 
  /* Ensure that all instructions are done before entering STOP mode */
  __DSB ();
  __ISB ();
 
  /* Select STOP mode entry */
  if (STOPEntry == PWR_STOPENTRY_WFI)
  {
    /* Request Wait For Interrupt */
    __WFI ();
  }
  else
  {
    /* Request Wait For Event */
    __WFE ();
  }
 
  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
}
 
void HAL_PWR_EnterSTANDBYMode (void)
{
  /* Configure the PWR mode for the different Domains */
#if defined (DUAL_CORE)
  /* Check CPU ID */
  if (HAL_GetCurrentCPUID () == CM7_CPUID)
  {
    /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
  }
  else
  {
    /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
  }
#else /* Single core devices */
  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
  SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
 
#if defined (PWR_CPUCR_PDDS_D2)
  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
  SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
#endif /* PWR_CPUCR_PDDS_D2 */
#endif /* defined (DUAL_CORE) */
 
  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 
  /* Ensure that all instructions are done before entering STOP mode */
  __DSB ();
  __ISB ();
 
  /* This option is used to ensure that store operations are completed */
#if defined (__CC_ARM)
  __force_stores();
#endif /* defined (__CC_ARM) */
 
  /* Request Wait For Interrupt */
  __WFI ();
}
 
void HAL_PWR_EnableSleepOnExit (void)
{
  /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
  SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
 
void HAL_PWR_DisableSleepOnExit (void)
{
  /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
 
void HAL_PWR_EnableSEVOnPend (void)
{
  /* Set SEVONPEND bit of Cortex-Mx System Control Register */
  SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
 
void HAL_PWR_DisableSEVOnPend (void)
{
  /* Clear SEVONPEND bit of Cortex System Control Register */
  CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
void HAL_PWR_PVD_IRQHandler (void)
{
#if defined (DUAL_CORE)
  /* Check Cortex-Mx ID */
  if (HAL_GetCurrentCPUID () == CM7_CPUID)
  {
    /* Check PWR EXTI D1 flag */
    if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
    {
      /* Clear PWR EXTI D1 pending bit */
      __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
 
      /* PWR PVD interrupt user callback */
      HAL_PWR_PVDCallback ();
    }
  }
  else
  {
    /* Check PWR EXTI D2 flag */
    if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
    {
      /* Clear PWR EXTI D2 pending bit */
      __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
 
      /* PWR PVD interrupt user callback */
      HAL_PWR_PVDCallback ();
    }
  }
#else /* Single core devices */
  /* PVD EXTI line interrupt detected */
  if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
  {
    /* Clear PWR EXTI pending bit */
    __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
 
    /* PWR PVD interrupt user callback */
    HAL_PWR_PVDCallback ();
  }
#endif /* defined (DUAL_CORE) */
}
 
__weak void HAL_PWR_PVDCallback (void)
{
  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_PWR_PVDCallback can be implemented in the user file
  */
}
 
#endif /* HAL_PWR_MODULE_ENABLED */
 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/