stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_DMA_H
22 #define STM32H7xx_HAL_DMA_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
40 
49 typedef struct
50 {
51  uint32_t Request;
54  uint32_t Direction;
58  uint32_t PeriphInc;
61  uint32_t MemInc;
64  uint32_t PeriphDataAlignment;
67  uint32_t MemDataAlignment;
70  uint32_t Mode;
75  uint32_t Priority;
78  uint32_t FIFOMode;
83  uint32_t FIFOThreshold;
86  uint32_t MemBurst;
92  uint32_t PeriphBurst;
97 }DMA_InitTypeDef;
98 
102 typedef enum
103 {
104  HAL_DMA_STATE_RESET = 0x00U,
105  HAL_DMA_STATE_READY = 0x01U,
106  HAL_DMA_STATE_BUSY = 0x02U,
107  HAL_DMA_STATE_ERROR = 0x03U,
108  HAL_DMA_STATE_ABORT = 0x04U,
109 }HAL_DMA_StateTypeDef;
110 
114 typedef enum
115 {
116  HAL_DMA_FULL_TRANSFER = 0x00U,
117  HAL_DMA_HALF_TRANSFER = 0x01U,
118 }HAL_DMA_LevelCompleteTypeDef;
119 
123 typedef enum
124 {
125  HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
126  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
127  HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
128  HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
129  HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
130  HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
131  HAL_DMA_XFER_ALL_CB_ID = 0x06U
132 }HAL_DMA_CallbackIDTypeDef;
133 
137 typedef struct __DMA_HandleTypeDef
138 {
139  void *Instance;
141  DMA_InitTypeDef Init;
143  HAL_LockTypeDef Lock;
145  __IO HAL_DMA_StateTypeDef State;
147  void *Parent;
149  void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);
151  void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
153  void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);
155  void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
157  void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);
159  void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);
161  __IO uint32_t ErrorCode;
163  uint32_t StreamBaseAddress;
165  uint32_t StreamIndex;
167  DMAMUX_Channel_TypeDef *DMAmuxChannel;
169  DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus;
171  uint32_t DMAmuxChannelStatusMask;
174  DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen;
176  DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus;
178  uint32_t DMAmuxRequestGenStatusMask;
180 }DMA_HandleTypeDef;
181 
187 /* Exported constants --------------------------------------------------------*/
188 
198 #define HAL_DMA_ERROR_NONE (0x00000000U)
199 #define HAL_DMA_ERROR_TE (0x00000001U)
200 #define HAL_DMA_ERROR_FE (0x00000002U)
201 #define HAL_DMA_ERROR_DME (0x00000004U)
202 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U)
203 #define HAL_DMA_ERROR_PARAM (0x00000040U)
204 #define HAL_DMA_ERROR_NO_XFER (0x00000080U)
205 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)
206 #define HAL_DMA_ERROR_SYNC (0x00000200U)
207 #define HAL_DMA_ERROR_REQGEN (0x00000400U)
208 #define HAL_DMA_ERROR_BUSY (0x00000800U)
218 /* DMAMUX1 requests */
219 #define DMA_REQUEST_MEM2MEM 0U
221 #define DMA_REQUEST_GENERATOR0 1U
222 #define DMA_REQUEST_GENERATOR1 2U
223 #define DMA_REQUEST_GENERATOR2 3U
224 #define DMA_REQUEST_GENERATOR3 4U
225 #define DMA_REQUEST_GENERATOR4 5U
226 #define DMA_REQUEST_GENERATOR5 6U
227 #define DMA_REQUEST_GENERATOR6 7U
228 #define DMA_REQUEST_GENERATOR7 8U
230 #define DMA_REQUEST_ADC1 9U
231 #define DMA_REQUEST_ADC2 10U
233 #define DMA_REQUEST_TIM1_CH1 11U
234 #define DMA_REQUEST_TIM1_CH2 12U
235 #define DMA_REQUEST_TIM1_CH3 13U
236 #define DMA_REQUEST_TIM1_CH4 14U
237 #define DMA_REQUEST_TIM1_UP 15U
238 #define DMA_REQUEST_TIM1_TRIG 16U
239 #define DMA_REQUEST_TIM1_COM 17U
241 #define DMA_REQUEST_TIM2_CH1 18U
242 #define DMA_REQUEST_TIM2_CH2 19U
243 #define DMA_REQUEST_TIM2_CH3 20U
244 #define DMA_REQUEST_TIM2_CH4 21U
245 #define DMA_REQUEST_TIM2_UP 22U
247 #define DMA_REQUEST_TIM3_CH1 23U
248 #define DMA_REQUEST_TIM3_CH2 24U
249 #define DMA_REQUEST_TIM3_CH3 25U
250 #define DMA_REQUEST_TIM3_CH4 26U
251 #define DMA_REQUEST_TIM3_UP 27U
252 #define DMA_REQUEST_TIM3_TRIG 28U
254 #define DMA_REQUEST_TIM4_CH1 29U
255 #define DMA_REQUEST_TIM4_CH2 30U
256 #define DMA_REQUEST_TIM4_CH3 31U
257 #define DMA_REQUEST_TIM4_UP 32U
259 #define DMA_REQUEST_I2C1_RX 33U
260 #define DMA_REQUEST_I2C1_TX 34U
261 #define DMA_REQUEST_I2C2_RX 35U
262 #define DMA_REQUEST_I2C2_TX 36U
264 #define DMA_REQUEST_SPI1_RX 37U
265 #define DMA_REQUEST_SPI1_TX 38U
266 #define DMA_REQUEST_SPI2_RX 39U
267 #define DMA_REQUEST_SPI2_TX 40U
269 #define DMA_REQUEST_USART1_RX 41U
270 #define DMA_REQUEST_USART1_TX 42U
271 #define DMA_REQUEST_USART2_RX 43U
272 #define DMA_REQUEST_USART2_TX 44U
273 #define DMA_REQUEST_USART3_RX 45U
274 #define DMA_REQUEST_USART3_TX 46U
276 #define DMA_REQUEST_TIM8_CH1 47U
277 #define DMA_REQUEST_TIM8_CH2 48U
278 #define DMA_REQUEST_TIM8_CH3 49U
279 #define DMA_REQUEST_TIM8_CH4 50U
280 #define DMA_REQUEST_TIM8_UP 51U
281 #define DMA_REQUEST_TIM8_TRIG 52U
282 #define DMA_REQUEST_TIM8_COM 53U
284 #define DMA_REQUEST_TIM5_CH1 55U
285 #define DMA_REQUEST_TIM5_CH2 56U
286 #define DMA_REQUEST_TIM5_CH3 57U
287 #define DMA_REQUEST_TIM5_CH4 58U
288 #define DMA_REQUEST_TIM5_UP 59U
289 #define DMA_REQUEST_TIM5_TRIG 60U
291 #define DMA_REQUEST_SPI3_RX 61U
292 #define DMA_REQUEST_SPI3_TX 62U
294 #define DMA_REQUEST_UART4_RX 63U
295 #define DMA_REQUEST_UART4_TX 64U
296 #define DMA_REQUEST_UART5_RX 65U
297 #define DMA_REQUEST_UART5_TX 66U
299 #define DMA_REQUEST_DAC1_CH1 67U
300 #define DMA_REQUEST_DAC1_CH2 68U
302 #define DMA_REQUEST_TIM6_UP 69U
303 #define DMA_REQUEST_TIM7_UP 70U
305 #define DMA_REQUEST_USART6_RX 71U
306 #define DMA_REQUEST_USART6_TX 72U
308 #define DMA_REQUEST_I2C3_RX 73U
309 #define DMA_REQUEST_I2C3_TX 74U
311 #if defined (PSSI)
312 #define DMA_REQUEST_DCMI_PSSI 75U
313 #define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */
314 #else
315 #define DMA_REQUEST_DCMI 75U
316 #endif /* PSSI */
317 
318 #define DMA_REQUEST_CRYP_IN 76U
319 #define DMA_REQUEST_CRYP_OUT 77U
321 #define DMA_REQUEST_HASH_IN 78U
323 #define DMA_REQUEST_UART7_RX 79U
324 #define DMA_REQUEST_UART7_TX 80U
325 #define DMA_REQUEST_UART8_RX 81U
326 #define DMA_REQUEST_UART8_TX 82U
328 #define DMA_REQUEST_SPI4_RX 83U
329 #define DMA_REQUEST_SPI4_TX 84U
330 #define DMA_REQUEST_SPI5_RX 85U
331 #define DMA_REQUEST_SPI5_TX 86U
333 #define DMA_REQUEST_SAI1_A 87U
334 #define DMA_REQUEST_SAI1_B 88U
336 #if defined(SAI2)
337 #define DMA_REQUEST_SAI2_A 89U
338 #define DMA_REQUEST_SAI2_B 90U
339 #endif /* SAI2 */
340 
341 #define DMA_REQUEST_SWPMI_RX 91U
342 #define DMA_REQUEST_SWPMI_TX 92U
344 #define DMA_REQUEST_SPDIF_RX_DT 93U
345 #define DMA_REQUEST_SPDIF_RX_CS 94U
347 #if defined(HRTIM1)
348 #define DMA_REQUEST_HRTIM_MASTER 95U
349 #define DMA_REQUEST_HRTIM_TIMER_A 96U
350 #define DMA_REQUEST_HRTIM_TIMER_B 97U
351 #define DMA_REQUEST_HRTIM_TIMER_C 98U
352 #define DMA_REQUEST_HRTIM_TIMER_D 99U
353 #define DMA_REQUEST_HRTIM_TIMER_E 100U
354 #endif /* HRTIM1 */
355 
356 #define DMA_REQUEST_DFSDM1_FLT0 101U
357 #define DMA_REQUEST_DFSDM1_FLT1 102U
358 #define DMA_REQUEST_DFSDM1_FLT2 103U
359 #define DMA_REQUEST_DFSDM1_FLT3 104U
361 #define DMA_REQUEST_TIM15_CH1 105U
362 #define DMA_REQUEST_TIM15_UP 106U
363 #define DMA_REQUEST_TIM15_TRIG 107U
364 #define DMA_REQUEST_TIM15_COM 108U
366 #define DMA_REQUEST_TIM16_CH1 109U
367 #define DMA_REQUEST_TIM16_UP 110U
369 #define DMA_REQUEST_TIM17_CH1 111U
370 #define DMA_REQUEST_TIM17_UP 112U
372 #if defined(SAI3)
373 #define DMA_REQUEST_SAI3_A 113U
374 #define DMA_REQUEST_SAI3_B 114U
375 #endif /* SAI3 */
376 
377 #if defined(ADC3)
378 #define DMA_REQUEST_ADC3 115U
379 #endif /* ADC3 */
380 
381 #if defined(UART9)
382 #define DMA_REQUEST_UART9_RX 116U
383 #define DMA_REQUEST_UART9_TX 117U
384 #endif /* UART9 */
385 
386 #if defined(USART10)
387 #define DMA_REQUEST_USART10_RX 118U
388 #define DMA_REQUEST_USART10_TX 119U
389 #endif /* USART10 */
390 
391 #if defined(FMAC)
392 #define DMA_REQUEST_FMAC_READ 120U
393 #define DMA_REQUEST_FMAC_WRITE 121U
394 #endif /* FMAC */
395 
396 #if defined(CORDIC)
397 #define DMA_REQUEST_CORDIC_READ 122U
398 #define DMA_REQUEST_CORDIC_WRITE 123U
399 #endif /* CORDIC */
400 
401 #if defined(I2C5)
402 #define DMA_REQUEST_I2C5_RX 124U
403 #define DMA_REQUEST_I2C5_TX 125U
404 #endif /* I2C5 */
405 
406 #if defined(TIM23)
407 #define DMA_REQUEST_TIM23_CH1 126U
408 #define DMA_REQUEST_TIM23_CH2 127U
409 #define DMA_REQUEST_TIM23_CH3 128U
410 #define DMA_REQUEST_TIM23_CH4 129U
411 #define DMA_REQUEST_TIM23_UP 130U
412 #define DMA_REQUEST_TIM23_TRIG 131U
413 #endif /* TIM23 */
414 
415 #if defined(TIM24)
416 #define DMA_REQUEST_TIM24_CH1 132U
417 #define DMA_REQUEST_TIM24_CH2 133U
418 #define DMA_REQUEST_TIM24_CH3 134U
419 #define DMA_REQUEST_TIM24_CH4 135U
420 #define DMA_REQUEST_TIM24_UP 136U
421 #define DMA_REQUEST_TIM24_TRIG 137U
422 #endif /* TIM24 */
423 
424 /* DMAMUX2 requests */
425 #define BDMA_REQUEST_MEM2MEM 0U
426 #define BDMA_REQUEST_GENERATOR0 1U
427 #define BDMA_REQUEST_GENERATOR1 2U
428 #define BDMA_REQUEST_GENERATOR2 3U
429 #define BDMA_REQUEST_GENERATOR3 4U
430 #define BDMA_REQUEST_GENERATOR4 5U
431 #define BDMA_REQUEST_GENERATOR5 6U
432 #define BDMA_REQUEST_GENERATOR6 7U
433 #define BDMA_REQUEST_GENERATOR7 8U
434 #define BDMA_REQUEST_LPUART1_RX 9U
435 #define BDMA_REQUEST_LPUART1_TX 10U
436 #define BDMA_REQUEST_SPI6_RX 11U
437 #define BDMA_REQUEST_SPI6_TX 12U
438 #define BDMA_REQUEST_I2C4_RX 13U
439 #define BDMA_REQUEST_I2C4_TX 14U
440 #if defined(SAI4)
441 #define BDMA_REQUEST_SAI4_A 15U
442 #define BDMA_REQUEST_SAI4_B 16U
443 #endif /* SAI4 */
444 #if defined(ADC3)
445 #define BDMA_REQUEST_ADC3 17U
446 #endif /* ADC3 */
447 #if defined(DAC2)
448 #define BDMA_REQUEST_DAC2_CH1 17U
449 #endif /* DAC2 */
450 #if defined(DFSDM2_Channel0)
451 #define BDMA_REQUEST_DFSDM2_FLT0 18U
452 #endif /* DFSDM1_Channel0 */
453 
462 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
463 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
464 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
473 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
474 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U)
483 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
484 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U)
493 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
494 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
495 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
504 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
505 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
506 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
515 #define DMA_NORMAL ((uint32_t)0x00000000U)
516 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
517 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
518 #define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM)
519 #define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT))
528 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
529 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
530 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
531 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
540 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
541 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
550 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
551 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
552 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
553 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
562 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
563 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
564 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
565 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
566 
574 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
575 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
576 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
577 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
578 
586 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
587 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
588 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
589 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
590 #define DMA_IT_FE ((uint32_t)0x00000080U)
591 
599 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)
600 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)
601 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
602 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
603 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
604 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
605 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
606 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
607 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
608 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
609 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
610 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
611 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
612 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
613 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
614 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
615 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
616 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
617 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
618 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
619 
627 #define BDMA_FLAG_GL0 ((uint32_t)0x00000001)
628 #define BDMA_FLAG_TC0 ((uint32_t)0x00000002)
629 #define BDMA_FLAG_HT0 ((uint32_t)0x00000004)
630 #define BDMA_FLAG_TE0 ((uint32_t)0x00000008)
631 #define BDMA_FLAG_GL1 ((uint32_t)0x00000010)
632 #define BDMA_FLAG_TC1 ((uint32_t)0x00000020)
633 #define BDMA_FLAG_HT1 ((uint32_t)0x00000040)
634 #define BDMA_FLAG_TE1 ((uint32_t)0x00000080)
635 #define BDMA_FLAG_GL2 ((uint32_t)0x00000100)
636 #define BDMA_FLAG_TC2 ((uint32_t)0x00000200)
637 #define BDMA_FLAG_HT2 ((uint32_t)0x00000400)
638 #define BDMA_FLAG_TE2 ((uint32_t)0x00000800)
639 #define BDMA_FLAG_GL3 ((uint32_t)0x00001000)
640 #define BDMA_FLAG_TC3 ((uint32_t)0x00002000)
641 #define BDMA_FLAG_HT3 ((uint32_t)0x00004000)
642 #define BDMA_FLAG_TE3 ((uint32_t)0x00008000)
643 #define BDMA_FLAG_GL4 ((uint32_t)0x00010000)
644 #define BDMA_FLAG_TC4 ((uint32_t)0x00020000)
645 #define BDMA_FLAG_HT4 ((uint32_t)0x00040000)
646 #define BDMA_FLAG_TE4 ((uint32_t)0x00080000)
647 #define BDMA_FLAG_GL5 ((uint32_t)0x00100000)
648 #define BDMA_FLAG_TC5 ((uint32_t)0x00200000)
649 #define BDMA_FLAG_HT5 ((uint32_t)0x00400000)
650 #define BDMA_FLAG_TE5 ((uint32_t)0x00800000)
651 #define BDMA_FLAG_GL6 ((uint32_t)0x01000000)
652 #define BDMA_FLAG_TC6 ((uint32_t)0x02000000)
653 #define BDMA_FLAG_HT6 ((uint32_t)0x04000000)
654 #define BDMA_FLAG_TE6 ((uint32_t)0x08000000)
655 #define BDMA_FLAG_GL7 ((uint32_t)0x10000000)
656 #define BDMA_FLAG_TC7 ((uint32_t)0x20000000)
657 #define BDMA_FLAG_HT7 ((uint32_t)0x40000000)
658 #define BDMA_FLAG_TE7 ((uint32_t)0x80000000)
659 
668 /* Exported macro ------------------------------------------------------------*/
677 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
678 
691 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
692 
698 #define __HAL_DMA_ENABLE(__HANDLE__) \
699 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \
700 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN))
701 
707 #define __HAL_DMA_DISABLE(__HANDLE__) \
708 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \
709 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN))
710 
711 /* Interrupt & Flag management */
712 
718 #if defined(BDMA1)
719 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
720 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
721  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
722  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
723  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
724  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
725  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
726  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
727  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
728  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
729  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
730  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
731  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
732  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
733  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
734  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
735  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
736  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\
737  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\
738  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\
739  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\
740  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\
741  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\
742  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\
743  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\
744  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\
745  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\
746  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\
747  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\
748  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\
749  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\
750  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\
751  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\
752  (uint32_t)0x00000000)
753 #else
754 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
755 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
756  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
757  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
758  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
759  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
760  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
761  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
762  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
763  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
764  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
765  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
766  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
767  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
768  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
769  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
770  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
771  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\
772  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\
773  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\
774  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\
775  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\
776  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\
777  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\
778  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\
779  (uint32_t)0x00000000)
780 #endif /* BDMA1 */
781 
787 #if defined(BDMA1)
788 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
789 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
790  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
791  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
792  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
793  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
794  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
795  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
796  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
797  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
798  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
799  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
800  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
801  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
802  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
803  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
804  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
805  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\
806  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\
807  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\
808  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\
809  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\
810  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\
811  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\
812  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\
813  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\
814  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\
815  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\
816  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\
817  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\
818  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\
819  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\
820  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\
821  (uint32_t)0x00000000)
822 #else
823 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
824 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
825  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
826  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
827  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
828  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
829  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
830  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
831  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
832  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
833  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
834  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
835  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
836  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
837  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
838  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
839  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
840  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\
841  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\
842  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\
843  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\
844  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\
845  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\
846  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\
847  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\
848  (uint32_t)0x00000000)
849 #endif /* BDMA1 */
850 
856 #if defined(BDMA1)
857 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
858 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
859  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
860  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
861  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
862  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
863  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
864  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
865  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
866  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
867  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
868  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
869  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
870  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
871  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
872  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
873  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
874  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\
875  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\
876  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\
877  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\
878  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\
879  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\
880  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\
881  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\
882  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\
883  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\
884  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\
885  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\
886  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\
887  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\
888  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\
889  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\
890  (uint32_t)0x00000000)
891 #else
892 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
893 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
894  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
895  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
896  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
897  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
898  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
899  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
900  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
901  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
902  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
903  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
904  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
905  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
906  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
907  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
908  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
909  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\
910  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\
911  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\
912  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\
913  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\
914  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\
915  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\
916  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\
917  (uint32_t)0x00000000)
918 #endif /* BDMA1 */
919 
925 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
926 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
927  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
928  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
929  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
930  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
931  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
932  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
933  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
934  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
935  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
936  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
937  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
938  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
939  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
940  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
941  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
942  (uint32_t)0x00000000)
943 
949 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
950 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
951  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
952  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
953  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
954  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
955  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
956  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
957  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
958  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
959  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
960  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
961  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
962  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
963  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
964  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
965  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
966  (uint32_t)0x00000000)
967 
973 #if defined(BDMA1)
974 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
975 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
976  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
977  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
978  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
979  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
980  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
981  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
982  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
983  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
984  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
985  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
986  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
987  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
988  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
989  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
990  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
991  (uint32_t)0x00000000)
992 #else
993 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
994 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
995  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
996  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
997  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
998  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
999  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
1000  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
1001  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
1002  (uint32_t)0x00000000)
1003 #endif /* BDMA1 */
1004 
1018 #if defined(BDMA1)
1019 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
1020 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\
1021  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\
1022  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\
1023  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\
1024  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
1025 #else
1026 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
1027 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\
1028  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
1029  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
1030  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
1031 #endif /* BDMA1 */
1032 
1046 #if defined(BDMA1)
1047 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1048 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
1049  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\
1050  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
1051  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
1052  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
1053 #else
1054 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1055 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\
1056  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
1057  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
1058  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
1059 #endif /* BDMA1 */
1060 
1061 #define DMA_TO_BDMA_IT(__DMA_IT__) \
1062 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
1063  (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
1064  (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
1065  (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\
1066  ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
1067  ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
1068  ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
1069  (uint32_t)0x00000000)
1070 
1071 
1072 #define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1073 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
1074 
1075 #define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1076 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
1077 
1090 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
1091  (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
1092  (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
1093 
1094 
1095 #define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
1096 
1097 #define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1098 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
1099 
1112 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
1113  (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
1114  (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
1115 
1116 
1117 #define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
1118 
1119 #define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1120  (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
1121  (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
1122 
1135 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1136  (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
1137  (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
1138 
1156 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1157  (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
1158  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
1159 
1166 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1167  (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
1168  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
1169 
1174 /* Include DMA HAL Extension module */
1175 #include "stm32h7xx_hal_dma_ex.h"
1176 
1177 /* Exported functions --------------------------------------------------------*/
1178 
1188 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
1189 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
1198 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
1199 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
1200 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
1201 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
1202 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
1203 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
1204 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
1205 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
1206 
1215 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
1216 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
1223 /* Private Constants -------------------------------------------------------------*/
1232 /* Private macros ------------------------------------------------------------*/
1238 #if defined(TIM24)
1239 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG))
1240 #elif defined(ADC3)
1241 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
1242 #else
1243 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
1244 #endif /* TIM24 */
1245 
1246 #if defined(ADC3)
1247 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
1248 #else
1249 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
1250 #endif /* ADC3 */
1251 
1252 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
1253  ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
1254  ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
1255 
1256 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
1257 
1258 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
1259  ((STATE) == DMA_PINC_DISABLE))
1260 
1261 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
1262  ((STATE) == DMA_MINC_DISABLE))
1263 
1264 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
1265  ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
1266  ((SIZE) == DMA_PDATAALIGN_WORD))
1267 
1268 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
1269  ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
1270  ((SIZE) == DMA_MDATAALIGN_WORD ))
1271 
1272 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
1273  ((MODE) == DMA_CIRCULAR) || \
1274  ((MODE) == DMA_PFCTRL) || \
1275  ((MODE) == DMA_DOUBLE_BUFFER_M0) || \
1276  ((MODE) == DMA_DOUBLE_BUFFER_M1))
1277 
1278 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
1279  ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
1280  ((PRIORITY) == DMA_PRIORITY_HIGH) || \
1281  ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
1282 
1283 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
1284  ((STATE) == DMA_FIFOMODE_ENABLE))
1285 
1286 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
1287  ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
1288  ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
1289  ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
1290 
1291 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
1292  ((BURST) == DMA_MBURST_INC4) || \
1293  ((BURST) == DMA_MBURST_INC8) || \
1294  ((BURST) == DMA_MBURST_INC16))
1295 
1296 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
1297  ((BURST) == DMA_PBURST_INC4) || \
1298  ((BURST) == DMA_PBURST_INC8) || \
1299  ((BURST) == DMA_PBURST_INC16))
1300 
1304 /* Private functions ---------------------------------------------------------*/
1321 #ifdef __cplusplus
1322 }
1323 #endif
1324 
1325 #endif /* STM32H7xx_HAL_DMA_H */
1326 
1327 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__DMA_HandleTypeDef::DMAmuxChannelStatusMask
uint32_t DMAmuxChannelStatusMask
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:171
__DMA_HandleTypeDef::DMAmuxChannelStatus
DMAMUX_ChannelStatus_TypeDef * DMAmuxChannelStatus
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:169
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:106
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:129
__DMA_HandleTypeDef::XferHalfCpltCallback
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:153
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
__DMA_HandleTypeDef::StreamIndex
uint32_t StreamIndex
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:167
DMAMUX_ChannelStatus_TypeDef
Definition: stm32h735xx.h:643
__DMA_HandleTypeDef::StreamBaseAddress
uint32_t StreamBaseAddress
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:165
__DMA_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:163
DMA_InitTypeDef
DMA Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:49
HAL_DMA_Abort_IT
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::XferM1CpltCallback
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:155
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:107
__DMA_HandleTypeDef::XferAbortCallback
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:161
__DMA_HandleTypeDef::Init
DMA_InitTypeDef Init
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:143
HAL_DMA_STATE_ABORT
@ HAL_DMA_STATE_ABORT
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:108
__DMA_HandleTypeDef::DMAmuxChannel
DMAMUX_Channel_TypeDef * DMAmuxChannel
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:167
__DMA_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:145
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
__DMA_HandleTypeDef::State
__IO HAL_DMA_StateTypeDef State
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:147
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32h735xx.h:654
stm32h7xx_hal_dma_ex.h
Header file of DMA HAL extension module.
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:130
HAL_DMA_XFER_M1HALFCPLT_CB_ID
@ HAL_DMA_XFER_M1HALFCPLT_CB_ID
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:128
HAL_DMA_FULL_TRANSFER
@ HAL_DMA_FULL_TRANSFER
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:116
HAL_DMA_UnRegisterCallback
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:131
HAL_DMA_PollForTransfer
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
HAL_DMA_GetState
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::Instance
DMA_Stream_TypeDef * Instance
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:141
HAL_DMA_CallbackIDTypeDef
HAL_DMA_CallbackIDTypeDef
HAL DMA Callbacks IDs structure definition.
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:123
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_DMA_XFER_M1CPLT_CB_ID
@ HAL_DMA_XFER_M1CPLT_CB_ID
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:127
HAL_DMA_Abort
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
DMAMUX_RequestGen_TypeDef
Definition: stm32h735xx.h:649
HAL_DMA_XFER_CPLT_CB_ID
@ HAL_DMA_XFER_CPLT_CB_ID
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:125
__DMA_HandleTypeDef::DMAmuxRequestGenStatusMask
uint32_t DMAmuxRequestGenStatusMask
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:178
__DMA_HandleTypeDef::DMAmuxRequestGen
DMAMUX_RequestGen_TypeDef * DMAmuxRequestGen
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:174
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:104
__DMA_HandleTypeDef::Parent
void * Parent
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:149
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:151
HAL_DMA_Init
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
HAL_DMA_HALF_TRANSFER
@ HAL_DMA_HALF_TRANSFER
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:117
HAL_DMA_DeInit
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
HAL_DMA_XFER_HALFCPLT_CB_ID
@ HAL_DMA_XFER_HALFCPLT_CB_ID
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:126
__DMA_HandleTypeDef::XferM1HalfCpltCallback
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:157
HAL_DMA_GetError
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
HAL_DMA_Start
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_DMA_StateTypeDef
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:102
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_LevelCompleteTypeDef
HAL DMA Transfer complete level structure definition.
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:114
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745
DMAMUX_Channel_TypeDef
Definition: stm32h735xx.h:638
HAL_DMA_IRQHandler
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::DMAmuxRequestGenStatus
DMAMUX_RequestGenStatus_TypeDef * DMAmuxRequestGenStatus
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:176
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:159
HAL_DMA_RegisterCallback
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:105

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:54