stm32f7xx_hal_i2c.c
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1 
307 /* Includes ------------------------------------------------------------------*/
308 #include "stm32f7xx_hal.h"
309 
319 #ifdef HAL_I2C_MODULE_ENABLED
320 
321 /* Private typedef -----------------------------------------------------------*/
322 /* Private define ------------------------------------------------------------*/
323 
327 #define TIMING_CLEAR_MASK (0xF0FFFFFFU)
328 #define I2C_TIMEOUT_ADDR (10000U)
329 #define I2C_TIMEOUT_BUSY (25U)
330 #define I2C_TIMEOUT_DIR (25U)
331 #define I2C_TIMEOUT_RXNE (25U)
332 #define I2C_TIMEOUT_STOPF (25U)
333 #define I2C_TIMEOUT_TC (25U)
334 #define I2C_TIMEOUT_TCR (25U)
335 #define I2C_TIMEOUT_TXIS (25U)
336 #define I2C_TIMEOUT_FLAG (25U)
338 #define MAX_NBYTE_SIZE 255U
339 #define SlaveAddr_SHIFT 7U
340 #define SlaveAddr_MSK 0x06U
341 
342 /* Private define for @ref PreviousState usage */
343 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
344 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
345 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
346 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
347 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
348 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
349 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
350 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
353 /* Private define to centralize the enable/disable of Interrupts */
354 #define I2C_XFER_TX_IT (0x00000001U)
355 #define I2C_XFER_RX_IT (0x00000002U)
356 #define I2C_XFER_LISTEN_IT (0x00000004U)
357 
358 #define I2C_XFER_ERROR_IT (0x00000011U)
359 #define I2C_XFER_CPLT_IT (0x00000012U)
360 #define I2C_XFER_RELOAD_IT (0x00000012U)
361 
362 /* Private define Sequential Transfer Options default/reset value */
363 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
364 
368 /* Private macro -------------------------------------------------------------*/
369 /* Private variables ---------------------------------------------------------*/
370 /* Private function prototypes -----------------------------------------------*/
371 
375 /* Private functions to handle DMA transfer */
376 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
377 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
378 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
379 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
380 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
381 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
382 
383 /* Private functions to handle IT transfer */
384 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
385 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
386 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
387 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
388 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
389 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
390 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
391 
392 /* Private functions to handle IT transfer */
393 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
394 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
395 
396 /* Private functions for I2C transfer IRQ handler */
397 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
398 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
399 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
400 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
401 
402 /* Private functions to handle flags during polling transfer */
403 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
404 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
405 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
406 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
407 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
408 
409 /* Private functions to centralize the enable/disable of Interrupts */
410 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
411 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
412 
413 /* Private function to flush TXDR register */
414 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
415 
416 /* Private function to handle start, restart or stop a transfer */
417 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
418 
419 /* Private function to Convert Specific options */
420 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
425 /* Exported functions --------------------------------------------------------*/
426 
469 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
470 {
471  /* Check the I2C handle allocation */
472  if (hi2c == NULL)
473  {
474  return HAL_ERROR;
475  }
476 
477  /* Check the parameters */
478  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
479  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
480  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
481  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
482  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
483  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
484  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
485  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
486 
487  if (hi2c->State == HAL_I2C_STATE_RESET)
488  {
489  /* Allocate lock resource and initialize it */
490  hi2c->Lock = HAL_UNLOCKED;
491 
492 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
493  /* Init the I2C Callback settings */
494  hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
495  hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
496  hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
497  hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
498  hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
499  hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
500  hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
501  hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
502  hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
503  hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
504 
505  if (hi2c->MspInitCallback == NULL)
506  {
507  hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
508  }
509 
510  /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
511  hi2c->MspInitCallback(hi2c);
512 #else
513  /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
514  HAL_I2C_MspInit(hi2c);
515 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
516  }
517 
518  hi2c->State = HAL_I2C_STATE_BUSY;
519 
520  /* Disable the selected I2C peripheral */
521  __HAL_I2C_DISABLE(hi2c);
522 
523  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
524  /* Configure I2Cx: Frequency range */
525  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
526 
527  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
528  /* Disable Own Address1 before set the Own Address1 configuration */
529  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
530 
531  /* Configure I2Cx: Own Address1 and ack own address1 mode */
532  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
533  {
534  hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
535  }
536  else /* I2C_ADDRESSINGMODE_10BIT */
537  {
538  hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
539  }
540 
541  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
542  /* Configure I2Cx: Addressing Master mode */
543  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
544  {
545  hi2c->Instance->CR2 = (I2C_CR2_ADD10);
546  }
547  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
548  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
549 
550  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
551  /* Disable Own Address2 before set the Own Address2 configuration */
552  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
553 
554  /* Configure I2Cx: Dual mode and Own Address2 */
555  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
556 
557  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
558  /* Configure I2Cx: Generalcall and NoStretch mode */
559  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
560 
561  /* Enable the selected I2C peripheral */
562  __HAL_I2C_ENABLE(hi2c);
563 
564  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
565  hi2c->State = HAL_I2C_STATE_READY;
566  hi2c->PreviousState = I2C_STATE_NONE;
567  hi2c->Mode = HAL_I2C_MODE_NONE;
568 
569  return HAL_OK;
570 }
571 
578 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
579 {
580  /* Check the I2C handle allocation */
581  if (hi2c == NULL)
582  {
583  return HAL_ERROR;
584  }
585 
586  /* Check the parameters */
587  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
588 
589  hi2c->State = HAL_I2C_STATE_BUSY;
590 
591  /* Disable the I2C Peripheral Clock */
592  __HAL_I2C_DISABLE(hi2c);
593 
594 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
595  if (hi2c->MspDeInitCallback == NULL)
596  {
597  hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
598  }
599 
600  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
601  hi2c->MspDeInitCallback(hi2c);
602 #else
603  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
604  HAL_I2C_MspDeInit(hi2c);
605 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
606 
607  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
608  hi2c->State = HAL_I2C_STATE_RESET;
609  hi2c->PreviousState = I2C_STATE_NONE;
610  hi2c->Mode = HAL_I2C_MODE_NONE;
611 
612  /* Release Lock */
613  __HAL_UNLOCK(hi2c);
614 
615  return HAL_OK;
616 }
617 
624 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
625 {
626  /* Prevent unused argument(s) compilation warning */
627  UNUSED(hi2c);
628 
629  /* NOTE : This function should not be modified, when the callback is needed,
630  the HAL_I2C_MspInit could be implemented in the user file
631  */
632 }
633 
640 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
641 {
642  /* Prevent unused argument(s) compilation warning */
643  UNUSED(hi2c);
644 
645  /* NOTE : This function should not be modified, when the callback is needed,
646  the HAL_I2C_MspDeInit could be implemented in the user file
647  */
648 }
649 
650 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
651 
672 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
673 {
674  HAL_StatusTypeDef status = HAL_OK;
675 
676  if (pCallback == NULL)
677  {
678  /* Update the error code */
679  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
680 
681  return HAL_ERROR;
682  }
683  /* Process locked */
684  __HAL_LOCK(hi2c);
685 
686  if (HAL_I2C_STATE_READY == hi2c->State)
687  {
688  switch (CallbackID)
689  {
690  case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
691  hi2c->MasterTxCpltCallback = pCallback;
692  break;
693 
694  case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
695  hi2c->MasterRxCpltCallback = pCallback;
696  break;
697 
698  case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
699  hi2c->SlaveTxCpltCallback = pCallback;
700  break;
701 
702  case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
703  hi2c->SlaveRxCpltCallback = pCallback;
704  break;
705 
706  case HAL_I2C_LISTEN_COMPLETE_CB_ID :
707  hi2c->ListenCpltCallback = pCallback;
708  break;
709 
710  case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
711  hi2c->MemTxCpltCallback = pCallback;
712  break;
713 
714  case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
715  hi2c->MemRxCpltCallback = pCallback;
716  break;
717 
718  case HAL_I2C_ERROR_CB_ID :
719  hi2c->ErrorCallback = pCallback;
720  break;
721 
722  case HAL_I2C_ABORT_CB_ID :
723  hi2c->AbortCpltCallback = pCallback;
724  break;
725 
726  case HAL_I2C_MSPINIT_CB_ID :
727  hi2c->MspInitCallback = pCallback;
728  break;
729 
730  case HAL_I2C_MSPDEINIT_CB_ID :
731  hi2c->MspDeInitCallback = pCallback;
732  break;
733 
734  default :
735  /* Update the error code */
736  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
737 
738  /* Return error status */
739  status = HAL_ERROR;
740  break;
741  }
742  }
743  else if (HAL_I2C_STATE_RESET == hi2c->State)
744  {
745  switch (CallbackID)
746  {
747  case HAL_I2C_MSPINIT_CB_ID :
748  hi2c->MspInitCallback = pCallback;
749  break;
750 
751  case HAL_I2C_MSPDEINIT_CB_ID :
752  hi2c->MspDeInitCallback = pCallback;
753  break;
754 
755  default :
756  /* Update the error code */
757  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
758 
759  /* Return error status */
760  status = HAL_ERROR;
761  break;
762  }
763  }
764  else
765  {
766  /* Update the error code */
767  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
768 
769  /* Return error status */
770  status = HAL_ERROR;
771  }
772 
773  /* Release Lock */
774  __HAL_UNLOCK(hi2c);
775  return status;
776 }
777 
799 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
800 {
801  HAL_StatusTypeDef status = HAL_OK;
802 
803  /* Process locked */
804  __HAL_LOCK(hi2c);
805 
806  if (HAL_I2C_STATE_READY == hi2c->State)
807  {
808  switch (CallbackID)
809  {
810  case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
811  hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
812  break;
813 
814  case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
815  hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
816  break;
817 
818  case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
819  hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
820  break;
821 
822  case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
823  hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
824  break;
825 
826  case HAL_I2C_LISTEN_COMPLETE_CB_ID :
827  hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
828  break;
829 
830  case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
831  hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
832  break;
833 
834  case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
835  hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
836  break;
837 
838  case HAL_I2C_ERROR_CB_ID :
839  hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
840  break;
841 
842  case HAL_I2C_ABORT_CB_ID :
843  hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
844  break;
845 
846  case HAL_I2C_MSPINIT_CB_ID :
847  hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
848  break;
849 
850  case HAL_I2C_MSPDEINIT_CB_ID :
851  hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
852  break;
853 
854  default :
855  /* Update the error code */
856  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
857 
858  /* Return error status */
859  status = HAL_ERROR;
860  break;
861  }
862  }
863  else if (HAL_I2C_STATE_RESET == hi2c->State)
864  {
865  switch (CallbackID)
866  {
867  case HAL_I2C_MSPINIT_CB_ID :
868  hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
869  break;
870 
871  case HAL_I2C_MSPDEINIT_CB_ID :
872  hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
873  break;
874 
875  default :
876  /* Update the error code */
877  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
878 
879  /* Return error status */
880  status = HAL_ERROR;
881  break;
882  }
883  }
884  else
885  {
886  /* Update the error code */
887  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
888 
889  /* Return error status */
890  status = HAL_ERROR;
891  }
892 
893  /* Release Lock */
894  __HAL_UNLOCK(hi2c);
895  return status;
896 }
897 
906 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
907 {
908  HAL_StatusTypeDef status = HAL_OK;
909 
910  if (pCallback == NULL)
911  {
912  /* Update the error code */
913  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
914 
915  return HAL_ERROR;
916  }
917  /* Process locked */
918  __HAL_LOCK(hi2c);
919 
920  if (HAL_I2C_STATE_READY == hi2c->State)
921  {
922  hi2c->AddrCallback = pCallback;
923  }
924  else
925  {
926  /* Update the error code */
927  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
928 
929  /* Return error status */
930  status = HAL_ERROR;
931  }
932 
933  /* Release Lock */
934  __HAL_UNLOCK(hi2c);
935  return status;
936 }
937 
945 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
946 {
947  HAL_StatusTypeDef status = HAL_OK;
948 
949  /* Process locked */
950  __HAL_LOCK(hi2c);
951 
952  if (HAL_I2C_STATE_READY == hi2c->State)
953  {
954  hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
955  }
956  else
957  {
958  /* Update the error code */
959  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
960 
961  /* Return error status */
962  status = HAL_ERROR;
963  }
964 
965  /* Release Lock */
966  __HAL_UNLOCK(hi2c);
967  return status;
968 }
969 
970 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
971 
1060 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1061 {
1062  uint32_t tickstart;
1063 
1064  if (hi2c->State == HAL_I2C_STATE_READY)
1065  {
1066  /* Process Locked */
1067  __HAL_LOCK(hi2c);
1068 
1069  /* Init tickstart for timeout management*/
1070  tickstart = HAL_GetTick();
1071 
1072  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1073  {
1074  return HAL_ERROR;
1075  }
1076 
1077  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1078  hi2c->Mode = HAL_I2C_MODE_MASTER;
1079  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1080 
1081  /* Prepare transfer parameters */
1082  hi2c->pBuffPtr = pData;
1083  hi2c->XferCount = Size;
1084  hi2c->XferISR = NULL;
1085 
1086  /* Send Slave Address */
1087  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1088  if (hi2c->XferCount > MAX_NBYTE_SIZE)
1089  {
1090  hi2c->XferSize = MAX_NBYTE_SIZE;
1091  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
1092  }
1093  else
1094  {
1095  hi2c->XferSize = hi2c->XferCount;
1096  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
1097  }
1098 
1099  while (hi2c->XferCount > 0U)
1100  {
1101  /* Wait until TXIS flag is set */
1102  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1103  {
1104  return HAL_ERROR;
1105  }
1106  /* Write data to TXDR */
1107  hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1108 
1109  /* Increment Buffer pointer */
1110  hi2c->pBuffPtr++;
1111 
1112  hi2c->XferCount--;
1113  hi2c->XferSize--;
1114 
1115  if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1116  {
1117  /* Wait until TCR flag is set */
1118  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1119  {
1120  return HAL_ERROR;
1121  }
1122 
1123  if (hi2c->XferCount > MAX_NBYTE_SIZE)
1124  {
1125  hi2c->XferSize = MAX_NBYTE_SIZE;
1126  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1127  }
1128  else
1129  {
1130  hi2c->XferSize = hi2c->XferCount;
1131  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1132  }
1133  }
1134  }
1135 
1136  /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1137  /* Wait until STOPF flag is set */
1138  if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1139  {
1140  return HAL_ERROR;
1141  }
1142 
1143  /* Clear STOP Flag */
1144  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1145 
1146  /* Clear Configuration Register 2 */
1147  I2C_RESET_CR2(hi2c);
1148 
1149  hi2c->State = HAL_I2C_STATE_READY;
1150  hi2c->Mode = HAL_I2C_MODE_NONE;
1151 
1152  /* Process Unlocked */
1153  __HAL_UNLOCK(hi2c);
1154 
1155  return HAL_OK;
1156  }
1157  else
1158  {
1159  return HAL_BUSY;
1160  }
1161 }
1162 
1174 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1175 {
1176  uint32_t tickstart;
1177 
1178  if (hi2c->State == HAL_I2C_STATE_READY)
1179  {
1180  /* Process Locked */
1181  __HAL_LOCK(hi2c);
1182 
1183  /* Init tickstart for timeout management*/
1184  tickstart = HAL_GetTick();
1185 
1186  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1187  {
1188  return HAL_ERROR;
1189  }
1190 
1191  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1192  hi2c->Mode = HAL_I2C_MODE_MASTER;
1193  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1194 
1195  /* Prepare transfer parameters */
1196  hi2c->pBuffPtr = pData;
1197  hi2c->XferCount = Size;
1198  hi2c->XferISR = NULL;
1199 
1200  /* Send Slave Address */
1201  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1202  if (hi2c->XferCount > MAX_NBYTE_SIZE)
1203  {
1204  hi2c->XferSize = MAX_NBYTE_SIZE;
1205  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
1206  }
1207  else
1208  {
1209  hi2c->XferSize = hi2c->XferCount;
1210  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
1211  }
1212 
1213  while (hi2c->XferCount > 0U)
1214  {
1215  /* Wait until RXNE flag is set */
1216  if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1217  {
1218  return HAL_ERROR;
1219  }
1220 
1221  /* Read data from RXDR */
1222  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1223 
1224  /* Increment Buffer pointer */
1225  hi2c->pBuffPtr++;
1226 
1227  hi2c->XferSize--;
1228  hi2c->XferCount--;
1229 
1230  if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1231  {
1232  /* Wait until TCR flag is set */
1233  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1234  {
1235  return HAL_ERROR;
1236  }
1237 
1238  if (hi2c->XferCount > MAX_NBYTE_SIZE)
1239  {
1240  hi2c->XferSize = MAX_NBYTE_SIZE;
1241  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1242  }
1243  else
1244  {
1245  hi2c->XferSize = hi2c->XferCount;
1246  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1247  }
1248  }
1249  }
1250 
1251  /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1252  /* Wait until STOPF flag is set */
1253  if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1254  {
1255  return HAL_ERROR;
1256  }
1257 
1258  /* Clear STOP Flag */
1259  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1260 
1261  /* Clear Configuration Register 2 */
1262  I2C_RESET_CR2(hi2c);
1263 
1264  hi2c->State = HAL_I2C_STATE_READY;
1265  hi2c->Mode = HAL_I2C_MODE_NONE;
1266 
1267  /* Process Unlocked */
1268  __HAL_UNLOCK(hi2c);
1269 
1270  return HAL_OK;
1271  }
1272  else
1273  {
1274  return HAL_BUSY;
1275  }
1276 }
1277 
1287 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1288 {
1289  uint32_t tickstart;
1290 
1291  if (hi2c->State == HAL_I2C_STATE_READY)
1292  {
1293  if ((pData == NULL) || (Size == 0U))
1294  {
1295  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1296  return HAL_ERROR;
1297  }
1298  /* Process Locked */
1299  __HAL_LOCK(hi2c);
1300 
1301  /* Init tickstart for timeout management*/
1302  tickstart = HAL_GetTick();
1303 
1304  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1305  hi2c->Mode = HAL_I2C_MODE_SLAVE;
1306  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1307 
1308  /* Prepare transfer parameters */
1309  hi2c->pBuffPtr = pData;
1310  hi2c->XferCount = Size;
1311  hi2c->XferISR = NULL;
1312 
1313  /* Enable Address Acknowledge */
1314  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1315 
1316  /* Wait until ADDR flag is set */
1317  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1318  {
1319  /* Disable Address Acknowledge */
1320  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1321  return HAL_ERROR;
1322  }
1323 
1324  /* Clear ADDR flag */
1325  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1326 
1327  /* If 10bit addressing mode is selected */
1328  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1329  {
1330  /* Wait until ADDR flag is set */
1331  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1332  {
1333  /* Disable Address Acknowledge */
1334  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1335  return HAL_ERROR;
1336  }
1337 
1338  /* Clear ADDR flag */
1339  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1340  }
1341 
1342  /* Wait until DIR flag is set Transmitter mode */
1343  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1344  {
1345  /* Disable Address Acknowledge */
1346  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1347  return HAL_ERROR;
1348  }
1349 
1350  while (hi2c->XferCount > 0U)
1351  {
1352  /* Wait until TXIS flag is set */
1353  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1354  {
1355  /* Disable Address Acknowledge */
1356  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1357  return HAL_ERROR;
1358  }
1359 
1360  /* Write data to TXDR */
1361  hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1362 
1363  /* Increment Buffer pointer */
1364  hi2c->pBuffPtr++;
1365 
1366  hi2c->XferCount--;
1367  }
1368 
1369  /* Wait until STOP flag is set */
1370  if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1371  {
1372  /* Disable Address Acknowledge */
1373  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1374 
1375  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1376  {
1377  /* Normal use case for Transmitter mode */
1378  /* A NACK is generated to confirm the end of transfer */
1379  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1380  }
1381  else
1382  {
1383  return HAL_ERROR;
1384  }
1385  }
1386 
1387  /* Clear STOP flag */
1388  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1389 
1390  /* Wait until BUSY flag is reset */
1391  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1392  {
1393  /* Disable Address Acknowledge */
1394  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1395  return HAL_ERROR;
1396  }
1397 
1398  /* Disable Address Acknowledge */
1399  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1400 
1401  hi2c->State = HAL_I2C_STATE_READY;
1402  hi2c->Mode = HAL_I2C_MODE_NONE;
1403 
1404  /* Process Unlocked */
1405  __HAL_UNLOCK(hi2c);
1406 
1407  return HAL_OK;
1408  }
1409  else
1410  {
1411  return HAL_BUSY;
1412  }
1413 }
1414 
1424 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1425 {
1426  uint32_t tickstart;
1427 
1428  if (hi2c->State == HAL_I2C_STATE_READY)
1429  {
1430  if ((pData == NULL) || (Size == 0U))
1431  {
1432  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1433  return HAL_ERROR;
1434  }
1435  /* Process Locked */
1436  __HAL_LOCK(hi2c);
1437 
1438  /* Init tickstart for timeout management*/
1439  tickstart = HAL_GetTick();
1440 
1441  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1442  hi2c->Mode = HAL_I2C_MODE_SLAVE;
1443  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1444 
1445  /* Prepare transfer parameters */
1446  hi2c->pBuffPtr = pData;
1447  hi2c->XferCount = Size;
1448  hi2c->XferISR = NULL;
1449 
1450  /* Enable Address Acknowledge */
1451  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1452 
1453  /* Wait until ADDR flag is set */
1454  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1455  {
1456  /* Disable Address Acknowledge */
1457  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1458  return HAL_ERROR;
1459  }
1460 
1461  /* Clear ADDR flag */
1462  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1463 
1464  /* Wait until DIR flag is reset Receiver mode */
1465  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1466  {
1467  /* Disable Address Acknowledge */
1468  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1469  return HAL_ERROR;
1470  }
1471 
1472  while (hi2c->XferCount > 0U)
1473  {
1474  /* Wait until RXNE flag is set */
1475  if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1476  {
1477  /* Disable Address Acknowledge */
1478  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1479 
1480  /* Store Last receive data if any */
1481  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1482  {
1483  /* Read data from RXDR */
1484  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1485 
1486  /* Increment Buffer pointer */
1487  hi2c->pBuffPtr++;
1488 
1489  hi2c->XferCount--;
1490  }
1491 
1492  return HAL_ERROR;
1493  }
1494 
1495  /* Read data from RXDR */
1496  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1497 
1498  /* Increment Buffer pointer */
1499  hi2c->pBuffPtr++;
1500 
1501  hi2c->XferCount--;
1502  }
1503 
1504  /* Wait until STOP flag is set */
1505  if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1506  {
1507  /* Disable Address Acknowledge */
1508  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1509  return HAL_ERROR;
1510  }
1511 
1512  /* Clear STOP flag */
1513  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1514 
1515  /* Wait until BUSY flag is reset */
1516  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1517  {
1518  /* Disable Address Acknowledge */
1519  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1520  return HAL_ERROR;
1521  }
1522 
1523  /* Disable Address Acknowledge */
1524  hi2c->Instance->CR2 |= I2C_CR2_NACK;
1525 
1526  hi2c->State = HAL_I2C_STATE_READY;
1527  hi2c->Mode = HAL_I2C_MODE_NONE;
1528 
1529  /* Process Unlocked */
1530  __HAL_UNLOCK(hi2c);
1531 
1532  return HAL_OK;
1533  }
1534  else
1535  {
1536  return HAL_BUSY;
1537  }
1538 }
1539 
1550 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1551 {
1552  uint32_t xfermode;
1553 
1554  if (hi2c->State == HAL_I2C_STATE_READY)
1555  {
1556  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1557  {
1558  return HAL_BUSY;
1559  }
1560 
1561  /* Process Locked */
1562  __HAL_LOCK(hi2c);
1563 
1564  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1565  hi2c->Mode = HAL_I2C_MODE_MASTER;
1566  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1567 
1568  /* Prepare transfer parameters */
1569  hi2c->pBuffPtr = pData;
1570  hi2c->XferCount = Size;
1571  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1572  hi2c->XferISR = I2C_Master_ISR_IT;
1573 
1574  if (hi2c->XferCount > MAX_NBYTE_SIZE)
1575  {
1576  hi2c->XferSize = MAX_NBYTE_SIZE;
1577  xfermode = I2C_RELOAD_MODE;
1578  }
1579  else
1580  {
1581  hi2c->XferSize = hi2c->XferCount;
1582  xfermode = I2C_AUTOEND_MODE;
1583  }
1584 
1585  /* Send Slave Address */
1586  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1587  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1588 
1589  /* Process Unlocked */
1590  __HAL_UNLOCK(hi2c);
1591 
1592  /* Note : The I2C interrupts must be enabled after unlocking current process
1593  to avoid the risk of I2C interrupt handle execution before current
1594  process unlock */
1595 
1596  /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1597  /* possible to enable all of these */
1598  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1599  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1600 
1601  return HAL_OK;
1602  }
1603  else
1604  {
1605  return HAL_BUSY;
1606  }
1607 }
1608 
1619 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1620 {
1621  uint32_t xfermode;
1622 
1623  if (hi2c->State == HAL_I2C_STATE_READY)
1624  {
1625  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1626  {
1627  return HAL_BUSY;
1628  }
1629 
1630  /* Process Locked */
1631  __HAL_LOCK(hi2c);
1632 
1633  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1634  hi2c->Mode = HAL_I2C_MODE_MASTER;
1635  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1636 
1637  /* Prepare transfer parameters */
1638  hi2c->pBuffPtr = pData;
1639  hi2c->XferCount = Size;
1640  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1641  hi2c->XferISR = I2C_Master_ISR_IT;
1642 
1643  if (hi2c->XferCount > MAX_NBYTE_SIZE)
1644  {
1645  hi2c->XferSize = MAX_NBYTE_SIZE;
1646  xfermode = I2C_RELOAD_MODE;
1647  }
1648  else
1649  {
1650  hi2c->XferSize = hi2c->XferCount;
1651  xfermode = I2C_AUTOEND_MODE;
1652  }
1653 
1654  /* Send Slave Address */
1655  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1656  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1657 
1658  /* Process Unlocked */
1659  __HAL_UNLOCK(hi2c);
1660 
1661  /* Note : The I2C interrupts must be enabled after unlocking current process
1662  to avoid the risk of I2C interrupt handle execution before current
1663  process unlock */
1664 
1665  /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1666  /* possible to enable all of these */
1667  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1668  I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1669 
1670  return HAL_OK;
1671  }
1672  else
1673  {
1674  return HAL_BUSY;
1675  }
1676 }
1677 
1686 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1687 {
1688  if (hi2c->State == HAL_I2C_STATE_READY)
1689  {
1690  /* Process Locked */
1691  __HAL_LOCK(hi2c);
1692 
1693  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1694  hi2c->Mode = HAL_I2C_MODE_SLAVE;
1695  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1696 
1697  /* Enable Address Acknowledge */
1698  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1699 
1700  /* Prepare transfer parameters */
1701  hi2c->pBuffPtr = pData;
1702  hi2c->XferCount = Size;
1703  hi2c->XferSize = hi2c->XferCount;
1704  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1705  hi2c->XferISR = I2C_Slave_ISR_IT;
1706 
1707  /* Process Unlocked */
1708  __HAL_UNLOCK(hi2c);
1709 
1710  /* Note : The I2C interrupts must be enabled after unlocking current process
1711  to avoid the risk of I2C interrupt handle execution before current
1712  process unlock */
1713 
1714  /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1715  /* possible to enable all of these */
1716  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1717  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1718 
1719  return HAL_OK;
1720  }
1721  else
1722  {
1723  return HAL_BUSY;
1724  }
1725 }
1726 
1735 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1736 {
1737  if (hi2c->State == HAL_I2C_STATE_READY)
1738  {
1739  /* Process Locked */
1740  __HAL_LOCK(hi2c);
1741 
1742  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1743  hi2c->Mode = HAL_I2C_MODE_SLAVE;
1744  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1745 
1746  /* Enable Address Acknowledge */
1747  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1748 
1749  /* Prepare transfer parameters */
1750  hi2c->pBuffPtr = pData;
1751  hi2c->XferCount = Size;
1752  hi2c->XferSize = hi2c->XferCount;
1753  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1754  hi2c->XferISR = I2C_Slave_ISR_IT;
1755 
1756  /* Process Unlocked */
1757  __HAL_UNLOCK(hi2c);
1758 
1759  /* Note : The I2C interrupts must be enabled after unlocking current process
1760  to avoid the risk of I2C interrupt handle execution before current
1761  process unlock */
1762 
1763  /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1764  /* possible to enable all of these */
1765  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1766  I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1767 
1768  return HAL_OK;
1769  }
1770  else
1771  {
1772  return HAL_BUSY;
1773  }
1774 }
1775 
1786 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1787 {
1788  uint32_t xfermode;
1789  HAL_StatusTypeDef dmaxferstatus;
1790 
1791  if (hi2c->State == HAL_I2C_STATE_READY)
1792  {
1793  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1794  {
1795  return HAL_BUSY;
1796  }
1797 
1798  /* Process Locked */
1799  __HAL_LOCK(hi2c);
1800 
1801  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1802  hi2c->Mode = HAL_I2C_MODE_MASTER;
1803  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1804 
1805  /* Prepare transfer parameters */
1806  hi2c->pBuffPtr = pData;
1807  hi2c->XferCount = Size;
1808  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1809  hi2c->XferISR = I2C_Master_ISR_DMA;
1810 
1811  if (hi2c->XferCount > MAX_NBYTE_SIZE)
1812  {
1813  hi2c->XferSize = MAX_NBYTE_SIZE;
1814  xfermode = I2C_RELOAD_MODE;
1815  }
1816  else
1817  {
1818  hi2c->XferSize = hi2c->XferCount;
1819  xfermode = I2C_AUTOEND_MODE;
1820  }
1821 
1822  if (hi2c->XferSize > 0U)
1823  {
1824  if (hi2c->hdmatx != NULL)
1825  {
1826  /* Set the I2C DMA transfer complete callback */
1827  hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1828 
1829  /* Set the DMA error callback */
1830  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1831 
1832  /* Set the unused DMA callbacks to NULL */
1833  hi2c->hdmatx->XferHalfCpltCallback = NULL;
1834  hi2c->hdmatx->XferAbortCallback = NULL;
1835 
1836  /* Enable the DMA stream */
1837  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
1838  }
1839  else
1840  {
1841  /* Update I2C state */
1842  hi2c->State = HAL_I2C_STATE_READY;
1843  hi2c->Mode = HAL_I2C_MODE_NONE;
1844 
1845  /* Update I2C error code */
1846  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1847 
1848  /* Process Unlocked */
1849  __HAL_UNLOCK(hi2c);
1850 
1851  return HAL_ERROR;
1852  }
1853 
1854  if (dmaxferstatus == HAL_OK)
1855  {
1856  /* Send Slave Address */
1857  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1858  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1859 
1860  /* Update XferCount value */
1861  hi2c->XferCount -= hi2c->XferSize;
1862 
1863  /* Process Unlocked */
1864  __HAL_UNLOCK(hi2c);
1865 
1866  /* Note : The I2C interrupts must be enabled after unlocking current process
1867  to avoid the risk of I2C interrupt handle execution before current
1868  process unlock */
1869  /* Enable ERR and NACK interrupts */
1870  I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1871 
1872  /* Enable DMA Request */
1873  hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1874  }
1875  else
1876  {
1877  /* Update I2C state */
1878  hi2c->State = HAL_I2C_STATE_READY;
1879  hi2c->Mode = HAL_I2C_MODE_NONE;
1880 
1881  /* Update I2C error code */
1882  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
1883 
1884  /* Process Unlocked */
1885  __HAL_UNLOCK(hi2c);
1886 
1887  return HAL_ERROR;
1888  }
1889  }
1890  else
1891  {
1892  /* Update Transfer ISR function pointer */
1893  hi2c->XferISR = I2C_Master_ISR_IT;
1894 
1895  /* Send Slave Address */
1896  /* Set NBYTES to write and generate START condition */
1897  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
1898 
1899  /* Process Unlocked */
1900  __HAL_UNLOCK(hi2c);
1901 
1902  /* Note : The I2C interrupts must be enabled after unlocking current process
1903  to avoid the risk of I2C interrupt handle execution before current
1904  process unlock */
1905  /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1906  /* possible to enable all of these */
1907  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1908  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1909  }
1910 
1911  return HAL_OK;
1912  }
1913  else
1914  {
1915  return HAL_BUSY;
1916  }
1917 }
1918 
1929 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1930 {
1931  uint32_t xfermode;
1932  HAL_StatusTypeDef dmaxferstatus;
1933 
1934  if (hi2c->State == HAL_I2C_STATE_READY)
1935  {
1936  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1937  {
1938  return HAL_BUSY;
1939  }
1940 
1941  /* Process Locked */
1942  __HAL_LOCK(hi2c);
1943 
1944  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1945  hi2c->Mode = HAL_I2C_MODE_MASTER;
1946  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1947 
1948  /* Prepare transfer parameters */
1949  hi2c->pBuffPtr = pData;
1950  hi2c->XferCount = Size;
1951  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1952  hi2c->XferISR = I2C_Master_ISR_DMA;
1953 
1954  if (hi2c->XferCount > MAX_NBYTE_SIZE)
1955  {
1956  hi2c->XferSize = MAX_NBYTE_SIZE;
1957  xfermode = I2C_RELOAD_MODE;
1958  }
1959  else
1960  {
1961  hi2c->XferSize = hi2c->XferCount;
1962  xfermode = I2C_AUTOEND_MODE;
1963  }
1964 
1965  if (hi2c->XferSize > 0U)
1966  {
1967  if (hi2c->hdmarx != NULL)
1968  {
1969  /* Set the I2C DMA transfer complete callback */
1970  hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
1971 
1972  /* Set the DMA error callback */
1973  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
1974 
1975  /* Set the unused DMA callbacks to NULL */
1976  hi2c->hdmarx->XferHalfCpltCallback = NULL;
1977  hi2c->hdmarx->XferAbortCallback = NULL;
1978 
1979  /* Enable the DMA stream */
1980  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
1981  }
1982  else
1983  {
1984  /* Update I2C state */
1985  hi2c->State = HAL_I2C_STATE_READY;
1986  hi2c->Mode = HAL_I2C_MODE_NONE;
1987 
1988  /* Update I2C error code */
1989  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1990 
1991  /* Process Unlocked */
1992  __HAL_UNLOCK(hi2c);
1993 
1994  return HAL_ERROR;
1995  }
1996 
1997  if (dmaxferstatus == HAL_OK)
1998  {
1999  /* Send Slave Address */
2000  /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2001  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2002 
2003  /* Update XferCount value */
2004  hi2c->XferCount -= hi2c->XferSize;
2005 
2006  /* Process Unlocked */
2007  __HAL_UNLOCK(hi2c);
2008 
2009  /* Note : The I2C interrupts must be enabled after unlocking current process
2010  to avoid the risk of I2C interrupt handle execution before current
2011  process unlock */
2012  /* Enable ERR and NACK interrupts */
2013  I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2014 
2015  /* Enable DMA Request */
2016  hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2017  }
2018  else
2019  {
2020  /* Update I2C state */
2021  hi2c->State = HAL_I2C_STATE_READY;
2022  hi2c->Mode = HAL_I2C_MODE_NONE;
2023 
2024  /* Update I2C error code */
2025  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2026 
2027  /* Process Unlocked */
2028  __HAL_UNLOCK(hi2c);
2029 
2030  return HAL_ERROR;
2031  }
2032  }
2033  else
2034  {
2035  /* Update Transfer ISR function pointer */
2036  hi2c->XferISR = I2C_Master_ISR_IT;
2037 
2038  /* Send Slave Address */
2039  /* Set NBYTES to read and generate START condition */
2040  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
2041 
2042  /* Process Unlocked */
2043  __HAL_UNLOCK(hi2c);
2044 
2045  /* Note : The I2C interrupts must be enabled after unlocking current process
2046  to avoid the risk of I2C interrupt handle execution before current
2047  process unlock */
2048  /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2049  /* possible to enable all of these */
2050  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2051  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2052  }
2053 
2054  return HAL_OK;
2055  }
2056  else
2057  {
2058  return HAL_BUSY;
2059  }
2060 }
2061 
2070 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2071 {
2072  HAL_StatusTypeDef dmaxferstatus;
2073 
2074  if (hi2c->State == HAL_I2C_STATE_READY)
2075  {
2076  if ((pData == NULL) || (Size == 0U))
2077  {
2078  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2079  return HAL_ERROR;
2080  }
2081  /* Process Locked */
2082  __HAL_LOCK(hi2c);
2083 
2084  hi2c->State = HAL_I2C_STATE_BUSY_TX;
2085  hi2c->Mode = HAL_I2C_MODE_SLAVE;
2086  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2087 
2088  /* Prepare transfer parameters */
2089  hi2c->pBuffPtr = pData;
2090  hi2c->XferCount = Size;
2091  hi2c->XferSize = hi2c->XferCount;
2092  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2093  hi2c->XferISR = I2C_Slave_ISR_DMA;
2094 
2095  if (hi2c->hdmatx != NULL)
2096  {
2097  /* Set the I2C DMA transfer complete callback */
2098  hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2099 
2100  /* Set the DMA error callback */
2101  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2102 
2103  /* Set the unused DMA callbacks to NULL */
2104  hi2c->hdmatx->XferHalfCpltCallback = NULL;
2105  hi2c->hdmatx->XferAbortCallback = NULL;
2106 
2107  /* Enable the DMA stream */
2108  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
2109  }
2110  else
2111  {
2112  /* Update I2C state */
2113  hi2c->State = HAL_I2C_STATE_LISTEN;
2114  hi2c->Mode = HAL_I2C_MODE_NONE;
2115 
2116  /* Update I2C error code */
2117  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2118 
2119  /* Process Unlocked */
2120  __HAL_UNLOCK(hi2c);
2121 
2122  return HAL_ERROR;
2123  }
2124 
2125  if (dmaxferstatus == HAL_OK)
2126  {
2127  /* Enable Address Acknowledge */
2128  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2129 
2130  /* Process Unlocked */
2131  __HAL_UNLOCK(hi2c);
2132 
2133  /* Note : The I2C interrupts must be enabled after unlocking current process
2134  to avoid the risk of I2C interrupt handle execution before current
2135  process unlock */
2136  /* Enable ERR, STOP, NACK, ADDR interrupts */
2137  I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2138 
2139  /* Enable DMA Request */
2140  hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2141  }
2142  else
2143  {
2144  /* Update I2C state */
2145  hi2c->State = HAL_I2C_STATE_LISTEN;
2146  hi2c->Mode = HAL_I2C_MODE_NONE;
2147 
2148  /* Update I2C error code */
2149  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2150 
2151  /* Process Unlocked */
2152  __HAL_UNLOCK(hi2c);
2153 
2154  return HAL_ERROR;
2155  }
2156 
2157  return HAL_OK;
2158  }
2159  else
2160  {
2161  return HAL_BUSY;
2162  }
2163 }
2164 
2173 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2174 {
2175  HAL_StatusTypeDef dmaxferstatus;
2176 
2177  if (hi2c->State == HAL_I2C_STATE_READY)
2178  {
2179  if ((pData == NULL) || (Size == 0U))
2180  {
2181  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2182  return HAL_ERROR;
2183  }
2184  /* Process Locked */
2185  __HAL_LOCK(hi2c);
2186 
2187  hi2c->State = HAL_I2C_STATE_BUSY_RX;
2188  hi2c->Mode = HAL_I2C_MODE_SLAVE;
2189  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2190 
2191  /* Prepare transfer parameters */
2192  hi2c->pBuffPtr = pData;
2193  hi2c->XferCount = Size;
2194  hi2c->XferSize = hi2c->XferCount;
2195  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2196  hi2c->XferISR = I2C_Slave_ISR_DMA;
2197 
2198  if (hi2c->hdmarx != NULL)
2199  {
2200  /* Set the I2C DMA transfer complete callback */
2201  hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2202 
2203  /* Set the DMA error callback */
2204  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2205 
2206  /* Set the unused DMA callbacks to NULL */
2207  hi2c->hdmarx->XferHalfCpltCallback = NULL;
2208  hi2c->hdmarx->XferAbortCallback = NULL;
2209 
2210  /* Enable the DMA stream */
2211  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
2212  }
2213  else
2214  {
2215  /* Update I2C state */
2216  hi2c->State = HAL_I2C_STATE_LISTEN;
2217  hi2c->Mode = HAL_I2C_MODE_NONE;
2218 
2219  /* Update I2C error code */
2220  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2221 
2222  /* Process Unlocked */
2223  __HAL_UNLOCK(hi2c);
2224 
2225  return HAL_ERROR;
2226  }
2227 
2228  if (dmaxferstatus == HAL_OK)
2229  {
2230  /* Enable Address Acknowledge */
2231  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2232 
2233  /* Process Unlocked */
2234  __HAL_UNLOCK(hi2c);
2235 
2236  /* Note : The I2C interrupts must be enabled after unlocking current process
2237  to avoid the risk of I2C interrupt handle execution before current
2238  process unlock */
2239  /* Enable ERR, STOP, NACK, ADDR interrupts */
2240  I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2241 
2242  /* Enable DMA Request */
2243  hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2244  }
2245  else
2246  {
2247  /* Update I2C state */
2248  hi2c->State = HAL_I2C_STATE_LISTEN;
2249  hi2c->Mode = HAL_I2C_MODE_NONE;
2250 
2251  /* Update I2C error code */
2252  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2253 
2254  /* Process Unlocked */
2255  __HAL_UNLOCK(hi2c);
2256 
2257  return HAL_ERROR;
2258  }
2259 
2260  return HAL_OK;
2261  }
2262  else
2263  {
2264  return HAL_BUSY;
2265  }
2266 }
2280 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2281 {
2282  uint32_t tickstart;
2283 
2284  /* Check the parameters */
2285  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2286 
2287  if (hi2c->State == HAL_I2C_STATE_READY)
2288  {
2289  if ((pData == NULL) || (Size == 0U))
2290  {
2291  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2292  return HAL_ERROR;
2293  }
2294 
2295  /* Process Locked */
2296  __HAL_LOCK(hi2c);
2297 
2298  /* Init tickstart for timeout management*/
2299  tickstart = HAL_GetTick();
2300 
2301  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2302  {
2303  return HAL_ERROR;
2304  }
2305 
2306  hi2c->State = HAL_I2C_STATE_BUSY_TX;
2307  hi2c->Mode = HAL_I2C_MODE_MEM;
2308  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2309 
2310  /* Prepare transfer parameters */
2311  hi2c->pBuffPtr = pData;
2312  hi2c->XferCount = Size;
2313  hi2c->XferISR = NULL;
2314 
2315  /* Send Slave Address and Memory Address */
2316  if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2317  {
2318  /* Process Unlocked */
2319  __HAL_UNLOCK(hi2c);
2320  return HAL_ERROR;
2321  }
2322 
2323  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2324  if (hi2c->XferCount > MAX_NBYTE_SIZE)
2325  {
2326  hi2c->XferSize = MAX_NBYTE_SIZE;
2327  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2328  }
2329  else
2330  {
2331  hi2c->XferSize = hi2c->XferCount;
2332  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2333  }
2334 
2335  do
2336  {
2337  /* Wait until TXIS flag is set */
2338  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2339  {
2340  return HAL_ERROR;
2341  }
2342 
2343  /* Write data to TXDR */
2344  hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2345 
2346  /* Increment Buffer pointer */
2347  hi2c->pBuffPtr++;
2348 
2349  hi2c->XferCount--;
2350  hi2c->XferSize--;
2351 
2352  if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2353  {
2354  /* Wait until TCR flag is set */
2355  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2356  {
2357  return HAL_ERROR;
2358  }
2359 
2360  if (hi2c->XferCount > MAX_NBYTE_SIZE)
2361  {
2362  hi2c->XferSize = MAX_NBYTE_SIZE;
2363  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2364  }
2365  else
2366  {
2367  hi2c->XferSize = hi2c->XferCount;
2368  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2369  }
2370  }
2371 
2372  }
2373  while (hi2c->XferCount > 0U);
2374 
2375  /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2376  /* Wait until STOPF flag is reset */
2377  if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2378  {
2379  return HAL_ERROR;
2380  }
2381 
2382  /* Clear STOP Flag */
2383  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2384 
2385  /* Clear Configuration Register 2 */
2386  I2C_RESET_CR2(hi2c);
2387 
2388  hi2c->State = HAL_I2C_STATE_READY;
2389  hi2c->Mode = HAL_I2C_MODE_NONE;
2390 
2391  /* Process Unlocked */
2392  __HAL_UNLOCK(hi2c);
2393 
2394  return HAL_OK;
2395  }
2396  else
2397  {
2398  return HAL_BUSY;
2399  }
2400 }
2401 
2415 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2416 {
2417  uint32_t tickstart;
2418 
2419  /* Check the parameters */
2420  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2421 
2422  if (hi2c->State == HAL_I2C_STATE_READY)
2423  {
2424  if ((pData == NULL) || (Size == 0U))
2425  {
2426  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2427  return HAL_ERROR;
2428  }
2429 
2430  /* Process Locked */
2431  __HAL_LOCK(hi2c);
2432 
2433  /* Init tickstart for timeout management*/
2434  tickstart = HAL_GetTick();
2435 
2436  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2437  {
2438  return HAL_ERROR;
2439  }
2440 
2441  hi2c->State = HAL_I2C_STATE_BUSY_RX;
2442  hi2c->Mode = HAL_I2C_MODE_MEM;
2443  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2444 
2445  /* Prepare transfer parameters */
2446  hi2c->pBuffPtr = pData;
2447  hi2c->XferCount = Size;
2448  hi2c->XferISR = NULL;
2449 
2450  /* Send Slave Address and Memory Address */
2451  if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2452  {
2453  /* Process Unlocked */
2454  __HAL_UNLOCK(hi2c);
2455  return HAL_ERROR;
2456  }
2457 
2458  /* Send Slave Address */
2459  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2460  if (hi2c->XferCount > MAX_NBYTE_SIZE)
2461  {
2462  hi2c->XferSize = MAX_NBYTE_SIZE;
2463  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
2464  }
2465  else
2466  {
2467  hi2c->XferSize = hi2c->XferCount;
2468  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
2469  }
2470 
2471  do
2472  {
2473  /* Wait until RXNE flag is set */
2474  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2475  {
2476  return HAL_ERROR;
2477  }
2478 
2479  /* Read data from RXDR */
2480  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2481 
2482  /* Increment Buffer pointer */
2483  hi2c->pBuffPtr++;
2484 
2485  hi2c->XferSize--;
2486  hi2c->XferCount--;
2487 
2488  if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2489  {
2490  /* Wait until TCR flag is set */
2491  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2492  {
2493  return HAL_ERROR;
2494  }
2495 
2496  if (hi2c->XferCount > MAX_NBYTE_SIZE)
2497  {
2498  hi2c->XferSize = MAX_NBYTE_SIZE;
2499  I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2500  }
2501  else
2502  {
2503  hi2c->XferSize = hi2c->XferCount;
2504  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2505  }
2506  }
2507  }
2508  while (hi2c->XferCount > 0U);
2509 
2510  /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2511  /* Wait until STOPF flag is reset */
2512  if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2513  {
2514  return HAL_ERROR;
2515  }
2516 
2517  /* Clear STOP Flag */
2518  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2519 
2520  /* Clear Configuration Register 2 */
2521  I2C_RESET_CR2(hi2c);
2522 
2523  hi2c->State = HAL_I2C_STATE_READY;
2524  hi2c->Mode = HAL_I2C_MODE_NONE;
2525 
2526  /* Process Unlocked */
2527  __HAL_UNLOCK(hi2c);
2528 
2529  return HAL_OK;
2530  }
2531  else
2532  {
2533  return HAL_BUSY;
2534  }
2535 }
2548 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2549 {
2550  uint32_t tickstart;
2551  uint32_t xfermode;
2552 
2553  /* Check the parameters */
2554  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2555 
2556  if (hi2c->State == HAL_I2C_STATE_READY)
2557  {
2558  if ((pData == NULL) || (Size == 0U))
2559  {
2560  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2561  return HAL_ERROR;
2562  }
2563 
2564  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2565  {
2566  return HAL_BUSY;
2567  }
2568 
2569  /* Process Locked */
2570  __HAL_LOCK(hi2c);
2571 
2572  /* Init tickstart for timeout management*/
2573  tickstart = HAL_GetTick();
2574 
2575  hi2c->State = HAL_I2C_STATE_BUSY_TX;
2576  hi2c->Mode = HAL_I2C_MODE_MEM;
2577  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2578 
2579  /* Prepare transfer parameters */
2580  hi2c->pBuffPtr = pData;
2581  hi2c->XferCount = Size;
2582  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2583  hi2c->XferISR = I2C_Master_ISR_IT;
2584 
2585  if (hi2c->XferCount > MAX_NBYTE_SIZE)
2586  {
2587  hi2c->XferSize = MAX_NBYTE_SIZE;
2588  xfermode = I2C_RELOAD_MODE;
2589  }
2590  else
2591  {
2592  hi2c->XferSize = hi2c->XferCount;
2593  xfermode = I2C_AUTOEND_MODE;
2594  }
2595 
2596  /* Send Slave Address and Memory Address */
2597  if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2598  {
2599  /* Process Unlocked */
2600  __HAL_UNLOCK(hi2c);
2601  return HAL_ERROR;
2602  }
2603 
2604  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2605  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
2606 
2607  /* Process Unlocked */
2608  __HAL_UNLOCK(hi2c);
2609 
2610  /* Note : The I2C interrupts must be enabled after unlocking current process
2611  to avoid the risk of I2C interrupt handle execution before current
2612  process unlock */
2613 
2614  /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2615  /* possible to enable all of these */
2616  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2617  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2618 
2619  return HAL_OK;
2620  }
2621  else
2622  {
2623  return HAL_BUSY;
2624  }
2625 }
2626 
2639 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2640 {
2641  uint32_t tickstart;
2642  uint32_t xfermode;
2643 
2644  /* Check the parameters */
2645  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2646 
2647  if (hi2c->State == HAL_I2C_STATE_READY)
2648  {
2649  if ((pData == NULL) || (Size == 0U))
2650  {
2651  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2652  return HAL_ERROR;
2653  }
2654 
2655  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2656  {
2657  return HAL_BUSY;
2658  }
2659 
2660  /* Process Locked */
2661  __HAL_LOCK(hi2c);
2662 
2663  /* Init tickstart for timeout management*/
2664  tickstart = HAL_GetTick();
2665 
2666  hi2c->State = HAL_I2C_STATE_BUSY_RX;
2667  hi2c->Mode = HAL_I2C_MODE_MEM;
2668  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2669 
2670  /* Prepare transfer parameters */
2671  hi2c->pBuffPtr = pData;
2672  hi2c->XferCount = Size;
2673  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2674  hi2c->XferISR = I2C_Master_ISR_IT;
2675 
2676  if (hi2c->XferCount > MAX_NBYTE_SIZE)
2677  {
2678  hi2c->XferSize = MAX_NBYTE_SIZE;
2679  xfermode = I2C_RELOAD_MODE;
2680  }
2681  else
2682  {
2683  hi2c->XferSize = hi2c->XferCount;
2684  xfermode = I2C_AUTOEND_MODE;
2685  }
2686 
2687  /* Send Slave Address and Memory Address */
2688  if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2689  {
2690  /* Process Unlocked */
2691  __HAL_UNLOCK(hi2c);
2692  return HAL_ERROR;
2693  }
2694 
2695  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2696  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2697 
2698  /* Process Unlocked */
2699  __HAL_UNLOCK(hi2c);
2700 
2701  /* Note : The I2C interrupts must be enabled after unlocking current process
2702  to avoid the risk of I2C interrupt handle execution before current
2703  process unlock */
2704 
2705  /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2706  /* possible to enable all of these */
2707  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2708  I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2709 
2710  return HAL_OK;
2711  }
2712  else
2713  {
2714  return HAL_BUSY;
2715  }
2716 }
2729 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2730 {
2731  uint32_t tickstart;
2732  uint32_t xfermode;
2733  HAL_StatusTypeDef dmaxferstatus;
2734 
2735  /* Check the parameters */
2736  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2737 
2738  if (hi2c->State == HAL_I2C_STATE_READY)
2739  {
2740  if ((pData == NULL) || (Size == 0U))
2741  {
2742  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2743  return HAL_ERROR;
2744  }
2745 
2746  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2747  {
2748  return HAL_BUSY;
2749  }
2750 
2751  /* Process Locked */
2752  __HAL_LOCK(hi2c);
2753 
2754  /* Init tickstart for timeout management*/
2755  tickstart = HAL_GetTick();
2756 
2757  hi2c->State = HAL_I2C_STATE_BUSY_TX;
2758  hi2c->Mode = HAL_I2C_MODE_MEM;
2759  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2760 
2761  /* Prepare transfer parameters */
2762  hi2c->pBuffPtr = pData;
2763  hi2c->XferCount = Size;
2764  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2765  hi2c->XferISR = I2C_Master_ISR_DMA;
2766 
2767  if (hi2c->XferCount > MAX_NBYTE_SIZE)
2768  {
2769  hi2c->XferSize = MAX_NBYTE_SIZE;
2770  xfermode = I2C_RELOAD_MODE;
2771  }
2772  else
2773  {
2774  hi2c->XferSize = hi2c->XferCount;
2775  xfermode = I2C_AUTOEND_MODE;
2776  }
2777 
2778  /* Send Slave Address and Memory Address */
2779  if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2780  {
2781  /* Process Unlocked */
2782  __HAL_UNLOCK(hi2c);
2783  return HAL_ERROR;
2784  }
2785 
2786 
2787  if (hi2c->hdmatx != NULL)
2788  {
2789  /* Set the I2C DMA transfer complete callback */
2790  hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2791 
2792  /* Set the DMA error callback */
2793  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2794 
2795  /* Set the unused DMA callbacks to NULL */
2796  hi2c->hdmatx->XferHalfCpltCallback = NULL;
2797  hi2c->hdmatx->XferAbortCallback = NULL;
2798 
2799  /* Enable the DMA stream */
2800  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
2801  }
2802  else
2803  {
2804  /* Update I2C state */
2805  hi2c->State = HAL_I2C_STATE_READY;
2806  hi2c->Mode = HAL_I2C_MODE_NONE;
2807 
2808  /* Update I2C error code */
2809  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2810 
2811  /* Process Unlocked */
2812  __HAL_UNLOCK(hi2c);
2813 
2814  return HAL_ERROR;
2815  }
2816 
2817  if (dmaxferstatus == HAL_OK)
2818  {
2819  /* Send Slave Address */
2820  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2821  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
2822 
2823  /* Update XferCount value */
2824  hi2c->XferCount -= hi2c->XferSize;
2825 
2826  /* Process Unlocked */
2827  __HAL_UNLOCK(hi2c);
2828 
2829  /* Note : The I2C interrupts must be enabled after unlocking current process
2830  to avoid the risk of I2C interrupt handle execution before current
2831  process unlock */
2832  /* Enable ERR and NACK interrupts */
2833  I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2834 
2835  /* Enable DMA Request */
2836  hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2837  }
2838  else
2839  {
2840  /* Update I2C state */
2841  hi2c->State = HAL_I2C_STATE_READY;
2842  hi2c->Mode = HAL_I2C_MODE_NONE;
2843 
2844  /* Update I2C error code */
2845  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2846 
2847  /* Process Unlocked */
2848  __HAL_UNLOCK(hi2c);
2849 
2850  return HAL_ERROR;
2851  }
2852 
2853  return HAL_OK;
2854  }
2855  else
2856  {
2857  return HAL_BUSY;
2858  }
2859 }
2860 
2873 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2874 {
2875  uint32_t tickstart;
2876  uint32_t xfermode;
2877  HAL_StatusTypeDef dmaxferstatus;
2878 
2879  /* Check the parameters */
2880  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2881 
2882  if (hi2c->State == HAL_I2C_STATE_READY)
2883  {
2884  if ((pData == NULL) || (Size == 0U))
2885  {
2886  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2887  return HAL_ERROR;
2888  }
2889 
2890  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2891  {
2892  return HAL_BUSY;
2893  }
2894 
2895  /* Process Locked */
2896  __HAL_LOCK(hi2c);
2897 
2898  /* Init tickstart for timeout management*/
2899  tickstart = HAL_GetTick();
2900 
2901  hi2c->State = HAL_I2C_STATE_BUSY_RX;
2902  hi2c->Mode = HAL_I2C_MODE_MEM;
2903  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2904 
2905  /* Prepare transfer parameters */
2906  hi2c->pBuffPtr = pData;
2907  hi2c->XferCount = Size;
2908  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2909  hi2c->XferISR = I2C_Master_ISR_DMA;
2910 
2911  if (hi2c->XferCount > MAX_NBYTE_SIZE)
2912  {
2913  hi2c->XferSize = MAX_NBYTE_SIZE;
2914  xfermode = I2C_RELOAD_MODE;
2915  }
2916  else
2917  {
2918  hi2c->XferSize = hi2c->XferCount;
2919  xfermode = I2C_AUTOEND_MODE;
2920  }
2921 
2922  /* Send Slave Address and Memory Address */
2923  if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2924  {
2925  /* Process Unlocked */
2926  __HAL_UNLOCK(hi2c);
2927  return HAL_ERROR;
2928  }
2929 
2930  if (hi2c->hdmarx != NULL)
2931  {
2932  /* Set the I2C DMA transfer complete callback */
2933  hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2934 
2935  /* Set the DMA error callback */
2936  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2937 
2938  /* Set the unused DMA callbacks to NULL */
2939  hi2c->hdmarx->XferHalfCpltCallback = NULL;
2940  hi2c->hdmarx->XferAbortCallback = NULL;
2941 
2942  /* Enable the DMA stream */
2943  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
2944  }
2945  else
2946  {
2947  /* Update I2C state */
2948  hi2c->State = HAL_I2C_STATE_READY;
2949  hi2c->Mode = HAL_I2C_MODE_NONE;
2950 
2951  /* Update I2C error code */
2952  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2953 
2954  /* Process Unlocked */
2955  __HAL_UNLOCK(hi2c);
2956 
2957  return HAL_ERROR;
2958  }
2959 
2960  if (dmaxferstatus == HAL_OK)
2961  {
2962  /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2963  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2964 
2965  /* Update XferCount value */
2966  hi2c->XferCount -= hi2c->XferSize;
2967 
2968  /* Process Unlocked */
2969  __HAL_UNLOCK(hi2c);
2970 
2971  /* Note : The I2C interrupts must be enabled after unlocking current process
2972  to avoid the risk of I2C interrupt handle execution before current
2973  process unlock */
2974  /* Enable ERR and NACK interrupts */
2975  I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2976 
2977  /* Enable DMA Request */
2978  hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2979  }
2980  else
2981  {
2982  /* Update I2C state */
2983  hi2c->State = HAL_I2C_STATE_READY;
2984  hi2c->Mode = HAL_I2C_MODE_NONE;
2985 
2986  /* Update I2C error code */
2987  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2988 
2989  /* Process Unlocked */
2990  __HAL_UNLOCK(hi2c);
2991 
2992  return HAL_ERROR;
2993  }
2994 
2995  return HAL_OK;
2996  }
2997  else
2998  {
2999  return HAL_BUSY;
3000  }
3001 }
3002 
3014 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3015 {
3016  uint32_t tickstart;
3017 
3018  __IO uint32_t I2C_Trials = 0UL;
3019 
3020  FlagStatus tmp1;
3021  FlagStatus tmp2;
3022 
3023  if (hi2c->State == HAL_I2C_STATE_READY)
3024  {
3025  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3026  {
3027  return HAL_BUSY;
3028  }
3029 
3030  /* Process Locked */
3031  __HAL_LOCK(hi2c);
3032 
3033  hi2c->State = HAL_I2C_STATE_BUSY;
3034  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3035 
3036  do
3037  {
3038  /* Generate Start */
3039  hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3040 
3041  /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3042  /* Wait until STOPF flag is set or a NACK flag is set*/
3043  tickstart = HAL_GetTick();
3044 
3045  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3046  tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3047 
3048  while ((tmp1 == RESET) && (tmp2 == RESET))
3049  {
3050  if (Timeout != HAL_MAX_DELAY)
3051  {
3052  if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3053  {
3054  /* Update I2C state */
3055  hi2c->State = HAL_I2C_STATE_READY;
3056 
3057  /* Update I2C error code */
3058  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3059 
3060  /* Process Unlocked */
3061  __HAL_UNLOCK(hi2c);
3062 
3063  return HAL_ERROR;
3064  }
3065  }
3066 
3067  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3068  tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3069  }
3070 
3071  /* Check if the NACKF flag has not been set */
3072  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3073  {
3074  /* Wait until STOPF flag is reset */
3075  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3076  {
3077  return HAL_ERROR;
3078  }
3079 
3080  /* Clear STOP Flag */
3081  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3082 
3083  /* Device is ready */
3084  hi2c->State = HAL_I2C_STATE_READY;
3085 
3086  /* Process Unlocked */
3087  __HAL_UNLOCK(hi2c);
3088 
3089  return HAL_OK;
3090  }
3091  else
3092  {
3093  /* Wait until STOPF flag is reset */
3094  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3095  {
3096  return HAL_ERROR;
3097  }
3098 
3099  /* Clear NACK Flag */
3100  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3101 
3102  /* Clear STOP Flag, auto generated with autoend*/
3103  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3104  }
3105 
3106  /* Check if the maximum allowed number of trials has been reached */
3107  if (I2C_Trials == Trials)
3108  {
3109  /* Generate Stop */
3110  hi2c->Instance->CR2 |= I2C_CR2_STOP;
3111 
3112  /* Wait until STOPF flag is reset */
3113  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3114  {
3115  return HAL_ERROR;
3116  }
3117 
3118  /* Clear STOP Flag */
3119  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3120  }
3121 
3122  /* Increment Trials */
3123  I2C_Trials++;
3124  }
3125  while (I2C_Trials < Trials);
3126 
3127  /* Update I2C state */
3128  hi2c->State = HAL_I2C_STATE_READY;
3129 
3130  /* Update I2C error code */
3131  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3132 
3133  /* Process Unlocked */
3134  __HAL_UNLOCK(hi2c);
3135 
3136  return HAL_ERROR;
3137  }
3138  else
3139  {
3140  return HAL_BUSY;
3141  }
3142 }
3143 
3156 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3157 {
3158  uint32_t xfermode;
3159  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3160 
3161  /* Check the parameters */
3162  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3163 
3164  if (hi2c->State == HAL_I2C_STATE_READY)
3165  {
3166  /* Process Locked */
3167  __HAL_LOCK(hi2c);
3168 
3169  hi2c->State = HAL_I2C_STATE_BUSY_TX;
3170  hi2c->Mode = HAL_I2C_MODE_MASTER;
3171  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3172 
3173  /* Prepare transfer parameters */
3174  hi2c->pBuffPtr = pData;
3175  hi2c->XferCount = Size;
3176  hi2c->XferOptions = XferOptions;
3177  hi2c->XferISR = I2C_Master_ISR_IT;
3178 
3179  /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3180  if (hi2c->XferCount > MAX_NBYTE_SIZE)
3181  {
3182  hi2c->XferSize = MAX_NBYTE_SIZE;
3183  xfermode = I2C_RELOAD_MODE;
3184  }
3185  else
3186  {
3187  hi2c->XferSize = hi2c->XferCount;
3188  xfermode = hi2c->XferOptions;
3189  }
3190 
3191  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3192  /* Mean Previous state is same as current state */
3193  if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3194  {
3195  xferrequest = I2C_NO_STARTSTOP;
3196  }
3197  else
3198  {
3199  /* Convert OTHER_xxx XferOptions if any */
3200  I2C_ConvertOtherXferOptions(hi2c);
3201 
3202  /* Update xfermode accordingly if no reload is necessary */
3203  if (hi2c->XferCount < MAX_NBYTE_SIZE)
3204  {
3205  xfermode = hi2c->XferOptions;
3206  }
3207  }
3208 
3209  /* Send Slave Address and set NBYTES to write */
3210  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3211 
3212  /* Process Unlocked */
3213  __HAL_UNLOCK(hi2c);
3214 
3215  /* Note : The I2C interrupts must be enabled after unlocking current process
3216  to avoid the risk of I2C interrupt handle execution before current
3217  process unlock */
3218  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3219 
3220  return HAL_OK;
3221  }
3222  else
3223  {
3224  return HAL_BUSY;
3225  }
3226 }
3227 
3240 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3241 {
3242  uint32_t xfermode;
3243  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3244  HAL_StatusTypeDef dmaxferstatus;
3245 
3246  /* Check the parameters */
3247  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3248 
3249  if (hi2c->State == HAL_I2C_STATE_READY)
3250  {
3251  /* Process Locked */
3252  __HAL_LOCK(hi2c);
3253 
3254  hi2c->State = HAL_I2C_STATE_BUSY_TX;
3255  hi2c->Mode = HAL_I2C_MODE_MASTER;
3256  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3257 
3258  /* Prepare transfer parameters */
3259  hi2c->pBuffPtr = pData;
3260  hi2c->XferCount = Size;
3261  hi2c->XferOptions = XferOptions;
3262  hi2c->XferISR = I2C_Master_ISR_DMA;
3263 
3264  /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3265  if (hi2c->XferCount > MAX_NBYTE_SIZE)
3266  {
3267  hi2c->XferSize = MAX_NBYTE_SIZE;
3268  xfermode = I2C_RELOAD_MODE;
3269  }
3270  else
3271  {
3272  hi2c->XferSize = hi2c->XferCount;
3273  xfermode = hi2c->XferOptions;
3274  }
3275 
3276  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3277  /* Mean Previous state is same as current state */
3278  if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3279  {
3280  xferrequest = I2C_NO_STARTSTOP;
3281  }
3282  else
3283  {
3284  /* Convert OTHER_xxx XferOptions if any */
3285  I2C_ConvertOtherXferOptions(hi2c);
3286 
3287  /* Update xfermode accordingly if no reload is necessary */
3288  if (hi2c->XferCount < MAX_NBYTE_SIZE)
3289  {
3290  xfermode = hi2c->XferOptions;
3291  }
3292  }
3293 
3294  if (hi2c->XferSize > 0U)
3295  {
3296  if (hi2c->hdmatx != NULL)
3297  {
3298  /* Set the I2C DMA transfer complete callback */
3299  hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3300 
3301  /* Set the DMA error callback */
3302  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3303 
3304  /* Set the unused DMA callbacks to NULL */
3305  hi2c->hdmatx->XferHalfCpltCallback = NULL;
3306  hi2c->hdmatx->XferAbortCallback = NULL;
3307 
3308  /* Enable the DMA stream */
3309  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
3310  }
3311  else
3312  {
3313  /* Update I2C state */
3314  hi2c->State = HAL_I2C_STATE_READY;
3315  hi2c->Mode = HAL_I2C_MODE_NONE;
3316 
3317  /* Update I2C error code */
3318  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3319 
3320  /* Process Unlocked */
3321  __HAL_UNLOCK(hi2c);
3322 
3323  return HAL_ERROR;
3324  }
3325 
3326  if (dmaxferstatus == HAL_OK)
3327  {
3328  /* Send Slave Address and set NBYTES to write */
3329  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3330 
3331  /* Update XferCount value */
3332  hi2c->XferCount -= hi2c->XferSize;
3333 
3334  /* Process Unlocked */
3335  __HAL_UNLOCK(hi2c);
3336 
3337  /* Note : The I2C interrupts must be enabled after unlocking current process
3338  to avoid the risk of I2C interrupt handle execution before current
3339  process unlock */
3340  /* Enable ERR and NACK interrupts */
3341  I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3342 
3343  /* Enable DMA Request */
3344  hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3345  }
3346  else
3347  {
3348  /* Update I2C state */
3349  hi2c->State = HAL_I2C_STATE_READY;
3350  hi2c->Mode = HAL_I2C_MODE_NONE;
3351 
3352  /* Update I2C error code */
3353  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3354 
3355  /* Process Unlocked */
3356  __HAL_UNLOCK(hi2c);
3357 
3358  return HAL_ERROR;
3359  }
3360  }
3361  else
3362  {
3363  /* Update Transfer ISR function pointer */
3364  hi2c->XferISR = I2C_Master_ISR_IT;
3365 
3366  /* Send Slave Address */
3367  /* Set NBYTES to write and generate START condition */
3368  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
3369 
3370  /* Process Unlocked */
3371  __HAL_UNLOCK(hi2c);
3372 
3373  /* Note : The I2C interrupts must be enabled after unlocking current process
3374  to avoid the risk of I2C interrupt handle execution before current
3375  process unlock */
3376  /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3377  /* possible to enable all of these */
3378  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3379  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3380  }
3381 
3382  return HAL_OK;
3383  }
3384  else
3385  {
3386  return HAL_BUSY;
3387  }
3388 }
3389 
3402 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3403 {
3404  uint32_t xfermode;
3405  uint32_t xferrequest = I2C_GENERATE_START_READ;
3406 
3407  /* Check the parameters */
3408  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3409 
3410  if (hi2c->State == HAL_I2C_STATE_READY)
3411  {
3412  /* Process Locked */
3413  __HAL_LOCK(hi2c);
3414 
3415  hi2c->State = HAL_I2C_STATE_BUSY_RX;
3416  hi2c->Mode = HAL_I2C_MODE_MASTER;
3417  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3418 
3419  /* Prepare transfer parameters */
3420  hi2c->pBuffPtr = pData;
3421  hi2c->XferCount = Size;
3422  hi2c->XferOptions = XferOptions;
3423  hi2c->XferISR = I2C_Master_ISR_IT;
3424 
3425  /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3426  if (hi2c->XferCount > MAX_NBYTE_SIZE)
3427  {
3428  hi2c->XferSize = MAX_NBYTE_SIZE;
3429  xfermode = I2C_RELOAD_MODE;
3430  }
3431  else
3432  {
3433  hi2c->XferSize = hi2c->XferCount;
3434  xfermode = hi2c->XferOptions;
3435  }
3436 
3437  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3438  /* Mean Previous state is same as current state */
3439  if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3440  {
3441  xferrequest = I2C_NO_STARTSTOP;
3442  }
3443  else
3444  {
3445  /* Convert OTHER_xxx XferOptions if any */
3446  I2C_ConvertOtherXferOptions(hi2c);
3447 
3448  /* Update xfermode accordingly if no reload is necessary */
3449  if (hi2c->XferCount < MAX_NBYTE_SIZE)
3450  {
3451  xfermode = hi2c->XferOptions;
3452  }
3453  }
3454 
3455  /* Send Slave Address and set NBYTES to read */
3456  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3457 
3458  /* Process Unlocked */
3459  __HAL_UNLOCK(hi2c);
3460 
3461  /* Note : The I2C interrupts must be enabled after unlocking current process
3462  to avoid the risk of I2C interrupt handle execution before current
3463  process unlock */
3464  I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3465 
3466  return HAL_OK;
3467  }
3468  else
3469  {
3470  return HAL_BUSY;
3471  }
3472 }
3473 
3486 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3487 {
3488  uint32_t xfermode;
3489  uint32_t xferrequest = I2C_GENERATE_START_READ;
3490  HAL_StatusTypeDef dmaxferstatus;
3491 
3492  /* Check the parameters */
3493  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3494 
3495  if (hi2c->State == HAL_I2C_STATE_READY)
3496  {
3497  /* Process Locked */
3498  __HAL_LOCK(hi2c);
3499 
3500  hi2c->State = HAL_I2C_STATE_BUSY_RX;
3501  hi2c->Mode = HAL_I2C_MODE_MASTER;
3502  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3503 
3504  /* Prepare transfer parameters */
3505  hi2c->pBuffPtr = pData;
3506  hi2c->XferCount = Size;
3507  hi2c->XferOptions = XferOptions;
3508  hi2c->XferISR = I2C_Master_ISR_DMA;
3509 
3510  /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3511  if (hi2c->XferCount > MAX_NBYTE_SIZE)
3512  {
3513  hi2c->XferSize = MAX_NBYTE_SIZE;
3514  xfermode = I2C_RELOAD_MODE;
3515  }
3516  else
3517  {
3518  hi2c->XferSize = hi2c->XferCount;
3519  xfermode = hi2c->XferOptions;
3520  }
3521 
3522  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3523  /* Mean Previous state is same as current state */
3524  if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3525  {
3526  xferrequest = I2C_NO_STARTSTOP;
3527  }
3528  else
3529  {
3530  /* Convert OTHER_xxx XferOptions if any */
3531  I2C_ConvertOtherXferOptions(hi2c);
3532 
3533  /* Update xfermode accordingly if no reload is necessary */
3534  if (hi2c->XferCount < MAX_NBYTE_SIZE)
3535  {
3536  xfermode = hi2c->XferOptions;
3537  }
3538  }
3539 
3540  if (hi2c->XferSize > 0U)
3541  {
3542  if (hi2c->hdmarx != NULL)
3543  {
3544  /* Set the I2C DMA transfer complete callback */
3545  hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3546 
3547  /* Set the DMA error callback */
3548  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3549 
3550  /* Set the unused DMA callbacks to NULL */
3551  hi2c->hdmarx->XferHalfCpltCallback = NULL;
3552  hi2c->hdmarx->XferAbortCallback = NULL;
3553 
3554  /* Enable the DMA stream */
3555  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
3556  }
3557  else
3558  {
3559  /* Update I2C state */
3560  hi2c->State = HAL_I2C_STATE_READY;
3561  hi2c->Mode = HAL_I2C_MODE_NONE;
3562 
3563  /* Update I2C error code */
3564  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3565 
3566  /* Process Unlocked */
3567  __HAL_UNLOCK(hi2c);
3568 
3569  return HAL_ERROR;
3570  }
3571 
3572  if (dmaxferstatus == HAL_OK)
3573  {
3574  /* Send Slave Address and set NBYTES to read */
3575  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3576 
3577  /* Update XferCount value */
3578  hi2c->XferCount -= hi2c->XferSize;
3579 
3580  /* Process Unlocked */
3581  __HAL_UNLOCK(hi2c);
3582 
3583  /* Note : The I2C interrupts must be enabled after unlocking current process
3584  to avoid the risk of I2C interrupt handle execution before current
3585  process unlock */
3586  /* Enable ERR and NACK interrupts */
3587  I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3588 
3589  /* Enable DMA Request */
3590  hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3591  }
3592  else
3593  {
3594  /* Update I2C state */
3595  hi2c->State = HAL_I2C_STATE_READY;
3596  hi2c->Mode = HAL_I2C_MODE_NONE;
3597 
3598  /* Update I2C error code */
3599  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3600 
3601  /* Process Unlocked */
3602  __HAL_UNLOCK(hi2c);
3603 
3604  return HAL_ERROR;
3605  }
3606  }
3607  else
3608  {
3609  /* Update Transfer ISR function pointer */
3610  hi2c->XferISR = I2C_Master_ISR_IT;
3611 
3612  /* Send Slave Address */
3613  /* Set NBYTES to read and generate START condition */
3614  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
3615 
3616  /* Process Unlocked */
3617  __HAL_UNLOCK(hi2c);
3618 
3619  /* Note : The I2C interrupts must be enabled after unlocking current process
3620  to avoid the risk of I2C interrupt handle execution before current
3621  process unlock */
3622  /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3623  /* possible to enable all of these */
3624  /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3625  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3626  }
3627 
3628  return HAL_OK;
3629  }
3630  else
3631  {
3632  return HAL_BUSY;
3633  }
3634 }
3635 
3646 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3647 {
3648  /* Check the parameters */
3649  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3650 
3651  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3652  {
3653  if ((pData == NULL) || (Size == 0U))
3654  {
3655  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3656  return HAL_ERROR;
3657  }
3658 
3659  /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3660  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3661 
3662  /* Process Locked */
3663  __HAL_LOCK(hi2c);
3664 
3665  /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3666  /* and then toggle the HAL slave RX state to TX state */
3667  if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3668  {
3669  /* Disable associated Interrupts */
3670  I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3671 
3672  /* Abort DMA Xfer if any */
3673  if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3674  {
3675  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3676 
3677  if (hi2c->hdmarx != NULL)
3678  {
3679  /* Set the I2C DMA Abort callback :
3680  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3681  hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3682 
3683  /* Abort DMA RX */
3684  if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3685  {
3686  /* Call Directly XferAbortCallback function in case of error */
3687  hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3688  }
3689  }
3690  }
3691  }
3692 
3693  hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3694  hi2c->Mode = HAL_I2C_MODE_SLAVE;
3695  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3696 
3697  /* Enable Address Acknowledge */
3698  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3699 
3700  /* Prepare transfer parameters */
3701  hi2c->pBuffPtr = pData;
3702  hi2c->XferCount = Size;
3703  hi2c->XferSize = hi2c->XferCount;
3704  hi2c->XferOptions = XferOptions;
3705  hi2c->XferISR = I2C_Slave_ISR_IT;
3706 
3707  if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
3708  {
3709  /* Clear ADDR flag after prepare the transfer parameters */
3710  /* This action will generate an acknowledge to the Master */
3711  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3712  }
3713 
3714  /* Process Unlocked */
3715  __HAL_UNLOCK(hi2c);
3716 
3717  /* Note : The I2C interrupts must be enabled after unlocking current process
3718  to avoid the risk of I2C interrupt handle execution before current
3719  process unlock */
3720  /* REnable ADDR interrupt */
3721  I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
3722 
3723  return HAL_OK;
3724  }
3725  else
3726  {
3727  return HAL_ERROR;
3728  }
3729 }
3730 
3741 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3742 {
3743  HAL_StatusTypeDef dmaxferstatus;
3744 
3745  /* Check the parameters */
3746  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3747 
3748  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3749  {
3750  if ((pData == NULL) || (Size == 0U))
3751  {
3752  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3753  return HAL_ERROR;
3754  }
3755 
3756  /* Process Locked */
3757  __HAL_LOCK(hi2c);
3758 
3759  /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3760  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3761 
3762  /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3763  /* and then toggle the HAL slave RX state to TX state */
3764  if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3765  {
3766  /* Disable associated Interrupts */
3767  I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3768 
3769  if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3770  {
3771  /* Abort DMA Xfer if any */
3772  if (hi2c->hdmarx != NULL)
3773  {
3774  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3775 
3776  /* Set the I2C DMA Abort callback :
3777  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3778  hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3779 
3780  /* Abort DMA RX */
3781  if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3782  {
3783  /* Call Directly XferAbortCallback function in case of error */
3784  hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3785  }
3786  }
3787  }
3788  }
3789  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
3790  {
3791  if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
3792  {
3793  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
3794 
3795  /* Abort DMA Xfer if any */
3796  if (hi2c->hdmatx != NULL)
3797  {
3798  /* Set the I2C DMA Abort callback :
3799  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3800  hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
3801 
3802  /* Abort DMA TX */
3803  if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
3804  {
3805  /* Call Directly XferAbortCallback function in case of error */
3806  hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
3807  }
3808  }
3809  }
3810  }
3811  else
3812  {
3813  /* Nothing to do */
3814  }
3815 
3816  hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3817  hi2c->Mode = HAL_I2C_MODE_SLAVE;
3818  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3819 
3820  /* Enable Address Acknowledge */
3821  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3822 
3823  /* Prepare transfer parameters */
3824  hi2c->pBuffPtr = pData;
3825  hi2c->XferCount = Size;
3826  hi2c->XferSize = hi2c->XferCount;
3827  hi2c->XferOptions = XferOptions;
3828  hi2c->XferISR = I2C_Slave_ISR_DMA;
3829 
3830  if (hi2c->hdmatx != NULL)
3831  {
3832  /* Set the I2C DMA transfer complete callback */
3833  hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
3834 
3835  /* Set the DMA error callback */
3836  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3837 
3838  /* Set the unused DMA callbacks to NULL */
3839  hi2c->hdmatx->XferHalfCpltCallback = NULL;
3840  hi2c->hdmatx->XferAbortCallback = NULL;
3841 
3842  /* Enable the DMA stream */
3843  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
3844  }
3845  else
3846  {
3847  /* Update I2C state */
3848  hi2c->State = HAL_I2C_STATE_LISTEN;
3849  hi2c->Mode = HAL_I2C_MODE_NONE;
3850 
3851  /* Update I2C error code */
3852  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3853 
3854  /* Process Unlocked */
3855  __HAL_UNLOCK(hi2c);
3856 
3857  return HAL_ERROR;
3858  }
3859 
3860  if (dmaxferstatus == HAL_OK)
3861  {
3862  /* Update XferCount value */
3863  hi2c->XferCount -= hi2c->XferSize;
3864 
3865  /* Reset XferSize */
3866  hi2c->XferSize = 0;
3867  }
3868  else
3869  {
3870  /* Update I2C state */
3871  hi2c->State = HAL_I2C_STATE_LISTEN;
3872  hi2c->Mode = HAL_I2C_MODE_NONE;
3873 
3874  /* Update I2C error code */
3875  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3876 
3877  /* Process Unlocked */
3878  __HAL_UNLOCK(hi2c);
3879 
3880  return HAL_ERROR;
3881  }
3882 
3883  if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
3884  {
3885  /* Clear ADDR flag after prepare the transfer parameters */
3886  /* This action will generate an acknowledge to the Master */
3887  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3888  }
3889 
3890  /* Process Unlocked */
3891  __HAL_UNLOCK(hi2c);
3892 
3893  /* Note : The I2C interrupts must be enabled after unlocking current process
3894  to avoid the risk of I2C interrupt handle execution before current
3895  process unlock */
3896  /* Enable ERR, STOP, NACK, ADDR interrupts */
3897  I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
3898 
3899  /* Enable DMA Request */
3900  hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3901 
3902  return HAL_OK;
3903  }
3904  else
3905  {
3906  return HAL_ERROR;
3907  }
3908 }
3909 
3920 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3921 {
3922  /* Check the parameters */
3923  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3924 
3925  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3926  {
3927  if ((pData == NULL) || (Size == 0U))
3928  {
3929  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3930  return HAL_ERROR;
3931  }
3932 
3933  /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3934  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
3935 
3936  /* Process Locked */
3937  __HAL_LOCK(hi2c);
3938 
3939  /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3940  /* and then toggle the HAL slave TX state to RX state */
3941  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
3942  {
3943  /* Disable associated Interrupts */
3944  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
3945 
3946  if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
3947  {
3948  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
3949 
3950  /* Abort DMA Xfer if any */
3951  if (hi2c->hdmatx != NULL)
3952  {
3953  /* Set the I2C DMA Abort callback :
3954  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3955  hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
3956 
3957  /* Abort DMA TX */
3958  if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
3959  {
3960  /* Call Directly XferAbortCallback function in case of error */
3961  hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
3962  }
3963  }
3964  }
3965  }
3966 
3967  hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
3968  hi2c->Mode = HAL_I2C_MODE_SLAVE;
3969  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3970 
3971  /* Enable Address Acknowledge */
3972  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3973 
3974  /* Prepare transfer parameters */
3975  hi2c->pBuffPtr = pData;
3976  hi2c->XferCount = Size;
3977  hi2c->XferSize = hi2c->XferCount;
3978  hi2c->XferOptions = XferOptions;
3979  hi2c->XferISR = I2C_Slave_ISR_IT;
3980 
3981  if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
3982  {
3983  /* Clear ADDR flag after prepare the transfer parameters */
3984  /* This action will generate an acknowledge to the Master */
3985  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3986  }
3987 
3988  /* Process Unlocked */
3989  __HAL_UNLOCK(hi2c);
3990 
3991  /* Note : The I2C interrupts must be enabled after unlocking current process
3992  to avoid the risk of I2C interrupt handle execution before current
3993  process unlock */
3994  /* REnable ADDR interrupt */
3995  I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
3996 
3997  return HAL_OK;
3998  }
3999  else
4000  {
4001  return HAL_ERROR;
4002  }
4003 }
4004 
4015 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4016 {
4017  HAL_StatusTypeDef dmaxferstatus;
4018 
4019  /* Check the parameters */
4020  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4021 
4022  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4023  {
4024  if ((pData == NULL) || (Size == 0U))
4025  {
4026  hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4027  return HAL_ERROR;
4028  }
4029 
4030  /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4031  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4032 
4033  /* Process Locked */
4034  __HAL_LOCK(hi2c);
4035 
4036  /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4037  /* and then toggle the HAL slave TX state to RX state */
4038  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4039  {
4040  /* Disable associated Interrupts */
4041  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4042 
4043  if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4044  {
4045  /* Abort DMA Xfer if any */
4046  if (hi2c->hdmatx != NULL)
4047  {
4048  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4049 
4050  /* Set the I2C DMA Abort callback :
4051  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4052  hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4053 
4054  /* Abort DMA TX */
4055  if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4056  {
4057  /* Call Directly XferAbortCallback function in case of error */
4058  hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4059  }
4060  }
4061  }
4062  }
4063  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4064  {
4065  if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4066  {
4067  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4068 
4069  /* Abort DMA Xfer if any */
4070  if (hi2c->hdmarx != NULL)
4071  {
4072  /* Set the I2C DMA Abort callback :
4073  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4074  hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4075 
4076  /* Abort DMA RX */
4077  if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4078  {
4079  /* Call Directly XferAbortCallback function in case of error */
4080  hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4081  }
4082  }
4083  }
4084  }
4085  else
4086  {
4087  /* Nothing to do */
4088  }
4089 
4090  hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4091  hi2c->Mode = HAL_I2C_MODE_SLAVE;
4092  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4093 
4094  /* Enable Address Acknowledge */
4095  hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4096 
4097  /* Prepare transfer parameters */
4098  hi2c->pBuffPtr = pData;
4099  hi2c->XferCount = Size;
4100  hi2c->XferSize = hi2c->XferCount;
4101  hi2c->XferOptions = XferOptions;
4102  hi2c->XferISR = I2C_Slave_ISR_DMA;
4103 
4104  if (hi2c->hdmarx != NULL)
4105  {
4106  /* Set the I2C DMA transfer complete callback */
4107  hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4108 
4109  /* Set the DMA error callback */
4110  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4111 
4112  /* Set the unused DMA callbacks to NULL */
4113  hi2c->hdmarx->XferHalfCpltCallback = NULL;
4114  hi2c->hdmarx->XferAbortCallback = NULL;
4115 
4116  /* Enable the DMA stream */
4117  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
4118  }
4119  else
4120  {
4121  /* Update I2C state */
4122  hi2c->State = HAL_I2C_STATE_LISTEN;
4123  hi2c->Mode = HAL_I2C_MODE_NONE;
4124 
4125  /* Update I2C error code */
4126  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4127 
4128  /* Process Unlocked */
4129  __HAL_UNLOCK(hi2c);
4130 
4131  return HAL_ERROR;
4132  }
4133 
4134  if (dmaxferstatus == HAL_OK)
4135  {
4136  /* Update XferCount value */
4137  hi2c->XferCount -= hi2c->XferSize;
4138 
4139  /* Reset XferSize */
4140  hi2c->XferSize = 0;
4141  }
4142  else
4143  {
4144  /* Update I2C state */
4145  hi2c->State = HAL_I2C_STATE_LISTEN;
4146  hi2c->Mode = HAL_I2C_MODE_NONE;
4147 
4148  /* Update I2C error code */
4149  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4150 
4151  /* Process Unlocked */
4152  __HAL_UNLOCK(hi2c);
4153 
4154  return HAL_ERROR;
4155  }
4156 
4157  if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
4158  {
4159  /* Clear ADDR flag after prepare the transfer parameters */
4160  /* This action will generate an acknowledge to the Master */
4161  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4162  }
4163 
4164  /* Process Unlocked */
4165  __HAL_UNLOCK(hi2c);
4166 
4167  /* Note : The I2C interrupts must be enabled after unlocking current process
4168  to avoid the risk of I2C interrupt handle execution before current
4169  process unlock */
4170  /* REnable ADDR interrupt */
4171  I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4172 
4173  /* Enable DMA Request */
4174  hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4175 
4176  return HAL_OK;
4177  }
4178  else
4179  {
4180  return HAL_ERROR;
4181  }
4182 }
4183 
4190 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4191 {
4192  if (hi2c->State == HAL_I2C_STATE_READY)
4193  {
4194  hi2c->State = HAL_I2C_STATE_LISTEN;
4195  hi2c->XferISR = I2C_Slave_ISR_IT;
4196 
4197  /* Enable the Address Match interrupt */
4198  I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4199 
4200  return HAL_OK;
4201  }
4202  else
4203  {
4204  return HAL_BUSY;
4205  }
4206 }
4207 
4214 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4215 {
4216  /* Declaration of tmp to prevent undefined behavior of volatile usage */
4217  uint32_t tmp;
4218 
4219  /* Disable Address listen mode only if a transfer is not ongoing */
4220  if (hi2c->State == HAL_I2C_STATE_LISTEN)
4221  {
4222  tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4223  hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4224  hi2c->State = HAL_I2C_STATE_READY;
4225  hi2c->Mode = HAL_I2C_MODE_NONE;
4226  hi2c->XferISR = NULL;
4227 
4228  /* Disable the Address Match interrupt */
4229  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4230 
4231  return HAL_OK;
4232  }
4233  else
4234  {
4235  return HAL_BUSY;
4236  }
4237 }
4238 
4247 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4248 {
4249  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4250  {
4251  /* Process Locked */
4252  __HAL_LOCK(hi2c);
4253 
4254  /* Disable Interrupts */
4255  I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4256  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4257 
4258  /* Set State at HAL_I2C_STATE_ABORT */
4259  hi2c->State = HAL_I2C_STATE_ABORT;
4260 
4261  /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4262  /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4263  I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4264 
4265  /* Process Unlocked */
4266  __HAL_UNLOCK(hi2c);
4267 
4268  /* Note : The I2C interrupts must be enabled after unlocking current process
4269  to avoid the risk of I2C interrupt handle execution before current
4270  process unlock */
4271  I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4272 
4273  return HAL_OK;
4274  }
4275  else
4276  {
4277  /* Wrong usage of abort function */
4278  /* This function should be used only in case of abort monitored by master device */
4279  return HAL_ERROR;
4280  }
4281 }
4282 
4297 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4298 {
4299  /* Get current IT Flags and IT sources value */
4300  uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4301  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4302 
4303  /* I2C events treatment -------------------------------------*/
4304  if (hi2c->XferISR != NULL)
4305  {
4306  hi2c->XferISR(hi2c, itflags, itsources);
4307  }
4308 }
4309 
4316 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4317 {
4318  uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4319  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4320  uint32_t tmperror;
4321 
4322  /* I2C Bus error interrupt occurred ------------------------------------*/
4323  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4324  {
4325  hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4326 
4327  /* Clear BERR flag */
4328  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4329  }
4330 
4331  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4332  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4333  {
4334  hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4335 
4336  /* Clear OVR flag */
4337  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4338  }
4339 
4340  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4341  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4342  {
4343  hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4344 
4345  /* Clear ARLO flag */
4346  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4347  }
4348 
4349  /* Store current volatile hi2c->ErrorCode, misra rule */
4350  tmperror = hi2c->ErrorCode;
4351 
4352  /* Call the Error Callback in case of Error detected */
4353  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4354  {
4355  I2C_ITError(hi2c, tmperror);
4356  }
4357 }
4358 
4365 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4366 {
4367  /* Prevent unused argument(s) compilation warning */
4368  UNUSED(hi2c);
4369 
4370  /* NOTE : This function should not be modified, when the callback is needed,
4371  the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4372  */
4373 }
4374 
4381 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4382 {
4383  /* Prevent unused argument(s) compilation warning */
4384  UNUSED(hi2c);
4385 
4386  /* NOTE : This function should not be modified, when the callback is needed,
4387  the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4388  */
4389 }
4390 
4396 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4397 {
4398  /* Prevent unused argument(s) compilation warning */
4399  UNUSED(hi2c);
4400 
4401  /* NOTE : This function should not be modified, when the callback is needed,
4402  the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4403  */
4404 }
4405 
4412 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4413 {
4414  /* Prevent unused argument(s) compilation warning */
4415  UNUSED(hi2c);
4416 
4417  /* NOTE : This function should not be modified, when the callback is needed,
4418  the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4419  */
4420 }
4421 
4430 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4431 {
4432  /* Prevent unused argument(s) compilation warning */
4433  UNUSED(hi2c);
4434  UNUSED(TransferDirection);
4435  UNUSED(AddrMatchCode);
4436 
4437  /* NOTE : This function should not be modified, when the callback is needed,
4438  the HAL_I2C_AddrCallback() could be implemented in the user file
4439  */
4440 }
4441 
4448 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4449 {
4450  /* Prevent unused argument(s) compilation warning */
4451  UNUSED(hi2c);
4452 
4453  /* NOTE : This function should not be modified, when the callback is needed,
4454  the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4455  */
4456 }
4457 
4464 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4465 {
4466  /* Prevent unused argument(s) compilation warning */
4467  UNUSED(hi2c);
4468 
4469  /* NOTE : This function should not be modified, when the callback is needed,
4470  the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4471  */
4472 }
4473 
4480 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4481 {
4482  /* Prevent unused argument(s) compilation warning */
4483  UNUSED(hi2c);
4484 
4485  /* NOTE : This function should not be modified, when the callback is needed,
4486  the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4487  */
4488 }
4489 
4496 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4497 {
4498  /* Prevent unused argument(s) compilation warning */
4499  UNUSED(hi2c);
4500 
4501  /* NOTE : This function should not be modified, when the callback is needed,
4502  the HAL_I2C_ErrorCallback could be implemented in the user file
4503  */
4504 }
4505 
4512 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4513 {
4514  /* Prevent unused argument(s) compilation warning */
4515  UNUSED(hi2c);
4516 
4517  /* NOTE : This function should not be modified, when the callback is needed,
4518  the HAL_I2C_AbortCpltCallback could be implemented in the user file
4519  */
4520 }
4521 
4547 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
4548 {
4549  /* Return I2C handle state */
4550  return hi2c->State;
4551 }
4552 
4559 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
4560 {
4561  return hi2c->Mode;
4562 }
4563 
4570 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
4571 {
4572  return hi2c->ErrorCode;
4573 }
4574 
4595 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
4596 {
4597  uint16_t devaddress;
4598  uint32_t tmpITFlags = ITFlags;
4599 
4600  /* Process Locked */
4601  __HAL_LOCK(hi2c);
4602 
4603  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4604  {
4605  /* Clear NACK Flag */
4606  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4607 
4608  /* Set corresponding Error Code */
4609  /* No need to generate STOP, it is automatically done */
4610  /* Error callback will be send during stop flag treatment */
4611  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4612 
4613  /* Flush TX register */
4614  I2C_Flush_TXDR(hi2c);
4615  }
4616  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4617  {
4618  /* Remove RXNE flag on temporary variable as read done */
4619  tmpITFlags &= ~I2C_FLAG_RXNE;
4620 
4621  /* Read data from RXDR */
4622  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4623 
4624  /* Increment Buffer pointer */
4625  hi2c->pBuffPtr++;
4626 
4627  hi2c->XferSize--;
4628  hi2c->XferCount--;
4629  }
4630  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4631  {
4632  /* Write data to TXDR */
4633  hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4634 
4635  /* Increment Buffer pointer */
4636  hi2c->pBuffPtr++;
4637 
4638  hi2c->XferSize--;
4639  hi2c->XferCount--;
4640  }
4641  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4642  {
4643  if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
4644  {
4645  devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
4646 
4647  if (hi2c->XferCount > MAX_NBYTE_SIZE)
4648  {
4649  hi2c->XferSize = MAX_NBYTE_SIZE;
4650  I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
4651  }
4652  else
4653  {
4654  hi2c->XferSize = hi2c->XferCount;
4655  if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4656  {
4657  I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
4658  }
4659  else
4660  {
4661  I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
4662  }
4663  }
4664  }
4665  else
4666  {
4667  /* Call TxCpltCallback() if no stop mode is set */
4668  if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4669  {
4670  /* Call I2C Master Sequential complete process */
4671  I2C_ITMasterSeqCplt(hi2c);
4672  }
4673  else
4674  {
4675  /* Wrong size Status regarding TCR flag event */
4676  /* Call the corresponding callback to inform upper layer of End of Transfer */
4677  I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4678  }
4679  }
4680  }
4681  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4682  {
4683  if (hi2c->XferCount == 0U)
4684  {
4685  if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4686  {
4687  /* Generate a stop condition in case of no transfer option */
4688  if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
4689  {
4690  /* Generate Stop */
4691  hi2c->Instance->CR2 |= I2C_CR2_STOP;
4692  }
4693  else
4694  {
4695  /* Call I2C Master Sequential complete process */
4696  I2C_ITMasterSeqCplt(hi2c);
4697  }
4698  }
4699  }
4700  else
4701  {
4702  /* Wrong size Status regarding TC flag event */
4703  /* Call the corresponding callback to inform upper layer of End of Transfer */
4704  I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4705  }
4706  }
4707  else
4708  {
4709  /* Nothing to do */
4710  }
4711 
4712  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
4713  {
4714  /* Call I2C Master complete process */
4715  I2C_ITMasterCplt(hi2c, tmpITFlags);
4716  }
4717 
4718  /* Process Unlocked */
4719  __HAL_UNLOCK(hi2c);
4720 
4721  return HAL_OK;
4722 }
4723 
4732 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
4733 {
4734  uint32_t tmpoptions = hi2c->XferOptions;
4735  uint32_t tmpITFlags = ITFlags;
4736 
4737  /* Process locked */
4738  __HAL_LOCK(hi2c);
4739 
4740  /* Check if STOPF is set */
4741  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
4742  {
4743  /* Call I2C Slave complete process */
4744  I2C_ITSlaveCplt(hi2c, tmpITFlags);
4745  }
4746 
4747  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4748  {
4749  /* Check that I2C transfer finished */
4750  /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
4751  /* Mean XferCount == 0*/
4752  /* So clear Flag NACKF only */
4753  if (hi2c->XferCount == 0U)
4754  {
4755  if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
4756  {
4757  /* Call I2C Listen complete process */
4758  I2C_ITListenCplt(hi2c, tmpITFlags);
4759  }
4760  else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
4761  {
4762  /* Clear NACK Flag */
4763  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4764 
4765  /* Flush TX register */
4766  I2C_Flush_TXDR(hi2c);
4767 
4768  /* Last Byte is Transmitted */
4769  /* Call I2C Slave Sequential complete process */
4770  I2C_ITSlaveSeqCplt(hi2c);
4771  }
4772  else
4773  {
4774  /* Clear NACK Flag */
4775  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4776  }
4777  }
4778  else
4779  {
4780  /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
4781  /* Clear NACK Flag */
4782  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4783 
4784  /* Set ErrorCode corresponding to a Non-Acknowledge */
4785  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4786 
4787  if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
4788  {
4789  /* Call the corresponding callback to inform upper layer of End of Transfer */
4790  I2C_ITError(hi2c, hi2c->ErrorCode);
4791  }
4792  }
4793  }
4794  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4795  {
4796  if (hi2c->XferCount > 0U)
4797  {
4798  /* Read data from RXDR */
4799  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4800 
4801  /* Increment Buffer pointer */
4802  hi2c->pBuffPtr++;
4803 
4804  hi2c->XferSize--;
4805  hi2c->XferCount--;
4806  }
4807 
4808  if ((hi2c->XferCount == 0U) && \
4809  (tmpoptions != I2C_NO_OPTION_FRAME))
4810  {
4811  /* Call I2C Slave Sequential complete process */
4812  I2C_ITSlaveSeqCplt(hi2c);
4813  }
4814  }
4815  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
4816  {
4817  I2C_ITAddrCplt(hi2c, tmpITFlags);
4818  }
4819  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4820  {
4821  /* Write data to TXDR only if XferCount not reach "0" */
4822  /* A TXIS flag can be set, during STOP treatment */
4823  /* Check if all Datas have already been sent */
4824  /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
4825  if (hi2c->XferCount > 0U)
4826  {
4827  /* Write data to TXDR */
4828  hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4829 
4830  /* Increment Buffer pointer */
4831  hi2c->pBuffPtr++;
4832 
4833  hi2c->XferCount--;
4834  hi2c->XferSize--;
4835  }
4836  else
4837  {
4838  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
4839  {
4840  /* Last Byte is Transmitted */
4841  /* Call I2C Slave Sequential complete process */
4842  I2C_ITSlaveSeqCplt(hi2c);
4843  }
4844  }
4845  }
4846  else
4847  {
4848  /* Nothing to do */
4849  }
4850 
4851  /* Process Unlocked */
4852  __HAL_UNLOCK(hi2c);
4853 
4854  return HAL_OK;
4855 }
4856 
4865 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
4866 {
4867  uint16_t devaddress;
4868  uint32_t xfermode;
4869 
4870  /* Process Locked */
4871  __HAL_LOCK(hi2c);
4872 
4873  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4874  {
4875  /* Clear NACK Flag */
4876  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4877 
4878  /* Set corresponding Error Code */
4879  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4880 
4881  /* No need to generate STOP, it is automatically done */
4882  /* But enable STOP interrupt, to treat it */
4883  /* Error callback will be send during stop flag treatment */
4884  I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4885 
4886  /* Flush TX register */
4887  I2C_Flush_TXDR(hi2c);
4888  }
4889  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4890  {
4891  /* Disable TC interrupt */
4892  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
4893 
4894  if (hi2c->XferCount != 0U)
4895  {
4896  /* Recover Slave address */
4897  devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
4898 
4899  /* Prepare the new XferSize to transfer */
4900  if (hi2c->XferCount > MAX_NBYTE_SIZE)
4901  {
4902  hi2c->XferSize = MAX_NBYTE_SIZE;
4903  xfermode = I2C_RELOAD_MODE;
4904  }
4905  else
4906  {
4907  hi2c->XferSize = hi2c->XferCount;
4908  if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4909  {
4910  xfermode = hi2c->XferOptions;
4911  }
4912  else
4913  {
4914  xfermode = I2C_AUTOEND_MODE;
4915  }
4916  }
4917 
4918  /* Set the new XferSize in Nbytes register */
4919  I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
4920 
4921  /* Update XferCount value */
4922  hi2c->XferCount -= hi2c->XferSize;
4923 
4924  /* Enable DMA Request */
4925  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4926  {
4927  hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4928  }
4929  else
4930  {
4931  hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4932  }
4933  }
4934  else
4935  {
4936  /* Call TxCpltCallback() if no stop mode is set */
4937  if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4938  {
4939  /* Call I2C Master Sequential complete process */
4940  I2C_ITMasterSeqCplt(hi2c);
4941  }
4942  else
4943  {
4944  /* Wrong size Status regarding TCR flag event */
4945  /* Call the corresponding callback to inform upper layer of End of Transfer */
4946  I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4947  }
4948  }
4949  }
4950  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4951  {
4952  if (hi2c->XferCount == 0U)
4953  {
4954  if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4955  {
4956  /* Generate a stop condition in case of no transfer option */
4957  if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
4958  {
4959  /* Generate Stop */
4960  hi2c->Instance->CR2 |= I2C_CR2_STOP;
4961  }
4962  else
4963  {
4964  /* Call I2C Master Sequential complete process */
4965  I2C_ITMasterSeqCplt(hi2c);
4966  }
4967  }
4968  }
4969  else
4970  {
4971  /* Wrong size Status regarding TC flag event */
4972  /* Call the corresponding callback to inform upper layer of End of Transfer */
4973  I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4974  }
4975  }
4976  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
4977  {
4978  /* Call I2C Master complete process */
4979  I2C_ITMasterCplt(hi2c, ITFlags);
4980  }
4981  else
4982  {
4983  /* Nothing to do */
4984  }
4985 
4986  /* Process Unlocked */
4987  __HAL_UNLOCK(hi2c);
4988 
4989  return HAL_OK;
4990 }
4991 
5000 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
5001 {
5002  uint32_t tmpoptions = hi2c->XferOptions;
5003  uint32_t treatdmanack = 0U;
5004 
5005  /* Process locked */
5006  __HAL_LOCK(hi2c);
5007 
5008  /* Check if STOPF is set */
5009  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5010  {
5011  /* Call I2C Slave complete process */
5012  I2C_ITSlaveCplt(hi2c, ITFlags);
5013  }
5014 
5015  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5016  {
5017  /* Check that I2C transfer finished */
5018  /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5019  /* Mean XferCount == 0 */
5020  /* So clear Flag NACKF only */
5021  if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5022  (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5023  {
5024  /* Split check of hdmarx, for MISRA compliance */
5025  if (hi2c->hdmarx != NULL)
5026  {
5027  if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5028  {
5029  if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
5030  {
5031  treatdmanack = 1U;
5032  }
5033  }
5034  }
5035 
5036  /* Split check of hdmatx, for MISRA compliance */
5037  if (hi2c->hdmatx != NULL)
5038  {
5039  if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5040  {
5041  if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
5042  {
5043  treatdmanack = 1U;
5044  }
5045  }
5046  }
5047 
5048  if (treatdmanack == 1U)
5049  {
5050  if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
5051  {
5052  /* Call I2C Listen complete process */
5053  I2C_ITListenCplt(hi2c, ITFlags);
5054  }
5055  else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5056  {
5057  /* Clear NACK Flag */
5058  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5059 
5060  /* Flush TX register */
5061  I2C_Flush_TXDR(hi2c);
5062 
5063  /* Last Byte is Transmitted */
5064  /* Call I2C Slave Sequential complete process */
5065  I2C_ITSlaveSeqCplt(hi2c);
5066  }
5067  else
5068  {
5069  /* Clear NACK Flag */
5070  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5071  }
5072  }
5073  else
5074  {
5075  /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5076  /* Clear NACK Flag */
5077  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5078 
5079  /* Set ErrorCode corresponding to a Non-Acknowledge */
5080  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5081 
5082  if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5083  {
5084  /* Call the corresponding callback to inform upper layer of End of Transfer */
5085  I2C_ITError(hi2c, hi2c->ErrorCode);
5086  }
5087  }
5088  }
5089  else
5090  {
5091  /* Only Clear NACK Flag, no DMA treatment is pending */
5092  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5093  }
5094  }
5095  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5096  {
5097  I2C_ITAddrCplt(hi2c, ITFlags);
5098  }
5099  else
5100  {
5101  /* Nothing to do */
5102  }
5103 
5104  /* Process Unlocked */
5105  __HAL_UNLOCK(hi2c);
5106 
5107  return HAL_OK;
5108 }
5109 
5122 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
5123 {
5124  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5125 
5126  /* Wait until TXIS flag is set */
5127  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5128  {
5129  return HAL_ERROR;
5130  }
5131 
5132  /* If Memory address size is 8Bit */
5133  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5134  {
5135  /* Send Memory Address */
5136  hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5137  }
5138  /* If Memory address size is 16Bit */
5139  else
5140  {
5141  /* Send MSB of Memory Address */
5142  hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5143 
5144  /* Wait until TXIS flag is set */
5145  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5146  {
5147  return HAL_ERROR;
5148  }
5149 
5150  /* Send LSB of Memory Address */
5151  hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5152  }
5153 
5154  /* Wait until TCR flag is set */
5155  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5156  {
5157  return HAL_ERROR;
5158  }
5159 
5160  return HAL_OK;
5161 }
5162 
5175 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
5176 {
5177  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5178 
5179  /* Wait until TXIS flag is set */
5180  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5181  {
5182  return HAL_ERROR;
5183  }
5184 
5185  /* If Memory address size is 8Bit */
5186  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5187  {
5188  /* Send Memory Address */
5189  hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5190  }
5191  /* If Memory address size is 16Bit */
5192  else
5193  {
5194  /* Send MSB of Memory Address */
5195  hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5196 
5197  /* Wait until TXIS flag is set */
5198  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5199  {
5200  return HAL_ERROR;
5201  }
5202 
5203  /* Send LSB of Memory Address */
5204  hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5205  }
5206 
5207  /* Wait until TC flag is set */
5208  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5209  {
5210  return HAL_ERROR;
5211  }
5212 
5213  return HAL_OK;
5214 }
5215 
5222 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5223 {
5224  uint8_t transferdirection;
5225  uint16_t slaveaddrcode;
5226  uint16_t ownadd1code;
5227  uint16_t ownadd2code;
5228 
5229  /* Prevent unused argument(s) compilation warning */
5230  UNUSED(ITFlags);
5231 
5232  /* In case of Listen state, need to inform upper layer of address match code event */
5233  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5234  {
5235  transferdirection = I2C_GET_DIR(hi2c);
5236  slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5237  ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5238  ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5239 
5240  /* If 10bits addressing mode is selected */
5241  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5242  {
5243  if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
5244  {
5245  slaveaddrcode = ownadd1code;
5246  hi2c->AddrEventCount++;
5247  if (hi2c->AddrEventCount == 2U)
5248  {
5249  /* Reset Address Event counter */
5250  hi2c->AddrEventCount = 0U;
5251 
5252  /* Clear ADDR flag */
5253  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5254 
5255  /* Process Unlocked */
5256  __HAL_UNLOCK(hi2c);
5257 
5258  /* Call Slave Addr callback */
5259 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5260  hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5261 #else
5262  HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5263 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5264  }
5265  }
5266  else
5267  {
5268  slaveaddrcode = ownadd2code;
5269 
5270  /* Disable ADDR Interrupts */
5271  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5272 
5273  /* Process Unlocked */
5274  __HAL_UNLOCK(hi2c);
5275 
5276  /* Call Slave Addr callback */
5277 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5278  hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5279 #else
5280  HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5281 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5282  }
5283  }
5284  /* else 7 bits addressing mode is selected */
5285  else
5286  {
5287  /* Disable ADDR Interrupts */
5288  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5289 
5290  /* Process Unlocked */
5291  __HAL_UNLOCK(hi2c);
5292 
5293  /* Call Slave Addr callback */
5294 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5295  hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5296 #else
5297  HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5298 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5299  }
5300  }
5301  /* Else clear address flag only */
5302  else
5303  {
5304  /* Clear ADDR flag */
5305  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5306 
5307  /* Process Unlocked */
5308  __HAL_UNLOCK(hi2c);
5309  }
5310 }
5311 
5317 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
5318 {
5319  /* Reset I2C handle mode */
5320  hi2c->Mode = HAL_I2C_MODE_NONE;
5321 
5322  /* No Generate Stop, to permit restart mode */
5323  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
5324  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5325  {
5326  hi2c->State = HAL_I2C_STATE_READY;
5327  hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5328  hi2c->XferISR = NULL;
5329 
5330  /* Disable Interrupts */
5331  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5332 
5333  /* Process Unlocked */
5334  __HAL_UNLOCK(hi2c);
5335 
5336  /* Call the corresponding callback to inform upper layer of End of Transfer */
5337 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5338  hi2c->MasterTxCpltCallback(hi2c);
5339 #else
5340  HAL_I2C_MasterTxCpltCallback(hi2c);
5341 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5342  }
5343  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
5344  else
5345  {
5346  hi2c->State = HAL_I2C_STATE_READY;
5347  hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5348  hi2c->XferISR = NULL;
5349 
5350  /* Disable Interrupts */
5351  I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5352 
5353  /* Process Unlocked */
5354  __HAL_UNLOCK(hi2c);
5355 
5356  /* Call the corresponding callback to inform upper layer of End of Transfer */
5357 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5358  hi2c->MasterRxCpltCallback(hi2c);
5359 #else
5360  HAL_I2C_MasterRxCpltCallback(hi2c);
5361 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5362  }
5363 }
5364 
5370 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
5371 {
5372  /* Reset I2C handle mode */
5373  hi2c->Mode = HAL_I2C_MODE_NONE;
5374 
5375  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
5376  {
5377  /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
5378  hi2c->State = HAL_I2C_STATE_LISTEN;
5379  hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5380 
5381  /* Disable Interrupts */
5382  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5383 
5384  /* Process Unlocked */
5385  __HAL_UNLOCK(hi2c);
5386 
5387  /* Call the corresponding callback to inform upper layer of End of Transfer */
5388 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5389  hi2c->SlaveTxCpltCallback(hi2c);
5390 #else
5391  HAL_I2C_SlaveTxCpltCallback(hi2c);
5392 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5393  }
5394 
5395  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
5396  {
5397  /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
5398  hi2c->State = HAL_I2C_STATE_LISTEN;
5399  hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5400 
5401  /* Disable Interrupts */
5402  I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5403 
5404  /* Process Unlocked */
5405  __HAL_UNLOCK(hi2c);
5406 
5407  /* Call the corresponding callback to inform upper layer of End of Transfer */
5408 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5409  hi2c->SlaveRxCpltCallback(hi2c);
5410 #else
5411  HAL_I2C_SlaveRxCpltCallback(hi2c);
5412 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5413  }
5414  else
5415  {
5416  /* Nothing to do */
5417  }
5418 }
5419 
5426 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5427 {
5428  uint32_t tmperror;
5429 
5430  /* Clear STOP Flag */
5431  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5432 
5433  /* Clear Configuration Register 2 */
5434  I2C_RESET_CR2(hi2c);
5435 
5436  /* Reset handle parameters */
5437  hi2c->PreviousState = I2C_STATE_NONE;
5438  hi2c->XferISR = NULL;
5439  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
5440 
5441  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
5442  {
5443  /* Clear NACK Flag */
5444  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5445 
5446  /* Set acknowledge error code */
5447  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5448  }
5449 
5450  /* Flush TX register */
5451  I2C_Flush_TXDR(hi2c);
5452 
5453  /* Disable Interrupts */
5454  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
5455 
5456  /* Store current volatile hi2c->ErrorCode, misra rule */
5457  tmperror = hi2c->ErrorCode;
5458 
5459  /* Call the corresponding callback to inform upper layer of End of Transfer */
5460  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
5461  {
5462  /* Call the corresponding callback to inform upper layer of End of Transfer */
5463  I2C_ITError(hi2c, hi2c->ErrorCode);
5464  }
5465  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
5466  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5467  {
5468  hi2c->State = HAL_I2C_STATE_READY;
5469 
5470  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5471  {
5472  hi2c->Mode = HAL_I2C_MODE_NONE;
5473 
5474  /* Process Unlocked */
5475  __HAL_UNLOCK(hi2c);
5476 
5477  /* Call the corresponding callback to inform upper layer of End of Transfer */
5478 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5479  hi2c->MemTxCpltCallback(hi2c);
5480 #else
5481  HAL_I2C_MemTxCpltCallback(hi2c);
5482 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5483  }
5484  else
5485  {
5486  hi2c->Mode = HAL_I2C_MODE_NONE;
5487 
5488  /* Process Unlocked */
5489  __HAL_UNLOCK(hi2c);
5490 
5491  /* Call the corresponding callback to inform upper layer of End of Transfer */
5492 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5493  hi2c->MasterTxCpltCallback(hi2c);
5494 #else
5495  HAL_I2C_MasterTxCpltCallback(hi2c);
5496 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5497  }
5498  }
5499  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
5500  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5501  {
5502  hi2c->State = HAL_I2C_STATE_READY;
5503 
5504  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5505  {
5506  hi2c->Mode = HAL_I2C_MODE_NONE;
5507 
5508  /* Process Unlocked */
5509  __HAL_UNLOCK(hi2c);
5510 
5511  /* Call the corresponding callback to inform upper layer of End of Transfer */
5512 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5513  hi2c->MemRxCpltCallback(hi2c);
5514 #else
5515  HAL_I2C_MemRxCpltCallback(hi2c);
5516 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5517  }
5518  else
5519  {
5520  hi2c->Mode = HAL_I2C_MODE_NONE;
5521 
5522  /* Process Unlocked */
5523  __HAL_UNLOCK(hi2c);
5524 
5525  /* Call the corresponding callback to inform upper layer of End of Transfer */
5526 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5527  hi2c->MasterRxCpltCallback(hi2c);
5528 #else
5529  HAL_I2C_MasterRxCpltCallback(hi2c);
5530 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5531  }
5532  }
5533  else
5534  {
5535  /* Nothing to do */
5536  }
5537 }
5538 
5545 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5546 {
5547  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
5548  uint32_t tmpITFlags = ITFlags;
5549 
5550  /* Clear STOP Flag */
5551  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5552 
5553  /* Disable all interrupts */
5554  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
5555 
5556  /* Disable Address Acknowledge */
5557  hi2c->Instance->CR2 |= I2C_CR2_NACK;
5558 
5559  /* Clear Configuration Register 2 */
5560  I2C_RESET_CR2(hi2c);
5561 
5562  /* Flush TX register */
5563  I2C_Flush_TXDR(hi2c);
5564 
5565  /* If a DMA is ongoing, Update handle size context */
5566  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
5567  {
5568  if (hi2c->hdmatx != NULL)
5569  {
5570  hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
5571  }
5572  }
5573  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
5574  {
5575  if (hi2c->hdmarx != NULL)
5576  {
5577  hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
5578  }
5579  }
5580  else
5581  {
5582  /* Do nothing */
5583  }
5584 
5585  /* Store Last receive data if any */
5586  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
5587  {
5588  /* Remove RXNE flag on temporary variable as read done */
5589  tmpITFlags &= ~I2C_FLAG_RXNE;
5590 
5591  /* Read data from RXDR */
5592  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5593 
5594  /* Increment Buffer pointer */
5595  hi2c->pBuffPtr++;
5596 
5597  if ((hi2c->XferSize > 0U))
5598  {
5599  hi2c->XferSize--;
5600  hi2c->XferCount--;
5601  }
5602  }
5603 
5604  /* All data are not transferred, so set error code accordingly */
5605  if (hi2c->XferCount != 0U)
5606  {
5607  /* Set ErrorCode corresponding to a Non-Acknowledge */
5608  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5609  }
5610 
5611  hi2c->PreviousState = I2C_STATE_NONE;
5612  hi2c->Mode = HAL_I2C_MODE_NONE;
5613  hi2c->XferISR = NULL;
5614 
5615  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
5616  {
5617  /* Call the corresponding callback to inform upper layer of End of Transfer */
5618  I2C_ITError(hi2c, hi2c->ErrorCode);
5619 
5620  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
5621  if (hi2c->State == HAL_I2C_STATE_LISTEN)
5622  {
5623  /* Call I2C Listen complete process */
5624  I2C_ITListenCplt(hi2c, tmpITFlags);
5625  }
5626  }
5627  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5628  {
5629  /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
5630  I2C_ITSlaveSeqCplt(hi2c);
5631 
5632  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
5633  hi2c->State = HAL_I2C_STATE_READY;
5634 
5635  /* Process Unlocked */
5636  __HAL_UNLOCK(hi2c);
5637 
5638  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
5639 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5640  hi2c->ListenCpltCallback(hi2c);
5641 #else
5642  HAL_I2C_ListenCpltCallback(hi2c);
5643 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5644  }
5645  /* Call the corresponding callback to inform upper layer of End of Transfer */
5646  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5647  {
5648  hi2c->State = HAL_I2C_STATE_READY;
5649 
5650  /* Process Unlocked */
5651  __HAL_UNLOCK(hi2c);
5652 
5653  /* Call the corresponding callback to inform upper layer of End of Transfer */
5654 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5655  hi2c->SlaveRxCpltCallback(hi2c);
5656 #else
5657  HAL_I2C_SlaveRxCpltCallback(hi2c);
5658 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5659  }
5660  else
5661  {
5662  hi2c->State = HAL_I2C_STATE_READY;
5663 
5664  /* Process Unlocked */
5665  __HAL_UNLOCK(hi2c);
5666 
5667  /* Call the corresponding callback to inform upper layer of End of Transfer */
5668 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5669  hi2c->SlaveTxCpltCallback(hi2c);
5670 #else
5671  HAL_I2C_SlaveTxCpltCallback(hi2c);
5672 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5673  }
5674 }
5675 
5682 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5683 {
5684  /* Reset handle parameters */
5685  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
5686  hi2c->PreviousState = I2C_STATE_NONE;
5687  hi2c->State = HAL_I2C_STATE_READY;
5688  hi2c->Mode = HAL_I2C_MODE_NONE;
5689  hi2c->XferISR = NULL;
5690 
5691  /* Store Last receive data if any */
5692  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
5693  {
5694  /* Read data from RXDR */
5695  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5696 
5697  /* Increment Buffer pointer */
5698  hi2c->pBuffPtr++;
5699 
5700  if ((hi2c->XferSize > 0U))
5701  {
5702  hi2c->XferSize--;
5703  hi2c->XferCount--;
5704 
5705  /* Set ErrorCode corresponding to a Non-Acknowledge */
5706  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5707  }
5708  }
5709 
5710  /* Disable all Interrupts*/
5711  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
5712 
5713  /* Clear NACK Flag */
5714  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5715 
5716  /* Process Unlocked */
5717  __HAL_UNLOCK(hi2c);
5718 
5719  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
5720 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5721  hi2c->ListenCpltCallback(hi2c);
5722 #else
5723  HAL_I2C_ListenCpltCallback(hi2c);
5724 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5725 }
5726 
5733 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
5734 {
5735  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
5736 
5737  /* Reset handle parameters */
5738  hi2c->Mode = HAL_I2C_MODE_NONE;
5739  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
5740  hi2c->XferCount = 0U;
5741 
5742  /* Set new error code */
5743  hi2c->ErrorCode |= ErrorCode;
5744 
5745  /* Disable Interrupts */
5746  if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
5747  (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
5748  (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5749  {
5750  /* Disable all interrupts, except interrupts related to LISTEN state */
5751  I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
5752 
5753  /* keep HAL_I2C_STATE_LISTEN if set */
5754  hi2c->State = HAL_I2C_STATE_LISTEN;
5755  hi2c->PreviousState = I2C_STATE_NONE;
5756  hi2c->XferISR = I2C_Slave_ISR_IT;
5757  }
5758  else
5759  {
5760  /* Disable all interrupts */
5761  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
5762 
5763  /* If state is an abort treatment on goind, don't change state */
5764  /* This change will be do later */
5765  if (hi2c->State != HAL_I2C_STATE_ABORT)
5766  {
5767  /* Set HAL_I2C_STATE_READY */
5768  hi2c->State = HAL_I2C_STATE_READY;
5769  }
5770  hi2c->PreviousState = I2C_STATE_NONE;
5771  hi2c->XferISR = NULL;
5772  }
5773 
5774  /* Abort DMA TX transfer if any */
5775  if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
5776  {
5777  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
5778 
5779  if (hi2c->hdmatx != NULL)
5780  {
5781  /* Set the I2C DMA Abort callback :
5782  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
5783  hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
5784 
5785  /* Process Unlocked */
5786  __HAL_UNLOCK(hi2c);
5787 
5788  /* Abort DMA TX */
5789  if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
5790  {
5791  /* Call Directly XferAbortCallback function in case of error */
5792  hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
5793  }
5794  }
5795  }
5796  /* Abort DMA RX transfer if any */
5797  else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
5798  {
5799  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
5800 
5801  if (hi2c->hdmarx != NULL)
5802  {
5803  /* Set the I2C DMA Abort callback :
5804  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
5805  hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
5806 
5807  /* Process Unlocked */
5808  __HAL_UNLOCK(hi2c);
5809 
5810  /* Abort DMA RX */
5811  if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
5812  {
5813  /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
5814  hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
5815  }
5816  }
5817  }
5818  else if (hi2c->State == HAL_I2C_STATE_ABORT)
5819  {
5820  hi2c->State = HAL_I2C_STATE_READY;
5821 
5822  /* Process Unlocked */
5823  __HAL_UNLOCK(hi2c);
5824 
5825  /* Call the corresponding callback to inform upper layer of End of Transfer */
5826 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5827  hi2c->AbortCpltCallback(hi2c);
5828 #else
5829  HAL_I2C_AbortCpltCallback(hi2c);
5830 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5831  }
5832  else
5833  {
5834  /* Process Unlocked */
5835  __HAL_UNLOCK(hi2c);
5836 
5837  /* Call the corresponding callback to inform upper layer of End of Transfer */
5838 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5839  hi2c->ErrorCallback(hi2c);
5840 #else
5841  HAL_I2C_ErrorCallback(hi2c);
5842 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5843  }
5844 }
5845 
5851 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
5852 {
5853  /* If a pending TXIS flag is set */
5854  /* Write a dummy data in TXDR to clear it */
5855  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
5856  {
5857  hi2c->Instance->TXDR = 0x00U;
5858  }
5859 
5860  /* Flush TX register if not empty */
5861  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
5862  {
5863  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
5864  }
5865 }
5866 
5872 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
5873 {
5874  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
5875 
5876  /* Disable DMA Request */
5877  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
5878 
5879  /* If last transfer, enable STOP interrupt */
5880  if (hi2c->XferCount == 0U)
5881  {
5882  /* Enable STOP interrupt */
5883  I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5884  }
5885  /* else prepare a new DMA transfer and enable TCReload interrupt */
5886  else
5887  {
5888  /* Update Buffer pointer */
5889  hi2c->pBuffPtr += hi2c->XferSize;
5890 
5891  /* Set the XferSize to transfer */
5892  if (hi2c->XferCount > MAX_NBYTE_SIZE)
5893  {
5894  hi2c->XferSize = MAX_NBYTE_SIZE;
5895  }
5896  else
5897  {
5898  hi2c->XferSize = hi2c->XferCount;
5899  }
5900 
5901  /* Enable the DMA stream */
5902  if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
5903  {
5904  /* Call the corresponding callback to inform upper layer of End of Transfer */
5905  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
5906  }
5907  else
5908  {
5909  /* Enable TC interrupts */
5910  I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
5911  }
5912  }
5913 }
5914 
5920 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
5921 {
5922  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
5923  uint32_t tmpoptions = hi2c->XferOptions;
5924 
5925  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5926  {
5927  /* Disable DMA Request */
5928  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
5929 
5930  /* Last Byte is Transmitted */
5931  /* Call I2C Slave Sequential complete process */
5932  I2C_ITSlaveSeqCplt(hi2c);
5933  }
5934  else
5935  {
5936  /* No specific action, Master fully manage the generation of STOP condition */
5937  /* Mean that this generation can arrive at any time, at the end or during DMA process */
5938  /* So STOP condition should be manage through Interrupt treatment */
5939  }
5940 }
5941 
5947 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
5948 {
5949  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
5950 
5951  /* Disable DMA Request */
5952  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
5953 
5954  /* If last transfer, enable STOP interrupt */
5955  if (hi2c->XferCount == 0U)
5956  {
5957  /* Enable STOP interrupt */
5958  I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5959  }
5960  /* else prepare a new DMA transfer and enable TCReload interrupt */
5961  else
5962  {
5963  /* Update Buffer pointer */
5964  hi2c->pBuffPtr += hi2c->XferSize;
5965 
5966  /* Set the XferSize to transfer */
5967  if (hi2c->XferCount > MAX_NBYTE_SIZE)
5968  {
5969  hi2c->XferSize = MAX_NBYTE_SIZE;
5970  }
5971  else
5972  {
5973  hi2c->XferSize = hi2c->XferCount;
5974  }
5975 
5976  /* Enable the DMA stream */
5977  if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
5978  {
5979  /* Call the corresponding callback to inform upper layer of End of Transfer */
5980  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
5981  }
5982  else
5983  {
5984  /* Enable TC interrupts */
5985  I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
5986  }
5987  }
5988 }
5989 
5995 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
5996 {
5997  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
5998  uint32_t tmpoptions = hi2c->XferOptions;
5999 
6000  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
6001  (tmpoptions != I2C_NO_OPTION_FRAME))
6002  {
6003  /* Disable DMA Request */
6004  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6005 
6006  /* Call I2C Slave Sequential complete process */
6007  I2C_ITSlaveSeqCplt(hi2c);
6008  }
6009  else
6010  {
6011  /* No specific action, Master fully manage the generation of STOP condition */
6012  /* Mean that this generation can arrive at any time, at the end or during DMA process */
6013  /* So STOP condition should be manage through Interrupt treatment */
6014  }
6015 }
6016 
6022 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6023 {
6024  uint32_t treatdmaerror = 0U;
6025  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
6026 
6027  if (hi2c->hdmatx != NULL)
6028  {
6029  if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
6030  {
6031  treatdmaerror = 1U;
6032  }
6033  }
6034 
6035  if (hi2c->hdmarx != NULL)
6036  {
6037  if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
6038  {
6039  treatdmaerror = 1U;
6040  }
6041  }
6042 
6043  /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
6044  if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
6045  {
6046  /* Disable Acknowledge */
6047  hi2c->Instance->CR2 |= I2C_CR2_NACK;
6048 
6049  /* Call the corresponding callback to inform upper layer of End of Transfer */
6050  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6051  }
6052 }
6053 
6060 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6061 {
6062  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
6063 
6064  /* Reset AbortCpltCallback */
6065  hi2c->hdmatx->XferAbortCallback = NULL;
6066  hi2c->hdmarx->XferAbortCallback = NULL;
6067 
6068  /* Check if come from abort from user */
6069  if (hi2c->State == HAL_I2C_STATE_ABORT)
6070  {
6071  hi2c->State = HAL_I2C_STATE_READY;
6072 
6073  /* Call the corresponding callback to inform upper layer of End of Transfer */
6074 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6075  hi2c->AbortCpltCallback(hi2c);
6076 #else
6077  HAL_I2C_AbortCpltCallback(hi2c);
6078 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6079  }
6080  else
6081  {
6082  /* Call the corresponding callback to inform upper layer of End of Transfer */
6083 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6084  hi2c->ErrorCallback(hi2c);
6085 #else
6086  HAL_I2C_ErrorCallback(hi2c);
6087 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6088  }
6089 }
6090 
6101 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
6102 {
6103  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6104  {
6105  /* Check for the Timeout */
6106  if (Timeout != HAL_MAX_DELAY)
6107  {
6108  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6109  {
6110  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6111  hi2c->State = HAL_I2C_STATE_READY;
6112  hi2c->Mode = HAL_I2C_MODE_NONE;
6113 
6114  /* Process Unlocked */
6115  __HAL_UNLOCK(hi2c);
6116  return HAL_ERROR;
6117  }
6118  }
6119  }
6120  return HAL_OK;
6121 }
6122 
6131 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6132 {
6133  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
6134  {
6135  /* Check if a NACK is detected */
6136  if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
6137  {
6138  return HAL_ERROR;
6139  }
6140 
6141  /* Check for the Timeout */
6142  if (Timeout != HAL_MAX_DELAY)
6143  {
6144  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6145  {
6146  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6147  hi2c->State = HAL_I2C_STATE_READY;
6148  hi2c->Mode = HAL_I2C_MODE_NONE;
6149 
6150  /* Process Unlocked */
6151  __HAL_UNLOCK(hi2c);
6152 
6153  return HAL_ERROR;
6154  }
6155  }
6156  }
6157  return HAL_OK;
6158 }
6159 
6168 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6169 {
6170  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6171  {
6172  /* Check if a NACK is detected */
6173  if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
6174  {
6175  return HAL_ERROR;
6176  }
6177 
6178  /* Check for the Timeout */
6179  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6180  {
6181  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6182  hi2c->State = HAL_I2C_STATE_READY;
6183  hi2c->Mode = HAL_I2C_MODE_NONE;
6184 
6185  /* Process Unlocked */
6186  __HAL_UNLOCK(hi2c);
6187 
6188  return HAL_ERROR;
6189  }
6190  }
6191  return HAL_OK;
6192 }
6193 
6202 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6203 {
6204  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
6205  {
6206  /* Check if a NACK is detected */
6207  if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
6208  {
6209  return HAL_ERROR;
6210  }
6211 
6212  /* Check if a STOPF is detected */
6213  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6214  {
6215  /* Check if an RXNE is pending */
6216  /* Store Last receive data if any */
6217  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
6218  {
6219  /* Return HAL_OK */
6220  /* The Reading of data from RXDR will be done in caller function */
6221  return HAL_OK;
6222  }
6223  else
6224  {
6225  /* Clear STOP Flag */
6226  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6227 
6228  /* Clear Configuration Register 2 */
6229  I2C_RESET_CR2(hi2c);
6230 
6231  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6232  hi2c->State = HAL_I2C_STATE_READY;
6233  hi2c->Mode = HAL_I2C_MODE_NONE;
6234 
6235  /* Process Unlocked */
6236  __HAL_UNLOCK(hi2c);
6237 
6238  return HAL_ERROR;
6239  }
6240  }
6241 
6242  /* Check for the Timeout */
6243  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6244  {
6245  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6246  hi2c->State = HAL_I2C_STATE_READY;
6247 
6248  /* Process Unlocked */
6249  __HAL_UNLOCK(hi2c);
6250 
6251  return HAL_ERROR;
6252  }
6253  }
6254  return HAL_OK;
6255 }
6256 
6265 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6266 {
6267  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6268  {
6269  /* Wait until STOP Flag is reset */
6270  /* AutoEnd should be initiate after AF */
6271  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6272  {
6273  /* Check for the Timeout */
6274  if (Timeout != HAL_MAX_DELAY)
6275  {
6276  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6277  {
6278  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6279  hi2c->State = HAL_I2C_STATE_READY;
6280  hi2c->Mode = HAL_I2C_MODE_NONE;
6281 
6282  /* Process Unlocked */
6283  __HAL_UNLOCK(hi2c);
6284 
6285  return HAL_ERROR;
6286  }
6287  }
6288  }
6289 
6290  /* Clear NACKF Flag */
6291  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6292 
6293  /* Clear STOP Flag */
6294  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6295 
6296  /* Flush TX register */
6297  I2C_Flush_TXDR(hi2c);
6298 
6299  /* Clear Configuration Register 2 */
6300  I2C_RESET_CR2(hi2c);
6301 
6302  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6303  hi2c->State = HAL_I2C_STATE_READY;
6304  hi2c->Mode = HAL_I2C_MODE_NONE;
6305 
6306  /* Process Unlocked */
6307  __HAL_UNLOCK(hi2c);
6308 
6309  return HAL_ERROR;
6310  }
6311  return HAL_OK;
6312 }
6313 
6333 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
6334 {
6335  /* Check the parameters */
6336  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
6337  assert_param(IS_TRANSFER_MODE(Mode));
6338  assert_param(IS_TRANSFER_REQUEST(Request));
6339 
6340  /* update CR2 register */
6341  MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
6342  (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
6343 }
6344 
6352 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
6353 {
6354  uint32_t tmpisr = 0U;
6355 
6356  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
6357  (hi2c->XferISR == I2C_Slave_ISR_DMA))
6358  {
6359  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
6360  {
6361  /* Enable ERR, STOP, NACK and ADDR interrupts */
6362  tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
6363  }
6364 
6365  if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
6366  {
6367  /* Enable ERR and NACK interrupts */
6368  tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
6369  }
6370 
6371  if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
6372  {
6373  /* Enable STOP interrupts */
6374  tmpisr |= I2C_IT_STOPI;
6375  }
6376 
6377  if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
6378  {
6379  /* Enable TC interrupts */
6380  tmpisr |= I2C_IT_TCI;
6381  }
6382  }
6383  else
6384  {
6385  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
6386  {
6387  /* Enable ERR, STOP, NACK, and ADDR interrupts */
6388  tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
6389  }
6390 
6391  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
6392  {
6393  /* Enable ERR, TC, STOP, NACK and RXI interrupts */
6394  tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
6395  }
6396 
6397  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
6398  {
6399  /* Enable ERR, TC, STOP, NACK and TXI interrupts */
6400  tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
6401  }
6402 
6403  if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
6404  {
6405  /* Enable STOP interrupts */
6406  tmpisr |= I2C_IT_STOPI;
6407  }
6408  }
6409 
6410  /* Enable interrupts only at the end */
6411  /* to avoid the risk of I2C interrupt handle execution before */
6412  /* all interrupts requested done */
6413  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
6414 }
6415 
6423 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
6424 {
6425  uint32_t tmpisr = 0U;
6426 
6427  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
6428  {
6429  /* Disable TC and TXI interrupts */
6430  tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
6431 
6432  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
6433  {
6434  /* Disable NACK and STOP interrupts */
6435  tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
6436  }
6437  }
6438 
6439  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
6440  {
6441  /* Disable TC and RXI interrupts */
6442  tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
6443 
6444  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
6445  {
6446  /* Disable NACK and STOP interrupts */
6447  tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
6448  }
6449  }
6450 
6451  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
6452  {
6453  /* Disable ADDR, NACK and STOP interrupts */
6454  tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
6455  }
6456 
6457  if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
6458  {
6459  /* Enable ERR and NACK interrupts */
6460  tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
6461  }
6462 
6463  if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
6464  {
6465  /* Enable STOP interrupts */
6466  tmpisr |= I2C_IT_STOPI;
6467  }
6468 
6469  if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
6470  {
6471  /* Enable TC interrupts */
6472  tmpisr |= I2C_IT_TCI;
6473  }
6474 
6475  /* Disable interrupts only at the end */
6476  /* to avoid a breaking situation like at "t" time */
6477  /* all disable interrupts request are not done */
6478  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
6479 }
6480 
6486 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
6487 {
6488  /* if user set XferOptions to I2C_OTHER_FRAME */
6489  /* it request implicitly to generate a restart condition */
6490  /* set XferOptions to I2C_FIRST_FRAME */
6491  if (hi2c->XferOptions == I2C_OTHER_FRAME)
6492  {
6493  hi2c->XferOptions = I2C_FIRST_FRAME;
6494  }
6495  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
6496  /* it request implicitly to generate a restart condition */
6497  /* then generate a stop condition at the end of transfer */
6498  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
6499  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
6500  {
6501  hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
6502  }
6503  else
6504  {
6505  /* Nothing to do */
6506  }
6507 }
6508 
6513 #endif /* HAL_I2C_MODULE_ENABLED */
6514 
6522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_I2C_MemTxCpltCallback
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
HAL_I2C_STATE_BUSY_TX_LISTEN
@ HAL_I2C_STATE_BUSY_TX_LISTEN
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:115
assert_param
#define assert_param(expr)
Include module's header file.
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:353
I2C_CR2_NACK
#define I2C_CR2_NACK
Definition: stm32f769xx.h:9911
I2C_GENERATE_START_READ
#define I2C_GENERATE_START_READ
Definition: stm32f7xx_hal_i2c.h:382
HAL_I2C_Init
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
I2C_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:216
I2C_FIRST_FRAME
#define I2C_FIRST_FRAME
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:353
I2C_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:210
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
HAL_I2C_STATE_BUSY_RX
@ HAL_I2C_STATE_BUSY_RX
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:113
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
I2C_GET_OWN_ADDRESS1
#define I2C_GET_OWN_ADDRESS1(__HANDLE__)
Definition: stm32f7xx_hal_i2c.h:740
I2C_CR2_RD_WRN
#define I2C_CR2_RD_WRN
Definition: stm32f769xx.h:9896
HAL_I2C_ERROR_AF
#define HAL_I2C_ERROR_AF
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:167
HAL_I2C_ERROR_DMA
#define HAL_I2C_ERROR_DMA
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:169
__I2C_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f7xx_hal_i2c.h:215
HAL_I2C_ER_IRQHandler
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
IS_TRANSFER_MODE
#define IS_TRANSFER_MODE(MODE)
Definition: stm32f7xx_hal_i2c.h:715
HAL_I2C_GetState
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
I2C_CR2_NBYTES
#define I2C_CR2_NBYTES
Definition: stm32f769xx.h:9914
I2C_InitTypeDef::OwnAddress1
uint32_t OwnAddress1
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:56
I2C_MEM_ADD_MSB
#define I2C_MEM_ADD_MSB(__ADDRESS__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:677
I2C_InitTypeDef::AddressingMode
uint32_t AddressingMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:59
HAL_I2C_Slave_Seq_Receive_DMA
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
HAL_I2C_GetMode
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
I2C_NO_STARTSTOP
#define I2C_NO_STARTSTOP
Definition: stm32f7xx_hal_i2c.h:380
__DMA_HandleTypeDef::XferHalfCpltCallback
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:153
HAL_I2C_ERROR_NONE
#define HAL_I2C_ERROR_NONE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:164
I2C_GET_OWN_ADDRESS2
#define I2C_GET_OWN_ADDRESS2(__HANDLE__)
Definition: stm32f7xx_hal_i2c.h:741
IS_I2C_NO_STRETCH
#define IS_I2C_NO_STRETCH(STRETCH)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:691
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
NULL
#define NULL
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/speex_resampler/thirdparty/resample.c:92
HAL_I2C_Master_Transmit
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
I2C_DUALADDRESS_ENABLE
#define I2C_DUALADDRESS_ENABLE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:309
I2C_FLAG_BUSY
#define I2C_FLAG_BUSY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:400
I2C_FLAG_OVR
#define I2C_FLAG_OVR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:386
IS_I2C_ALL_INSTANCE
#define IS_I2C_ALL_INSTANCE(INSTANCE)
Definition: stm32f407xx.h:15129
I2C_MEM_ADD_LSB
#define I2C_MEM_ADD_LSB(__ADDRESS__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:678
I2C_InitTypeDef::OwnAddress2
uint32_t OwnAddress2
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:65
HAL_I2C_Slave_Transmit_DMA
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
HAL_I2C_Slave_Receive_IT
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
HAL_UNLOCKED
@ HAL_UNLOCKED
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:53
HAL_I2C_Mem_Read_DMA
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
I2C_HandleTypeDef::hdmatx
DMA_HandleTypeDef * hdmatx
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:206
I2C_ADDRESSINGMODE_10BIT
#define I2C_ADDRESSINGMODE_10BIT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:300
I2C_IT_TXI
#define I2C_IT_TXI
Definition: stm32f7xx_hal_i2c.h:400
I2C_HandleTypeDef::Mode
__IO HAL_I2C_ModeTypeDef Mode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:214
HAL_DMA_Abort_IT
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__HAL_I2C_DISABLE_IT
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:440
HAL_I2C_Master_Abort_IT
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
HAL_I2C_ListenCpltCallback
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
I2C_ADDRESSINGMODE_7BIT
#define I2C_ADDRESSINGMODE_7BIT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:299
I2C_HandleTypeDef::PreviousState
__IO uint32_t PreviousState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:203
I2C_HandleTypeDef::XferOptions
__IO uint32_t XferOptions
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:201
I2C_CR2_STOP
#define I2C_CR2_STOP
Definition: stm32f769xx.h:9908
HAL_I2C_Slave_Seq_Receive_IT
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
I2C_CHECK_FLAG
#define I2C_CHECK_FLAG(__ISR__, __FLAG__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:709
I2C_InitTypeDef::DualAddressMode
uint32_t DualAddressMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:62
I2C_GENERATE_START_WRITE
#define I2C_GENERATE_START_WRITE
Definition: stm32f7xx_hal_i2c.h:383
__DMA_HandleTypeDef::XferAbortCallback
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:161
I2C_AUTOEND_MODE
#define I2C_AUTOEND_MODE
Definition: stm32f7xx_hal_i2c.h:371
IS_I2C_GENERAL_CALL
#define IS_I2C_GENERAL_CALL(CALL)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:689
__I2C_HandleTypeDef::XferSize
uint16_t XferSize
Definition: stm32f7xx_hal_i2c.h:194
HAL_I2C_STATE_RESET
@ HAL_I2C_STATE_RESET
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:109
HAL_ERROR
@ HAL_ERROR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:43
I2C_HandleTypeDef::hdmarx
DMA_HandleTypeDef * hdmarx
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:208
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323
HAL_I2C_Master_Transmit_IT
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
I2C_FLAG_ADDR
#define I2C_FLAG_ADDR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:395
__I2C_HandleTypeDef::XferCount
__IO uint16_t XferCount
Definition: stm32f7xx_hal_i2c.h:196
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32f769xx.h:662
HAL_I2C_EV_IRQHandler
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
I2C_CHECK_IT_SOURCE
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:710
I2C_IT_ERRI
#define I2C_IT_ERRI
Definition: stm32f7xx_hal_i2c.h:394
I2C_OAR1_OA1EN
#define I2C_OAR1_OA1EN
Definition: stm32f769xx.h:9934
HAL_I2C_Mem_Write
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f769xx.h:668
I2C_InitTypeDef::NoStretchMode
uint32_t NoStretchMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:71
I2C_CR1_RXDMAEN
#define I2C_CR1_RXDMAEN
Definition: stm32f769xx.h:9866
HAL_I2C_Slave_Transmit_IT
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
HAL_I2C_ERROR_TIMEOUT
#define HAL_I2C_ERROR_TIMEOUT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:170
IS_TRANSFER_REQUEST
#define IS_TRANSFER_REQUEST(REQUEST)
Definition: stm32f7xx_hal_i2c.h:719
HAL_OK
@ HAL_OK
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:42
I2C_FLAG_BERR
#define I2C_FLAG_BERR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:389
HAL_I2C_EnableListen_IT
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
HAL_I2C_MODE_SLAVE
@ HAL_I2C_MODE_SLAVE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:151
HAL_I2C_StateTypeDef
HAL_I2C_StateTypeDef
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:107
HAL_I2C_STATE_BUSY
@ HAL_I2C_STATE_BUSY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:111
HAL_I2C_STATE_BUSY_RX_LISTEN
@ HAL_I2C_STATE_BUSY_RX_LISTEN
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:117
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f769xx.h:664
I2C_GENERATE_START
#define I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
Definition: stm32f7xx_hal_i2c.h:749
HAL_I2C_ERROR_SIZE
#define HAL_I2C_ERROR_SIZE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:171
UNUSED
#define UNUSED(x)
Definition: porcupine/demo/c/dr_libs/old/dr.h:92
I2C_OTHER_FRAME
#define I2C_OTHER_FRAME
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:363
__I2C_HandleTypeDef::Instance
I2C_TypeDef * Instance
Definition: stm32f7xx_hal_i2c.h:188
IS_I2C_MEMADD_SIZE
#define IS_I2C_MEMADD_SIZE(SIZE)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:693
HAL_I2C_STATE_READY
@ HAL_I2C_STATE_READY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:110
I2C_CR2_RD_WRN_Pos
#define I2C_CR2_RD_WRN_Pos
Definition: stm32f769xx.h:9894
HAL_I2C_ERROR_DMA_PARAM
#define HAL_I2C_ERROR_DMA_PARAM
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:172
__HAL_DMA_GET_COUNTER
#define __HAL_DMA_GET_COUNTER(__HANDLE__)
Returns the number of remaining data units in the current DMAy Streamx transfer.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:636
HAL_I2C_Master_Seq_Transmit_DMA
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
HAL_I2C_ERROR_INVALID_PARAM
#define HAL_I2C_ERROR_INVALID_PARAM
Definition: stm32f7xx_hal_i2c.h:177
I2C_GENERATE_STOP
#define I2C_GENERATE_STOP
Definition: stm32f7xx_hal_i2c.h:381
IS_I2C_OWN_ADDRESS1
#define IS_I2C_OWN_ADDRESS1(ADDRESS1)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:696
__HAL_LOCK
#define __HAL_LOCK(__HANDLE__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:93
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f769xx.h:667
HAL_I2C_AbortCpltCallback
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
HAL_I2C_STATE_BUSY_TX
@ HAL_I2C_STATE_BUSY_TX
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:112
HAL_I2C_MasterRxCpltCallback
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:224
I2C_IT_STOPI
#define I2C_IT_STOPI
Definition: stm32f7xx_hal_i2c.h:396
HAL_I2C_ERROR_ARLO
#define HAL_I2C_ERROR_ARLO
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:166
RESET
@ RESET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:187
I2C_FLAG_TC
#define I2C_FLAG_TC
Definition: stm32f7xx_hal_i2c.h:414
I2C_IT_TCI
#define I2C_IT_TCI
Definition: stm32f7xx_hal_i2c.h:395
HAL_BUSY
@ HAL_BUSY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:44
I2C_FLAG_ARLO
#define I2C_FLAG_ARLO
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:388
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
I2C_InitTypeDef::Timing
uint32_t Timing
Definition: stm32f7xx_hal_i2c.h:50
IS_I2C_OWN_ADDRESS2_MASK
#define IS_I2C_OWN_ADDRESS2_MASK(MASK)
Definition: stm32f7xx_hal_i2c.h:697
I2C_IT_RXI
#define I2C_IT_RXI
Definition: stm32f7xx_hal_i2c.h:399
HAL_I2C_Master_Seq_Receive_DMA
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
I2C_GET_DIR
#define I2C_GET_DIR(__HANDLE__)
Definition: stm32f7xx_hal_i2c.h:738
HAL_I2C_ERROR_OVR
#define HAL_I2C_ERROR_OVR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:168
I2C_MEMADD_SIZE_8BIT
#define I2C_MEMADD_SIZE_8BIT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:335
HAL_I2C_Slave_Seq_Transmit_DMA
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
HAL_I2C_SlaveTxCpltCallback
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
I2C_NEXT_FRAME
#define I2C_NEXT_FRAME
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:355
__HAL_UNLOCK
#define __HAL_UNLOCK(__HANDLE__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:105
HAL_I2C_IsDeviceReady
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
__I2C_HandleTypeDef::pBuffPtr
uint8_t * pBuffPtr
Definition: stm32f7xx_hal_i2c.h:192
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:61
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f407xx.h:561
I2C_FLAG_AF
#define I2C_FLAG_AF
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:387
I2C_FLAG_STOPF
#define I2C_FLAG_STOPF
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:392
I2C_RELOAD_MODE
#define I2C_RELOAD_MODE
Definition: stm32f7xx_hal_i2c.h:370
I2C_CR2_ADD10
#define I2C_CR2_ADD10
Definition: stm32f769xx.h:9899
I2C_InitTypeDef::GeneralCallMode
uint32_t GeneralCallMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:68
I2C_CR2_SADD
#define I2C_CR2_SADD
Definition: stm32f769xx.h:9893
__I2C_HandleTypeDef::XferOptions
__IO uint32_t XferOptions
Definition: stm32f7xx_hal_i2c.h:198
I2C_IT_ADDRI
#define I2C_IT_ADDRI
Definition: stm32f7xx_hal_i2c.h:398
HAL_I2C_MspInit
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
__HAL_I2C_CLEAR_FLAG
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:490
HAL_I2C_DisableListen_IT
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
I2C_HandleTypeDef::Init
I2C_InitTypeDef Init
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:193
HAL_I2C_AddrCallback
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
I2C_SOFTEND_MODE
#define I2C_SOFTEND_MODE
Definition: stm32f7xx_hal_i2c.h:372
I2C_OTHER_AND_LAST_FRAME
#define I2C_OTHER_AND_LAST_FRAME
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:364
I2C_InitTypeDef::OwnAddress2Masks
uint32_t OwnAddress2Masks
Definition: stm32f7xx_hal_i2c.h:66
__I2C_HandleTypeDef::State
__IO HAL_I2C_StateTypeDef State
Definition: stm32f7xx_hal_i2c.h:211
I2C_RESET_CR2
#define I2C_RESET_CR2(__HANDLE__)
Definition: stm32f7xx_hal_i2c.h:735
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:151
SET
@ SET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:188
I2C_IT_NACKI
#define I2C_IT_NACKI
Definition: stm32f7xx_hal_i2c.h:397
HAL_I2C_Slave_Receive
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
HAL_I2C_Master_Receive_IT
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
I2C_FLAG_DIR
#define I2C_FLAG_DIR
Definition: stm32f7xx_hal_i2c.h:423
I2C_CR2_START
#define I2C_CR2_START
Definition: stm32f769xx.h:9905
I2C_HandleTypeDef::pBuffPtr
uint8_t * pBuffPtr
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:195
HAL_I2C_MODE_MASTER
@ HAL_I2C_MODE_MASTER
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:150
HAL_I2C_ERROR_BERR
#define HAL_I2C_ERROR_BERR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:165
FlagStatus
FlagStatus
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:185
__HAL_I2C_DISABLE
#define __HAL_I2C_DISABLE(__HANDLE__)
Disable the specified I2C peripheral.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:527
I2C_HandleTypeDef
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:188
HAL_I2C_STATE_LISTEN
@ HAL_I2C_STATE_LISTEN
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:114
I2C_CR2_NBYTES_Pos
#define I2C_CR2_NBYTES_Pos
Definition: stm32f769xx.h:9912
HAL_I2C_Mem_Write_DMA
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
HAL_I2C_Master_Transmit_DMA
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:706
IS_I2C_OWN_ADDRESS2
#define IS_I2C_OWN_ADDRESS2(ADDRESS2)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:697
I2C_FLAG_TXIS
#define I2C_FLAG_TXIS
Definition: stm32f7xx_hal_i2c.h:409
HAL_I2C_Slave_Receive_DMA
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
__HAL_I2C_ENABLE_IT
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable or disable the specified I2C interrupts.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:439
HAL_I2C_GetError
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
I2C_CR2_RELOAD
#define I2C_CR2_RELOAD
Definition: stm32f769xx.h:9917
HAL_I2C_Slave_Transmit
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
HAL_I2C_Master_Receive
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
I2C_GET_ADDR_MATCH
#define I2C_GET_ADDR_MATCH(__HANDLE__)
Definition: stm32f7xx_hal_i2c.h:737
HAL_I2C_Mem_Write_IT
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
HAL_DMA_GetError
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
I2C_DIRECTION_RECEIVE
#define I2C_DIRECTION_RECEIVE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:344
I2C_FIRST_AND_LAST_FRAME
#define I2C_FIRST_AND_LAST_FRAME
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:356
__HAL_I2C_ENABLE
#define __HAL_I2C_ENABLE(__HANDLE__)
Enable the specified I2C peripheral.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:521
IS_I2C_DUAL_ADDRESS
#define IS_I2C_DUAL_ADDRESS(ADDRESS)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:687
I2C_HandleTypeDef::XferCount
__IO uint16_t XferCount
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:199
HAL_I2C_Mem_Read
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
I2C_CR1_TXDMAEN
#define I2C_CR1_TXDMAEN
Definition: stm32f769xx.h:9863
HAL_I2C_STATE_ABORT
@ HAL_I2C_STATE_ABORT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:119
READ_REG
#define READ_REG(REG)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:222
IS_I2C_ADDRESSING_MODE
#define IS_I2C_ADDRESSING_MODE(ADDRESS)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:685
I2C_FLAG_TCR
#define I2C_FLAG_TCR
Definition: stm32f7xx_hal_i2c.h:415
HAL_I2C_MODE_MEM
@ HAL_I2C_MODE_MEM
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:152
HAL_I2C_Slave_Seq_Transmit_IT
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
I2C_CR2_AUTOEND
#define I2C_CR2_AUTOEND
Definition: stm32f769xx.h:9920
I2C_DIRECTION_TRANSMIT
#define I2C_DIRECTION_TRANSMIT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:345
IS_I2C_TRANSFER_OPTIONS_REQUEST
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:698
__HAL_I2C_GET_FLAG
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
Checks whether the specified I2C flag is set or not.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:476
I2C_GET_STOP_MODE
#define I2C_GET_STOP_MODE(__HANDLE__)
Definition: stm32f7xx_hal_i2c.h:739
I2C_HandleTypeDef::Instance
I2C_TypeDef * Instance
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:191
HAL_DMA_ERROR_FE
#define HAL_DMA_ERROR_FE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:188
I2C_FLAG_RXNE
#define I2C_FLAG_RXNE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:391
HAL_I2C_ErrorCallback
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f407xx.h:562
__I2C_HandleTypeDef
Definition: stm32f7xx_hal_i2c.h:186
I2C_HandleTypeDef::State
__IO HAL_I2C_StateTypeDef State
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:212
HAL_I2C_MspDeInit
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
HAL_I2C_Master_Seq_Receive_IT
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745
HAL_I2C_Master_Receive_DMA
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
HAL_I2C_ModeTypeDef
HAL_I2C_ModeTypeDef
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:147
HAL_I2C_Mem_Read_IT
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
HAL_I2C_Master_Seq_Transmit_IT
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
I2C_FLAG_TXE
#define I2C_FLAG_TXE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:390
HAL_I2C_DeInit
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
HAL_I2C_MODE_NONE
@ HAL_I2C_MODE_NONE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:149
stm32f7xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_I2C_SlaveRxCpltCallback
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f407xx.h:560
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:159
I2C_HandleTypeDef::XferSize
uint16_t XferSize
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h:197
HAL_I2C_MasterTxCpltCallback
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
__I2C_HandleTypeDef::hdmatx
DMA_HandleTypeDef * hdmatx
Definition: stm32f7xx_hal_i2c.h:205
HAL_I2C_MemRxCpltCallback
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
__I2C_HandleTypeDef::hdmarx
DMA_HandleTypeDef * hdmarx
Definition: stm32f7xx_hal_i2c.h:207
I2C_OAR1_OA1MODE
#define I2C_OAR1_OA1MODE
Definition: stm32f769xx.h:9931
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f407xx.h:559

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:53