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98 #include "stm32f4xx_hal.h"
109 #ifdef HAL_DMA_MODULE_ENABLED
115 __IO uint32_t Reserved0;
117 } DMA_Base_Registers;
124 #define HAL_TIMEOUT_DMA_ABORT 5U
133 static void DMA_SetConfig(
DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
175 DMA_Base_Registers *regs;
216 if((
HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
272 if (DMA_CheckFifoParam(hdma) !=
HAL_OK)
290 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
312 DMA_Base_Registers *regs;
352 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
427 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
474 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
548 if((
HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
614 uint32_t mask_cpltlevel;
619 DMA_Base_Registers *regs;
656 if((Timeout == 0U)||((
HAL_GetTick() - tickstart ) > Timeout))
936 if (++
count > timeout)
1150 static void DMA_SetConfig(
DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
1186 uint32_t stream_number = (((uint32_t)hdma->
Instance & 0xFFU) - 16U) / 24U;
1189 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
1190 hdma->
StreamIndex = flagBitshiftOffset[stream_number];
1192 if (stream_number > 3U)
#define assert_param(expr)
Include module's header file.
#define __HAL_DMA_DISABLE(__HANDLE__)
Disable the specified DMA Stream.
HAL_StatusTypeDef
HAL Status structures definition
#define IS_DMA_PRIORITY(PRIORITY)
@ HAL_DMA_XFER_ERROR_CB_ID
#define DMA_MDATAALIGN_BYTE
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
DMA handle Structure definition.
#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE)
#define HAL_DMA_ERROR_TIMEOUT
uint32_t StreamBaseAddress
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
#define __HAL_DMA_ENABLE(__HANDLE__)
Enable the specified DMA Stream.
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD)
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
#define HAL_DMA_ERROR_NO_XFER
#define IS_DMA_CHANNEL(CHANNEL)
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
uint32_t PeriphDataAlignment
__IO HAL_DMA_StateTypeDef State
#define DMA_MBURST_SINGLE
#define DMA_SxCR_MBURST_1
@ HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_M1HALFCPLT_CB_ID
#define IS_DMA_FIFO_MODE_STATE(STATE)
#define IS_DMA_MEMORY_INC_STATE(STATE)
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or disabled.
#define IS_DMA_MODE(MODE)
#define __HAL_LOCK(__HANDLE__)
#define DMA_MDATAALIGN_HALFWORD
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
DMA_Stream_TypeDef * Instance
#define IS_DMA_PERIPHERAL_BURST(BURST)
uint32_t MemDataAlignment
HAL_DMA_CallbackIDTypeDef
HAL DMA Error Code structure definition.
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ HAL_DMA_XFER_M1CPLT_CB_ID
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL
#define IS_DMA_BUFFER_SIZE(SIZE)
#define __HAL_UNLOCK(__HANDLE__)
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
#define DMA_FIFO_THRESHOLD_1QUARTERFULL
#define IS_DMA_DIRECTION(DIRECTION)
@ HAL_DMA_XFER_CPLT_CB_ID
#define HAL_DMA_ERROR_DME
#define DMA_FIFOMODE_ENABLE
#define HAL_DMA_ERROR_NOT_SUPPORTED
#define DMA_FIFOMODE_DISABLE
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define DMA_MEMORY_TO_PERIPH
#define IS_DMA_MEMORY_BURST(BURST)
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
#define DMA_FLAG_DMEIF0_4
#define IS_DMA_PERIPHERAL_INC_STATE(STATE)
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
@ HAL_DMA_XFER_HALFCPLT_CB_ID
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
#define HAL_DMA_ERROR_PARAM
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
#define HAL_DMA_ERROR_NONE
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
HAL_DMA_LevelCompleteTypeDef
HAL DMA Error Code structure definition.
#define DMA_FIFO_THRESHOLD_FULL
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
#define DMA_FIFO_THRESHOLD_HALFFULL