test_mips.c
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1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013 */
3 
4 #include <stdio.h>
5 #include <stdlib.h>
6 
7 #include <capstone/platform.h>
8 #include <capstone/capstone.h>
9 
10 struct platform {
11  cs_arch arch;
12  cs_mode mode;
13  unsigned char *code;
14  size_t size;
15  const char *comment;
16 };
17 
18 static csh handle;
19 
20 static void print_string_hex(const char *comment, unsigned char *str, size_t len)
21 {
22  unsigned char *c;
23 
24  printf("%s", comment);
25  for (c = str; c < str + len; c++) {
26  printf("0x%02x ", *c & 0xff);
27  }
28 
29  printf("\n");
30 }
31 
32 static void print_insn_detail(cs_insn *ins)
33 {
34  int i;
35  cs_mips *mips;
36 
37  // detail can be NULL on "data" instruction if SKIPDATA option is turned ON
38  if (ins->detail == NULL)
39  return;
40 
41  mips = &(ins->detail->mips);
42  if (mips->op_count)
43  printf("\top_count: %u\n", mips->op_count);
44 
45  for (i = 0; i < mips->op_count; i++) {
46  cs_mips_op *op = &(mips->operands[i]);
47  switch((int)op->type) {
48  default:
49  break;
50  case MIPS_OP_REG:
51  printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
52  break;
53  case MIPS_OP_IMM:
54  printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
55  break;
56  case MIPS_OP_MEM:
57  printf("\t\toperands[%u].type: MEM\n", i);
58  if (op->mem.base != MIPS_REG_INVALID)
59  printf("\t\t\toperands[%u].mem.base: REG = %s\n",
60  i, cs_reg_name(handle, op->mem.base));
61  if (op->mem.disp != 0)
62  printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
63 
64  break;
65  }
66 
67  }
68 
69  printf("\n");
70 }
71 
72 static void test()
73 {
74 //#define MIPS_CODE "\x8f\xa2\x00\x00"
75 //#define MIPS_CODE "\x00\x00\xa7\xac\x10\x00\xa2\x8f"
76 //#define MIPS_CODE "\x21\x30\xe6\x70" // clo $6, $7
77 //#define MIPS_CODE "\x00\x00\x00\x00" // nop
78 //#define MIPS_CODE "\xc6\x23\xe9\xe4" // swc1 $f9, 0x23c6($7)
79 //#define MIPS_CODE "\x21\x38\x00\x01" // move $7, $8
80 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
81 //#define MIPS_CODE "\x04\x11\x00\x01" // bal 0x8
82 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
83 #define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
84 #define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
85 #define MIPS_64SD "\x70\x00\xb2\xff"
86 
87  struct platform platforms[] = {
88  {
91  (unsigned char *)MIPS_CODE,
92  sizeof(MIPS_CODE) - 1,
93  "MIPS-32 (Big-endian)"
94  },
95  {
98  (unsigned char *)MIPS_CODE2,
99  sizeof(MIPS_CODE2) - 1,
100  "MIPS-64-EL (Little-endian)"
101  },
102  {
103  CS_ARCH_MIPS,
105  (unsigned char*)MIPS_32R6M,
106  sizeof(MIPS_32R6M) - 1,
107  "MIPS-32R6 | Micro (Big-endian)"
108  },
109  {
110  CS_ARCH_MIPS,
112  (unsigned char*)MIPS_32R6,
113  sizeof(MIPS_32R6) - 1,
114  "MIPS-32R6 (Big-endian)"
115  },
116  {
117  CS_ARCH_MIPS,
119  (unsigned char *)MIPS_64SD,
120  sizeof(MIPS_64SD) - 1,
121  "MIPS-64-EL + Mips II (Little-endian)"
122  },
123  {
124  CS_ARCH_MIPS,
126  (unsigned char *)MIPS_64SD,
127  sizeof(MIPS_64SD) - 1,
128  "MIPS-64-EL (Little-endian)"
129  },
130  };
131 
132  uint64_t address = 0x1000;
133  cs_insn *insn;
134  int i;
135  size_t count;
136 
137  for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
138  cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
139  if (err) {
140  printf("Failed on cs_open() with error returned: %u\n", err);
141  abort();
142  }
143 
145 
146  count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
147  if (count) {
148  size_t j;
149 
150  printf("****************\n");
151  printf("Platform: %s\n", platforms[i].comment);
153  printf("Disasm:\n");
154 
155  for (j = 0; j < count; j++) {
156  printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
157  print_insn_detail(&insn[j]);
158  }
159  printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
160 
161  // free memory allocated by cs_disasm()
162  cs_free(insn, count);
163  } else {
164  printf("****************\n");
165  printf("Platform: %s\n", platforms[i].comment);
167  printf("ERROR: Failed to disasm given code!\n");
168  abort();
169  }
170 
171  printf("\n");
172 
173  cs_close(&handle);
174  }
175 }
176 
177 int main()
178 {
179  test();
180 
181  return 0;
182 }
xds_interop_client.str
str
Definition: xds_interop_client.py:487
CS_MODE_MIPS2
@ CS_MODE_MIPS2
Mips II ISA.
Definition: capstone.h:115
cs_close
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle)
Definition: cs.c:522
MIPS_OP_REG
@ MIPS_OP_REG
= CS_OP_REG (Register operand).
Definition: mips.h:24
CS_MODE_LITTLE_ENDIAN
@ CS_MODE_LITTLE_ENDIAN
little-endian mode (default mode)
Definition: capstone.h:104
platform::code
unsigned char * code
Definition: test_arm_regression.c:21
cs_disasm
CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn)
Definition: cs.c:822
handle
static csh handle
Definition: test_mips.c:18
MIPS_OP_MEM
@ MIPS_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: mips.h:26
printf
_Use_decl_annotations_ int __cdecl printf(const char *_Format,...)
Definition: cs_driver.c:91
MIPS_32R6
#define MIPS_32R6
error_ref_leak.err
err
Definition: error_ref_leak.py:35
cs_open
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
Definition: cs.c:474
platform::mode
cs_mode mode
Definition: test_arm_regression.c:20
cs_arch
cs_arch
Architecture type.
Definition: capstone.h:74
mode
const char int mode
Definition: bloaty/third_party/zlib/contrib/minizip/ioapi.h:135
CS_OPT_DETAIL
@ CS_OPT_DETAIL
Break down instruction structure into details.
Definition: capstone.h:172
test
static void test()
Definition: test_mips.c:72
MIPS_CODE2
#define MIPS_CODE2
cs_option
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
Definition: cs.c:670
CS_MODE_MICRO
@ CS_MODE_MICRO
MicroMips mode (MIPS)
Definition: capstone.h:112
cs_mode
cs_mode
Mode type.
Definition: capstone.h:103
capstone.h
c
void c(T a)
Definition: miscompile_with_no_unique_address_test.cc:40
print_string_hex
static void print_string_hex(const char *comment, unsigned char *str, size_t len)
Definition: test_mips.c:20
cs_reg_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
Definition: cs.c:1176
platform.h
uint64_t
unsigned __int64 uint64_t
Definition: stdint-msvc2008.h:90
MIPS_CODE
#define MIPS_CODE
CS_OPT_ON
@ CS_OPT_ON
Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
Definition: capstone.h:184
platform::comment
char * comment
Definition: test_arm_regression.c:23
CS_MODE_BIG_ENDIAN
@ CS_MODE_BIG_ENDIAN
big-endian mode
Definition: capstone.h:124
MIPS_REG_INVALID
@ MIPS_REG_INVALID
Definition: mips.h:31
CS_MODE_MIPS32R6
@ CS_MODE_MIPS32R6
Mips32r6 ISA.
Definition: capstone.h:114
arch
cs_arch arch
Definition: cstool.c:13
platform::arch
cs_arch arch
Definition: test_arm_regression.c:19
CS_ARCH_MIPS
@ CS_ARCH_MIPS
Mips architecture.
Definition: capstone.h:77
csh
size_t csh
Definition: capstone.h:71
cs_mips_op
Instruction operand.
Definition: mips.h:240
CS_MODE_MIPS64
@ CS_MODE_MIPS64
Mips64 ISA (Mips)
Definition: capstone.h:126
print_insn_detail
static void print_insn_detail(cs_insn *ins)
Definition: test_mips.c:32
count
int * count
Definition: bloaty/third_party/googletest/googlemock/test/gmock_stress_test.cc:96
MIPS_64SD
#define MIPS_64SD
cs_free
CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
Definition: cs.c:1039
code
Definition: bloaty/third_party/zlib/contrib/infback9/inftree9.h:24
len
int len
Definition: abseil-cpp/absl/base/internal/low_level_alloc_test.cc:46
platforms
struct platform platforms[]
Definition: fuzz_diff.c:18
MIPS_OP_IMM
@ MIPS_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: mips.h:25
mips
Definition: test_winkernel.cpp:63
size
voidpf void uLong size
Definition: bloaty/third_party/zlib/contrib/minizip/ioapi.h:136
CS_MODE_MIPS32
@ CS_MODE_MIPS32
Mips32 ISA (Mips)
Definition: capstone.h:125
MIPS_32R6M
#define MIPS_32R6M
op
static grpc_op * op
Definition: test/core/fling/client.cc:47
platform
Definition: test_arm_regression.c:18
cs_mips
Instruction structure.
Definition: mips.h:250
platform::size
size_t size
Definition: test_arm_regression.c:22
i
uint64_t i
Definition: abseil-cpp/absl/container/btree_benchmark.cc:230
main
int main()
Definition: test_mips.c:177


grpc
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autogenerated on Thu Mar 13 2025 03:01:31