test_iter.c
Go to the documentation of this file.
1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013 */
3 
4 // This sample code demonstrates the APIs cs_malloc() & cs_disasm_iter().
5 #include <stdio.h>
6 #include <stdlib.h>
7 
8 #include <capstone/platform.h>
9 #include <capstone/capstone.h>
10 
11 struct platform {
12  cs_arch arch;
13  cs_mode mode;
14  unsigned char *code;
15  size_t size;
16  const char *comment;
19 };
20 
21 static void print_string_hex(unsigned char *str, size_t len)
22 {
23  unsigned char *c;
24 
25  printf("Code: ");
26  for (c = str; c < str + len; c++) {
27  printf("0x%02x ", *c & 0xff);
28  }
29  printf("\n");
30 }
31 
32 static void test()
33 {
34 #ifdef CAPSTONE_HAS_X86
35 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
36 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
37 //#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng
38 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
39 #endif
40 #ifdef CAPSTONE_HAS_ARM
41 //#define ARM_CODE "\x04\xe0\x2d\xe5"
42 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
43 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
44 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
45 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
46 #endif
47 #ifdef CAPSTONE_HAS_MIPS
48 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
49 //#define MIPS_CODE "\x21\x38\x00\x01"
50 //#define MIPS_CODE "\x21\x30\xe6\x70"
51 //#define MIPS_CODE "\x1c\x00\x40\x14"
52 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
53 #endif
54 #ifdef CAPSTONE_HAS_ARM64
55 //#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
56 //#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw
57 //#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2
58 //#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0
59 //#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2
60 //#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e"
61 //#define ARM64_CODE "\x21\x7c\x00\x53"
62 #define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
63 #endif
64 //#define THUMB_CODE "\x0a\xbf" // itet eq
65 //#define X86_CODE32 "\x77\x04" // ja +6
66 #ifdef CAPSTONE_HAS_POWERPC
67 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
68 #endif
69 #ifdef CAPSTONE_HAS_SPARC
70 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
71 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
72 #endif
73 #ifdef CAPSTONE_HAS_SYSZ
74 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
75 #endif
76 #ifdef CAPSTONE_HAS_XCORE
77 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
78 #endif
79 #ifdef CAPSTONE_HAS_M680X
80 #define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
81 #endif
82 #ifdef CAPSTONE_HAS_MOS65XX
83 #define MOS65XX_CODE "\x0d\x34\x12\x08\x09\xFF\x10\x80\x20\x00\x00\x98"
84 #endif
85 
86 
87  struct platform platforms[] = {
88 #ifdef CAPSTONE_HAS_X86
89  {
91  CS_MODE_16,
92  (unsigned char *)X86_CODE16,
93  sizeof(X86_CODE32) - 1,
94  "X86 16bit (Intel syntax)"
95  },
96  {
98  CS_MODE_32,
99  (unsigned char *)X86_CODE32,
100  sizeof(X86_CODE32) - 1,
101  "X86 32bit (ATT syntax)",
104  },
105  {
106  CS_ARCH_X86,
107  CS_MODE_32,
108  (unsigned char *)X86_CODE32,
109  sizeof(X86_CODE32) - 1,
110  "X86 32 (Intel syntax)"
111  },
112  {
113  CS_ARCH_X86,
114  CS_MODE_64,
115  (unsigned char *)X86_CODE64,
116  sizeof(X86_CODE64) - 1,
117  "X86 64 (Intel syntax)"
118  },
119 #endif
120 #ifdef CAPSTONE_HAS_ARM
121  {
122  CS_ARCH_ARM,
123  CS_MODE_ARM,
124  (unsigned char *)ARM_CODE,
125  sizeof(ARM_CODE) - 1,
126  "ARM"
127  },
128  {
129  CS_ARCH_ARM,
131  (unsigned char *)THUMB_CODE2,
132  sizeof(THUMB_CODE2) - 1,
133  "THUMB-2"
134  },
135  {
136  CS_ARCH_ARM,
137  CS_MODE_ARM,
138  (unsigned char *)ARM_CODE2,
139  sizeof(ARM_CODE2) - 1,
140  "ARM: Cortex-A15 + NEON"
141  },
142  {
143  CS_ARCH_ARM,
145  (unsigned char *)THUMB_CODE,
146  sizeof(THUMB_CODE) - 1,
147  "THUMB"
148  },
149 #endif
150 #ifdef CAPSTONE_HAS_MIPS
151  {
152  CS_ARCH_MIPS,
154  (unsigned char *)MIPS_CODE,
155  sizeof(MIPS_CODE) - 1,
156  "MIPS-32 (Big-endian)"
157  },
158  {
159  CS_ARCH_MIPS,
161  (unsigned char *)MIPS_CODE2,
162  sizeof(MIPS_CODE2) - 1,
163  "MIPS-64-EL (Little-endian)"
164  },
165 #endif
166 #ifdef CAPSTONE_HAS_ARM64
167  {
169  CS_MODE_ARM,
170  (unsigned char *)ARM64_CODE,
171  sizeof(ARM64_CODE) - 1,
172  "ARM-64"
173  },
174 #endif
175 #ifdef CAPSTONE_HAS_POWERPC
176  {
177  CS_ARCH_PPC,
179  (unsigned char*)PPC_CODE,
180  sizeof(PPC_CODE) - 1,
181  "PPC-64"
182  },
183 #endif
184 #ifdef CAPSTONE_HAS_SPARC
185  {
188  (unsigned char*)SPARC_CODE,
189  sizeof(SPARC_CODE) - 1,
190  "Sparc"
191  },
192  {
195  (unsigned char*)SPARCV9_CODE,
196  sizeof(SPARCV9_CODE) - 1,
197  "SparcV9"
198  },
199 #endif
200 #ifdef CAPSTONE_HAS_SYSZ
201  {
202  CS_ARCH_SYSZ,
203  (cs_mode)0,
204  (unsigned char*)SYSZ_CODE,
205  sizeof(SYSZ_CODE) - 1,
206  "SystemZ"
207  },
208 #endif
209 #ifdef CAPSTONE_HAS_XCORE
210  {
212  (cs_mode)0,
213  (unsigned char*)XCORE_CODE,
214  sizeof(XCORE_CODE) - 1,
215  "XCore"
216  },
217 #endif
218 #ifdef CAPSTONE_HAS_M680X
219  {
222  (unsigned char*)M680X_CODE,
223  sizeof(M680X_CODE) - 1,
224  "M680X_6809"
225  },
226 #endif
227 #ifdef CAPSTONE_HAS_MOS65XX
228  {
231  (unsigned char*)MOS65XX_CODE,
232  sizeof(MOS65XX_CODE) - 1,
233  "MOS65XX"
234  },
235 #endif
236  };
237 
238  csh handle;
239  uint64_t address;
240  cs_insn *insn;
241  cs_detail *detail;
242  int i;
243  cs_err err;
244  const uint8_t *code;
245  size_t size;
246 
247  for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
248  printf("****************\n");
249  printf("Platform: %s\n", platforms[i].comment);
251  if (err) {
252  printf("Failed on cs_open() with error returned: %u\n", err);
253  abort();
254  }
255 
256  if (platforms[i].opt_type)
258 
260 
261  // allocate memory for the cache to be used by cs_disasm_iter()
262  insn = cs_malloc(handle);
263 
265  printf("Disasm:\n");
266 
267  address = 0x1000;
268  code = platforms[i].code;
269  size = platforms[i].size;
270  while(cs_disasm_iter(handle, &code, &size, &address, insn)) {
271  int n;
272 
273  printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
274  insn->address, insn->mnemonic, insn->op_str,
275  insn->id, cs_insn_name(handle, insn->id));
276 
277  // print implicit registers used by this instruction
278  detail = insn->detail;
279 
280  if (detail->regs_read_count > 0) {
281  printf("\tImplicit registers read: ");
282  for (n = 0; n < detail->regs_read_count; n++) {
283  printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
284  }
285  printf("\n");
286  }
287 
288  // print implicit registers modified by this instruction
289  if (detail->regs_write_count > 0) {
290  printf("\tImplicit registers modified: ");
291  for (n = 0; n < detail->regs_write_count; n++) {
292  printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
293  }
294  printf("\n");
295  }
296 
297  // print the groups this instruction belong to
298  if (detail->groups_count > 0) {
299  printf("\tThis instruction belongs to groups: ");
300  for (n = 0; n < detail->groups_count; n++) {
301  printf("%s ", cs_group_name(handle, detail->groups[n]));
302  }
303  printf("\n");
304  }
305  }
306 
307  printf("\n");
308 
309  // free memory allocated by cs_malloc()
310  cs_free(insn, 1);
311 
312  cs_close(&handle);
313  }
314 }
315 
316 int main()
317 {
318  test();
319 
320  return 0;
321 }
xds_interop_client.str
str
Definition: xds_interop_client.py:487
ARM_CODE2
#define ARM_CODE2
cs_close
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle)
Definition: cs.c:522
cs_opt_type
cs_opt_type
Runtime option for the disassembled engine.
Definition: capstone.h:169
CS_OPT_SYNTAX
@ CS_OPT_SYNTAX
Assembly output syntax.
Definition: capstone.h:171
main
int main()
Definition: test_iter.c:316
CS_MODE_32
@ CS_MODE_32
32-bit mode (X86)
Definition: capstone.h:107
CS_MODE_LITTLE_ENDIAN
@ CS_MODE_LITTLE_ENDIAN
little-endian mode (default mode)
Definition: capstone.h:104
platform::opt_type
cs_opt_type opt_type
Definition: test_basic.c:16
platform::code
unsigned char * code
Definition: test_arm_regression.c:21
CS_ARCH_MOS65XX
@ CS_ARCH_MOS65XX
MOS65XX architecture (including MOS6502)
Definition: capstone.h:87
CS_MODE_ARM
@ CS_MODE_ARM
32-bit ARM
Definition: capstone.h:105
MOS65XX_CODE
#define MOS65XX_CODE
CS_ARCH_PPC
@ CS_ARCH_PPC
PowerPC architecture.
Definition: capstone.h:79
printf
_Use_decl_annotations_ int __cdecl printf(const char *_Format,...)
Definition: cs_driver.c:91
error_ref_leak.err
err
Definition: error_ref_leak.py:35
test_basic.M680X_CODE
M680X_CODE
Definition: test_basic.py:36
cs_open
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
Definition: cs.c:474
platform::mode
cs_mode mode
Definition: test_arm_regression.c:20
cs_arch
cs_arch
Architecture type.
Definition: capstone.h:74
mode
const char int mode
Definition: bloaty/third_party/zlib/contrib/minizip/ioapi.h:135
CS_OPT_DETAIL
@ CS_OPT_DETAIL
Break down instruction structure into details.
Definition: capstone.h:172
detail
Definition: test_winkernel.cpp:39
uint8_t
unsigned char uint8_t
Definition: stdint-msvc2008.h:78
CS_MODE_16
@ CS_MODE_16
16-bit mode (X86)
Definition: capstone.h:106
grpc_status._async.code
code
Definition: grpcio_status/grpc_status/_async.py:34
CS_ARCH_M680X
@ CS_ARCH_M680X
680X architecture
Definition: capstone.h:85
MIPS_CODE2
#define MIPS_CODE2
cs_option
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
Definition: cs.c:670
X86_CODE16
#define X86_CODE16
cs_mode
cs_mode
Mode type.
Definition: capstone.h:103
capstone.h
cs_insn_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_insn_name(csh ud, unsigned int insn)
Definition: cs.c:1188
c
void c(T a)
Definition: miscompile_with_no_unique_address_test.cc:40
X86_CODE64
#define X86_CODE64
ARM_CODE
#define ARM_CODE
cs_opt_value
cs_opt_value
Runtime option value (associated with option type above)
Definition: capstone.h:182
CS_ARCH_SYSZ
@ CS_ARCH_SYSZ
SystemZ architecture.
Definition: capstone.h:81
cs_reg_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
Definition: cs.c:1176
SPARCV9_CODE
#define SPARCV9_CODE
CS_ARCH_X86
@ CS_ARCH_X86
X86 architecture (including x86 & x86-64)
Definition: capstone.h:78
platform.h
uint64_t
unsigned __int64 uint64_t
Definition: stdint-msvc2008.h:90
MIPS_CODE
#define MIPS_CODE
print_string_hex
static void print_string_hex(unsigned char *str, size_t len)
Definition: test_iter.c:21
CS_OPT_SYNTAX_ATT
@ CS_OPT_SYNTAX_ATT
X86 ATT asm syntax (CS_OPT_SYNTAX).
Definition: capstone.h:187
THUMB_CODE2
#define THUMB_CODE2
THUMB_CODE
#define THUMB_CODE
CS_OPT_ON
@ CS_OPT_ON
Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
Definition: capstone.h:184
CS_MODE_THUMB
@ CS_MODE_THUMB
ARM's Thumb mode, including Thumb-2.
Definition: capstone.h:109
platform::comment
char * comment
Definition: test_arm_regression.c:23
CS_MODE_BIG_ENDIAN
@ CS_MODE_BIG_ENDIAN
big-endian mode
Definition: capstone.h:124
arch
cs_arch arch
Definition: cstool.c:13
CS_MODE_M680X_6809
@ CS_MODE_M680X_6809
M680X Motorola 6809 mode.
Definition: capstone.h:133
platform::arch
cs_arch arch
Definition: test_arm_regression.c:19
XCORE_CODE
#define XCORE_CODE
n
int n
Definition: abseil-cpp/absl/container/btree_test.cc:1080
ARM64_CODE
#define ARM64_CODE
CS_ARCH_SPARC
@ CS_ARCH_SPARC
Sparc architecture.
Definition: capstone.h:80
CS_ARCH_MIPS
@ CS_ARCH_MIPS
Mips architecture.
Definition: capstone.h:77
csh
size_t csh
Definition: capstone.h:71
SPARC_CODE
#define SPARC_CODE
cs_disasm_iter
CAPSTONE_EXPORT bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size, uint64_t *address, cs_insn *insn)
Definition: cs.c:1080
CS_MODE_MIPS64
@ CS_MODE_MIPS64
Mips64 ISA (Mips)
Definition: capstone.h:126
X86_CODE32
#define X86_CODE32
CS_MODE_64
@ CS_MODE_64
64-bit mode (X86, PPC)
Definition: capstone.h:108
CS_ARCH_ARM
@ CS_ARCH_ARM
ARM architecture (including Thumb, Thumb-2)
Definition: capstone.h:75
cs_group_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_group_name(csh ud, unsigned int group)
Definition: cs.c:1200
platform::opt_value
cs_opt_value opt_value
Definition: test_basic.c:17
cs_malloc
CAPSTONE_EXPORT cs_insn *CAPSTONE_API cs_malloc(csh ud)
Definition: cs.c:1052
PPC_CODE
#define PPC_CODE
cs_free
CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
Definition: cs.c:1039
CS_MODE_V9
@ CS_MODE_V9
SparcV9 mode (Sparc)
Definition: capstone.h:116
handle
static csh handle
Definition: test_arm_regression.c:16
CS_ARCH_ARM64
@ CS_ARCH_ARM64
ARM-64, also called AArch64.
Definition: capstone.h:76
code
Definition: bloaty/third_party/zlib/contrib/infback9/inftree9.h:24
len
int len
Definition: abseil-cpp/absl/base/internal/low_level_alloc_test.cc:46
platforms
struct platform platforms[]
Definition: fuzz_diff.c:18
size
voidpf void uLong size
Definition: bloaty/third_party/zlib/contrib/minizip/ioapi.h:136
SYSZ_CODE
#define SYSZ_CODE
CS_MODE_MIPS32
@ CS_MODE_MIPS32
Mips32 ISA (Mips)
Definition: capstone.h:125
CS_ARCH_XCORE
@ CS_ARCH_XCORE
XCore architecture.
Definition: capstone.h:82
platform
Definition: test_arm_regression.c:18
platform::size
size_t size
Definition: test_arm_regression.c:22
i
uint64_t i
Definition: abseil-cpp/absl/container/btree_benchmark.cc:230
test
static void test()
Definition: test_iter.c:32
test_evm.detail
detail
Definition: test_evm.py:9


grpc
Author(s):
autogenerated on Fri May 16 2025 03:00:28