ocaml.c
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1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
3 
4 #include <stdio.h> // debug
5 #include <string.h>
6 #include <caml/mlvalues.h>
7 #include <caml/memory.h>
8 #include <caml/alloc.h>
9 #include <caml/fail.h>
10 
11 #include "capstone/capstone.h"
12 
13 #define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
14 
15 
16 // count the number of positive members in @list
17 static unsigned int list_count(uint8_t *list, unsigned int max)
18 {
19  unsigned int i;
20 
21  for(i = 0; i < max; i++)
22  if (list[i] == 0)
23  return i;
24 
25  return max;
26 }
27 
28 CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t code_len, uint64_t addr, size_t count)
29 {
30  CAMLparam0();
31  CAMLlocal5(list, cons, rec_insn, array, tmp);
32  CAMLlocal4(arch_info, op_info_val, tmp2, tmp3);
33  cs_insn *insn;
34  size_t c;
35 
36  list = Val_emptylist;
37 
38  c = cs_disasm(handle, code, code_len, addr, count, &insn);
39  if (c) {
40  //printf("Found %lu insn, addr: %lx\n", c, addr);
41  uint64_t j;
42  for (j = c; j > 0; j--) {
43  unsigned int lcount, i;
44  cons = caml_alloc(2, 0);
45 
46  rec_insn = caml_alloc(10, 0);
47  Store_field(rec_insn, 0, Val_int(insn[j-1].id));
48  Store_field(rec_insn, 1, Val_int(insn[j-1].address));
49  Store_field(rec_insn, 2, Val_int(insn[j-1].size));
50 
51  // copy raw bytes of instruction
52  lcount = insn[j-1].size;
53  if (lcount) {
54  array = caml_alloc(lcount, 0);
55  for (i = 0; i < lcount; i++) {
56  Store_field(array, i, Val_int(insn[j-1].bytes[i]));
57  }
58  } else
59  array = Atom(0); // empty list
60  Store_field(rec_insn, 3, array);
61 
62  Store_field(rec_insn, 4, caml_copy_string(insn[j-1].mnemonic));
63  Store_field(rec_insn, 5, caml_copy_string(insn[j-1].op_str));
64 
65  // copy read registers
66  if (insn[0].detail) {
67  lcount = (insn[j-1]).detail->regs_read_count;
68  if (lcount) {
69  array = caml_alloc(lcount, 0);
70  for (i = 0; i < lcount; i++) {
71  Store_field(array, i, Val_int(insn[j-1].detail->regs_read[i]));
72  }
73  } else
74  array = Atom(0); // empty list
75  } else
76  array = Atom(0); // empty list
77  Store_field(rec_insn, 6, array);
78 
79  if (insn[0].detail) {
80  lcount = (insn[j-1]).detail->regs_write_count;
81  if (lcount) {
82  array = caml_alloc(lcount, 0);
83  for (i = 0; i < lcount; i++) {
84  Store_field(array, i, Val_int(insn[j-1].detail->regs_write[i]));
85  }
86  } else
87  array = Atom(0); // empty list
88  } else
89  array = Atom(0); // empty list
90  Store_field(rec_insn, 7, array);
91 
92  if (insn[0].detail) {
93  lcount = (insn[j-1]).detail->groups_count;
94  if (lcount) {
95  array = caml_alloc(lcount, 0);
96  for (i = 0; i < lcount; i++) {
97  Store_field(array, i, Val_int(insn[j-1].detail->groups[i]));
98  }
99  } else
100  array = Atom(0); // empty list
101  } else
102  array = Atom(0); // empty list
103  Store_field(rec_insn, 8, array);
104 
105  if (insn[j-1].detail) {
106  switch(arch) {
107  case CS_ARCH_ARM:
108  arch_info = caml_alloc(1, 0);
109 
110  op_info_val = caml_alloc(10, 0);
111  Store_field(op_info_val, 0, Val_bool(insn[j-1].detail->arm.usermode));
112  Store_field(op_info_val, 1, Val_int(insn[j-1].detail->arm.vector_size));
113  Store_field(op_info_val, 2, Val_int(insn[j-1].detail->arm.vector_data));
114  Store_field(op_info_val, 3, Val_int(insn[j-1].detail->arm.cps_mode));
115  Store_field(op_info_val, 4, Val_int(insn[j-1].detail->arm.cps_flag));
116  Store_field(op_info_val, 5, Val_int(insn[j-1].detail->arm.cc));
117  Store_field(op_info_val, 6, Val_bool(insn[j-1].detail->arm.update_flags));
118  Store_field(op_info_val, 7, Val_bool(insn[j-1].detail->arm.writeback));
119  Store_field(op_info_val, 8, Val_int(insn[j-1].detail->arm.mem_barrier));
120 
121  lcount = insn[j-1].detail->arm.op_count;
122  if (lcount > 0) {
123  array = caml_alloc(lcount, 0);
124  for (i = 0; i < lcount; i++) {
125  tmp2 = caml_alloc(6, 0);
126  switch(insn[j-1].detail->arm.operands[i].type) {
127  case ARM_OP_REG:
128  case ARM_OP_SYSREG:
129  tmp = caml_alloc(1, 1);
130  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].reg));
131  break;
132  case ARM_OP_CIMM:
133  tmp = caml_alloc(1, 2);
134  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm));
135  break;
136  case ARM_OP_PIMM:
137  tmp = caml_alloc(1, 3);
138  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm));
139  break;
140  case ARM_OP_IMM:
141  tmp = caml_alloc(1, 4);
142  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm));
143  break;
144  case ARM_OP_FP:
145  tmp = caml_alloc(1, 5);
146  Store_field(tmp, 0, caml_copy_double(insn[j-1].detail->arm.operands[i].fp));
147  break;
148  case ARM_OP_MEM:
149  tmp = caml_alloc(1, 6);
150  tmp3 = caml_alloc(5, 0);
151  Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm.operands[i].mem.base));
152  Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm.operands[i].mem.index));
153  Store_field(tmp3, 2, Val_int(insn[j-1].detail->arm.operands[i].mem.scale));
154  Store_field(tmp3, 3, Val_int(insn[j-1].detail->arm.operands[i].mem.disp));
155  Store_field(tmp3, 4, Val_int(insn[j-1].detail->arm.operands[i].mem.lshift));
156  Store_field(tmp, 0, tmp3);
157  break;
158  case ARM_OP_SETEND:
159  tmp = caml_alloc(1, 7);
160  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].setend));
161  break;
162  default: break;
163  }
164  tmp3 = caml_alloc(2, 0);
165  Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm.operands[i].shift.type));
166  Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm.operands[i].shift.value));
167  Store_field(tmp2, 0, Val_int(insn[j-1].detail->arm.operands[i].vector_index));
168  Store_field(tmp2, 1, tmp3);
169  Store_field(tmp2, 2, tmp);
170  Store_field(tmp2, 3, Val_bool(insn[j-1].detail->arm.operands[i].subtracted));
171  Store_field(tmp2, 4, Val_int(insn[j-1].detail->arm.operands[i].access));
172  Store_field(tmp2, 5, Val_int(insn[j-1].detail->arm.operands[i].neon_lane));
173  Store_field(array, i, tmp2);
174  }
175  } else // empty list
176  array = Atom(0);
177 
178  Store_field(op_info_val, 9, array);
179 
180  // finally, insert this into arch_info
181  Store_field(arch_info, 0, op_info_val);
182 
183  Store_field(rec_insn, 9, arch_info);
184 
185  break;
186  case CS_ARCH_ARM64:
187  arch_info = caml_alloc(1, 1);
188 
189  op_info_val = caml_alloc(4, 0);
190  Store_field(op_info_val, 0, Val_int(insn[j-1].detail->arm64.cc));
191  Store_field(op_info_val, 1, Val_bool(insn[j-1].detail->arm64.update_flags));
192  Store_field(op_info_val, 2, Val_bool(insn[j-1].detail->arm64.writeback));
193 
194  lcount = insn[j-1].detail->arm64.op_count;
195  if (lcount > 0) {
196  array = caml_alloc(lcount, 0);
197  for (i = 0; i < lcount; i++) {
198  tmp2 = caml_alloc(6, 0);
199  switch(insn[j-1].detail->arm64.operands[i].type) {
200  case ARM64_OP_REG:
201  tmp = caml_alloc(1, 1);
202  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg));
203  break;
204  case ARM64_OP_CIMM:
205  tmp = caml_alloc(1, 2);
206  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].imm));
207  break;
208  case ARM64_OP_IMM:
209  tmp = caml_alloc(1, 3);
210  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].imm));
211  break;
212  case ARM64_OP_FP:
213  tmp = caml_alloc(1, 4);
214  Store_field(tmp, 0, caml_copy_double(insn[j-1].detail->arm64.operands[i].fp));
215  break;
216  case ARM64_OP_MEM:
217  tmp = caml_alloc(1, 5);
218  tmp3 = caml_alloc(3, 0);
219  Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm64.operands[i].mem.base));
220  Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm64.operands[i].mem.index));
221  Store_field(tmp3, 2, Val_int(insn[j-1].detail->arm64.operands[i].mem.disp));
222  Store_field(tmp, 0, tmp3);
223  break;
224  case ARM64_OP_REG_MRS:
225  tmp = caml_alloc(1, 6);
226  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg));
227  break;
228  case ARM64_OP_REG_MSR:
229  tmp = caml_alloc(1, 7);
230  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg));
231  break;
232  case ARM64_OP_PSTATE:
233  tmp = caml_alloc(1, 8);
234  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].pstate));
235  break;
236  case ARM64_OP_SYS:
237  tmp = caml_alloc(1, 9);
238  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].sys));
239  break;
240  case ARM64_OP_PREFETCH:
241  tmp = caml_alloc(1, 10);
242  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].prefetch));
243  break;
244  case ARM64_OP_BARRIER:
245  tmp = caml_alloc(1, 11);
246  Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].barrier));
247  break;
248  default: break;
249  }
250  tmp3 = caml_alloc(2, 0);
251  Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm64.operands[i].shift.type));
252  Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm64.operands[i].shift.value));
253 
254  Store_field(tmp2, 0, Val_int(insn[j-1].detail->arm64.operands[i].vector_index));
255  Store_field(tmp2, 1, Val_int(insn[j-1].detail->arm64.operands[i].vas));
256  Store_field(tmp2, 2, Val_int(insn[j-1].detail->arm64.operands[i].vess));
257  Store_field(tmp2, 3, tmp3);
258  Store_field(tmp2, 4, Val_int(insn[j-1].detail->arm64.operands[i].ext));
259  Store_field(tmp2, 5, tmp);
260 
261  Store_field(array, i, tmp2);
262  }
263  } else // empty array
264  array = Atom(0);
265 
266  Store_field(op_info_val, 3, array);
267 
268  // finally, insert this into arch_info
269  Store_field(arch_info, 0, op_info_val);
270 
271  Store_field(rec_insn, 9, arch_info);
272 
273  break;
274  case CS_ARCH_MIPS:
275  arch_info = caml_alloc(1, 2);
276 
277  op_info_val = caml_alloc(1, 0);
278 
279  lcount = insn[j-1].detail->mips.op_count;
280  if (lcount > 0) {
281  array = caml_alloc(lcount, 0);
282  for (i = 0; i < lcount; i++) {
283  tmp2 = caml_alloc(1, 0);
284  switch(insn[j-1].detail->mips.operands[i].type) {
285  case MIPS_OP_REG:
286  tmp = caml_alloc(1, 1);
287  Store_field(tmp, 0, Val_int(insn[j-1].detail->mips.operands[i].reg));
288  break;
289  case MIPS_OP_IMM:
290  tmp = caml_alloc(1, 2);
291  Store_field(tmp, 0, Val_int(insn[j-1].detail->mips.operands[i].imm));
292  break;
293  case MIPS_OP_MEM:
294  tmp = caml_alloc(1, 3);
295  tmp3 = caml_alloc(2, 0);
296  Store_field(tmp3, 0, Val_int(insn[j-1].detail->mips.operands[i].mem.base));
297  Store_field(tmp3, 1, Val_int(insn[j-1].detail->mips.operands[i].mem.disp));
298  Store_field(tmp, 0, tmp3);
299  break;
300  default: break;
301  }
302  Store_field(tmp2, 0, tmp);
303  Store_field(array, i, tmp2);
304  }
305  } else // empty array
306  array = Atom(0);
307 
308  Store_field(op_info_val, 0, array);
309 
310  // finally, insert this into arch_info
311  Store_field(arch_info, 0, op_info_val);
312 
313  Store_field(rec_insn, 9, arch_info);
314 
315  break;
316  case CS_ARCH_X86:
317  arch_info = caml_alloc(1, 3);
318 
319  op_info_val = caml_alloc(17, 0);
320 
321  // fill prefix
322  lcount = list_count(insn[j-1].detail->x86.prefix, ARR_SIZE(insn[j-1].detail->x86.prefix));
323  if (lcount) {
324  array = caml_alloc(lcount, 0);
325  for (i = 0; i < lcount; i++) {
326  Store_field(array, i, Val_int(insn[j-1].detail->x86.prefix[i]));
327  }
328  } else
329  array = Atom(0);
330  Store_field(op_info_val, 0, array);
331 
332  // fill opcode
333  lcount = list_count(insn[j-1].detail->x86.opcode, ARR_SIZE(insn[j-1].detail->x86.opcode));
334  if (lcount) {
335  array = caml_alloc(lcount, 0);
336  for (i = 0; i < lcount; i++) {
337  Store_field(array, i, Val_int(insn[j-1].detail->x86.opcode[i]));
338  }
339  } else
340  array = Atom(0);
341  Store_field(op_info_val, 1, array);
342 
343  Store_field(op_info_val, 2, Val_int(insn[j-1].detail->x86.rex));
344 
345  Store_field(op_info_val, 3, Val_int(insn[j-1].detail->x86.addr_size));
346 
347  Store_field(op_info_val, 4, Val_int(insn[j-1].detail->x86.modrm));
348 
349  Store_field(op_info_val, 5, Val_int(insn[j-1].detail->x86.sib));
350 
351  Store_field(op_info_val, 6, Val_int(insn[j-1].detail->x86.disp));
352 
353  Store_field(op_info_val, 7, Val_int(insn[j-1].detail->x86.sib_index));
354 
355  Store_field(op_info_val, 8, Val_int(insn[j-1].detail->x86.sib_scale));
356 
357  Store_field(op_info_val, 9, Val_int(insn[j-1].detail->x86.sib_base));
358 
359  Store_field(op_info_val, 10, Val_int(insn[j-1].detail->x86.xop_cc));
360  Store_field(op_info_val, 11, Val_int(insn[j-1].detail->x86.sse_cc));
361  Store_field(op_info_val, 12, Val_int(insn[j-1].detail->x86.avx_cc));
362  Store_field(op_info_val, 13, Val_int(insn[j-1].detail->x86.avx_sae));
363  Store_field(op_info_val, 14, Val_int(insn[j-1].detail->x86.avx_rm));
364  Store_field(op_info_val, 15, Val_int(insn[j-1].detail->x86.eflags));
365 
366  lcount = insn[j-1].detail->x86.op_count;
367  if (lcount > 0) {
368  array = caml_alloc(lcount, 0);
369  for (i = 0; i < lcount; i++) {
370  switch(insn[j-1].detail->x86.operands[i].type) {
371  case X86_OP_REG:
372  tmp = caml_alloc(5, 1);
373  Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].reg));
374  break;
375  case X86_OP_IMM:
376  tmp = caml_alloc(5, 2);
377  Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].imm));
378  break;
379  case X86_OP_MEM:
380  tmp = caml_alloc(5, 3);
381  tmp2 = caml_alloc(5, 0);
382  Store_field(tmp2, 0, Val_int(insn[j-1].detail->x86.operands[i].mem.segment));
383  Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].mem.base));
384  Store_field(tmp2, 2, Val_int(insn[j-1].detail->x86.operands[i].mem.index));
385  Store_field(tmp2, 3, Val_int(insn[j-1].detail->x86.operands[i].mem.scale));
386  Store_field(tmp2, 4, Val_int(insn[j-1].detail->x86.operands[i].mem.disp));
387 
388  Store_field(tmp, 0, tmp2);
389  break;
390  default:
391  break;
392  }
393  Store_field(tmp, 1, Val_int(insn[j-1].detail->x86.operands[i].size));
394  Store_field(tmp, 2, Val_int(insn[j-1].detail->x86.operands[i].access));
395  Store_field(tmp, 3, Val_int(insn[j-1].detail->x86.operands[i].avx_bcast));
396  Store_field(tmp, 4, Val_int(insn[j-1].detail->x86.operands[i].avx_zero_opmask));
397  tmp2 = caml_alloc(1, 0);
398  Store_field(tmp2, 0, tmp);
399  Store_field(array, i, tmp2);
400  }
401  } else // empty array
402  array = Atom(0);
403  Store_field(op_info_val, 16, array);
404 
405  // finally, insert this into arch_info
406  Store_field(arch_info, 0, op_info_val);
407 
408  Store_field(rec_insn, 9, arch_info);
409  break;
410 
411  case CS_ARCH_PPC:
412  arch_info = caml_alloc(1, 4);
413 
414  op_info_val = caml_alloc(4, 0);
415 
416  Store_field(op_info_val, 0, Val_int(insn[j-1].detail->ppc.bc));
417  Store_field(op_info_val, 1, Val_int(insn[j-1].detail->ppc.bh));
418  Store_field(op_info_val, 2, Val_bool(insn[j-1].detail->ppc.update_cr0));
419 
420  lcount = insn[j-1].detail->ppc.op_count;
421  if (lcount > 0) {
422  array = caml_alloc(lcount, 0);
423  for (i = 0; i < lcount; i++) {
424  tmp2 = caml_alloc(1, 0);
425  switch(insn[j-1].detail->ppc.operands[i].type) {
426  case PPC_OP_REG:
427  tmp = caml_alloc(1, 1);
428  Store_field(tmp, 0, Val_int(insn[j-1].detail->ppc.operands[i].reg));
429  break;
430  case PPC_OP_IMM:
431  tmp = caml_alloc(1, 2);
432  Store_field(tmp, 0, Val_int(insn[j-1].detail->ppc.operands[i].imm));
433  break;
434  case PPC_OP_MEM:
435  tmp = caml_alloc(1, 3);
436  tmp3 = caml_alloc(2, 0);
437  Store_field(tmp3, 0, Val_int(insn[j-1].detail->ppc.operands[i].mem.base));
438  Store_field(tmp3, 1, Val_int(insn[j-1].detail->ppc.operands[i].mem.disp));
439  Store_field(tmp, 0, tmp3);
440  break;
441  case PPC_OP_CRX:
442  tmp = caml_alloc(1, 4);
443  tmp3 = caml_alloc(3, 0);
444  Store_field(tmp3, 0, Val_int(insn[j-1].detail->ppc.operands[i].crx.scale));
445  Store_field(tmp3, 1, Val_int(insn[j-1].detail->ppc.operands[i].crx.reg));
446  Store_field(tmp3, 2, Val_int(insn[j-1].detail->ppc.operands[i].crx.cond));
447  Store_field(tmp, 0, tmp3);
448  break;
449  default: break;
450  }
451  Store_field(tmp2, 0, tmp);
452  Store_field(array, i, tmp2);
453  }
454  } else // empty array
455  array = Atom(0);
456 
457  Store_field(op_info_val, 3, array);
458 
459  // finally, insert this into arch_info
460  Store_field(arch_info, 0, op_info_val);
461 
462  Store_field(rec_insn, 9, arch_info);
463 
464  break;
465 
466  case CS_ARCH_SPARC:
467  arch_info = caml_alloc(1, 5);
468 
469  op_info_val = caml_alloc(3, 0);
470 
471  Store_field(op_info_val, 0, Val_int(insn[j-1].detail->sparc.cc));
472  Store_field(op_info_val, 1, Val_int(insn[j-1].detail->sparc.hint));
473 
474  lcount = insn[j-1].detail->sparc.op_count;
475  if (lcount > 0) {
476  array = caml_alloc(lcount, 0);
477  for (i = 0; i < lcount; i++) {
478  tmp2 = caml_alloc(1, 0);
479  switch(insn[j-1].detail->sparc.operands[i].type) {
480  case SPARC_OP_REG:
481  tmp = caml_alloc(1, 1);
482  Store_field(tmp, 0, Val_int(insn[j-1].detail->sparc.operands[i].reg));
483  break;
484  case SPARC_OP_IMM:
485  tmp = caml_alloc(1, 2);
486  Store_field(tmp, 0, Val_int(insn[j-1].detail->sparc.operands[i].imm));
487  break;
488  case SPARC_OP_MEM:
489  tmp = caml_alloc(1, 3);
490  tmp3 = caml_alloc(3, 0);
491  Store_field(tmp3, 0, Val_int(insn[j-1].detail->sparc.operands[i].mem.base));
492  Store_field(tmp3, 1, Val_int(insn[j-1].detail->sparc.operands[i].mem.index));
493  Store_field(tmp3, 2, Val_int(insn[j-1].detail->sparc.operands[i].mem.disp));
494  Store_field(tmp, 0, tmp3);
495  break;
496  default: break;
497  }
498  Store_field(tmp2, 0, tmp);
499  Store_field(array, i, tmp2);
500  }
501  } else // empty array
502  array = Atom(0);
503 
504  Store_field(op_info_val, 2, array);
505 
506  // finally, insert this into arch_info
507  Store_field(arch_info, 0, op_info_val);
508 
509  Store_field(rec_insn, 9, arch_info);
510 
511  break;
512 
513  case CS_ARCH_SYSZ:
514  arch_info = caml_alloc(1, 6);
515 
516  op_info_val = caml_alloc(2, 0);
517 
518  Store_field(op_info_val, 0, Val_int(insn[j-1].detail->sysz.cc));
519 
520  lcount = insn[j-1].detail->sysz.op_count;
521  if (lcount > 0) {
522  array = caml_alloc(lcount, 0);
523  for (i = 0; i < lcount; i++) {
524  tmp2 = caml_alloc(1, 0);
525  switch(insn[j-1].detail->sysz.operands[i].type) {
526  case SYSZ_OP_REG:
527  tmp = caml_alloc(1, 1);
528  Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].reg));
529  break;
530  case SYSZ_OP_ACREG:
531  tmp = caml_alloc(1, 2);
532  Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].reg));
533  break;
534  case SYSZ_OP_IMM:
535  tmp = caml_alloc(1, 3);
536  Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].imm));
537  break;
538  case SYSZ_OP_MEM:
539  tmp = caml_alloc(1, 4);
540  tmp3 = caml_alloc(4, 0);
541  Store_field(tmp3, 0, Val_int(insn[j-1].detail->sysz.operands[i].mem.base));
542  Store_field(tmp3, 1, Val_int(insn[j-1].detail->sysz.operands[i].mem.index));
543  Store_field(tmp3, 2, caml_copy_int64(insn[j-1].detail->sysz.operands[i].mem.length));
544  Store_field(tmp3, 3, caml_copy_int64(insn[j-1].detail->sysz.operands[i].mem.disp));
545  Store_field(tmp, 0, tmp3);
546  break;
547  default: break;
548  }
549  Store_field(tmp2, 0, tmp);
550  Store_field(array, i, tmp2);
551  }
552  } else // empty array
553  array = Atom(0);
554 
555  Store_field(op_info_val, 1, array);
556 
557  // finally, insert this into arch_info
558  Store_field(arch_info, 0, op_info_val);
559 
560  Store_field(rec_insn, 9, arch_info);
561 
562  break;
563 
564  case CS_ARCH_XCORE:
565  arch_info = caml_alloc(1, 7);
566 
567  op_info_val = caml_alloc(1, 0);
568 
569  lcount = insn[j-1].detail->xcore.op_count;
570  if (lcount > 0) {
571  array = caml_alloc(lcount, 0);
572  for (i = 0; i < lcount; i++) {
573  tmp2 = caml_alloc(1, 0);
574  switch(insn[j-1].detail->xcore.operands[i].type) {
575  case XCORE_OP_REG:
576  tmp = caml_alloc(1, 1);
577  Store_field(tmp, 0, Val_int(insn[j-1].detail->xcore.operands[i].reg));
578  break;
579  case XCORE_OP_IMM:
580  tmp = caml_alloc(1, 2);
581  Store_field(tmp, 0, Val_int(insn[j-1].detail->xcore.operands[i].imm));
582  break;
583  case XCORE_OP_MEM:
584  tmp = caml_alloc(1, 3);
585  tmp3 = caml_alloc(4, 0);
586  Store_field(tmp3, 0, Val_int(insn[j-1].detail->xcore.operands[i].mem.base));
587  Store_field(tmp3, 1, Val_int(insn[j-1].detail->xcore.operands[i].mem.index));
588  Store_field(tmp3, 2, caml_copy_int64(insn[j-1].detail->xcore.operands[i].mem.disp));
589  Store_field(tmp3, 3, caml_copy_int64(insn[j-1].detail->xcore.operands[i].mem.direct));
590  Store_field(tmp, 0, tmp3);
591  break;
592  default: break;
593  }
594  Store_field(tmp2, 0, tmp);
595  Store_field(array, i, tmp2);
596  }
597  } else // empty array
598  array = Atom(0);
599 
600  Store_field(op_info_val, 0, array);
601 
602  // finally, insert this into arch_info
603  Store_field(arch_info, 0, op_info_val);
604 
605  Store_field(rec_insn, 9, arch_info);
606 
607  break;
608 
609  case CS_ARCH_M680X:
610  arch_info = caml_alloc(1, 8);
611 
612  op_info_val = caml_alloc(2, 0); // struct cs_m680x
613  Store_field(op_info_val, 0, Val_int(insn[j-1].detail->m680x.flags));
614 
615  lcount = insn[j-1].detail->m680x.op_count;
616  if (lcount > 0) {
617  array = caml_alloc(lcount, 0);
618  for (i = 0; i < lcount; i++) {
619  tmp2 = caml_alloc(3, 0); // m680x_op
620  switch(insn[j-1].detail->m680x.operands[i].type) {
621  case M680X_OP_IMMEDIATE:
622  tmp = caml_alloc(1, 1); // imm
623  Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].imm));
624  break;
625  case M680X_OP_REGISTER:
626  tmp = caml_alloc(1, 2); // reg
627  Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].reg));
628  break;
629  case M680X_OP_INDEXED:
630  tmp = caml_alloc(1, 3);
631  tmp3 = caml_alloc(7, 0); // m680x_op_idx
632  Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].idx.base_reg));
633  Store_field(tmp3, 1, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_reg));
634  Store_field(tmp3, 2, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset));
635  Store_field(tmp3, 3, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_addr));
636  Store_field(tmp3, 4, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_bits));
637  Store_field(tmp3, 5, Val_int(insn[j-1].detail->m680x.operands[i].idx.inc_dec));
638  Store_field(tmp3, 6, Val_int(insn[j-1].detail->m680x.operands[i].idx.flags));
639  Store_field(tmp, 0, tmp3);
640  break;
641  case M680X_OP_RELATIVE:
642  tmp = caml_alloc(1, 4);
643  tmp3 = caml_alloc(2, 0); // m680x_op_rel
644  Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].rel.address));
645  Store_field(tmp3, 1, Val_int(insn[j-1].detail->m680x.operands[i].rel.offset));
646  Store_field(tmp, 0, tmp3);
647  break;
648  case M680X_OP_EXTENDED:
649  tmp = caml_alloc(1, 5);
650  tmp3 = caml_alloc(2, 0); // m680x_op_ext
651  Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].ext.address));
652  Store_field(tmp3, 1, Val_bool(insn[j-1].detail->m680x.operands[i].ext.indirect));
653  Store_field(tmp, 0, tmp3);
654  break;
655  case M680X_OP_DIRECT:
656  tmp = caml_alloc(1, 6); // direct_addr
657  Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].direct_addr));
658  break;
659  case M680X_OP_CONSTANT:
660  tmp = caml_alloc(1, 7); // const_val
661  Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].const_val));
662  break;
663  default: break;
664  }
665  Store_field(tmp2, 0, tmp); // add union
666  Store_field(tmp2, 1, Val_int(insn[j-1].detail->m680x.operands[i].size));
667  Store_field(tmp2, 2, Val_int(insn[j-1].detail->m680x.operands[i].access));
668  Store_field(array, i, tmp2); // add operand to operand array
669  }
670  } else // empty list
671  array = Atom(0);
672 
673  Store_field(op_info_val, 1, array);
674 
675  // finally, insert this into arch_info
676  Store_field(arch_info, 0, op_info_val);
677 
678  Store_field(rec_insn, 9, arch_info);
679 
680  break;
681 
682  default: break;
683  }
684  }
685 
686  Store_field(cons, 0, rec_insn); // head
687  Store_field(cons, 1, list); // tail
688  list = cons;
689  }
690  cs_free(insn, count);
691  }
692 
693  // do not free the handle here
694  //cs_close(&handle);
695  CAMLreturn(list);
696 }
697 
698 CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _addr, value _count)
699 {
700  CAMLparam5(_arch, _mode, _code, _addr, _count);
701  CAMLlocal1(head);
702  csh handle;
703  cs_arch arch;
704  cs_mode mode = 0;
705  const uint8_t *code;
706  uint64_t addr;
707  size_t count, code_len;
708 
709  switch (Int_val(_arch)) {
710  case 0:
711  arch = CS_ARCH_ARM;
712  break;
713  case 1:
714  arch = CS_ARCH_ARM64;
715  break;
716  case 2:
717  arch = CS_ARCH_MIPS;
718  break;
719  case 3:
720  arch = CS_ARCH_X86;
721  break;
722  case 4:
723  arch = CS_ARCH_PPC;
724  break;
725  case 5:
726  arch = CS_ARCH_SPARC;
727  break;
728  case 6:
729  arch = CS_ARCH_SYSZ;
730  break;
731  case 7:
732  arch = CS_ARCH_XCORE;
733  break;
734  case 8:
735  arch = CS_ARCH_M68K;
736  break;
737  case 9:
738  arch = CS_ARCH_TMS320C64X;
739  break;
740  case 10:
741  arch = CS_ARCH_M680X;
742  break;
743  default:
744  caml_invalid_argument("Invalid arch");
745  return Val_emptylist;
746  }
747 
748  while (_mode != Val_emptylist) {
749  head = Field(_mode, 0); /* accessing the head */
750  switch (Int_val(head)) {
751  case 0:
752  mode |= CS_MODE_LITTLE_ENDIAN;
753  break;
754  case 1:
755  mode |= CS_MODE_ARM;
756  break;
757  case 2:
758  mode |= CS_MODE_16;
759  break;
760  case 3:
761  mode |= CS_MODE_32;
762  break;
763  case 4:
764  mode |= CS_MODE_64;
765  break;
766  case 5:
767  mode |= CS_MODE_THUMB;
768  break;
769  case 6:
770  mode |= CS_MODE_MCLASS;
771  break;
772  case 7:
773  mode |= CS_MODE_V8;
774  break;
775  case 8:
776  mode |= CS_MODE_MICRO;
777  break;
778  case 9:
779  mode |= CS_MODE_MIPS3;
780  break;
781  case 10:
782  mode |= CS_MODE_MIPS32R6;
783  break;
784  case 11:
785  mode |= CS_MODE_MIPS2;
786  break;
787  case 12:
788  mode |= CS_MODE_V9;
789  break;
790  case 13:
791  mode |= CS_MODE_BIG_ENDIAN;
792  break;
793  case 14:
794  mode |= CS_MODE_MIPS32;
795  break;
796  case 15:
797  mode |= CS_MODE_MIPS64;
798  break;
799  case 16:
800  mode |= CS_MODE_QPX;
801  break;
802  case 17:
803  mode |= CS_MODE_M680X_6301;
804  break;
805  case 18:
806  mode |= CS_MODE_M680X_6309;
807  break;
808  case 19:
809  mode |= CS_MODE_M680X_6800;
810  break;
811  case 20:
812  mode |= CS_MODE_M680X_6801;
813  break;
814  case 21:
815  mode |= CS_MODE_M680X_6805;
816  break;
817  case 22:
818  mode |= CS_MODE_M680X_6808;
819  break;
820  case 23:
821  mode |= CS_MODE_M680X_6809;
822  break;
823  case 24:
824  mode |= CS_MODE_M680X_6811;
825  break;
826  case 25:
827  mode |= CS_MODE_M680X_CPU12;
828  break;
829  case 26:
830  mode |= CS_MODE_M680X_HCS08;
831  break;
832  default:
833  caml_invalid_argument("Invalid mode");
834  return Val_emptylist;
835  }
836  _mode = Field(_mode, 1); /* point to the tail for next loop */
837  }
838 
839  cs_err ret = cs_open(arch, mode, &handle);
840  if (ret != CS_ERR_OK) {
841  return Val_emptylist;
842  }
843 
844  code = (uint8_t *)String_val(_code);
845  code_len = caml_string_length(_code);
846  addr = Int64_val(_addr);
847  count = Int64_val(_count);
848 
849  CAMLreturn(_cs_disasm(arch, handle, code, code_len, addr, count));
850 }
851 
852 CAMLprim value ocaml_cs_disasm_internal(value _arch, value _handle, value _code, value _addr, value _count)
853 {
854  CAMLparam5(_arch, _handle, _code, _addr, _count);
855  csh handle;
856  cs_arch arch;
857  const uint8_t *code;
858  uint64_t addr, count, code_len;
859 
860  handle = Int64_val(_handle);
861 
862  arch = Int_val(_arch);
863  code = (uint8_t *)String_val(_code);
864  code_len = caml_string_length(_code);
865  addr = Int64_val(_addr);
866  count = Int64_val(_count);
867 
868  CAMLreturn(_cs_disasm(arch, handle, code, code_len, addr, count));
869 }
870 
871 CAMLprim value ocaml_open(value _arch, value _mode)
872 {
873  CAMLparam2(_arch, _mode);
874  CAMLlocal2(list, head);
875  csh handle;
876  cs_arch arch;
877  cs_mode mode = 0;
878 
879  list = Val_emptylist;
880 
881  switch (Int_val(_arch)) {
882  case 0:
883  arch = CS_ARCH_ARM;
884  break;
885  case 1:
886  arch = CS_ARCH_ARM64;
887  break;
888  case 2:
889  arch = CS_ARCH_MIPS;
890  break;
891  case 3:
892  arch = CS_ARCH_X86;
893  break;
894  case 4:
895  arch = CS_ARCH_PPC;
896  break;
897  case 5:
898  arch = CS_ARCH_SPARC;
899  break;
900  case 6:
901  arch = CS_ARCH_SYSZ;
902  break;
903  case 7:
904  arch = CS_ARCH_XCORE;
905  break;
906  case 8:
907  arch = CS_ARCH_M68K;
908  break;
909  case 9:
910  arch = CS_ARCH_TMS320C64X;
911  break;
912  case 10:
913  arch = CS_ARCH_M680X;
914  break;
915  default:
916  caml_invalid_argument("Invalid arch");
917  return Val_emptylist;
918  }
919 
920 
921  while (_mode != Val_emptylist) {
922  head = Field(_mode, 0); /* accessing the head */
923  switch (Int_val(head)) {
924  case 0:
925  mode |= CS_MODE_LITTLE_ENDIAN;
926  break;
927  case 1:
928  mode |= CS_MODE_ARM;
929  break;
930  case 2:
931  mode |= CS_MODE_16;
932  break;
933  case 3:
934  mode |= CS_MODE_32;
935  break;
936  case 4:
937  mode |= CS_MODE_64;
938  break;
939  case 5:
940  mode |= CS_MODE_THUMB;
941  break;
942  case 6:
943  mode |= CS_MODE_MCLASS;
944  break;
945  case 7:
946  mode |= CS_MODE_V8;
947  break;
948  case 8:
949  mode |= CS_MODE_MICRO;
950  break;
951  case 9:
952  mode |= CS_MODE_MIPS3;
953  break;
954  case 10:
955  mode |= CS_MODE_MIPS32R6;
956  break;
957  case 11:
958  mode |= CS_MODE_MIPS2;
959  break;
960  case 12:
961  mode |= CS_MODE_V9;
962  break;
963  case 13:
964  mode |= CS_MODE_BIG_ENDIAN;
965  break;
966  case 14:
967  mode |= CS_MODE_MIPS32;
968  break;
969  case 15:
970  mode |= CS_MODE_MIPS64;
971  break;
972  case 16:
973  mode |= CS_MODE_QPX;
974  break;
975  case 17:
976  mode |= CS_MODE_M680X_6301;
977  break;
978  case 18:
979  mode |= CS_MODE_M680X_6309;
980  break;
981  case 19:
982  mode |= CS_MODE_M680X_6800;
983  break;
984  case 20:
985  mode |= CS_MODE_M680X_6801;
986  break;
987  case 21:
988  mode |= CS_MODE_M680X_6805;
989  break;
990  case 22:
991  mode |= CS_MODE_M680X_6808;
992  break;
993  case 23:
994  mode |= CS_MODE_M680X_6809;
995  break;
996  case 24:
997  mode |= CS_MODE_M680X_6811;
998  break;
999  case 25:
1000  mode |= CS_MODE_M680X_CPU12;
1001  break;
1002  case 26:
1003  mode |= CS_MODE_M680X_HCS08;
1004  break;
1005  default:
1006  caml_invalid_argument("Invalid mode");
1007  return Val_emptylist;
1008  }
1009  _mode = Field(_mode, 1); /* point to the tail for next loop */
1010  }
1011 
1012  if (cs_open(arch, mode, &handle) != 0)
1013  CAMLreturn(Val_int(0));
1014 
1015  CAMLlocal1(result);
1016  result = caml_alloc(1, 0);
1017  Store_field(result, 0, caml_copy_int64(handle));
1018  CAMLreturn(result);
1019 }
1020 
1021 CAMLprim value ocaml_option(value _handle, value _opt, value _value)
1022 {
1023  CAMLparam3(_handle, _opt, _value);
1024  cs_opt_type opt;
1025  int err;
1026 
1027  switch (Int_val(_opt)) {
1028  case 0:
1029  opt = CS_OPT_SYNTAX;
1030  break;
1031  case 1:
1032  opt = CS_OPT_DETAIL;
1033  break;
1034  case 2:
1035  opt = CS_OPT_MODE;
1036  break;
1037  case 3:
1038  opt = CS_OPT_MEM;
1039  break;
1040  case 4:
1041  opt = CS_OPT_SKIPDATA;
1042  break;
1043  case 5:
1044  opt = CS_OPT_SKIPDATA_SETUP;
1045  break;
1046  default:
1047  caml_invalid_argument("Invalid option");
1048  CAMLreturn(Val_int(CS_ERR_OPTION));
1049  }
1050 
1051  err = cs_option(Int64_val(_handle), opt, Int64_val(_value));
1052 
1053  CAMLreturn(Val_int(err));
1054 }
1055 
1056 CAMLprim value ocaml_register_name(value _handle, value _reg)
1057 {
1058  const char *name = cs_reg_name(Int64_val(_handle), Int_val(_reg));
1059  if (!name) {
1060  caml_invalid_argument("invalid reg_id");
1061  name = "invalid";
1062  }
1063 
1064  return caml_copy_string(name);
1065 }
1066 
1067 CAMLprim value ocaml_instruction_name(value _handle, value _insn)
1068 {
1069  const char *name = cs_insn_name(Int64_val(_handle), Int_val(_insn));
1070  if (!name) {
1071  caml_invalid_argument("invalid insn_id");
1072  name = "invalid";
1073  }
1074 
1075  return caml_copy_string(name);
1076 }
1077 
1078 CAMLprim value ocaml_group_name(value _handle, value _insn)
1079 {
1080  const char *name = cs_group_name(Int64_val(_handle), Int_val(_insn));
1081  if (!name) {
1082  caml_invalid_argument("invalid insn_id");
1083  name = "invalid";
1084  }
1085 
1086  return caml_copy_string(name);
1087 }
1088 
1089 CAMLprim value ocaml_version(void)
1090 {
1091  int version = cs_version(NULL, NULL);
1092  return Val_int(version);
1093 }
1094 
1095 CAMLprim value ocaml_close(value _handle)
1096 {
1097  CAMLparam1(_handle);
1098  csh h;
1099 
1100  h = Int64_val(_handle);
1101 
1102  CAMLreturn(Val_int(cs_close(&h)));
1103 }
SPARC_OP_IMM
@ SPARC_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: sparc.h:73
ARM64_OP_FP
@ ARM64_OP_FP
= CS_OP_FP (Floating-Point operand).
Definition: arm64.h:238
CS_MODE_MIPS2
@ CS_MODE_MIPS2
Mips II ISA.
Definition: capstone.h:115
_gevent_test_main.result
result
Definition: _gevent_test_main.py:96
cs_close
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle)
Definition: cs.c:522
ARM64_OP_PREFETCH
@ ARM64_OP_PREFETCH
Prefetch operand (PRFM).
Definition: arm64.h:244
CS_OPT_MEM
@ CS_OPT_MEM
User-defined dynamic memory related functions.
Definition: capstone.h:174
MIPS_OP_REG
@ MIPS_OP_REG
= CS_OP_REG (Register operand).
Definition: mips.h:24
cs_opt_type
cs_opt_type
Runtime option for the disassembled engine.
Definition: capstone.h:169
CS_OPT_SYNTAX
@ CS_OPT_SYNTAX
Assembly output syntax.
Definition: capstone.h:171
CS_MODE_32
@ CS_MODE_32
32-bit mode (X86)
Definition: capstone.h:107
CS_MODE_M680X_6800
@ CS_MODE_M680X_6800
M680X Motorola 6800,6802 mode.
Definition: capstone.h:129
M680X_OP_CONSTANT
@ M680X_OP_CONSTANT
Used e.g. for a bit index or page number.
Definition: m680x.h:63
M680X_OP_EXTENDED
@ M680X_OP_EXTENDED
= Extended addressing operand.
Definition: m680x.h:60
CS_MODE_LITTLE_ENDIAN
@ CS_MODE_LITTLE_ENDIAN
little-endian mode (default mode)
Definition: capstone.h:104
ARM64_OP_REG_MRS
@ ARM64_OP_REG_MRS
MRS register operand.
Definition: arm64.h:240
M680X_OP_DIRECT
@ M680X_OP_DIRECT
= Direct addressing operand.
Definition: m680x.h:61
ocaml_group_name
CAMLprim value ocaml_group_name(value _handle, value _insn)
Definition: ocaml.c:1078
M680X_OP_IMMEDIATE
@ M680X_OP_IMMEDIATE
= Immediate operand.
Definition: m680x.h:58
CS_MODE_M680X_6805
@ CS_MODE_M680X_6805
M680X Motorola/Freescale 6805 mode.
Definition: capstone.h:131
CS_ARCH_M68K
@ CS_ARCH_M68K
68K architecture
Definition: capstone.h:83
CS_MODE_ARM
@ CS_MODE_ARM
32-bit ARM
Definition: capstone.h:105
cs_disasm
CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn)
Definition: cs.c:822
CS_MODE_M680X_CPU12
@ CS_MODE_M680X_CPU12
used on M68HC12/HCS12
Definition: capstone.h:135
X86_OP_IMM
@ X86_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: x86.h:161
string.h
CS_ARCH_PPC
@ CS_ARCH_PPC
PowerPC architecture.
Definition: capstone.h:79
MIPS_OP_MEM
@ MIPS_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: mips.h:26
CS_MODE_M680X_6801
@ CS_MODE_M680X_6801
M680X Motorola 6801,6803 mode.
Definition: capstone.h:130
ocaml_cs_disasm
CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _addr, value _count)
Definition: ocaml.c:698
error_ref_leak.err
err
Definition: error_ref_leak.py:35
cs_open
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
Definition: cs.c:474
cs_arch
cs_arch
Architecture type.
Definition: capstone.h:74
PPC_OP_MEM
@ PPC_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: ppc.h:46
mode
const char int mode
Definition: bloaty/third_party/zlib/contrib/minizip/ioapi.h:135
setup.name
name
Definition: setup.py:542
XCORE_OP_MEM
@ XCORE_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: xcore.h:22
version
Definition: version.py:1
SYSZ_OP_REG
@ SYSZ_OP_REG
= CS_OP_REG (Register operand).
Definition: systemz.h:40
CS_OPT_DETAIL
@ CS_OPT_DETAIL
Break down instruction structure into details.
Definition: capstone.h:172
ARM64_OP_REG
@ ARM64_OP_REG
= CS_OP_REG (Register operand).
Definition: arm64.h:235
detail
Definition: test_winkernel.cpp:39
uint8_t
unsigned char uint8_t
Definition: stdint-msvc2008.h:78
ARM64_OP_SYS
@ ARM64_OP_SYS
SYS operand for IC/DC/AT/TLBI instructions.
Definition: arm64.h:243
CS_MODE_16
@ CS_MODE_16
16-bit mode (X86)
Definition: capstone.h:106
grpc_status._async.code
code
Definition: grpcio_status/grpc_status/_async.py:34
CS_ARCH_M680X
@ CS_ARCH_M680X
680X architecture
Definition: capstone.h:85
CS_ARCH_TMS320C64X
@ CS_ARCH_TMS320C64X
TMS320C64x architecture.
Definition: capstone.h:84
SYSZ_OP_ACREG
@ SYSZ_OP_ACREG
Access register operand.
Definition: systemz.h:43
cs_option
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
Definition: cs.c:670
CS_MODE_M680X_6808
@ CS_MODE_M680X_6808
M680X Motorola/Freescale/NXP 68HC08 mode.
Definition: capstone.h:132
ARM64_OP_REG_MSR
@ ARM64_OP_REG_MSR
MSR register operand.
Definition: arm64.h:241
CS_MODE_MICRO
@ CS_MODE_MICRO
MicroMips mode (MIPS)
Definition: capstone.h:112
ARM64_OP_PSTATE
@ ARM64_OP_PSTATE
PState operand.
Definition: arm64.h:242
cs_mode
cs_mode
Mode type.
Definition: capstone.h:103
capstone.h
cs_insn_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_insn_name(csh ud, unsigned int insn)
Definition: cs.c:1188
c
void c(T a)
Definition: miscompile_with_no_unique_address_test.cc:40
capstone.CS_ERR_OK
CS_ERR_OK
Definition: third_party/bloaty/third_party/capstone/bindings/python/capstone/__init__.py:237
array
Definition: undname.c:101
ocaml_close
CAMLprim value ocaml_close(value _handle)
Definition: ocaml.c:1095
max
int max
Definition: bloaty/third_party/zlib/examples/enough.c:170
CS_ARCH_SYSZ
@ CS_ARCH_SYSZ
SystemZ architecture.
Definition: capstone.h:81
CS_MODE_QPX
@ CS_MODE_QPX
Quad Processing eXtensions mode (PPC)
Definition: capstone.h:117
_cs_disasm
CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t *code, size_t code_len, uint64_t addr, size_t count)
Definition: ocaml.c:28
cs_reg_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
Definition: cs.c:1176
CS_ARCH_X86
@ CS_ARCH_X86
X86 architecture (including x86 & x86-64)
Definition: capstone.h:78
uint64_t
unsigned __int64 uint64_t
Definition: stdint-msvc2008.h:90
ARM_OP_PIMM
@ ARM_OP_PIMM
P-Immediate (coprocessor registers)
Definition: arm.h:168
SPARC_OP_REG
@ SPARC_OP_REG
= CS_OP_REG (Register operand).
Definition: sparc.h:72
XCORE_OP_REG
@ XCORE_OP_REG
= CS_OP_REG (Register operand).
Definition: xcore.h:20
CS_MODE_THUMB
@ CS_MODE_THUMB
ARM's Thumb mode, including Thumb-2.
Definition: capstone.h:109
X86_OP_MEM
@ X86_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: x86.h:162
ARM_OP_REG
@ ARM_OP_REG
= CS_OP_REG (Register operand).
Definition: arm.h:163
CS_MODE_BIG_ENDIAN
@ CS_MODE_BIG_ENDIAN
big-endian mode
Definition: capstone.h:124
CS_MODE_MIPS32R6
@ CS_MODE_MIPS32R6
Mips32r6 ISA.
Definition: capstone.h:114
CS_OPT_SKIPDATA
@ CS_OPT_SKIPDATA
Skip data when disassembling. Then engine is in SKIPDATA mode.
Definition: capstone.h:175
CS_MODE_MCLASS
@ CS_MODE_MCLASS
ARM's Cortex-M series.
Definition: capstone.h:110
arch
cs_arch arch
Definition: cstool.c:13
CS_MODE_M680X_6809
@ CS_MODE_M680X_6809
M680X Motorola 6809 mode.
Definition: capstone.h:133
ARM_OP_SYSREG
@ ARM_OP_SYSREG
MSR/MRS special register operand.
Definition: arm.h:170
ARM_OP_FP
@ ARM_OP_FP
= CS_OP_FP (Floating-Point operand).
Definition: arm.h:166
SYSZ_OP_MEM
@ SYSZ_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: systemz.h:42
ocaml_open
CAMLprim value ocaml_open(value _arch, value _mode)
Definition: ocaml.c:871
ocaml_register_name
CAMLprim value ocaml_register_name(value _handle, value _reg)
Definition: ocaml.c:1056
CS_MODE_M680X_6309
@ CS_MODE_M680X_6309
M680X Hitachi 6309 mode.
Definition: capstone.h:128
CS_ARCH_SPARC
@ CS_ARCH_SPARC
Sparc architecture.
Definition: capstone.h:80
CS_ARCH_MIPS
@ CS_ARCH_MIPS
Mips architecture.
Definition: capstone.h:77
CS_MODE_M680X_HCS08
@ CS_MODE_M680X_HCS08
M680X Freescale/NXP HCS08 mode.
Definition: capstone.h:137
value
const char * value
Definition: hpack_parser_table.cc:165
Field
struct Field Field
Definition: bloaty/third_party/protobuf/php/ext/google/protobuf/protobuf.h:647
csh
size_t csh
Definition: capstone.h:71
ARM64_OP_CIMM
@ ARM64_OP_CIMM
C-Immediate.
Definition: arm64.h:239
ocaml_instruction_name
CAMLprim value ocaml_instruction_name(value _handle, value _insn)
Definition: ocaml.c:1067
PPC_OP_REG
@ PPC_OP_REG
= CS_OP_REG (Register operand).
Definition: ppc.h:44
CS_MODE_MIPS64
@ CS_MODE_MIPS64
Mips64 ISA (Mips)
Definition: capstone.h:126
bytes
uint8 bytes[10]
Definition: bloaty/third_party/protobuf/src/google/protobuf/io/coded_stream_unittest.cc:153
count
int * count
Definition: bloaty/third_party/googletest/googlemock/test/gmock_stress_test.cc:96
CS_MODE_64
@ CS_MODE_64
64-bit mode (X86, PPC)
Definition: capstone.h:108
CS_OPT_SKIPDATA_SETUP
@ CS_OPT_SKIPDATA_SETUP
Setup user-defined function for SKIPDATA option.
Definition: capstone.h:176
CS_ARCH_ARM
@ CS_ARCH_ARM
ARM architecture (including Thumb, Thumb-2)
Definition: capstone.h:75
ARM64_OP_BARRIER
@ ARM64_OP_BARRIER
Memory barrier operand (ISB/DMB/DSB instructions).
Definition: arm64.h:245
ocaml_version
CAMLprim value ocaml_version(void)
Definition: ocaml.c:1089
ret
UniquePtr< SSL_SESSION > ret
Definition: ssl_x509.cc:1029
list_count
static unsigned int list_count(uint8_t *list, unsigned int max)
Definition: ocaml.c:17
SYSZ_OP_IMM
@ SYSZ_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: systemz.h:41
cs_group_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_group_name(csh ud, unsigned int group)
Definition: cs.c:1200
M680X_OP_RELATIVE
@ M680X_OP_RELATIVE
= Relative addressing operand.
Definition: m680x.h:62
ARM_OP_IMM
@ ARM_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: arm.h:164
ocaml_cs_disasm_internal
CAMLprim value ocaml_cs_disasm_internal(value _arch, value _handle, value _code, value _addr, value _count)
Definition: ocaml.c:852
ocaml_option
CAMLprim value ocaml_option(value _handle, value _opt, value _value)
Definition: ocaml.c:1021
M680X_OP_INDEXED
@ M680X_OP_INDEXED
= Indexed addressing operand.
Definition: m680x.h:59
ARM64_OP_IMM
@ ARM64_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: arm64.h:236
ARM_OP_CIMM
@ ARM_OP_CIMM
C-Immediate (coprocessor registers)
Definition: arm.h:167
CS_MODE_MIPS3
@ CS_MODE_MIPS3
Mips III ISA.
Definition: capstone.h:113
XCORE_OP_IMM
@ XCORE_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: xcore.h:21
cs_free
CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
Definition: cs.c:1039
CS_MODE_V9
@ CS_MODE_V9
SparcV9 mode (Sparc)
Definition: capstone.h:116
handle
static csh handle
Definition: test_arm_regression.c:16
M680X_OP_REGISTER
@ M680X_OP_REGISTER
= Register operand.
Definition: m680x.h:57
CS_MODE_M680X_6301
@ CS_MODE_M680X_6301
M680X Hitachi 6301,6303 mode.
Definition: capstone.h:127
grpc_testing._channel._invocation._code
def _code(handler)
Definition: _invocation.py:50
CS_OPT_MODE
@ CS_OPT_MODE
Change engine's mode at run-time.
Definition: capstone.h:173
ARM64_OP_MEM
@ ARM64_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: arm64.h:237
capstone.CS_ERR_OPTION
CS_ERR_OPTION
Definition: third_party/bloaty/third_party/capstone/bindings/python/capstone/__init__.py:243
CS_ARCH_ARM64
@ CS_ARCH_ARM64
ARM-64, also called AArch64.
Definition: capstone.h:76
ARM_OP_SETEND
@ ARM_OP_SETEND
operand for SETEND instruction
Definition: arm.h:169
ARM_OP_MEM
@ ARM_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: arm.h:165
code
Definition: bloaty/third_party/zlib/contrib/infback9/inftree9.h:24
autogen_x86imm.tmp
tmp
Definition: autogen_x86imm.py:12
PPC_OP_IMM
@ PPC_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: ppc.h:45
MIPS_OP_IMM
@ MIPS_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: mips.h:25
size
voidpf void uLong size
Definition: bloaty/third_party/zlib/contrib/minizip/ioapi.h:136
CS_MODE_MIPS32
@ CS_MODE_MIPS32
Mips32 ISA (Mips)
Definition: capstone.h:125
CS_MODE_M680X_6811
@ CS_MODE_M680X_6811
M680X Motorola/Freescale/NXP 68HC11 mode.
Definition: capstone.h:134
SPARC_OP_MEM
@ SPARC_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: sparc.h:74
CS_ARCH_XCORE
@ CS_ARCH_XCORE
XCore architecture.
Definition: capstone.h:82
CS_MODE_V8
@ CS_MODE_V8
ARMv8 A32 encodings for ARM.
Definition: capstone.h:111
cs_version
CAPSTONE_EXPORT unsigned int CAPSTONE_API cs_version(int *major, int *minor)
Definition: cs.c:377
addr
struct sockaddr_in addr
Definition: libuv/docs/code/tcp-echo-server/main.c:10
if
if(p->owned &&p->wrapped !=NULL)
Definition: call.c:42
X86_OP_REG
@ X86_OP_REG
= CS_OP_REG (Register operand).
Definition: x86.h:160
i
uint64_t i
Definition: abseil-cpp/absl/container/btree_benchmark.cc:230
ARR_SIZE
#define ARR_SIZE(a)
Definition: ocaml.c:13
PPC_OP_CRX
@ PPC_OP_CRX
Condition Register field.
Definition: ppc.h:47

grpc
Author(s):
autogenerated on Thu Mar 13 2025 03:00:45