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12 int main(
int argc,
char **argv)
15 printf(
"Usage: %s <testcase>\n", argv[0]);
23 "X86 32 (Intel syntax)"
28 "X86 64 (Intel syntax)"
43 "ARM: Cortex-A15 + NEON"
63 "MIPS-32 (Big-endian)"
68 "MIPS-64-EL (Little-endian)"
73 "MIPS-32R6 | Micro (Big-endian)"
78 "MIPS-32R6 (Big-endian)"
124 unsigned char *
buf = NULL;
125 FILE *fp = fopen(argv[1],
"r");
127 if (fp == NULL)
return 1;
132 if (bufsize == -1)
return 1;
134 buf = malloc(bufsize + 1);
136 if (
buf == NULL)
return 1;
137 if (fseek(fp, 0
L,
SEEK_SET) != 0)
return 1;
139 size_t len = fread(
buf,
sizeof(
char), bufsize, fp);
141 if (
len == 0)
return 2;
151 if (bufsize < 3)
return 0;
154 int i = (
int)
buf[0] % platforms_len;
156 unsigned char *buf_ptr =
buf + 1;
157 long buf_ptr_size = bufsize - 1;
163 printf(
"Failed on cs_open() with error returned: %u\n",
err);
178 for (j = 0; j <
count; j++) {
179 cs_insn *
i = &(all_insn[j]);
180 printf(
"0x%"PRIx64
":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
181 i->address,
i->mnemonic,
i->op_str,
186 if (
detail->regs_read_count > 0) {
187 printf(
"\tImplicit registers read: ");
188 for (
n = 0;
n <
detail->regs_read_count;
n++) {
194 if (
detail->regs_write_count > 0) {
195 printf(
"\tImplicit registers modified: ");
196 for (
n = 0;
n <
detail->regs_write_count;
n++) {
202 if (
detail->groups_count > 0) {
203 printf(
"\tThis instruction belongs to groups: ");
204 for (
n = 0;
n <
detail->groups_count;
n++) {
210 printf(
"0x%"PRIx64
":\n", all_insn[j-1].address + all_insn[j-1].
size);
213 printf(
"ERROR: Failed to disasm given code!\n");
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle)
@ CS_MODE_32
32-bit mode (X86)
@ CS_MODE_LITTLE_ENDIAN
little-endian mode (default mode)
@ CS_ARCH_M68K
68K architecture
CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn)
@ CS_ARCH_PPC
PowerPC architecture.
_Use_decl_annotations_ int __cdecl printf(const char *_Format,...)
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
cs_arch
Architecture type.
@ CS_OPT_DETAIL
Break down instruction structure into details.
int main(int argc, char **argv)
@ CS_ARCH_M680X
680X architecture
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
@ CS_MODE_MICRO
MicroMips mode (MIPS)
const CAPSTONE_EXPORT char *CAPSTONE_API cs_insn_name(csh ud, unsigned int insn)
@ CS_ARCH_SYSZ
SystemZ architecture.
const CAPSTONE_EXPORT char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
@ CS_ARCH_X86
X86 architecture (including x86 & x86-64)
unsigned __int64 uint64_t
@ CS_OPT_ON
Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
@ CS_MODE_THUMB
ARM's Thumb mode, including Thumb-2.
@ CS_MODE_BIG_ENDIAN
big-endian mode
@ CS_MODE_MIPS32R6
Mips32r6 ISA.
@ CS_MODE_MCLASS
ARM's Cortex-M series.
@ CS_MODE_M680X_6809
M680X Motorola 6809 mode.
@ CS_ARCH_SPARC
Sparc architecture.
@ CS_ARCH_MIPS
Mips architecture.
@ CS_MODE_MIPS64
Mips64 ISA (Mips)
@ CS_MODE_64
64-bit mode (X86, PPC)
@ CS_ARCH_ARM
ARM architecture (including Thumb, Thumb-2)
const CAPSTONE_EXPORT char *CAPSTONE_API cs_group_name(csh ud, unsigned int group)
CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
@ CS_MODE_V9
SparcV9 mode (Sparc)
@ CS_ARCH_ARM64
ARM-64, also called AArch64.
struct platform platforms[]
@ CS_MODE_MIPS32
Mips32 ISA (Mips)
@ CS_ARCH_XCORE
XCore architecture.
@ CS_MODE_V8
ARMv8 A32 encodings for ARM.
grpc
Author(s):
autogenerated on Thu Mar 13 2025 02:59:23