cstool_arm64.c
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1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
3 
4 #include <stdio.h>
5 #include <stdlib.h>
6 
7 #include <capstone/capstone.h>
8 
9 void print_string_hex(char *comment, unsigned char *str, size_t len);
10 
11 void print_insn_detail_arm64(csh handle, cs_insn *ins)
12 {
13  cs_arm64 *arm64;
14  int i;
15  cs_regs regs_read, regs_write;
16  uint8_t regs_read_count, regs_write_count;
18 
19  // detail can be NULL if SKIPDATA option is turned ON
20  if (ins->detail == NULL)
21  return;
22 
23  arm64 = &(ins->detail->arm64);
24  if (arm64->op_count)
25  printf("\top_count: %u\n", arm64->op_count);
26 
27  for (i = 0; i < arm64->op_count; i++) {
28  cs_arm64_op *op = &(arm64->operands[i]);
29  switch(op->type) {
30  default:
31  break;
32  case ARM64_OP_REG:
33  printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
34  break;
35  case ARM64_OP_IMM:
36  printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
37  break;
38  case ARM64_OP_FP:
39 #if defined(_KERNEL_MODE)
40  // Issue #681: Windows kernel does not support formatting float point
41  printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
42 #else
43  printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
44 #endif
45  break;
46  case ARM64_OP_MEM:
47  printf("\t\toperands[%u].type: MEM\n", i);
48  if (op->mem.base != ARM64_REG_INVALID)
49  printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
50  if (op->mem.index != ARM64_REG_INVALID)
51  printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
52  if (op->mem.disp != 0)
53  printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
54 
55  break;
56  case ARM64_OP_CIMM:
57  printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm);
58  break;
59  case ARM64_OP_REG_MRS:
60  printf("\t\toperands[%u].type: REG_MRS = 0x%x\n", i, op->reg);
61  break;
62  case ARM64_OP_REG_MSR:
63  printf("\t\toperands[%u].type: REG_MSR = 0x%x\n", i, op->reg);
64  break;
65  case ARM64_OP_PSTATE:
66  printf("\t\toperands[%u].type: PSTATE = 0x%x\n", i, op->pstate);
67  break;
68  case ARM64_OP_SYS:
69  printf("\t\toperands[%u].type: SYS = 0x%x\n", i, op->sys);
70  break;
71  case ARM64_OP_PREFETCH:
72  printf("\t\toperands[%u].type: PREFETCH = 0x%x\n", i, op->prefetch);
73  break;
74  case ARM64_OP_BARRIER:
75  printf("\t\toperands[%u].type: BARRIER = 0x%x\n", i, op->barrier);
76  break;
77  }
78 
79  access = op->access;
80  switch(access) {
81  default:
82  break;
83  case CS_AC_READ:
84  printf("\t\toperands[%u].access: READ\n", i);
85  break;
86  case CS_AC_WRITE:
87  printf("\t\toperands[%u].access: WRITE\n", i);
88  break;
89  case CS_AC_READ | CS_AC_WRITE:
90  printf("\t\toperands[%u].access: READ | WRITE\n", i);
91  break;
92  }
93 
94  if (op->shift.type != ARM64_SFT_INVALID &&
95  op->shift.value)
96  printf("\t\t\tShift: type = %u, value = %u\n",
97  op->shift.type, op->shift.value);
98 
99  if (op->ext != ARM64_EXT_INVALID)
100  printf("\t\t\tExt: %u\n", op->ext);
101 
102  if (op->vas != ARM64_VAS_INVALID)
103  printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas);
104 
105  if (op->vess != ARM64_VESS_INVALID)
106  printf("\t\t\tVector Element Size Specifier: %u\n", op->vess);
107 
108  if (op->vector_index != -1)
109  printf("\t\t\tVector Index: %u\n", op->vector_index);
110  }
111 
112  if (arm64->update_flags)
113  printf("\tUpdate-flags: True\n");
114 
115  if (arm64->writeback)
116  printf("\tWrite-back: True\n");
117 
118  if (arm64->cc)
119  printf("\tCode-condition: %u\n", arm64->cc);
120 
121  // Print out all registers accessed by this instruction (either implicit or explicit)
122  if (!cs_regs_access(handle, ins,
123  regs_read, &regs_read_count,
124  regs_write, &regs_write_count)) {
125  if (regs_read_count) {
126  printf("\tRegisters read:");
127  for(i = 0; i < regs_read_count; i++) {
128  printf(" %s", cs_reg_name(handle, regs_read[i]));
129  }
130  printf("\n");
131  }
132 
133  if (regs_write_count) {
134  printf("\tRegisters modified:");
135  for(i = 0; i < regs_write_count; i++) {
136  printf(" %s", cs_reg_name(handle, regs_write[i]));
137  }
138  printf("\n");
139  }
140  }
141 }
xds_interop_client.str
str
Definition: xds_interop_client.py:487
ARM64_OP_FP
@ ARM64_OP_FP
= CS_OP_FP (Floating-Point operand).
Definition: arm64.h:238
ARM64_OP_PREFETCH
@ ARM64_OP_PREFETCH
Prefetch operand (PRFM).
Definition: arm64.h:244
print_string_hex
void print_string_hex(char *comment, unsigned char *str, size_t len)
ARM64_OP_REG_MRS
@ ARM64_OP_REG_MRS
MRS register operand.
Definition: arm64.h:240
cs_arm64_op
Instruction operand.
Definition: arm64.h:630
printf
_Use_decl_annotations_ int __cdecl printf(const char *_Format,...)
Definition: cs_driver.c:91
ARM64_OP_REG
@ ARM64_OP_REG
= CS_OP_REG (Register operand).
Definition: arm64.h:235
ARM64_VESS_INVALID
@ ARM64_VESS_INVALID
Definition: arm64.h:208
uint8_t
unsigned char uint8_t
Definition: stdint-msvc2008.h:78
ARM64_OP_SYS
@ ARM64_OP_SYS
SYS operand for IC/DC/AT/TLBI instructions.
Definition: arm64.h:243
CS_AC_READ
@ CS_AC_READ
Operand read from memory or register.
Definition: capstone.h:205
cs_regs_access
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_regs_access(csh ud, const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count)
Definition: cs.c:1539
ARM64_VAS_INVALID
@ ARM64_VAS_INVALID
Definition: arm64.h:194
ARM64_OP_REG_MSR
@ ARM64_OP_REG_MSR
MSR register operand.
Definition: arm64.h:241
ARM64_OP_PSTATE
@ ARM64_OP_PSTATE
PState operand.
Definition: arm64.h:242
capstone.h
cs_reg_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
Definition: cs.c:1176
arm64
Definition: test_winkernel.cpp:59
csh
size_t csh
Definition: capstone.h:71
ARM64_OP_CIMM
@ ARM64_OP_CIMM
C-Immediate.
Definition: arm64.h:239
ARM64_SFT_INVALID
@ ARM64_SFT_INVALID
Definition: arm64.h:19
ARM64_OP_BARRIER
@ ARM64_OP_BARRIER
Memory barrier operand (ISB/DMB/DSB instructions).
Definition: arm64.h:245
print_insn_detail_arm64
void print_insn_detail_arm64(csh handle, cs_insn *ins)
Definition: cstool_arm64.c:11
ARM64_EXT_INVALID
@ ARM64_EXT_INVALID
Definition: arm64.h:29
ARM64_OP_IMM
@ ARM64_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: arm64.h:236
handle
static csh handle
Definition: test_arm_regression.c:16
ARM64_OP_MEM
@ ARM64_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: arm64.h:237
len
int len
Definition: abseil-cpp/absl/base/internal/low_level_alloc_test.cc:46
access
Definition: bloaty/third_party/zlib/examples/zran.c:75
ARM64_REG_INVALID
@ ARM64_REG_INVALID
Definition: arm64.h:348
op
static grpc_op * op
Definition: test/core/fling/client.cc:47
i
uint64_t i
Definition: abseil-cpp/absl/container/btree_benchmark.cc:230
CS_AC_WRITE
@ CS_AC_WRITE
Operand write to memory or register.
Definition: capstone.h:206
cs_arm64
Instruction structure.
Definition: arm64.h:658


grpc
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autogenerated on Fri May 16 2025 02:58:08