13 #ifdef CAPSTONE_HAS_ARM
22 #include "../../MCFixedLenDisassembler.h"
23 #include "../../MCInst.h"
24 #include "../../MCInstrDesc.h"
25 #include "../../MCRegisterInfo.h"
26 #include "../../LEB128.h"
27 #include "../../MCDisassembler.h"
28 #include "../../cs_priv.h"
29 #include "../../utils.h"
36 #define GET_SUBTARGETINFO_ENUM
37 #include "ARMGenSubtargetInfo.inc"
39 #define GET_INSTRINFO_MC_DESC
40 #include "ARMGenInstrInfo.inc"
42 #define GET_INSTRINFO_ENUM
43 #include "ARMGenInstrInfo.inc"
47 if (
it->size >=
sizeof(
it->ITStates)) {
51 it->ITStates[
it->size] =
v;
61 return (
it->size > 0);
67 return (
it->size == 1);
76 if (ITStatus_instrInITBlock(
it))
78 CC =
it->ITStates[
it->size-1];
92 static void ITStatus_setITState(
ARM_ITStatus *
it,
char Firstcond,
char Mask)
95 unsigned CondBit0 = Firstcond & 1;
97 unsigned char CCBits = (
unsigned char)Firstcond & 0xf;
102 bool T = ((Mask >>
Pos) & 1) == (
int)CondBit0;
104 ITStatus_push_back(
it, CCBits);
106 ITStatus_push_back(
it, CCBits ^ 1);
108 ITStatus_push_back(
it, CCBits);
185 unsigned Insn,
uint64_t Adddress,
const void *Decoder);
376 Bits &= (~ARM_FeatureVFPOnlySP);
382 Bits &= ~ARM_HasV8Ops;
386 Bits &= (~ARM_FeatureMClass);
401 Bits &= ~ARM_ModeThumb;
402 Bits &= ~ARM_FeatureThumb2;
408 #include "ARMGenDisassemblerTables.inc"
425 #define GET_REGINFO_MC_DESC
426 #include "ARMGenRegisterInfo.inc"
440 ARMMCRegisterClasses, 100,
441 0, 0, ARMRegDiffLists, 0,
442 ARMSubRegIdxLists, 57,
480 MI->
flat_insn->detail->arm.operands[
i].vector_index = -1;
481 MI->
flat_insn->detail->arm.operands[
i].neon_lane = -1;
486 insn = (
code[3] << 0) |
497 result = decodeInstruction_4(DecoderTableARM32, MI, insn,
Address, NULL, ud->
mode);
508 result = decodeInstruction_4(DecoderTableVFP32, MI, insn,
Address, NULL, ud->
mode);
515 result = decodeInstruction_4(DecoderTableVFPV832, MI, insn,
Address, NULL, ud->
mode);
522 result = decodeInstruction_4(DecoderTableNEONData32, MI, insn,
Address, NULL, ud->
mode);
527 if (!DecodePredicateOperand(MI, 0xE,
Address, NULL))
533 result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn,
Address, NULL, ud->
mode);
538 if (!DecodePredicateOperand(MI, 0xE,
Address, NULL))
544 result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn,
Address, NULL, ud->
mode);
549 if (!DecodePredicateOperand(MI, 0xE,
Address, NULL))
555 result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn,
Address, NULL, ud->
mode);
562 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn,
Address, NULL, ud->
mode);
577 static void AddThumb1SBit(
MCInst *MI,
bool InITBlock)
583 for (
i = 0;
i < NumOps; ++
i) {
604 unsigned short NumOps;
623 if (ITStatus_instrInITBlock(&(ud->
ITBlock)))
635 if (ITStatus_instrInITBlock(&(ud->
ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->
ITBlock)))
647 if (ITStatus_instrInITBlock(&(ud->
ITBlock)))
648 ITStatus_advanceITState(&(ud->
ITBlock));
653 for (
i = 0;
i < NumOps; ++
i) {
682 unsigned short NumOps;
687 if (ITStatus_instrInITBlock(&(ud->
ITBlock)))
688 ITStatus_advanceITState(&(ud->
ITBlock));
693 for (
i = 0;
i < NumOps; ++
i) {
711 unsigned Firstcond, Mask;
712 uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn;
723 MI->
flat_insn->detail->arm.operands[
i].vector_index = -1;
724 MI->
flat_insn->detail->arm.operands[
i].neon_lane = -1;
733 result = decodeInstruction_2(DecoderTableThumb16, MI, insn16,
Address, NULL, ud->
mode);
741 result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16,
Address, NULL, ud->
mode);
744 InITBlock = ITStatus_instrInITBlock(&(ud->
ITBlock));
746 AddThumb1SBit(MI, InITBlock);
751 result = decodeInstruction_2(DecoderTableThumb216, MI, insn16,
Address, NULL, ud->
mode);
768 ITStatus_setITState(&(ud->
ITBlock), (
char)Firstcond, (
char)Mask);
780 insn32 = (
code[3] << 0) |
785 insn32 = (
code[3] << 8) |
791 result = decodeInstruction_4(DecoderTableThumb32, MI, insn32,
Address, NULL, ud->
mode);
794 InITBlock = ITStatus_instrInITBlock(&(ud->
ITBlock));
796 AddThumb1SBit(MI, InITBlock);
801 result = decodeInstruction_4(DecoderTableThumb232, MI, insn32,
Address, NULL, ud->
mode);
808 if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
810 result = decodeInstruction_4(DecoderTableVFP32, MI, insn32,
Address, NULL, ud->
mode);
813 UpdateThumbVFPPredicate(ud, MI);
819 result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32,
Address, NULL, ud->
mode);
825 if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
827 result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32,
Address, NULL, ud->
mode);
835 if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) {
837 NEONLdStInsn = insn32;
838 NEONLdStInsn &= 0xF0FFFFFF;
839 NEONLdStInsn |= 0x04000000;
840 result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
Address, NULL, ud->
mode);
848 if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) {
850 NEONDataInsn = insn32;
851 NEONDataInsn &= 0xF0FFFFFF;
852 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
853 NEONDataInsn |= 0x12000000;
854 result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn,
Address, NULL, ud->
mode);
863 NEONCryptoInsn = insn32;
864 NEONCryptoInsn &= 0xF0FFFFFF;
865 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
866 NEONCryptoInsn |= 0x12000000;
867 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
876 NEONv8Insn &= 0xF3FFFFFF;
877 result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn,
Address, NULL, ud->
mode);
906 static const uint16_t GPRDecoderTable[] = {
907 ARM_R0, ARM_R1, ARM_R2, ARM_R3,
908 ARM_R4, ARM_R5, ARM_R6, ARM_R7,
909 ARM_R8, ARM_R9, ARM_R10, ARM_R11,
910 ARM_R12, ARM_SP, ARM_LR, ARM_PC
920 Register = GPRDecoderTable[RegNo];
933 Check(&
S, DecodeGPRRegisterClass(Inst, RegNo,
Address, Decoder));
948 Check(&
S, DecodeGPRRegisterClass(Inst, RegNo,
Address, Decoder));
957 return DecodeGPRRegisterClass(Inst, RegNo,
Address, Decoder);
960 static const uint16_t GPRPairDecoderTable[] = {
961 ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7,
962 ARM_R8_R9, ARM_R10_R11, ARM_R12_SP
968 unsigned RegisterPair;
974 if ((RegNo & 1) || RegNo == 0xe)
977 RegisterPair = GPRPairDecoderTable[RegNo/2];
985 unsigned Register = 0;
1017 if (RegNo == 13 || RegNo == 15)
1019 Check(&
S, DecodeGPRRegisterClass(Inst, RegNo,
Address, Decoder));
1023 static const uint16_t SPRDecoderTable[] = {
1024 ARM_S0, ARM_S1, ARM_S2, ARM_S3,
1025 ARM_S4, ARM_S5, ARM_S6, ARM_S7,
1026 ARM_S8, ARM_S9, ARM_S10, ARM_S11,
1027 ARM_S12, ARM_S13, ARM_S14, ARM_S15,
1028 ARM_S16, ARM_S17, ARM_S18, ARM_S19,
1029 ARM_S20, ARM_S21, ARM_S22, ARM_S23,
1030 ARM_S24, ARM_S25, ARM_S26, ARM_S27,
1031 ARM_S28, ARM_S29, ARM_S30, ARM_S31
1041 Register = SPRDecoderTable[RegNo];
1046 static const uint16_t DPRDecoderTable[] = {
1047 ARM_D0, ARM_D1, ARM_D2, ARM_D3,
1048 ARM_D4, ARM_D5, ARM_D6, ARM_D7,
1049 ARM_D8, ARM_D9, ARM_D10, ARM_D11,
1050 ARM_D12, ARM_D13, ARM_D14, ARM_D15,
1051 ARM_D16, ARM_D17, ARM_D18, ARM_D19,
1052 ARM_D20, ARM_D21, ARM_D22, ARM_D23,
1053 ARM_D24, ARM_D25, ARM_D26, ARM_D27,
1054 ARM_D28, ARM_D29, ARM_D30, ARM_D31
1069 Register = DPRDecoderTable[RegNo];
1080 return DecodeDPRRegisterClass(Inst, RegNo,
Address, Decoder);
1084 DecodeDPR_VFP2RegisterClass(
MCInst *Inst,
unsigned RegNo,
1089 return DecodeDPRRegisterClass(Inst, RegNo,
Address, Decoder);
1092 static const uint16_t QPRDecoderTable[] = {
1093 ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3,
1094 ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7,
1095 ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11,
1096 ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15
1103 if (RegNo > 31 || (RegNo & 1) != 0)
1107 Register = QPRDecoderTable[RegNo];
1112 static const uint16_t DPairDecoderTable[] = {
1113 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6,
1114 ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12,
1115 ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18,
1116 ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24,
1117 ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30,
1128 Register = DPairDecoderTable[RegNo];
1133 static const uint16_t DPairSpacedDecoderTable[] = {
1134 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5,
1135 ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9,
1136 ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13,
1137 ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17,
1138 ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21,
1139 ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25,
1140 ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29,
1141 ARM_D28_D30, ARM_D29_D31
1151 Register = DPairSpacedDecoderTable[RegNo];
1172 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1173 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1174 unsigned imm = fieldFromInstruction_4(Val, 7, 5);
1177 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
1199 Op = Shift | (imm << 3);
1211 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1212 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1213 unsigned Rs = fieldFromInstruction_4(Val, 8, 4);
1216 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rm,
Address, Decoder)))
1218 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rs,
Address, Decoder)))
1249 bool NeedDisjointWriteback =
false;
1250 unsigned WritebackReg = 0;
1260 case ARM_t2LDMIA_UPD:
1261 case ARM_t2LDMDB_UPD:
1262 case ARM_t2STMIA_UPD:
1263 case ARM_t2STMDB_UPD:
1264 NeedDisjointWriteback =
true;
1271 for (
i = 0;
i < 16; ++
i) {
1272 if (Val & (1 <<
i)) {
1273 if (!
Check(&
S, DecodeGPRRegisterClass(Inst,
i,
Address, Decoder)))
1281 if (
opcode == ARM_t2LDMIA_UPD && WritebackReg == ARM_SP) {
1282 if (Val & (1 << 13) || ((Val & (1 << 15)) && (Val & (1 << 14)))) {
1297 unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
1298 unsigned regs = fieldFromInstruction_4(Val, 0, 8);
1301 if (regs == 0 || (Vd + regs) > 32) {
1302 regs = Vd + regs > 32 ? 32 - Vd : regs;
1303 regs = (1
u > regs? 1
u : regs);
1307 if (!
Check(&
S, DecodeSPRRegisterClass(Inst, Vd,
Address, Decoder)))
1309 for (
i = 0;
i < (regs - 1); ++
i) {
1310 if (!
Check(&
S, DecodeSPRRegisterClass(Inst, ++Vd,
Address, Decoder)))
1322 unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
1323 unsigned regs = fieldFromInstruction_4(Val, 1, 7);
1326 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1327 regs = Vd + regs > 32 ? 32 - Vd : regs;
1328 regs = (1
u > regs? 1
u : regs);
1329 regs = (16
u > regs? regs : 16
u);
1333 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Vd,
Address, Decoder)))
1336 for (
i = 0;
i < (regs - 1); ++
i) {
1337 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, ++Vd,
Address, Decoder)))
1352 unsigned msb = fieldFromInstruction_4(Val, 5, 5);
1353 unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
1365 msb_mask = 0xFFFFFFFF;
1366 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1367 lsb_mask = (1U << lsb) - 1;
1378 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1379 unsigned CRd = fieldFromInstruction_4(Insn, 12, 4);
1380 unsigned coproc = fieldFromInstruction_4(Insn, 8, 4);
1381 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
1382 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1383 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
1386 case ARM_LDC_OFFSET:
1389 case ARM_LDC_OPTION:
1390 case ARM_LDCL_OFFSET:
1393 case ARM_LDCL_OPTION:
1394 case ARM_STC_OFFSET:
1397 case ARM_STC_OPTION:
1398 case ARM_STCL_OFFSET:
1401 case ARM_STCL_OPTION:
1402 case ARM_t2LDC_OFFSET:
1404 case ARM_t2LDC_POST:
1405 case ARM_t2LDC_OPTION:
1406 case ARM_t2LDCL_OFFSET:
1407 case ARM_t2LDCL_PRE:
1408 case ARM_t2LDCL_POST:
1409 case ARM_t2LDCL_OPTION:
1410 case ARM_t2STC_OFFSET:
1412 case ARM_t2STC_POST:
1413 case ARM_t2STC_OPTION:
1414 case ARM_t2STCL_OFFSET:
1415 case ARM_t2STCL_PRE:
1416 case ARM_t2STCL_POST:
1417 case ARM_t2STCL_OPTION:
1418 if (coproc == 0xA || coproc == 0xB)
1427 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1431 case ARM_t2LDC2_OFFSET:
1432 case ARM_t2LDC2L_OFFSET:
1433 case ARM_t2LDC2_PRE:
1434 case ARM_t2LDC2L_PRE:
1435 case ARM_t2STC2_OFFSET:
1436 case ARM_t2STC2L_OFFSET:
1437 case ARM_t2STC2_PRE:
1438 case ARM_t2STC2L_PRE:
1439 case ARM_LDC2_OFFSET:
1440 case ARM_LDC2L_OFFSET:
1443 case ARM_STC2_OFFSET:
1444 case ARM_STC2L_OFFSET:
1447 case ARM_t2LDC_OFFSET:
1448 case ARM_t2LDCL_OFFSET:
1450 case ARM_t2LDCL_PRE:
1451 case ARM_t2STC_OFFSET:
1452 case ARM_t2STCL_OFFSET:
1454 case ARM_t2STCL_PRE:
1455 case ARM_LDC_OFFSET:
1456 case ARM_LDCL_OFFSET:
1459 case ARM_STC_OFFSET:
1460 case ARM_STCL_OFFSET:
1466 case ARM_t2LDC2_POST:
1467 case ARM_t2LDC2L_POST:
1468 case ARM_t2STC2_POST:
1469 case ARM_t2STC2L_POST:
1471 case ARM_LDC2L_POST:
1473 case ARM_STC2L_POST:
1474 case ARM_t2LDC_POST:
1475 case ARM_t2LDCL_POST:
1476 case ARM_t2STC_POST:
1477 case ARM_t2STCL_POST:
1492 case ARM_LDC_OFFSET:
1495 case ARM_LDC_OPTION:
1496 case ARM_LDCL_OFFSET:
1499 case ARM_LDCL_OPTION:
1500 case ARM_STC_OFFSET:
1503 case ARM_STC_OPTION:
1504 case ARM_STCL_OFFSET:
1507 case ARM_STCL_OPTION:
1508 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
1525 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1526 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
1527 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1528 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
1529 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1530 unsigned reg = fieldFromInstruction_4(Insn, 25, 1);
1531 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
1532 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
1533 unsigned idx_mode = 0, amt,
tmp;
1537 case ARM_STR_POST_IMM:
1538 case ARM_STR_POST_REG:
1539 case ARM_STRB_POST_IMM:
1540 case ARM_STRB_POST_REG:
1541 case ARM_STRT_POST_REG:
1542 case ARM_STRT_POST_IMM:
1543 case ARM_STRBT_POST_REG:
1544 case ARM_STRBT_POST_IMM:
1545 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1552 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
1557 case ARM_LDR_POST_IMM:
1558 case ARM_LDR_POST_REG:
1559 case ARM_LDRB_POST_IMM:
1560 case ARM_LDRB_POST_REG:
1561 case ARM_LDRBT_POST_REG:
1562 case ARM_LDRBT_POST_IMM:
1563 case ARM_LDRT_POST_REG:
1564 case ARM_LDRT_POST_IMM:
1565 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1572 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1576 if (!fieldFromInstruction_4(Insn, 23, 1))
1579 writeback = (
P == 0) || (
W == 1);
1582 else if (!
P && writeback)
1585 if (writeback && (Rn == 15 || Rn == Rt))
1589 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rm,
Address, Decoder)))
1592 switch( fieldFromInstruction_4(Insn, 5, 2)) {
1608 amt = fieldFromInstruction_4(Insn, 7, 5);
1620 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
1632 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
1633 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1634 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1635 unsigned imm = fieldFromInstruction_4(Val, 7, 5);
1636 unsigned U = fieldFromInstruction_4(Val, 12, 1);
1657 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1659 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
1675 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
1676 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1677 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1678 unsigned type = fieldFromInstruction_4(Insn, 22, 1);
1679 unsigned imm = fieldFromInstruction_4(Insn, 8, 4);
1680 unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8;
1681 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1682 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
1683 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
1684 unsigned Rt2 = Rt + 1;
1686 bool writeback = (
W == 1) | (
P == 0);
1705 if (
P == 0 &&
W == 1)
1708 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1710 if (
type && Rm == 15)
1714 if (!
type && fieldFromInstruction_4(Insn, 8, 4))
1722 if (writeback && (Rn == 15 || Rn == Rt))
1724 if (!
type && Rm == 15)
1730 if (
type && Rn == 15){
1735 if (
P == 0 &&
W == 1)
1737 if (!
type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1739 if (!
type && writeback && Rn == 15)
1741 if (writeback && (Rn == Rt || Rn == Rt2))
1747 if (
type && Rn == 15){
1754 if (!
type && Rm == 15)
1756 if (!
type && writeback && (Rn == 15 || Rn == Rt))
1761 case ARM_LDRSH_POST:
1764 case ARM_LDRSB_POST:
1765 if (
type && Rn == 15){
1770 if (
type && (Rt == 15 || (writeback && Rn == Rt)))
1772 if (!
type && (Rt == 15 || Rm == 15))
1774 if (!
type && writeback && (Rn == 15 || Rn == Rt))
1796 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1804 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
1813 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt+1,
Address, Decoder)))
1831 case ARM_LDRSH_POST:
1834 case ARM_LDRSB_POST:
1837 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1845 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1852 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
1857 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
1868 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1869 unsigned mode = fieldFromInstruction_4(Insn, 23, 2);
1887 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1898 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
1899 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1900 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1901 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1904 return DecodeCPSInstruction(Inst, Insn,
Address, Decoder);
1906 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rd,
Address, Decoder)))
1908 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rm,
Address, Decoder)))
1910 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rn,
Address, Decoder)))
1912 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
1922 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1923 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1924 unsigned reglist = fieldFromInstruction_4(Insn, 0, 16);
1982 if (fieldFromInstruction_4(Insn, 20, 1) == 0) {
1984 if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 &&
1985 fieldFromInstruction_4(Insn, 20, 1) == 0))
1992 return DecodeRFEInstruction(Inst, Insn,
Address, Decoder);
1995 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1997 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
1999 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
2001 if (!
Check(&
S, DecodeRegListOperand(Inst, reglist,
Address, Decoder)))
2010 unsigned imod = fieldFromInstruction_4(Insn, 18, 2);
2011 unsigned M = fieldFromInstruction_4(Insn, 17, 1);
2012 unsigned iflags = fieldFromInstruction_4(Insn, 6, 3);
2013 unsigned mode = fieldFromInstruction_4(Insn, 0, 5);
2019 if (fieldFromInstruction_4(Insn, 5, 1) != 0 ||
2020 fieldFromInstruction_4(Insn, 16, 1) != 0 ||
2021 fieldFromInstruction_4(Insn, 20, 8) != 0x10)
2036 }
else if (imod && !M) {
2041 }
else if (!imod && M) {
2058 unsigned imod = fieldFromInstruction_4(Insn, 9, 2);
2059 unsigned M = fieldFromInstruction_4(Insn, 8, 1);
2060 unsigned iflags = fieldFromInstruction_4(Insn, 5, 3);
2061 unsigned mode = fieldFromInstruction_4(Insn, 0, 5);
2077 }
else if (imod && !M) {
2082 }
else if (!imod && M) {
2088 int imm = fieldFromInstruction_4(Insn, 0, 8);
2103 unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
2106 imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0);
2107 imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8);
2108 imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12);
2109 imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11);
2112 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rd,
Address, Decoder)))
2114 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rd,
Address, Decoder)))
2127 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2128 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2131 imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0);
2132 imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12);
2135 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rd,
Address, Decoder)))
2138 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rd,
Address, Decoder)))
2143 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
2154 unsigned Rd = fieldFromInstruction_4(Insn, 16, 4);
2155 unsigned Rn = fieldFromInstruction_4(Insn, 0, 4);
2156 unsigned Rm = fieldFromInstruction_4(Insn, 8, 4);
2157 unsigned Ra = fieldFromInstruction_4(Insn, 12, 4);
2158 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2161 return DecodeCPSInstruction(Inst, Insn,
Address, Decoder);
2163 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rd,
Address, Decoder)))
2165 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rn,
Address, Decoder)))
2167 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rm,
Address, Decoder)))
2169 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Ra,
Address, Decoder)))
2172 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
2183 unsigned add = fieldFromInstruction_4(Val, 12, 1);
2184 unsigned imm = fieldFromInstruction_4(Val, 0, 12);
2185 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
2187 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
2190 if (!
add) imm *= (
unsigned int)-1;
2204 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
2205 unsigned U = fieldFromInstruction_4(Val, 8, 1);
2206 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
2208 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
2222 return DecodeGPRRegisterClass(Inst, Val,
Address, Decoder);
2236 unsigned S = fieldFromInstruction_4(Insn, 26, 1);
2237 unsigned J1 = fieldFromInstruction_4(Insn, 13, 1);
2238 unsigned J2 = fieldFromInstruction_4(Insn, 11, 1);
2239 unsigned I1 = !(J1 ^
S);
2240 unsigned I2 = !(J2 ^
S);
2241 unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10);
2242 unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11);
2243 unsigned tmp = (
S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2255 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2256 unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2;
2260 imm |= fieldFromInstruction_4(Insn, 24, 1) << 1;
2266 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
2278 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
2279 unsigned align = fieldFromInstruction_4(Val, 4, 2);
2281 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
2295 unsigned wb, Rn, Rm;
2296 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2297 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2298 wb = fieldFromInstruction_4(Insn, 16, 4);
2299 Rn = fieldFromInstruction_4(Insn, 16, 4);
2300 Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
2301 Rm = fieldFromInstruction_4(Insn, 0, 4);
2305 case ARM_VLD1q16:
case ARM_VLD1q32:
case ARM_VLD1q64:
case ARM_VLD1q8:
2306 case ARM_VLD1q16wb_fixed:
case ARM_VLD1q16wb_register:
2307 case ARM_VLD1q32wb_fixed:
case ARM_VLD1q32wb_register:
2308 case ARM_VLD1q64wb_fixed:
case ARM_VLD1q64wb_register:
2309 case ARM_VLD1q8wb_fixed:
case ARM_VLD1q8wb_register:
2310 case ARM_VLD2d16:
case ARM_VLD2d32:
case ARM_VLD2d8:
2311 case ARM_VLD2d16wb_fixed:
case ARM_VLD2d16wb_register:
2312 case ARM_VLD2d32wb_fixed:
case ARM_VLD2d32wb_register:
2313 case ARM_VLD2d8wb_fixed:
case ARM_VLD2d8wb_register:
2314 if (!
Check(&
S, DecodeDPairRegisterClass(Inst, Rd,
Address, Decoder)))
2320 case ARM_VLD2b16wb_fixed:
2321 case ARM_VLD2b16wb_register:
2322 case ARM_VLD2b32wb_fixed:
2323 case ARM_VLD2b32wb_register:
2324 case ARM_VLD2b8wb_fixed:
2325 case ARM_VLD2b8wb_register:
2326 if (!
Check(&
S, DecodeDPairSpacedRegisterClass(Inst, Rd,
Address, Decoder)))
2330 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
2339 case ARM_VLD3d8_UPD:
2340 case ARM_VLD3d16_UPD:
2341 case ARM_VLD3d32_UPD:
2345 case ARM_VLD4d8_UPD:
2346 case ARM_VLD4d16_UPD:
2347 case ARM_VLD4d32_UPD:
2348 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+1)%32,
Address, Decoder)))
2354 case ARM_VLD3q8_UPD:
2355 case ARM_VLD3q16_UPD:
2356 case ARM_VLD3q32_UPD:
2360 case ARM_VLD4q8_UPD:
2361 case ARM_VLD4q16_UPD:
2362 case ARM_VLD4q32_UPD:
2363 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+2)%32,
Address, Decoder)))
2374 case ARM_VLD3d8_UPD:
2375 case ARM_VLD3d16_UPD:
2376 case ARM_VLD3d32_UPD:
2380 case ARM_VLD4d8_UPD:
2381 case ARM_VLD4d16_UPD:
2382 case ARM_VLD4d32_UPD:
2383 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+2)%32,
Address, Decoder)))
2389 case ARM_VLD3q8_UPD:
2390 case ARM_VLD3q16_UPD:
2391 case ARM_VLD3q32_UPD:
2395 case ARM_VLD4q8_UPD:
2396 case ARM_VLD4q16_UPD:
2397 case ARM_VLD4q32_UPD:
2398 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+4)%32,
Address, Decoder)))
2410 case ARM_VLD4d8_UPD:
2411 case ARM_VLD4d16_UPD:
2412 case ARM_VLD4d32_UPD:
2413 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+3)%32,
Address, Decoder)))
2419 case ARM_VLD4q8_UPD:
2420 case ARM_VLD4q16_UPD:
2421 case ARM_VLD4q32_UPD:
2422 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+6)%32,
Address, Decoder)))
2431 case ARM_VLD1d8wb_fixed:
2432 case ARM_VLD1d16wb_fixed:
2433 case ARM_VLD1d32wb_fixed:
2434 case ARM_VLD1d64wb_fixed:
2435 case ARM_VLD1d8wb_register:
2436 case ARM_VLD1d16wb_register:
2437 case ARM_VLD1d32wb_register:
2438 case ARM_VLD1d64wb_register:
2439 case ARM_VLD1q8wb_fixed:
2440 case ARM_VLD1q16wb_fixed:
2441 case ARM_VLD1q32wb_fixed:
2442 case ARM_VLD1q64wb_fixed:
2443 case ARM_VLD1q8wb_register:
2444 case ARM_VLD1q16wb_register:
2445 case ARM_VLD1q32wb_register:
2446 case ARM_VLD1q64wb_register:
2447 case ARM_VLD1d8Twb_fixed:
2448 case ARM_VLD1d8Twb_register:
2449 case ARM_VLD1d16Twb_fixed:
2450 case ARM_VLD1d16Twb_register:
2451 case ARM_VLD1d32Twb_fixed:
2452 case ARM_VLD1d32Twb_register:
2453 case ARM_VLD1d64Twb_fixed:
2454 case ARM_VLD1d64Twb_register:
2455 case ARM_VLD1d8Qwb_fixed:
2456 case ARM_VLD1d8Qwb_register:
2457 case ARM_VLD1d16Qwb_fixed:
2458 case ARM_VLD1d16Qwb_register:
2459 case ARM_VLD1d32Qwb_fixed:
2460 case ARM_VLD1d32Qwb_register:
2461 case ARM_VLD1d64Qwb_fixed:
2462 case ARM_VLD1d64Qwb_register:
2463 case ARM_VLD2d8wb_fixed:
2464 case ARM_VLD2d16wb_fixed:
2465 case ARM_VLD2d32wb_fixed:
2466 case ARM_VLD2q8wb_fixed:
2467 case ARM_VLD2q16wb_fixed:
2468 case ARM_VLD2q32wb_fixed:
2469 case ARM_VLD2d8wb_register:
2470 case ARM_VLD2d16wb_register:
2471 case ARM_VLD2d32wb_register:
2472 case ARM_VLD2q8wb_register:
2473 case ARM_VLD2q16wb_register:
2474 case ARM_VLD2q32wb_register:
2475 case ARM_VLD2b8wb_fixed:
2476 case ARM_VLD2b16wb_fixed:
2477 case ARM_VLD2b32wb_fixed:
2478 case ARM_VLD2b8wb_register:
2479 case ARM_VLD2b16wb_register:
2480 case ARM_VLD2b32wb_register:
2483 case ARM_VLD3d8_UPD:
2484 case ARM_VLD3d16_UPD:
2485 case ARM_VLD3d32_UPD:
2486 case ARM_VLD3q8_UPD:
2487 case ARM_VLD3q16_UPD:
2488 case ARM_VLD3q32_UPD:
2489 case ARM_VLD4d8_UPD:
2490 case ARM_VLD4d16_UPD:
2491 case ARM_VLD4d32_UPD:
2492 case ARM_VLD4q8_UPD:
2493 case ARM_VLD4q16_UPD:
2494 case ARM_VLD4q32_UPD:
2495 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, wb,
Address, Decoder)))
2503 if (!
Check(&
S, DecodeAddrMode6Operand(Inst, Rn,
Address, Decoder)))
2520 case ARM_VLD1d8wb_fixed:
2521 case ARM_VLD1d16wb_fixed:
2522 case ARM_VLD1d32wb_fixed:
2523 case ARM_VLD1d64wb_fixed:
2524 case ARM_VLD1d8Twb_fixed:
2525 case ARM_VLD1d16Twb_fixed:
2526 case ARM_VLD1d32Twb_fixed:
2527 case ARM_VLD1d64Twb_fixed:
2528 case ARM_VLD1d8Qwb_fixed:
2529 case ARM_VLD1d16Qwb_fixed:
2530 case ARM_VLD1d32Qwb_fixed:
2531 case ARM_VLD1d64Qwb_fixed:
2532 case ARM_VLD1d8wb_register:
2533 case ARM_VLD1d16wb_register:
2534 case ARM_VLD1d32wb_register:
2535 case ARM_VLD1d64wb_register:
2536 case ARM_VLD1q8wb_fixed:
2537 case ARM_VLD1q16wb_fixed:
2538 case ARM_VLD1q32wb_fixed:
2539 case ARM_VLD1q64wb_fixed:
2540 case ARM_VLD1q8wb_register:
2541 case ARM_VLD1q16wb_register:
2542 case ARM_VLD1q32wb_register:
2543 case ARM_VLD1q64wb_register:
2547 if (Rm != 0xD && Rm != 0xF &&
2548 !
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
2551 case ARM_VLD2d8wb_fixed:
2552 case ARM_VLD2d16wb_fixed:
2553 case ARM_VLD2d32wb_fixed:
2554 case ARM_VLD2b8wb_fixed:
2555 case ARM_VLD2b16wb_fixed:
2556 case ARM_VLD2b32wb_fixed:
2557 case ARM_VLD2q8wb_fixed:
2558 case ARM_VLD2q16wb_fixed:
2559 case ARM_VLD2q32wb_fixed:
2570 unsigned type = fieldFromInstruction_4(Insn, 8, 4);
2571 unsigned align = fieldFromInstruction_4(Insn, 4, 2);
2576 load = fieldFromInstruction_4(Insn, 21, 1);
2577 return load ? DecodeVLDInstruction(Inst, Insn,
Address, Decoder)
2578 : DecodeVSTInstruction(Inst, Insn,
Address, Decoder);
2585 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2588 type = fieldFromInstruction_4(Insn, 8, 4);
2589 align = fieldFromInstruction_4(Insn, 4, 2);
2593 load = fieldFromInstruction_4(Insn, 21, 1);
2594 return load ? DecodeVLDInstruction(Inst, Insn,
Address, Decoder)
2595 : DecodeVSTInstruction(Inst, Insn,
Address, Decoder);
2602 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2605 align = fieldFromInstruction_4(Insn, 4, 2);
2608 load = fieldFromInstruction_4(Insn, 21, 1);
2609 return load ? DecodeVLDInstruction(Inst, Insn,
Address, Decoder)
2610 : DecodeVSTInstruction(Inst, Insn,
Address, Decoder);
2617 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2620 load = fieldFromInstruction_4(Insn, 21, 1);
2621 return load ? DecodeVLDInstruction(Inst, Insn,
Address, Decoder)
2622 : DecodeVSTInstruction(Inst, Insn,
Address, Decoder);
2629 unsigned wb, Rn, Rm;
2630 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2631 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2632 wb = fieldFromInstruction_4(Insn, 16, 4);
2633 Rn = fieldFromInstruction_4(Insn, 16, 4);
2634 Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
2635 Rm = fieldFromInstruction_4(Insn, 0, 4);
2639 case ARM_VST1d8wb_fixed:
2640 case ARM_VST1d16wb_fixed:
2641 case ARM_VST1d32wb_fixed:
2642 case ARM_VST1d64wb_fixed:
2643 case ARM_VST1d8wb_register:
2644 case ARM_VST1d16wb_register:
2645 case ARM_VST1d32wb_register:
2646 case ARM_VST1d64wb_register:
2647 case ARM_VST1q8wb_fixed:
2648 case ARM_VST1q16wb_fixed:
2649 case ARM_VST1q32wb_fixed:
2650 case ARM_VST1q64wb_fixed:
2651 case ARM_VST1q8wb_register:
2652 case ARM_VST1q16wb_register:
2653 case ARM_VST1q32wb_register:
2654 case ARM_VST1q64wb_register:
2655 case ARM_VST1d8Twb_fixed:
2656 case ARM_VST1d16Twb_fixed:
2657 case ARM_VST1d32Twb_fixed:
2658 case ARM_VST1d64Twb_fixed:
2659 case ARM_VST1d8Twb_register:
2660 case ARM_VST1d16Twb_register:
2661 case ARM_VST1d32Twb_register:
2662 case ARM_VST1d64Twb_register:
2663 case ARM_VST1d8Qwb_fixed:
2664 case ARM_VST1d16Qwb_fixed:
2665 case ARM_VST1d32Qwb_fixed:
2666 case ARM_VST1d64Qwb_fixed:
2667 case ARM_VST1d8Qwb_register:
2668 case ARM_VST1d16Qwb_register:
2669 case ARM_VST1d32Qwb_register:
2670 case ARM_VST1d64Qwb_register:
2671 case ARM_VST2d8wb_fixed:
2672 case ARM_VST2d16wb_fixed:
2673 case ARM_VST2d32wb_fixed:
2674 case ARM_VST2d8wb_register:
2675 case ARM_VST2d16wb_register:
2676 case ARM_VST2d32wb_register:
2677 case ARM_VST2q8wb_fixed:
2678 case ARM_VST2q16wb_fixed:
2679 case ARM_VST2q32wb_fixed:
2680 case ARM_VST2q8wb_register:
2681 case ARM_VST2q16wb_register:
2682 case ARM_VST2q32wb_register:
2683 case ARM_VST2b8wb_fixed:
2684 case ARM_VST2b16wb_fixed:
2685 case ARM_VST2b32wb_fixed:
2686 case ARM_VST2b8wb_register:
2687 case ARM_VST2b16wb_register:
2688 case ARM_VST2b32wb_register:
2693 case ARM_VST3d8_UPD:
2694 case ARM_VST3d16_UPD:
2695 case ARM_VST3d32_UPD:
2696 case ARM_VST3q8_UPD:
2697 case ARM_VST3q16_UPD:
2698 case ARM_VST3q32_UPD:
2699 case ARM_VST4d8_UPD:
2700 case ARM_VST4d16_UPD:
2701 case ARM_VST4d32_UPD:
2702 case ARM_VST4q8_UPD:
2703 case ARM_VST4q16_UPD:
2704 case ARM_VST4q32_UPD:
2705 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, wb,
Address, Decoder)))
2713 if (!
Check(&
S, DecodeAddrMode6Operand(Inst, Rn,
Address, Decoder)))
2721 else if (Rm != 0xF) {
2722 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
2726 case ARM_VST1d8wb_fixed:
2727 case ARM_VST1d16wb_fixed:
2728 case ARM_VST1d32wb_fixed:
2729 case ARM_VST1d64wb_fixed:
2730 case ARM_VST1q8wb_fixed:
2731 case ARM_VST1q16wb_fixed:
2732 case ARM_VST1q32wb_fixed:
2733 case ARM_VST1q64wb_fixed:
2734 case ARM_VST1d8Twb_fixed:
2735 case ARM_VST1d16Twb_fixed:
2736 case ARM_VST1d32Twb_fixed:
2737 case ARM_VST1d64Twb_fixed:
2738 case ARM_VST1d8Qwb_fixed:
2739 case ARM_VST1d16Qwb_fixed:
2740 case ARM_VST1d32Qwb_fixed:
2741 case ARM_VST1d64Qwb_fixed:
2742 case ARM_VST2d8wb_fixed:
2743 case ARM_VST2d16wb_fixed:
2744 case ARM_VST2d32wb_fixed:
2745 case ARM_VST2q8wb_fixed:
2746 case ARM_VST2q16wb_fixed:
2747 case ARM_VST2q32wb_fixed:
2748 case ARM_VST2b8wb_fixed:
2749 case ARM_VST2b16wb_fixed:
2750 case ARM_VST2b32wb_fixed:
2761 case ARM_VST1q16wb_fixed:
2762 case ARM_VST1q16wb_register:
2763 case ARM_VST1q32wb_fixed:
2764 case ARM_VST1q32wb_register:
2765 case ARM_VST1q64wb_fixed:
2766 case ARM_VST1q64wb_register:
2767 case ARM_VST1q8wb_fixed:
2768 case ARM_VST1q8wb_register:
2772 case ARM_VST2d16wb_fixed:
2773 case ARM_VST2d16wb_register:
2774 case ARM_VST2d32wb_fixed:
2775 case ARM_VST2d32wb_register:
2776 case ARM_VST2d8wb_fixed:
2777 case ARM_VST2d8wb_register:
2778 if (!
Check(&
S, DecodeDPairRegisterClass(Inst, Rd,
Address, Decoder)))
2784 case ARM_VST2b16wb_fixed:
2785 case ARM_VST2b16wb_register:
2786 case ARM_VST2b32wb_fixed:
2787 case ARM_VST2b32wb_register:
2788 case ARM_VST2b8wb_fixed:
2789 case ARM_VST2b8wb_register:
2790 if (!
Check(&
S, DecodeDPairSpacedRegisterClass(Inst, Rd,
Address, Decoder)))
2794 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
2803 case ARM_VST3d8_UPD:
2804 case ARM_VST3d16_UPD:
2805 case ARM_VST3d32_UPD:
2809 case ARM_VST4d8_UPD:
2810 case ARM_VST4d16_UPD:
2811 case ARM_VST4d32_UPD:
2812 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+1)%32,
Address, Decoder)))
2818 case ARM_VST3q8_UPD:
2819 case ARM_VST3q16_UPD:
2820 case ARM_VST3q32_UPD:
2824 case ARM_VST4q8_UPD:
2825 case ARM_VST4q16_UPD:
2826 case ARM_VST4q32_UPD:
2827 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+2)%32,
Address, Decoder)))
2839 case ARM_VST3d8_UPD:
2840 case ARM_VST3d16_UPD:
2841 case ARM_VST3d32_UPD:
2845 case ARM_VST4d8_UPD:
2846 case ARM_VST4d16_UPD:
2847 case ARM_VST4d32_UPD:
2848 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+2)%32,
Address, Decoder)))
2854 case ARM_VST3q8_UPD:
2855 case ARM_VST3q16_UPD:
2856 case ARM_VST3q32_UPD:
2860 case ARM_VST4q8_UPD:
2861 case ARM_VST4q16_UPD:
2862 case ARM_VST4q32_UPD:
2863 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+4)%32,
Address, Decoder)))
2875 case ARM_VST4d8_UPD:
2876 case ARM_VST4d16_UPD:
2877 case ARM_VST4d32_UPD:
2878 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+3)%32,
Address, Decoder)))
2884 case ARM_VST4q8_UPD:
2885 case ARM_VST4q16_UPD:
2886 case ARM_VST4q32_UPD:
2887 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+6)%32,
Address, Decoder)))
2902 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2903 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2904 Rn = fieldFromInstruction_4(Insn, 16, 4);
2905 Rm = fieldFromInstruction_4(Insn, 0, 4);
2906 align = fieldFromInstruction_4(Insn, 4, 1);
2907 size = fieldFromInstruction_4(Insn, 6, 2);
2914 case ARM_VLD1DUPq16:
case ARM_VLD1DUPq32:
case ARM_VLD1DUPq8:
2915 case ARM_VLD1DUPq16wb_fixed:
case ARM_VLD1DUPq16wb_register:
2916 case ARM_VLD1DUPq32wb_fixed:
case ARM_VLD1DUPq32wb_register:
2917 case ARM_VLD1DUPq8wb_fixed:
case ARM_VLD1DUPq8wb_register:
2918 if (!
Check(&
S, DecodeDPairRegisterClass(Inst, Rd,
Address, Decoder)))
2922 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
2927 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
2931 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
2938 if (Rm != 0xD && Rm != 0xF &&
2939 !
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
2950 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2951 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2952 Rn = fieldFromInstruction_4(Insn, 16, 4);
2953 Rm = fieldFromInstruction_4(Insn, 0, 4);
2954 align = fieldFromInstruction_4(Insn, 4, 1);
2955 size = 1 << fieldFromInstruction_4(Insn, 6, 2);
2959 case ARM_VLD2DUPd16:
case ARM_VLD2DUPd32:
case ARM_VLD2DUPd8:
2960 case ARM_VLD2DUPd16wb_fixed:
case ARM_VLD2DUPd16wb_register:
2961 case ARM_VLD2DUPd32wb_fixed:
case ARM_VLD2DUPd32wb_register:
2962 case ARM_VLD2DUPd8wb_fixed:
case ARM_VLD2DUPd8wb_register:
2963 if (!
Check(&
S, DecodeDPairRegisterClass(Inst, Rd,
Address, Decoder)))
2966 case ARM_VLD2DUPd16x2:
case ARM_VLD2DUPd32x2:
case ARM_VLD2DUPd8x2:
2967 case ARM_VLD2DUPd16x2wb_fixed:
case ARM_VLD2DUPd16x2wb_register:
2968 case ARM_VLD2DUPd32x2wb_fixed:
case ARM_VLD2DUPd32x2wb_register:
2969 case ARM_VLD2DUPd8x2wb_fixed:
case ARM_VLD2DUPd8x2wb_register:
2970 if (!
Check(&
S, DecodeDPairSpacedRegisterClass(Inst, Rd,
Address, Decoder)))
2974 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
2982 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
2986 if (Rm != 0xD && Rm != 0xF) {
2987 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
2998 unsigned Rn, Rm,
inc;
2999 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3000 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3001 Rn = fieldFromInstruction_4(Insn, 16, 4);
3002 Rm = fieldFromInstruction_4(Insn, 0, 4);
3003 inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
3005 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
3007 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+
inc)%32,
Address, Decoder)))
3009 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+2*
inc)%32,
Address, Decoder)))
3012 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3016 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3022 else if (Rm != 0xF) {
3023 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
3035 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3036 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3037 Rn = fieldFromInstruction_4(Insn, 16, 4);
3038 Rm = fieldFromInstruction_4(Insn, 0, 4);
3039 size = fieldFromInstruction_4(Insn, 6, 2);
3040 inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
3041 align = fieldFromInstruction_4(Insn, 4, 1);
3056 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
3058 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+
inc)%32,
Address, Decoder)))
3060 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+2*
inc)%32,
Address, Decoder)))
3062 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, (Rd+3*
inc)%32,
Address, Decoder)))
3065 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3069 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3075 else if (Rm != 0xF) {
3076 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
3088 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3089 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3090 imm = fieldFromInstruction_4(Insn, 0, 4);
3091 imm |= fieldFromInstruction_4(Insn, 16, 3) << 4;
3092 imm |= fieldFromInstruction_4(Insn, 24, 1) << 7;
3093 imm |= fieldFromInstruction_4(Insn, 8, 4) << 8;
3094 imm |= fieldFromInstruction_4(Insn, 5, 1) << 12;
3095 Q = fieldFromInstruction_4(Insn, 6, 1);
3098 if (!
Check(&
S, DecodeQPRRegisterClass(Inst, Rd,
Address, Decoder)))
3101 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
3108 case ARM_VORRiv4i16:
3109 case ARM_VORRiv2i32:
3110 case ARM_VBICiv4i16:
3111 case ARM_VBICiv2i32:
3112 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
3115 case ARM_VORRiv8i16:
3116 case ARM_VORRiv4i32:
3117 case ARM_VBICiv8i16:
3118 case ARM_VBICiv4i32:
3119 if (!
Check(&
S, DecodeQPRRegisterClass(Inst, Rd,
Address, Decoder)))
3134 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3135 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3136 Rm = fieldFromInstruction_4(Insn, 0, 4);
3137 Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
3138 size = fieldFromInstruction_4(Insn, 18, 2);
3140 if (!
Check(&
S, DecodeQPRRegisterClass(Inst, Rd,
Address, Decoder)))
3142 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rm,
Address, Decoder)))
3181 unsigned Rn, Rm,
op;
3182 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3183 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3184 Rn = fieldFromInstruction_4(Insn, 16, 4);
3185 Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4;
3186 Rm = fieldFromInstruction_4(Insn, 0, 4);
3187 Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
3188 op = fieldFromInstruction_4(Insn, 6, 1);
3190 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
3193 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
3200 if (!
Check(&
S, DecodeDPairRegisterClass(Inst, Rn,
Address, Decoder)))
3204 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rn,
Address, Decoder)))
3208 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rm,
Address, Decoder)))
3219 unsigned dst = fieldFromInstruction_2(Insn, 8, 3);
3220 unsigned imm = fieldFromInstruction_2(Insn, 0, 8);
3265 unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
3266 unsigned Rm = fieldFromInstruction_4(Val, 3, 3);
3268 if (!
Check(&
S, DecodetGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3270 if (!
Check(&
S, DecodetGPRRegisterClass(Inst, Rm,
Address, Decoder)))
3281 unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
3282 unsigned imm = fieldFromInstruction_4(Val, 3, 5);
3284 if (!
Check(&
S, DecodetGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3294 unsigned imm = Val << 2;
3316 unsigned Rn = fieldFromInstruction_4(Val, 6, 4);
3317 unsigned Rm = fieldFromInstruction_4(Val, 2, 4);
3318 unsigned imm = fieldFromInstruction_4(Val, 0, 2);
3331 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3333 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rm,
Address, Decoder)))
3345 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3346 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3348 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3349 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3378 return DecodeT2LoadLabel(Inst, Insn,
Address, Decoder);
3403 if (!hasV7Ops || !hasMP)
3407 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
3411 addrmode = fieldFromInstruction_4(Insn, 4, 2);
3412 addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2;
3413 addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6;
3414 if (!
Check(&
S, DecodeT2AddrModeSOReg(Inst, addrmode,
Address, Decoder)))
3425 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3426 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3427 unsigned U = fieldFromInstruction_4(Insn, 9, 1);
3428 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
3429 unsigned add = fieldFromInstruction_4(Insn, 9, 1);
3432 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3433 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3463 return DecodeT2LoadLabel(Inst, Insn,
Address, Decoder);
3490 if (!hasV7Ops || !hasMP)
3494 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
3498 if (!
Check(&
S, DecodeT2AddrModeImm8(Inst, imm,
Address, Decoder)))
3508 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3509 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3510 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
3512 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3513 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3525 case ARM_t2LDRSHi12:
3531 case ARM_t2LDRSBi12:
3543 return DecodeT2LoadLabel(Inst, Insn,
Address, Decoder);
3548 case ARM_t2LDRSHi12:
3553 case ARM_t2LDRSBi12:
3569 if (!hasV7Ops || !hasMP)
3573 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
3577 if (!
Check(&
S, DecodeT2AddrModeImm12(Inst, imm,
Address, Decoder)))
3587 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3588 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3589 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
3612 return DecodeT2LoadLabel(Inst, Insn,
Address, Decoder);
3615 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rt,
Address, Decoder)))
3617 if (!
Check(&
S, DecodeT2AddrModeImm8(Inst, imm,
Address, Decoder)))
3627 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3628 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
3629 int imm = fieldFromInstruction_4(Insn, 0, 12);
3631 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3639 case ARM_t2LDRSBpci:
3642 case ARM_t2LDRSHpci:
3657 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
3679 int imm = Val & 0xFF;
3681 if (!(Val & 0x100)) imm *= -1;
3693 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
3694 unsigned imm = fieldFromInstruction_4(Val, 0, 9);
3696 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3698 if (!
Check(&
S, DecodeT2Imm8S4(Inst, imm,
Address, Decoder)))
3709 unsigned Rn = fieldFromInstruction_4(Val, 8, 4);
3710 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
3712 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rn,
Address, Decoder)))
3723 int imm = Val & 0xFF;
3726 else if (!(Val & 0x100))
3738 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
3739 unsigned imm = fieldFromInstruction_4(Val, 0, 9);
3772 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3785 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3786 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3787 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
3788 addr |= fieldFromInstruction_4(Insn, 9, 1) << 8;
3790 load = fieldFromInstruction_4(Insn, 20, 1);
3795 case ARM_t2LDR_POST:
3798 case ARM_t2LDRB_PRE:
3799 case ARM_t2LDRB_POST:
3802 case ARM_t2LDRH_PRE:
3803 case ARM_t2LDRH_POST:
3806 case ARM_t2LDRSB_PRE:
3807 case ARM_t2LDRSB_POST:
3813 case ARM_t2LDRSH_PRE:
3814 case ARM_t2LDRSH_POST:
3820 return DecodeT2LoadLabel(Inst, Insn,
Address, Decoder);
3824 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3828 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
3832 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3847 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
3848 unsigned imm = fieldFromInstruction_4(Val, 0, 12);
3861 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3871 unsigned imm = fieldFromInstruction_2(Insn, 0, 7);
3886 unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3);
3887 Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3;
3889 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rdm,
Address, Decoder)))
3892 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rdm,
Address, Decoder)))
3895 unsigned Rm = fieldFromInstruction_2(Insn, 3, 4);
3899 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
3909 unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2;
3910 unsigned flags = fieldFromInstruction_2(Insn, 0, 3);
3922 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3923 unsigned add = fieldFromInstruction_4(Insn, 4, 1);
3925 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rm,
Address, Decoder)))
3942 unsigned S = (Val >> 23) & 1;
3943 unsigned J1 = (Val >> 22) & 1;
3944 unsigned J2 = (Val >> 21) & 1;
3945 unsigned I1 = !(J1 ^
S);
3946 unsigned I2 = !(J2 ^
S);
3947 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3957 if (Val == 0xA || Val == 0xB)
3969 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3970 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3973 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
3975 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rm,
Address, Decoder)))
3985 unsigned pred = fieldFromInstruction_4(Insn, 22, 4);
3986 if (pred == 0xE || pred == 0xF) {
3988 unsigned opc = fieldFromInstruction_4(Insn, 4, 28);
4003 imm = fieldFromInstruction_4(Insn, 0, 4);
4004 return DecodeMemBarrierOption(Inst, imm,
Address, Decoder);
4007 brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1;
4008 brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19;
4009 brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18;
4010 brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12;
4011 brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20;
4013 if (!
Check(&
S, DecodeT2BROperand(Inst, brtarget,
Address, Decoder)))
4015 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4027 unsigned ctrl = fieldFromInstruction_4(Val, 10, 2);
4029 unsigned byte = fieldFromInstruction_4(Val, 8, 2);
4030 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
4046 unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80;
4047 unsigned rot = fieldFromInstruction_4(Val, 7, 5);
4048 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4072 unsigned S = (Val >> 23) & 1;
4073 unsigned J1 = (Val >> 22) & 1;
4074 unsigned J2 = (Val >> 21) & 1;
4075 unsigned I1 = !(J1 ^
S);
4076 unsigned I2 = !(J2 ^
S);
4077 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4109 if (FeatureBits & ARM_FeatureMClass) {
4110 unsigned ValLow = Val & 0xff;
4129 if (!(FeatureBits & ARM_HasV7Ops))
4138 unsigned Mask = fieldFromInstruction_4(Val, 10, 2);
4139 if (!(FeatureBits & ARM_HasV7Ops)) {
4152 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4153 (!(FeatureBits & ARM_FeatureDSPThumb2) && (Mask & 1)))
4171 unsigned R = fieldFromInstruction_4(Val, 5, 1);
4172 unsigned SysM = fieldFromInstruction_4(Val, 0, 5);
4178 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4179 SysM == 0x1a || SysM == 0x1b)
4182 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4183 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4196 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4197 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4198 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4203 if (!
Check(&
S, DecodeGPRPairRegisterClass(Inst, Rt,
Address, Decoder)))
4205 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4207 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4218 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4219 unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
4220 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4221 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4223 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rd,
Address, Decoder)))
4226 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4229 if (!
Check(&
S, DecodeGPRPairRegisterClass(Inst, Rt,
Address, Decoder)))
4231 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4233 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4244 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4245 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4246 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4247 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4248 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4249 pred = fieldFromInstruction_4(Insn, 28, 4);
4253 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
4255 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4257 if (!
Check(&
S, DecodeAddrModeImm12Operand(Inst, imm,
Address, Decoder)))
4259 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4270 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4271 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4272 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4273 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4274 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4275 pred = fieldFromInstruction_4(Insn, 28, 4);
4276 Rm = fieldFromInstruction_4(Insn, 0, 4);
4281 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
4283 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4285 if (!
Check(&
S, DecodeSORegMemOperand(Inst, imm,
Address, Decoder)))
4287 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4298 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4299 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4300 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4301 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4302 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4303 pred = fieldFromInstruction_4(Insn, 28, 4);
4307 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4309 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
4311 if (!
Check(&
S, DecodeAddrModeImm12Operand(Inst, imm,
Address, Decoder)))
4313 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4324 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4325 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4326 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4327 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4328 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4329 pred = fieldFromInstruction_4(Insn, 28, 4);
4333 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4335 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt,
Address, Decoder)))
4337 if (!
Check(&
S, DecodeSORegMemOperand(Inst, imm,
Address, Decoder)))
4339 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4350 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4351 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4352 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4353 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4354 size = fieldFromInstruction_4(Insn, 10, 2);
4360 if (fieldFromInstruction_4(Insn, 4, 1))
4362 index = fieldFromInstruction_4(Insn, 5, 3);
4365 if (fieldFromInstruction_4(Insn, 5, 1))
4367 index = fieldFromInstruction_4(Insn, 6, 2);
4368 if (fieldFromInstruction_4(Insn, 4, 1))
4372 if (fieldFromInstruction_4(Insn, 6, 1))
4374 index = fieldFromInstruction_4(Insn, 7, 1);
4376 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4387 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4390 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4393 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4398 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
4404 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4416 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4417 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4418 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4419 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4420 size = fieldFromInstruction_4(Insn, 10, 2);
4426 if (fieldFromInstruction_4(Insn, 4, 1))
4428 index = fieldFromInstruction_4(Insn, 5, 3);
4431 if (fieldFromInstruction_4(Insn, 5, 1))
4433 index = fieldFromInstruction_4(Insn, 6, 2);
4434 if (fieldFromInstruction_4(Insn, 4, 1))
4438 if (fieldFromInstruction_4(Insn, 6, 1))
4440 index = fieldFromInstruction_4(Insn, 7, 1);
4442 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4454 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4457 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4462 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
4468 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4480 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4481 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4482 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4483 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4484 size = fieldFromInstruction_4(Insn, 10, 2);
4490 index = fieldFromInstruction_4(Insn, 5, 3);
4491 if (fieldFromInstruction_4(Insn, 4, 1))
4495 index = fieldFromInstruction_4(Insn, 6, 2);
4496 if (fieldFromInstruction_4(Insn, 4, 1))
4498 if (fieldFromInstruction_4(Insn, 5, 1))
4502 if (fieldFromInstruction_4(Insn, 5, 1))
4504 index = fieldFromInstruction_4(Insn, 7, 1);
4505 if (fieldFromInstruction_4(Insn, 4, 1) != 0)
4507 if (fieldFromInstruction_4(Insn, 6, 1))
4512 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4517 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4520 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4525 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
4531 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4545 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4546 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4547 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4548 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4549 size = fieldFromInstruction_4(Insn, 10, 2);
4555 index = fieldFromInstruction_4(Insn, 5, 3);
4556 if (fieldFromInstruction_4(Insn, 4, 1))
4560 index = fieldFromInstruction_4(Insn, 6, 2);
4561 if (fieldFromInstruction_4(Insn, 4, 1))
4563 if (fieldFromInstruction_4(Insn, 5, 1))
4567 if (fieldFromInstruction_4(Insn, 5, 1))
4569 index = fieldFromInstruction_4(Insn, 7, 1);
4570 if (fieldFromInstruction_4(Insn, 4, 1) != 0)
4572 if (fieldFromInstruction_4(Insn, 6, 1))
4578 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4581 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4586 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
4592 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4606 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4607 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4608 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4609 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4610 size = fieldFromInstruction_4(Insn, 10, 2);
4616 if (fieldFromInstruction_4(Insn, 4, 1))
4618 index = fieldFromInstruction_4(Insn, 5, 3);
4621 if (fieldFromInstruction_4(Insn, 4, 1))
4623 index = fieldFromInstruction_4(Insn, 6, 2);
4624 if (fieldFromInstruction_4(Insn, 5, 1))
4628 if (fieldFromInstruction_4(Insn, 4, 2))
4630 index = fieldFromInstruction_4(Insn, 7, 1);
4631 if (fieldFromInstruction_4(Insn, 6, 1))
4636 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4644 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4647 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4652 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
4658 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4674 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4675 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4676 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4677 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4678 size = fieldFromInstruction_4(Insn, 10, 2);
4684 if (fieldFromInstruction_4(Insn, 4, 1))
4686 index = fieldFromInstruction_4(Insn, 5, 3);
4689 if (fieldFromInstruction_4(Insn, 4, 1))
4691 index = fieldFromInstruction_4(Insn, 6, 2);
4692 if (fieldFromInstruction_4(Insn, 5, 1))
4696 if (fieldFromInstruction_4(Insn, 4, 2))
4698 index = fieldFromInstruction_4(Insn, 7, 1);
4699 if (fieldFromInstruction_4(Insn, 6, 1))
4705 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4708 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4713 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
4719 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4735 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4736 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4737 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4738 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4739 size = fieldFromInstruction_4(Insn, 10, 2);
4745 if (fieldFromInstruction_4(Insn, 4, 1))
4747 index = fieldFromInstruction_4(Insn, 5, 3);
4750 if (fieldFromInstruction_4(Insn, 4, 1))
4752 index = fieldFromInstruction_4(Insn, 6, 2);
4753 if (fieldFromInstruction_4(Insn, 5, 1))
4757 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4763 align = 4 << fieldFromInstruction_4(Insn, 4, 2);
break;
4766 index = fieldFromInstruction_4(Insn, 7, 1);
4767 if (fieldFromInstruction_4(Insn, 6, 1))
4772 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4782 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4785 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4790 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
4796 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4814 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4815 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4816 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4817 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4818 size = fieldFromInstruction_4(Insn, 10, 2);
4824 if (fieldFromInstruction_4(Insn, 4, 1))
4826 index = fieldFromInstruction_4(Insn, 5, 3);
4829 if (fieldFromInstruction_4(Insn, 4, 1))
4831 index = fieldFromInstruction_4(Insn, 6, 2);
4832 if (fieldFromInstruction_4(Insn, 5, 1))
4836 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4842 align = 4 << fieldFromInstruction_4(Insn, 4, 2);
break;
4845 index = fieldFromInstruction_4(Insn, 7, 1);
4846 if (fieldFromInstruction_4(Insn, 6, 1))
4852 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4855 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4860 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rm,
Address, Decoder)))
4866 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Rd,
Address, Decoder)))
4883 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4884 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
4885 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
4886 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4887 Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
4889 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4892 if (!
Check(&
S, DecodeSPRRegisterClass(Inst, Rm ,
Address, Decoder)))
4894 if (!
Check(&
S, DecodeSPRRegisterClass(Inst, Rm+1,
Address, Decoder)))
4896 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt ,
Address, Decoder)))
4898 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt2 ,
Address, Decoder)))
4900 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4910 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4911 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
4912 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
4913 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4914 Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
4916 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4919 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt ,
Address, Decoder)))
4921 if (!
Check(&
S, DecodeGPRRegisterClass(Inst, Rt2 ,
Address, Decoder)))
4923 if (!
Check(&
S, DecodeSPRRegisterClass(Inst, Rm ,
Address, Decoder)))
4925 if (!
Check(&
S, DecodeSPRRegisterClass(Inst, Rm+1,
Address, Decoder)))
4927 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
4937 unsigned pred = fieldFromInstruction_4(Insn, 4, 4);
4938 unsigned mask = fieldFromInstruction_4(Insn, 0, 4);
4958 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4959 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
4960 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4961 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
4962 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
4963 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
4964 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
4965 bool writeback = (
W == 1) | (
P == 0);
4967 addr |= (U << 8) | (Rn << 9);
4969 if (writeback && (Rn == Rt || Rn == Rt2))
4975 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rt,
Address, Decoder)))
4978 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rt2,
Address, Decoder)))
4981 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rn,
Address, Decoder)))
4995 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4996 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
4997 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4998 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
4999 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
5000 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
5001 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
5002 bool writeback = (
W == 1) | (
P == 0);
5004 addr |= (U << 8) | (Rn << 9);
5006 if (writeback && (Rn == Rt || Rn == Rt2))
5010 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rn,
Address, Decoder)))
5013 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rt,
Address, Decoder)))
5016 if (!
Check(&
S, DecoderGPRRegisterClass(Inst, Rt2,
Address, Decoder)))
5029 unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
5030 unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
5033 Val = fieldFromInstruction_4(Insn, 0, 8);
5034 Val |= fieldFromInstruction_4(Insn, 12, 3) << 8;
5035 Val |= fieldFromInstruction_4(Insn, 26, 1) << 11;
5060 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5061 unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4);
5062 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5063 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5066 return DecodeCPSInstruction(Inst, Insn,
Address, Decoder);
5070 if (Rt == Rn || Rn == Rt2)
5073 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rt,
Address, Decoder)))
5075 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rt2,
Address, Decoder)))
5077 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rn,
Address, Decoder)))
5079 if (!
Check(&
S, DecodePredicateOperand(Inst, pred,
Address, Decoder)))
5089 unsigned Vm, imm, cmode,
op;
5090 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
5091 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
5092 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
5093 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
5094 imm = fieldFromInstruction_4(Insn, 16, 6);
5095 cmode = fieldFromInstruction_4(Insn, 8, 4);
5096 op = fieldFromInstruction_4(Insn, 5, 1);
5099 if (!(imm & 0x38) && cmode == 0xF) {
5102 return DecodeNEONModImmInstruction(Inst, Insn,
Address, Decoder);
5107 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Vd,
Address, Decoder)))
5109 if (!
Check(&
S, DecodeDPRRegisterClass(Inst, Vm,
Address, Decoder)))
5120 unsigned Vm, imm, cmode,
op;
5121 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
5122 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
5123 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
5124 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
5125 imm = fieldFromInstruction_4(Insn, 16, 6);
5126 cmode = fieldFromInstruction_4(Insn, 8, 4);
5127 op = fieldFromInstruction_4(Insn, 5, 1);
5130 if (!(imm & 0x38) && cmode == 0xF) {
5133 return DecodeNEONModImmInstruction(Inst, Insn,
Address, Decoder);
5138 if (!
Check(&
S, DecodeQPRRegisterClass(Inst, Vd,
Address, Decoder)))
5140 if (!
Check(&
S, DecodeQPRRegisterClass(Inst, Vm,
Address, Decoder)))
5152 unsigned Rn = fieldFromInstruction_4(Val, 16, 4);
5153 unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
5154 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
5155 Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4);
5156 Cond = fieldFromInstruction_4(Val, 28, 4);
5158 if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt)
5161 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rt,
Address, Decoder)))
5163 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rn,
Address, Decoder)))
5165 if (!
Check(&
S, DecodeAddrMode7Operand(Inst, Rn,
Address, Decoder)))
5167 if (!
Check(&
S, DecodePostIdxReg(Inst, Rm,
Address, Decoder)))
5169 if (!
Check(&
S, DecodePredicateOperand(Inst, Cond,
Address, Decoder)))
5181 unsigned CRm = fieldFromInstruction_4(Val, 0, 4);
5182 unsigned opc1 = fieldFromInstruction_4(Val, 4, 4);
5183 unsigned cop = fieldFromInstruction_4(Val, 8, 4);
5184 unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
5185 unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4);
5187 if ((cop & ~0x1) == 0xa)
5195 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rt,
Address, Decoder)))
5197 if (!
Check(&
S, DecodeGPRnopcRegisterClass(Inst, Rt2,
Address, Decoder)))