135 if (++count > 200000)
140 while (greset.b.ahbidle == 0);
143 greset.b.csftrst = 1;
148 if (++count > 200000)
153 while (greset.b.csftrst == 1);
176 uint32_t count32b= 0 ,
i= 0;
179 count32b = (len + 3) / 4;
181 for (
i = 0;
i < count32b;
i++)
203 uint32_t count32b = (len + 3) / 4;
207 for( i = 0; i < count32b; i++)
212 return ((
void *)dest);
225 uint32_t
i , baseAddress = 0;
244 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED 248 #ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT 260 #ifdef USB_OTG_ULPI_PHY_ENABLED 263 #ifdef USB_OTG_EMBEDDED_PHY_ENABLED 268 #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED 272 #ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED 276 #ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT 299 (i * USB_OTG_EP_REG_OFFSET));
335 #if defined (STM32F446xx) || defined (STM32F469_479xx) 358 #ifdef USB_OTG_INTERNAL_VBUS_ENABLED 361 #ifdef USB_OTG_EXTERNAL_VBUS_ENABLED 425 #if defined (STM32F446xx) || defined (STM32F469_479xx) 488 greset.b.txfflsh = 1;
489 greset.b.txfnum = num;
494 if (++count > 200000)
499 while (greset.b.txfflsh == 1);
518 greset.b.rxfflsh = 1;
523 if (++count > 200000)
528 while (greset.b.rxfflsh == 1);
642 USB_OTG_OTGCTL_TypeDef gotgctl;
647 nptxfifosize.
d32 = 0;
670 USB_OTG_ResetPort(pdev);
678 #ifdef USB_OTG_FS_CORE 684 nptxfifosize.
b.
depth = TXH_NP_FS_FIFOSIZ;
688 ptxfifosize.
b.
depth = TXH_P_FS_FIFOSIZ;
692 #ifdef USB_OTG_HS_CORE 698 nptxfifosize.
b.
depth = TXH_NP_HS_FIFOSIZ;
701 ptxfifosize.
b.
startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ;
702 ptxfifosize.
b.
depth = TXH_P_HS_FIFOSIZ;
709 gotgctl.b.hstsethnpen = 1;
725 USB_OTG_DriveVbus(pdev, 1);
728 USB_OTG_EnableHostInt(pdev);
759 hprt0.
d32 = USB_OTG_ReadHPRT0(pdev);
760 if ((hprt0.
b.
prtpwr == 0 ) && (state == 1 ))
765 if ((hprt0.
b.
prtpwr == 1 ) && (state == 0 ))
869 hprt0.
d32 = USB_OTG_ReadHPRT0(pdev);
889 uint32_t intr_enable = 0;
901 hcint.
d32 = 0xFFFFFFFF;
912 switch (pdev->host.hc[hc_num].ep_type)
921 if (pdev->host.hc[hc_num].ep_is_in)
928 if (pdev->host.hc[hc_num].do_ping)
942 if (pdev->host.hc[hc_num].ep_is_in)
953 if (pdev->host.hc[hc_num].ep_is_in)
966 intr_enable = (1 << hc_num);
975 hcchar.
b.
devaddr = pdev->host.hc[hc_num].dev_addr;
976 hcchar.
b.
epnum = pdev->host.hc[hc_num].ep_num;
977 hcchar.
b.
epdir = pdev->host.hc[hc_num].ep_is_in;
979 hcchar.
b.
eptype = pdev->host.hc[hc_num].ep_type;
980 hcchar.
b.
mps = pdev->host.hc[hc_num].max_packet;
1004 uint16_t len_words = 0;
1006 uint16_t num_packets;
1007 uint16_t max_hc_pkt_count;
1009 max_hc_pkt_count = 256;
1015 if (pdev->host.hc[hc_num].xfer_len > 0)
1017 num_packets = (pdev->host.hc[hc_num].xfer_len + \
1018 pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet;
1020 if (num_packets > max_hc_pkt_count)
1022 num_packets = max_hc_pkt_count;
1023 pdev->host.hc[hc_num].xfer_len = num_packets * \
1024 pdev->host.hc[hc_num].max_packet;
1031 if (pdev->host.hc[hc_num].ep_is_in)
1033 pdev->host.hc[hc_num].xfer_len = num_packets * \
1034 pdev->host.hc[hc_num].max_packet;
1037 hctsiz.
b.
xfersize = pdev->host.hc[hc_num].xfer_len;
1038 hctsiz.
b.
pktcnt = num_packets;
1039 hctsiz.
b.
pid = pdev->host.hc[hc_num].data_pid;
1049 hcchar.
b.
oddfrm = USB_OTG_IsEvenFrame(pdev);
1058 if((pdev->host.hc[hc_num].ep_is_in == 0) &&
1059 (pdev->host.hc[hc_num].xfer_len > 0))
1061 switch(pdev->host.hc[hc_num].ep_type)
1068 len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
1083 len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
1099 pdev->host.hc[hc_num].xfer_buff ,
1100 hc_num, pdev->host.hc[hc_num].xfer_len);
1201 #ifdef USE_DEVICE_MODE 1239 nptxfifosize.
d32 = 0;
1250 #ifdef USB_OTG_FS_CORE 1284 #ifdef USB_OTG_HS_CORE 1303 nptxfifosize.
b.
depth = TX0_FIFO_HS_SIZE;
1310 txfifosize.
b.
depth = TX1_FIFO_HS_SIZE;
1316 txfifosize.
b.
depth = TX2_FIFO_HS_SIZE;
1322 txfifosize.
b.
depth = TX3_FIFO_HS_SIZE;
1327 txfifosize.
b.
depth = TX4_FIFO_HS_SIZE;
1333 txfifosize.
b.
depth = TX5_FIFO_HS_SIZE;
1395 USB_OTG_EnableDevInt(pdev);
1434 #ifdef VBUS_SENSING_ENABLED 1536 daintmsk.
ep.
in = 1 << ep->
num;
1556 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED 1586 daintmsk.
ep.
in = 1 << ep->
num;
1597 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED 1621 uint32_t fifoemptymsk = 0;
1664 fifoemptymsk = 1 << ep->
num;
1675 if (((dsts.
b.
soffn)&0x1) == 0)
1754 uint32_t fifoemptymsk = 0;
1804 fifoemptymsk |= 1 << ep->
num;
1853 __IO uint32_t *depctl_addr;
1889 __IO uint32_t *depctl_addr;
1923 return ((v & 0xffff0000) >> 16);
1952 return (v & 0xffff);
1974 (uint32_t)&pdev->dev.setup_packet);
1979 doepctl.
d32 = 0x80008000;
1996 if (pdev->dev.DevRemoteWakeup)
2056 pdev->dev.device_status = 1;
2084 __IO uint32_t *depctl_addr;
2085 uint32_t Status = 0;
2097 else if (depctl.
b.
naksts == 1)
2114 else if (depctl.
b.
naksts == 1)
2138 __IO uint32_t *depctl_addr;
2150 USB_OTG_EPSetStall(pdev, ep);
return;
2161 USB_OTG_EPClearStall(pdev, ep);
2195 USB_OTG_EPClearStall(pdev, ep);
static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_EnableCommonInt Initializes the commmon interrupts, used in both device and modes...
USB_OTG_STS USB_OTG_FlushTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t num)
USB_OTG_FlushTxFifo : Flush a Tx FIFO.
struct _USB_OTG_DTHRCTL_TypeDef::@79 b
Specific api's relative to the used hardware platform.
uint32_t disablevbussensing
struct _USB_OTG_HPTXSTS_TypeDef::@86 b
USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_EnableGlobalInt Enables the controller's Global Int in the AHB Config reg.
#define USB_OTG_DATA_FIFO_OFFSET
struct _USB_OTG_HCFG_TypeDef::@83 b
USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
USB_OTG_SelectCore Initialize core registers address.
struct _USB_OTG_HCINTMSK_TypeDef::@95 b
#define USB_OTG_PCGCCTL_OFFSET
#define USB_OTG_FS_BASE_ADDR
#define DCFG_FRAME_INTERVAL_80
struct _USB_OTG_GINTMSK_TypeDef::@64 b
#define USB_OTG_EP_RX_VALID
#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL
#define USB_OTG_EP_RX_NAK
__IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS]
#define USB_OTG_EP_RX_STALL
struct _USB_OTG_FSIZ_TypeDef::@68 b
#define USB_OTG_EP_REG_OFFSET
USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP.
uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_IsHostMode : Check if it is host mode.
#define USB_OTG_HOST_PORT_REGS_OFFSET
uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_IsDeviceMode : Check if it is device mode.
void USB_OTG_BSP_uDelay(const uint32_t usec)
USB_OTG_BSP_uDelay This function provides delay time in micro sec.
USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_DisableGlobalInt Enables the controller's Global Int in the AHB Config reg.
#define DSTS_ENUMSPD_LS_PHY_6MHZ
struct _USB_OTG_DEP0XFRSIZ_TypeDef::@82 b
#define USB_OTG_SPEED_FULL
#define DSTS_ENUMSPD_FS_PHY_48MHZ
static volatile uint8_t * status
#define USB_OTG_DEV_OUT_EP_REG_OFFSET
USB_OTG_INEPREGS * INEP_REGS[USB_OTG_MAX_TX_FIFOS]
USB_OTG_OUTEPREGS * OUTEP_REGS[USB_OTG_MAX_TX_FIFOS]
#define USB_OTG_CHAN_REGS_OFFSET
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ
#define USB_OTG_EP_TX_STALL
#define USB_OTG_CORE_GLOBAL_REGS_OFFSET
#define USB_OTG_DATA_FIFO_SIZE
__IO uint32_t DIEPTXF0_HNPTXFSIZ
#define USB_OTG_HOST_GLOBAL_REG_OFFSET
struct _USB_OTG_HPRT0_TypeDef::@88 b
#define HPRT0_PRTSPD_LOW_SPEED
#define USB_OTG_DEV_GLOBAL_REG_OFFSET
#define USB_OTG_FS_MAX_PACKET_SIZE
#define USB_OTG_WRITE_REG32(reg, value)
#define USB_OTG_EP_RX_DIS
static volatile uint8_t addr
struct _USB_OTG_HCTSIZn_TypeDef::@94 b
struct _USB_OTG_GAHBCFG_TypeDef::@61 b
uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_ReadCoreItr : returns the Core Interrupt register.
#define USB_OTG_READ_REG32(reg)
void USB_OTG_BSP_mDelay(const uint32_t msec)
USB_OTG_BSP_mDelay This function provides delay time in milli sec.
struct _USB_OTG_GUSBCFG_TypeDef::@62 b
#define USB_OTG_EMBEDDED_PHY
#define USB_OTG_SPEED_PARAM_HIGH
USB_OTG_STS USB_OTG_FlushRxFifo(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_FlushRxFifo : Flush a Rx FIFO.
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ
#define USB_OTG_EP_TX_DIS
#define USB_OTG_HS_BASE_ADDR
USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev, uint8_t mode)
USB_OTG_SetCurrentMode : Set ID line.
struct _USB_OTG_DAINT_TypeDef::@78 ep
#define USB_OTG_EP_TX_NAK
static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_CoreReset : Soft reset of the core.
__IO uint32_t * DFIFO[USB_OTG_MAX_TX_FIFOS]
Header of the Core Layer.
struct _USB_OTG_GCCFG_TypeDef::@72 b
struct _USB_OTG_HNPTXSTS_TypeDef::@69 b
#define USB_OTG_EP_TX_VALID
uint32_t term_sel_dl_pulse
struct _USB_OTG_DEPCTL_TypeDef::@80 b
struct _USB_OTG_PCGCCTL_TypeDef::@96 b
#define USB_OTG_HOST_CHAN_REGS_OFFSET
#define USB_OTG_SPEED_PARAM_FULL
#define USB_OTG_DEV_IN_EP_REG_OFFSET
void * USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, uint8_t *dest, uint16_t len)
USB_OTG_ReadPacket : Reads a packet from the Rx FIFO.
void USB_OTG_BSP_ConfigVBUS(uint32_t speed)
USB_OTG_BSP_ConfigVBUS Configures the IO for the Vbus and OverCurrent.
struct _USB_OTG_DIEPINTn_TypeDef::@76 b
uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_GetMode : Get current mode.
struct _USB_OTG_DEPXFRSIZ_TypeDef::@81 b
struct _USB_OTG_DSTS_TypeDef::@75 b
uint32_t ulpi_ext_vbus_drv
USB_OTG_HC_REGS * HC_REGS[USB_OTG_MAX_TX_FIFOS]
USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or ho...
#define USB_OTG_MODIFY_REG32(reg, clear_mask, set_mask)
struct _USB_OTG_DCTL_TypeDef::@74 b
struct _USB_OTG_DCFG_TypeDef::@73 b
struct _USB_OTG_HCCHAR_TypeDef::@91 b
void USB_OTG_BSP_DriveVBUS(uint32_t speed, uint8_t state)
BSP_Drive_VBUS Drives the Vbus signal through IO.
uint32_t USB_OTG_ReadOtgItr(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register.