Structure type to access the Trace Port Interface Register (TPI). More...
#include <core_cm3.h>
Public Attributes | |
| __IO uint32_t | ACPR |
| __IO uint32_t | CLAIMCLR |
| __IO uint32_t | CLAIMSET |
| __IO uint32_t | CSPSR |
| __I uint32_t | DEVID |
| __I uint32_t | DEVTYPE |
| __IO uint32_t | FFCR |
| __I uint32_t | FFSR |
| __I uint32_t | FIFO0 |
| __I uint32_t | FIFO1 |
| __I uint32_t | FSCR |
| __I uint32_t | ITATBCTR0 |
| __I uint32_t | ITATBCTR2 |
| __IO uint32_t | ITCTRL |
| uint32_t | RESERVED0 [2] |
| uint32_t | RESERVED1 [55] |
| uint32_t | RESERVED2 [131] |
| uint32_t | RESERVED3 [759] |
| uint32_t | RESERVED4 [1] |
| uint32_t | RESERVED5 [39] |
| uint32_t | RESERVED7 [8] |
| __IO uint32_t | SPPR |
| __IO uint32_t | SSPSR |
| __I uint32_t | TRIGGER |
Structure type to access the Trace Port Interface Register (TPI).
Definition at line 906 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __IO uint32_t TPI_Type::ACPR |
Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register
Definition at line 911 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __IO uint32_t TPI_Type::CLAIMCLR |
Offset: 0xFA4 (R/W) Claim tag clear
Definition at line 928 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __IO uint32_t TPI_Type::CLAIMSET |
Offset: 0xFA0 (R/W) Claim tag set
Definition at line 927 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __IO uint32_t TPI_Type::CSPSR |
Offset: 0x004 (R/W) Current Parallel Port Size Register
Definition at line 909 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::DEVID |
Offset: 0xFC8 (R/ ) TPIU_DEVID
Definition at line 930 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::DEVTYPE |
Offset: 0xFCC (R/ ) TPIU_DEVTYPE
Definition at line 931 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __IO uint32_t TPI_Type::FFCR |
Offset: 0x304 (R/W) Formatter and Flush Control Register
Definition at line 916 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::FFSR |
Offset: 0x300 (R/ ) Formatter and Flush Status Register
Definition at line 915 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::FIFO0 |
Offset: 0xEEC (R/ ) Integration ETM Data
Definition at line 920 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::FIFO1 |
Offset: 0xEFC (R/ ) Integration ITM Data
Definition at line 924 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::FSCR |
Offset: 0x308 (R/ ) Formatter Synchronization Counter Register
Definition at line 917 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::ITATBCTR0 |
Offset: 0xEF8 (R/ ) ITATBCTR0
Definition at line 923 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::ITATBCTR2 |
Offset: 0xEF0 (R/ ) ITATBCTR2
Definition at line 921 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __IO uint32_t TPI_Type::ITCTRL |
Offset: 0xF00 (R/W) Integration Mode Control
Definition at line 925 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| uint32_t TPI_Type::RESERVED0 |
Definition at line 910 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| uint32_t TPI_Type::RESERVED1 |
Definition at line 912 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| uint32_t TPI_Type::RESERVED2 |
Definition at line 914 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| uint32_t TPI_Type::RESERVED3 |
Definition at line 918 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| uint32_t TPI_Type::RESERVED4 |
Definition at line 922 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| uint32_t TPI_Type::RESERVED5 |
Definition at line 926 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| uint32_t TPI_Type::RESERVED7 |
Definition at line 929 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __IO uint32_t TPI_Type::SPPR |
Offset: 0x0F0 (R/W) Selected Pin Protocol Register
Definition at line 913 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __IO uint32_t TPI_Type::SSPSR |
Offset: 0x000 (R/ ) Supported Parallel Port Size Register
Definition at line 908 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| __I uint32_t TPI_Type::TRIGGER |
Offset: 0xEE8 (R/ ) TRIGGER
Definition at line 919 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.