stm32h7xx_hal_i2s.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_I2S_H
22 #define STM32H7xx_HAL_I2S_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Mode;
52  uint32_t Standard;
55  uint32_t DataFormat;
58  uint32_t MCLKOutput;
61  uint32_t AudioFreq;
64  uint32_t CPOL;
67  uint32_t FirstBit;
70  uint32_t WSInversion;
73  uint32_t Data24BitAlignment;
76  uint32_t MasterKeepIOState;
79 } I2S_InitTypeDef;
80 
84 typedef enum
85 {
86  HAL_I2S_STATE_RESET = 0x00UL,
87  HAL_I2S_STATE_READY = 0x01UL,
88  HAL_I2S_STATE_BUSY = 0x02UL,
89  HAL_I2S_STATE_BUSY_TX = 0x03UL,
90  HAL_I2S_STATE_BUSY_RX = 0x04UL,
91  HAL_I2S_STATE_BUSY_TX_RX = 0x05UL,
92  HAL_I2S_STATE_TIMEOUT = 0x06UL,
93  HAL_I2S_STATE_ERROR = 0x07UL
94 } HAL_I2S_StateTypeDef;
95 
99 typedef struct __I2S_HandleTypeDef
100 {
101  SPI_TypeDef *Instance;
103  I2S_InitTypeDef Init;
105  uint16_t *pTxBuffPtr;
107  __IO uint16_t TxXferSize;
109  __IO uint16_t TxXferCount;
111  uint16_t *pRxBuffPtr;
113  __IO uint16_t RxXferSize;
115  __IO uint16_t RxXferCount;
122  void (*RxISR)(struct __I2S_HandleTypeDef *hi2s);
124  void (*TxISR)(struct __I2S_HandleTypeDef *hi2s);
126  DMA_HandleTypeDef *hdmatx;
128  DMA_HandleTypeDef *hdmarx;
130  __IO HAL_LockTypeDef Lock;
132  __IO HAL_I2S_StateTypeDef State;
134  __IO uint32_t ErrorCode;
137 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
138  void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
139  void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
140  void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
141  void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
142  void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
143  void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
144  void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);
145  void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);
146  void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);
148 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
149 } I2S_HandleTypeDef;
150 
151 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
152 
156 typedef enum
157 {
158  HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL,
159  HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL,
160  HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02UL,
161  HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL,
162  HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL,
163  HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL,
164  HAL_I2S_ERROR_CB_ID = 0x06UL,
165  HAL_I2S_MSPINIT_CB_ID = 0x07UL,
166  HAL_I2S_MSPDEINIT_CB_ID = 0x08UL
168 } HAL_I2S_CallbackIDTypeDef;
169 
173 typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s);
175 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
176 
180 /* Exported constants --------------------------------------------------------*/
187 #define HAL_I2S_ERROR_NONE (0x00000000UL)
188 #define HAL_I2S_ERROR_TIMEOUT (0x00000001UL)
189 #define HAL_I2S_ERROR_OVR (0x00000002UL)
190 #define HAL_I2S_ERROR_UDR (0x00000004UL)
191 #define HAL_I2S_ERROR_DMA (0x00000008UL)
192 #define HAL_I2S_ERROR_PRESCALER (0x00000010UL)
193 #define HAL_I2S_ERROR_FRE (0x00000020UL)
194 #define HAL_I2S_ERROR_NO_OGT (0x00000040UL)
195 #define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL)
196 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
197 #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL)
198 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
199 
206 #define I2S_MODE_SLAVE_TX (0x00000000UL)
207 #define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
208 #define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
209 #define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
210 #define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
211 #define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
212 
219 #define I2S_STANDARD_PHILIPS (0x00000000UL)
220 #define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
221 #define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
222 #define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
223 #define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
224 
231 #define I2S_DATAFORMAT_16B (0x00000000UL)
232 #define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
233 #define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
234 #define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)
235 
242 #define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
243 #define I2S_MCLKOUTPUT_DISABLE (0x00000000UL)
244 
251 #define I2S_AUDIOFREQ_192K (192000UL)
252 #define I2S_AUDIOFREQ_96K (96000UL)
253 #define I2S_AUDIOFREQ_48K (48000UL)
254 #define I2S_AUDIOFREQ_44K (44100UL)
255 #define I2S_AUDIOFREQ_32K (32000UL)
256 #define I2S_AUDIOFREQ_22K (22050UL)
257 #define I2S_AUDIOFREQ_16K (16000UL)
258 #define I2S_AUDIOFREQ_11K (11025UL)
259 #define I2S_AUDIOFREQ_8K (8000UL)
260 #define I2S_AUDIOFREQ_DEFAULT (2UL)
261 
268 #define I2S_CPOL_LOW (0x00000000UL)
269 #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
270 
277 #define I2S_FIRSTBIT_MSB (0x00000000UL)
278 #define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
279 
286 #define I2S_WS_INVERSION_DISABLE (0x00000000UL)
287 #define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
288 
295 #define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
296 #define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
297 
304 #define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
305 #define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
306 
313 #define I2S_IT_RXP SPI_IER_RXPIE
314 #define I2S_IT_TXP SPI_IER_TXPIE
315 #define I2S_IT_DXP SPI_IER_DXPIE
316 #define I2S_IT_UDR SPI_IER_UDRIE
317 #define I2S_IT_OVR SPI_IER_OVRIE
318 #define I2S_IT_FRE SPI_IER_TIFREIE
319 #define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
320 
327 #define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
328 #define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
329 #define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
330 #define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
331 #define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
332 #define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
333 
334 #define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
335 
343 /* Exported macros -----------------------------------------------------------*/
352 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
353 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
354  (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
355  (__HANDLE__)->MspInitCallback = NULL; \
356  (__HANDLE__)->MspDeInitCallback = NULL; \
357  } while(0)
358 #else
359 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
360 #endif
361 
366 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
367 
372 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
373 
387 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
388 
402 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
403 
418 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
419 
432 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
433 
438 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
439 
444 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
445 
450 #define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
451 
456 /* Exported functions --------------------------------------------------------*/
464 /* Initialization/de-initialization functions ********************************/
465 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
466 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
467 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
468 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
469 
470 /* Callbacks Register/UnRegister functions ***********************************/
471 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
472 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
473 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
474 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
475 
482 /* I/O operation functions ***************************************************/
483 /* Blocking mode: Polling */
484 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
485 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
486 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
487  uint16_t Size, uint32_t Timeout);
488 
489 /* Non-Blocking mode: Interrupt */
490 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
491 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
492 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
493  uint16_t Size);
494 
495 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
496 
497 /* Non-Blocking mode: DMA */
498 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
499 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
500 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
501  uint16_t Size);
502 
503 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
504 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
505 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
506 
507 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
508 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
509 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
510 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
511 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
512 void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
513 void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
514 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
522 /* Peripheral Control and State functions ************************************/
523 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
524 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
533 /* Private types -------------------------------------------------------------*/
534 /* Private variables ---------------------------------------------------------*/
535 /* Private constants ---------------------------------------------------------*/
544 /* Private macros ------------------------------------------------------------*/
560 #define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
561 
574 #define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
575 
581 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
582  ((__MODE__) == I2S_MODE_SLAVE_RX) || \
583  ((__MODE__) == I2S_MODE_MASTER_TX) || \
584  ((__MODE__) == I2S_MODE_MASTER_RX) || \
585  ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \
586  ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
587 
588 #define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \
589  ((__MODE__) == I2S_MODE_MASTER_RX) || \
590  ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
591 
592 #define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
593  ((__MODE__) == I2S_MODE_SLAVE_RX) || \
594  ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
595 
596 #define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \
597  ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
598 
599 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
600  ((__STANDARD__) == I2S_STANDARD_MSB) || \
601  ((__STANDARD__) == I2S_STANDARD_LSB) || \
602  ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
603  ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
604 
605 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
606  ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
607  ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
608  ((__FORMAT__) == I2S_DATAFORMAT_32B))
609 
610 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
611  ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
612 
613 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
614  ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
615  ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
616 
617 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
618  ((__CPOL__) == I2S_CPOL_HIGH))
619 
620 #define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \
621  ((__BIT__) == I2S_FIRSTBIT_LSB))
622 
623 #define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \
624  ((__WSINV__) == I2S_WS_INVERSION_ENABLE))
625 
626 #define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
627  ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
628 
629 #define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
630  ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
631 
632 
645 #ifdef __cplusplus
646 }
647 #endif
648 
649 #endif /* STM32H7xx_HAL_I2S_H */
650 
651 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_I2S_MspDeInit
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f407xx.h:711
HAL_I2S_TxHalfCpltCallback
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
Tx Half Transfer completed callbacks.
Definition: stm32f4_discovery_audio.c:469
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
I2S_InitTypeDef::WSInversion
uint32_t WSInversion
Definition: stm32h7xx_hal_i2s.h:70
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
I2S_InitTypeDef::FirstBit
uint32_t FirstBit
Definition: stm32h7xx_hal_i2s.h:67
I2S_InitTypeDef::MasterKeepIOState
uint32_t MasterKeepIOState
Definition: stm32h7xx_hal_i2s.h:76
HAL_I2S_STATE_BUSY_TX_RX
@ HAL_I2S_STATE_BUSY_TX_RX
Definition: stm32h7xx_hal_i2s.h:91
HAL_I2S_Receive
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
HAL_I2S_TxCpltCallback
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
Definition: stm32f4_discovery_audio.c:456
HAL_I2S_STATE_BUSY_TX
@ HAL_I2S_STATE_BUSY_TX
Definition: stm32h7xx_hal_i2s.h:89
__I2S_HandleTypeDef::RxISR
void(* RxISR)(struct __I2S_HandleTypeDef *hi2s)
Definition: stm32h7xx_hal_i2s.h:122
HAL_I2S_RxCpltCallback
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
Definition: stm32f4_discovery_audio.c:844
I2S_HandleTypeDef
I2S handle Structure definition.
Definition: stm32f7xx_hal_i2s.h:91
__I2S_HandleTypeDef::TxXferSize
__IO uint16_t TxXferSize
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:99
HAL_I2S_STATE_BUSY
@ HAL_I2S_STATE_BUSY
Definition: stm32h7xx_hal_i2s.h:88
HAL_I2SEx_TxRxHalfCpltCallback
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
HAL_I2S_STATE_TIMEOUT
@ HAL_I2S_STATE_TIMEOUT
Definition: stm32h7xx_hal_i2s.h:92
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
HAL_I2S_Transmit
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
HAL_I2S_DMAPause
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
HAL_I2S_GetError
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
I2S_HandleTypeDef
struct __I2S_HandleTypeDef I2S_HandleTypeDef
I2S handle Structure definition.
__I2S_HandleTypeDef
I2S handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:91
HAL_I2S_STATE_BUSY_RX
@ HAL_I2S_STATE_BUSY_RX
Definition: stm32h7xx_hal_i2s.h:90
HAL_I2S_Receive_DMA
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
HAL_I2S_RxHalfCpltCallback
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
Rx Half Transfer completed callbacks.
Definition: stm32f4_discovery_audio.c:854
__I2S_HandleTypeDef::Instance
SPI_TypeDef * Instance
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:93
HAL_I2S_DMAResume
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
__I2S_HandleTypeDef::TxXferCount
__IO uint16_t TxXferCount
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:101
HAL_I2S_GetState
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
HAL_I2S_STATE_READY
@ HAL_I2S_STATE_READY
Definition: stm32h7xx_hal_i2s.h:87
__I2S_HandleTypeDef::pTxBuffPtr
uint16_t * pTxBuffPtr
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:97
HAL_I2S_Transmit_IT
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
HAL_I2S_Init
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
__I2S_HandleTypeDef::RxXferCount
__IO uint16_t RxXferCount
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:107
__I2S_HandleTypeDef::RxXferSize
__IO uint16_t RxXferSize
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:105
__I2S_HandleTypeDef::pRxBuffPtr
uint16_t * pRxBuffPtr
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:103
__I2S_HandleTypeDef::Init
I2S_InitTypeDef Init
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:95
HAL_I2S_ErrorCallback
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
I2S error callbacks.
Definition: stm32f4_discovery_audio.c:1110
HAL_I2S_IRQHandler
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
I2S_InitTypeDef::Data24BitAlignment
uint32_t Data24BitAlignment
Definition: stm32h7xx_hal_i2s.h:73
__I2S_HandleTypeDef::Lock
__IO HAL_LockTypeDef Lock
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:119
HAL_I2SEx_TxRxCpltCallback
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
HAL_I2SEx_TransmitReceive
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
__I2S_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:123
__I2S_HandleTypeDef::hdmatx
DMA_HandleTypeDef * hdmatx
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:115
HAL_I2SEx_TransmitReceive_IT
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
HAL_I2S_STATE_ERROR
@ HAL_I2S_STATE_ERROR
Definition: stm32h7xx_hal_i2s.h:93
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_I2S_STATE_RESET
@ HAL_I2S_STATE_RESET
Definition: stm32h7xx_hal_i2s.h:86
__I2S_HandleTypeDef::State
__IO HAL_I2S_StateTypeDef State
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:121
HAL_I2S_DMAStop
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
I2S_InitTypeDef
I2S Init structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:47
HAL_I2S_StateTypeDef
HAL_I2S_StateTypeDef
HAL State structures definition.
Definition: stm32h7xx_hal_i2s.h:84
HAL_I2S_MspInit
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
__I2S_HandleTypeDef::hdmarx
DMA_HandleTypeDef * hdmarx
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h:117
__I2C_HandleTypeDef::Mode
__IO HAL_I2C_ModeTypeDef Mode
Definition: stm32f7xx_hal_i2c.h:213
HAL_I2S_DeInit
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
HAL_I2S_Transmit_DMA
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
HAL_I2S_Receive_IT
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
__I2S_HandleTypeDef::TxISR
void(* TxISR)(struct __I2S_HandleTypeDef *hi2s)
Definition: stm32h7xx_hal_i2s.h:124
HAL_I2SEx_TransmitReceive_DMA
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)

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autogenerated on Fri Apr 1 2022 02:14:54