Serial Peripheral Interface. More...
#include <stm32f407xx.h>
Public Attributes | |
| __IO uint32_t | CFG1 |
| __IO uint32_t | CFG2 |
| __IO uint32_t | CR1 |
| __IO uint32_t | CR2 |
| __IO uint32_t | CRCPOLY |
| __IO uint32_t | CRCPR |
| __IO uint32_t | DR |
| __IO uint32_t | I2SCFGR |
| __IO uint32_t | I2SPR |
| __IO uint32_t | IER |
| __IO uint32_t | IFCR |
| uint32_t | RESERVED0 |
| uint32_t | RESERVED1 [3] |
| uint32_t | RESERVED2 [3] |
| __IO uint32_t | RXCRC |
| __IO uint32_t | RXCRCR |
| __IO uint32_t | RXDR |
| __IO uint32_t | SR |
| __IO uint32_t | TXCRC |
| __IO uint32_t | TXCRCR |
| __IO uint32_t | TXDR |
| __IO uint32_t | UDRDR |
Serial Peripheral Interface.
Definition at line 711 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::CFG1 |
SPI Configuration register 1, Address offset: 0x08
Definition at line 1487 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::CFG2 |
SPI Configuration register 2, Address offset: 0x0C
Definition at line 1488 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::CR1 |
SPI control register 1 (not used in I2S mode), Address offset: 0x00
SPI/I2S Control register 1, Address offset: 0x00
Definition at line 713 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::CR2 |
SPI control register 2, Address offset: 0x04
SPI Control register 2, Address offset: 0x04
Definition at line 714 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::CRCPOLY |
SPI CRC Polynomial register, Address offset: 0x40
Definition at line 1497 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::CRCPR |
SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10
Definition at line 717 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::DR |
SPI data register, Address offset: 0x0C
Definition at line 716 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::I2SCFGR |
SPI_I2S configuration register, Address offset: 0x1C
I2S Configuration register, Address offset: 0x50
Definition at line 720 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::I2SPR |
SPI_I2S prescaler register, Address offset: 0x20
Definition at line 721 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::IER |
SPI/I2S Interrupt Enable register, Address offset: 0x10
Definition at line 1489 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::IFCR |
SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18
Definition at line 1491 of file stm32h735xx.h.
| uint32_t SPI_TypeDef::RESERVED0 |
Reserved, 0x1C
Definition at line 1492 of file stm32h735xx.h.
| uint32_t SPI_TypeDef::RESERVED1 |
Reserved, 0x24-0x2C
Definition at line 1494 of file stm32h735xx.h.
| uint32_t SPI_TypeDef::RESERVED2 |
Reserved, 0x34-0x3C
Definition at line 1496 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::RXCRC |
SPI Receiver CRC register, Address offset: 0x48
Definition at line 1499 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::RXCRCR |
SPI RX CRC register (not used in I2S mode), Address offset: 0x14
Definition at line 718 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::RXDR |
SPI/I2S Receive data register, Address offset: 0x30
Definition at line 1495 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::SR |
SPI status register, Address offset: 0x08
SPI/I2S Status register, Address offset: 0x14
Definition at line 715 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::TXCRC |
SPI Transmitter CRC register, Address offset: 0x44
Definition at line 1498 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::TXCRCR |
SPI TX CRC register (not used in I2S mode), Address offset: 0x18
Definition at line 719 of file stm32f407xx.h.
| __IO uint32_t SPI_TypeDef::TXDR |
SPI/I2S Transmit data register, Address offset: 0x20
Definition at line 1493 of file stm32h735xx.h.
| __IO uint32_t SPI_TypeDef::UDRDR |
SPI Underrun data register, Address offset: 0x4C
Definition at line 1500 of file stm32h735xx.h.