DCMI. More...

#include <stm32f407xx.h>

Public Attributes
__IO uint32_t	CR

__IO uint32_t	CWSIZER

__IO uint32_t	CWSTRTR

__IO uint32_t	DR

__IO uint32_t	ESCR

__IO uint32_t	ESUR

__IO uint32_t	ICR

__IO uint32_t	IER

__IO uint32_t	MISR

__IO uint32_t	RISR

__IO uint32_t	SR

Detailed Description

DCMI.

Definition at line 327 of file stm32f407xx.h.

Member Data Documentation

◆ CR

__IO uint32_t DCMI_TypeDef::CR

DCMI control register 1, Address offset: 0x00

Definition at line 329 of file stm32f407xx.h.

◆ CWSIZER

__IO uint32_t DCMI_TypeDef::CWSIZER

DCMI crop window size, Address offset: 0x24

Definition at line 338 of file stm32f407xx.h.

◆ CWSTRTR

__IO uint32_t DCMI_TypeDef::CWSTRTR

DCMI crop window start, Address offset: 0x20

Definition at line 337 of file stm32f407xx.h.

◆ DR

__IO uint32_t DCMI_TypeDef::DR

DCMI data register, Address offset: 0x28

Definition at line 339 of file stm32f407xx.h.

◆ ESCR

__IO uint32_t DCMI_TypeDef::ESCR

DCMI embedded synchronization code register, Address offset: 0x18

Definition at line 335 of file stm32f407xx.h.

◆ ESUR

__IO uint32_t DCMI_TypeDef::ESUR

DCMI embedded synchronization unmask register, Address offset: 0x1C

Definition at line 336 of file stm32f407xx.h.

◆ ICR

__IO uint32_t DCMI_TypeDef::ICR

DCMI interrupt clear register, Address offset: 0x14

Definition at line 334 of file stm32f407xx.h.

◆ IER

__IO uint32_t DCMI_TypeDef::IER

DCMI interrupt enable register, Address offset: 0x0C

Definition at line 332 of file stm32f407xx.h.

◆ MISR

__IO uint32_t DCMI_TypeDef::MISR

DCMI masked interrupt status register, Address offset: 0x10

Definition at line 333 of file stm32f407xx.h.

◆ RISR

__IO uint32_t DCMI_TypeDef::RISR

DCMI raw interrupt status register, Address offset: 0x08

Definition at line 331 of file stm32f407xx.h.

◆ SR

__IO uint32_t DCMI_TypeDef::SR

DCMI status register, Address offset: 0x04

Definition at line 330 of file stm32f407xx.h.

The documentation for this struct was generated from the following files:

Public Attributes