Flexible Memory Controller Bank3. More...

#include <stm32f469xx.h>

Public Attributes
__IO uint32_t	ECCR

__IO uint32_t	PATT

__IO uint32_t	PCR

__IO uint32_t	PMEM

uint32_t	RESERVED

uint32_t	RESERVED0

__IO uint32_t	SR

Detailed Description

Flexible Memory Controller Bank3.

Definition at line 611 of file stm32f469xx.h.

Member Data Documentation

◆ ECCR

__IO uint32_t FMC_Bank3_TypeDef::ECCR

NAND Flash ECC result registers, Address offset: 0x94

NAND Flash ECC result registers 3, Address offset: 0x94

Definition at line 618 of file stm32f469xx.h.

◆ PATT

__IO uint32_t FMC_Bank3_TypeDef::PATT

NAND Flash Attribute memory space timing register, Address offset: 0x8C

NAND Flash Attribute memory space timing register 3, Address offset: 0x8C

Definition at line 616 of file stm32f469xx.h.

◆ PCR

__IO uint32_t FMC_Bank3_TypeDef::PCR

NAND Flash control register, Address offset: 0x80

NAND Flash control register 3, Address offset: 0x80

Definition at line 613 of file stm32f469xx.h.

◆ PMEM

__IO uint32_t FMC_Bank3_TypeDef::PMEM

NAND Flash Common memory space timing register, Address offset: 0x88

NAND Flash Common memory space timing register 3, Address offset: 0x88

Definition at line 615 of file stm32f469xx.h.

◆ RESERVED

uint32_t FMC_Bank3_TypeDef::RESERVED

Reserved, 0x90

Definition at line 617 of file stm32f469xx.h.

◆ RESERVED0

uint32_t FMC_Bank3_TypeDef::RESERVED0

Reserved, 0x90

Definition at line 603 of file stm32f769xx.h.

◆ SR

__IO uint32_t FMC_Bank3_TypeDef::SR

NAND Flash FIFO status and interrupt register, Address offset: 0x84

NAND Flash FIFO status and interrupt register 3, Address offset: 0x84

Definition at line 614 of file stm32f469xx.h.

The documentation for this struct was generated from the following files:

Public Attributes