utils/cmsis/same70/include/component/uart.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_UART_COMPONENT_
36 #define _SAME70_UART_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t UART_CR;
48  __IO uint32_t UART_MR;
49  __O uint32_t UART_IER;
50  __O uint32_t UART_IDR;
51  __I uint32_t UART_IMR;
52  __I uint32_t UART_SR;
53  __I uint32_t UART_RHR;
54  __O uint32_t UART_THR;
55  __IO uint32_t UART_BRGR;
56  __IO uint32_t UART_CMPR;
57  __I uint32_t Reserved1[47];
58  __IO uint32_t UART_WPMR;
59  __I uint32_t Reserved2[5];
60  __I uint32_t UART_VERSION;
61 } Uart;
62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
63 /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
64 #define UART_CR_RSTRX (0x1u << 2)
65 #define UART_CR_RSTTX (0x1u << 3)
66 #define UART_CR_RXEN (0x1u << 4)
67 #define UART_CR_RXDIS (0x1u << 5)
68 #define UART_CR_TXEN (0x1u << 6)
69 #define UART_CR_TXDIS (0x1u << 7)
70 #define UART_CR_RSTSTA (0x1u << 8)
71 #define UART_CR_REQCLR (0x1u << 12)
72 #define UART_CR_DBGE (0x1u << 15)
73 /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
74 #define UART_MR_FILTER (0x1u << 4)
75 #define UART_MR_FILTER_DISABLED (0x0u << 4)
76 #define UART_MR_FILTER_ENABLED (0x1u << 4)
77 #define UART_MR_PAR_Pos 9
78 #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos)
79 #define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)))
80 #define UART_MR_PAR_EVEN (0x0u << 9)
81 #define UART_MR_PAR_ODD (0x1u << 9)
82 #define UART_MR_PAR_SPACE (0x2u << 9)
83 #define UART_MR_PAR_MARK (0x3u << 9)
84 #define UART_MR_PAR_NO (0x4u << 9)
85 #define UART_MR_BRSRCCK (0x1u << 12)
86 #define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12)
87 #define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12)
88 #define UART_MR_CHMODE_Pos 14
89 #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos)
90 #define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)))
91 #define UART_MR_CHMODE_NORMAL (0x0u << 14)
92 #define UART_MR_CHMODE_AUTOMATIC (0x1u << 14)
93 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14)
94 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14)
95 /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
96 #define UART_IER_RXRDY (0x1u << 0)
97 #define UART_IER_TXRDY (0x1u << 1)
98 #define UART_IER_OVRE (0x1u << 5)
99 #define UART_IER_FRAME (0x1u << 6)
100 #define UART_IER_PARE (0x1u << 7)
101 #define UART_IER_TXEMPTY (0x1u << 9)
102 #define UART_IER_CMP (0x1u << 15)
103 /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
104 #define UART_IDR_RXRDY (0x1u << 0)
105 #define UART_IDR_TXRDY (0x1u << 1)
106 #define UART_IDR_OVRE (0x1u << 5)
107 #define UART_IDR_FRAME (0x1u << 6)
108 #define UART_IDR_PARE (0x1u << 7)
109 #define UART_IDR_TXEMPTY (0x1u << 9)
110 #define UART_IDR_CMP (0x1u << 15)
111 /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
112 #define UART_IMR_RXRDY (0x1u << 0)
113 #define UART_IMR_TXRDY (0x1u << 1)
114 #define UART_IMR_OVRE (0x1u << 5)
115 #define UART_IMR_FRAME (0x1u << 6)
116 #define UART_IMR_PARE (0x1u << 7)
117 #define UART_IMR_TXEMPTY (0x1u << 9)
118 #define UART_IMR_CMP (0x1u << 15)
119 /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
120 #define UART_SR_RXRDY (0x1u << 0)
121 #define UART_SR_TXRDY (0x1u << 1)
122 #define UART_SR_OVRE (0x1u << 5)
123 #define UART_SR_FRAME (0x1u << 6)
124 #define UART_SR_PARE (0x1u << 7)
125 #define UART_SR_TXEMPTY (0x1u << 9)
126 #define UART_SR_CMP (0x1u << 15)
127 #define UART_SR_SWES (0x1u << 21)
128 #define UART_SR_CLKREQ (0x1u << 22)
129 #define UART_SR_WKUPREQ (0x1u << 23)
130 /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
131 #define UART_RHR_RXCHR_Pos 0
132 #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos)
133 /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
134 #define UART_THR_TXCHR_Pos 0
135 #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos)
136 #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
137 /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
138 #define UART_BRGR_CD_Pos 0
139 #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos)
140 #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
141 /* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */
142 #define UART_CMPR_VAL1_Pos 0
143 #define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos)
144 #define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))
145 #define UART_CMPR_CMPMODE (0x1u << 12)
146 #define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12)
147 #define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12)
148 #define UART_CMPR_CMPPAR (0x1u << 14)
149 #define UART_CMPR_VAL2_Pos 16
150 #define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos)
151 #define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))
152 /* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */
153 #define UART_WPMR_WPEN (0x1u << 0)
154 #define UART_WPMR_WPKEY_Pos 8
155 #define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos)
156 #define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)))
157 #define UART_WPMR_WPKEY_PASSWD (0x554152u << 8)
158 /* -------- UART_VERSION : (UART Offset: 0x00FC) Version Register -------- */
159 #define UART_VERSION_VERSION_Pos 0
160 #define UART_VERSION_VERSION_Msk (0xfffu << UART_VERSION_VERSION_Pos)
161 #define UART_VERSION_MFN_Pos 16
162 #define UART_VERSION_MFN_Msk (0x7u << UART_VERSION_MFN_Pos)
165 
166 
167 #endif /* _SAME70_UART_COMPONENT_ */
__IO uint32_t UART_CMPR
(Uart Offset: 0x0024) Comparison Register
#define __IO
Definition: core_cm7.h:266
__IO uint32_t UART_MR
(Uart Offset: 0x0004) Mode Register
#define __O
Definition: core_cm7.h:265
Uart hardware registers.
__O uint32_t UART_THR
(Uart Offset: 0x001C) Transmit Holding Register
__O uint32_t UART_IDR
(Uart Offset: 0x000C) Interrupt Disable Register
__O uint32_t UART_CR
(Uart Offset: 0x0000) Control Register
__IO uint32_t UART_BRGR
(Uart Offset: 0x0020) Baud Rate Generator Register
__I uint32_t UART_RHR
(Uart Offset: 0x0018) Receive Holding Register
__I uint32_t UART_IMR
(Uart Offset: 0x0010) Interrupt Mask Register
__I uint32_t UART_VERSION
(Uart Offset: 0x00FC) Version Register
__I uint32_t UART_SR
(Uart Offset: 0x0014) Status Register
__IO uint32_t UART_WPMR
(Uart Offset: 0x00E4) Write Protection Mode Register
__O uint32_t UART_IER
(Uart Offset: 0x0008) Interrupt Enable Register
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:05