766 __O uint32_t TC_QIER
(Tc Offset: 0xC8) QDEC Interrupt Enable Register
void tc_write_rc(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register C (RC) on the selected channel.
#define UNUSED(v)
Marking v as a unused parameter or value.
uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel)
Read TC Register B (RB) on the specified channel.
uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc)
Read TC QDEC interrupt mask.
void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources)
Disable TC QDEC interrupts.
void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable)
Enable or disable write protection of TC registers.
void tc_stop(Tc *p_tc, uint32_t ul_channel)
Stop the TC clock on the specified channel.
SAM Timer Counter (TC) driver.
void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, uint32_t ul_sources)
Disable TC interrupts on the specified channel.
__IO uint32_t TC_RA
(TcChannel Offset: 0x14) Register A
__I uint32_t TC_CV
(TcChannel Offset: 0x10) Counter Value
uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel)
Read the counter value on the specified channel.
__I uint32_t TC_QIMR
(Tc Offset: 0xD0) QDEC Interrupt Mask Register
__O uint32_t TC_QIDR
(Tc Offset: 0xCC) QDEC Interrupt Disable Register
void tc_write_rb(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register B (RB) on the specified channel.
void tc_start(Tc *p_tc, uint32_t ul_channel)
Start the TC clock on the specified channel.
void tc_sync_trigger(Tc *p_tc)
Asserts a SYNC signal to generate a software trigger on all channels.
#define FREQ_SLOW_CLOCK_EXT
TcChannel hardware registers.
__IO uint32_t TC_SMMR
(TcChannel Offset: 0x8) Stepper Motor Mode Register
void tc_init(Tc *p_tc, uint32_t ul_channel, uint32_t ul_mode)
Configure TC for timer, waveform generation, or capture.
__I uint32_t TC_IMR
(TcChannel Offset: 0x2C) Interrupt Mask Register
__I uint32_t TC_SR
(TcChannel Offset: 0x20) Status Register
uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel)
Read TC Register A (RA) on the specified channel.
__IO uint32_t TC_BMR
(Tc Offset: 0xC4) Block Mode Register
uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel)
Read the TC interrupt mask for the specified channel.
__O uint32_t TC_CCR
(TcChannel Offset: 0x0) Channel Control Register
__IO uint32_t TC_RC
(TcChannel Offset: 0x1C) Register C
#define TC_CCR_CLKDIS
(TC_CCR) Counter Clock Disable Command
uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel)
Get the current status for the specified TC channel.
void tc_write_ra(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register A (RA) on the specified channel.
__I uint32_t TC_QISR
(Tc Offset: 0xD4) QDEC Interrupt Status Register
TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]
(Tc Offset: 0x0) channel = 0 .. 2
#define TC_BCR_SYNC
(TC_BCR) Synchro Command
uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, uint32_t *p_uldiv, uint32_t *p_ultcclks, uint32_t ul_boardmck)
Find the best MCK divisor.
#define TC_WPMR_WPKEY_PASSWD
uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel)
Read TC Register C (RC) on the specified channel.
__IO uint32_t TC_RB
(TcChannel Offset: 0x18) Register B
void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, uint32_t ul_sources)
Enable the TC interrupts on the specified channel.
__O uint32_t TC_IDR
(TcChannel Offset: 0x28) Interrupt Disable Register
__IO uint32_t TC_CMR
(TcChannel Offset: 0x4) Channel Mode Register
void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources)
Enable TC QDEC interrupts.
#define TC_CCR_SWTRG
(TC_CCR) Software Trigger Command
#define TC_WPMR_WPEN
(TC_WPMR) Write Protection Enable
__IO uint32_t TC_WPMR
(Tc Offset: 0xE4) Write Protection Mode Register
__O uint32_t TC_IER
(TcChannel Offset: 0x24) Interrupt Enable Register
uint32_t tc_get_qdec_interrupt_status(Tc *p_tc)
Get current TC QDEC interrupt status.
__O uint32_t TC_BCR
(Tc Offset: 0xC0) Block Control Register
void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode)
Configure the TC Block mode.
#define Assert(expr)
This macro is used to test fatal errors.
#define TC_CCR_CLKEN
(TC_CCR) Counter Clock Enable Command
uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, uint32_t ul_steppermode)
Configure TC for 2-bit Gray Counter for Stepper Motor.