Qspi hardware registers. More...
#include <qspi.h>
Public Attributes | |
__O uint32_t | QSPI_CR |
(Qspi Offset: 0x00) Control Register More... | |
__IO uint32_t | QSPI_IAR |
(Qspi Offset: 0x30) Instruction Address Register More... | |
__IO uint32_t | QSPI_ICR |
(Qspi Offset: 0x34) Instruction Code Register More... | |
__O uint32_t | QSPI_IDR |
(Qspi Offset: 0x18) Interrupt Disable Register More... | |
__O uint32_t | QSPI_IER |
(Qspi Offset: 0x14) Interrupt Enable Register More... | |
__IO uint32_t | QSPI_IFR |
(Qspi Offset: 0x38) Instruction Frame Register More... | |
__I uint32_t | QSPI_IMR |
(Qspi Offset: 0x1C) Interrupt Mask Register More... | |
__IO uint32_t | QSPI_MR |
(Qspi Offset: 0x04) Mode Register More... | |
__I uint32_t | QSPI_RDR |
(Qspi Offset: 0x08) Receive Data Register More... | |
__IO uint32_t | QSPI_SCR |
(Qspi Offset: 0x20) Serial Clock Register More... | |
__O uint32_t | QSPI_SKR |
(Qspi Offset: 0x44) Scrambling Key Register More... | |
__IO uint32_t | QSPI_SMR |
(Qspi Offset: 0x40) Scrambling Mode Register More... | |
__I uint32_t | QSPI_SR |
(Qspi Offset: 0x10) Status Register More... | |
__O uint32_t | QSPI_TDR |
(Qspi Offset: 0x0C) Transmit Data Register More... | |
__I uint32_t | QSPI_VERSION |
(Qspi Offset: 0x00FC) Version Register More... | |
__IO uint32_t | QSPI_WPMR |
(Qspi Offset: 0xE4) Write Protection Mode Register More... | |
__I uint32_t | QSPI_WPSR |
(Qspi Offset: 0xE8) Write Protection Status Register More... | |
__I uint32_t | Reserved1 [3] |
__I uint32_t | Reserved2 [1] |
__I uint32_t | Reserved3 [39] |
__I uint32_t | Reserved4 [4] |
Qspi hardware registers.
Definition at line 46 of file component/qspi.h.
__O uint32_t Qspi::QSPI_CR |
(Qspi Offset: 0x00) Control Register
Definition at line 47 of file component/qspi.h.
__IO uint32_t Qspi::QSPI_IAR |
(Qspi Offset: 0x30) Instruction Address Register
Definition at line 57 of file component/qspi.h.
__IO uint32_t Qspi::QSPI_ICR |
(Qspi Offset: 0x34) Instruction Code Register
Definition at line 58 of file component/qspi.h.
__O uint32_t Qspi::QSPI_IDR |
(Qspi Offset: 0x18) Interrupt Disable Register
Definition at line 53 of file component/qspi.h.
__O uint32_t Qspi::QSPI_IER |
(Qspi Offset: 0x14) Interrupt Enable Register
Definition at line 52 of file component/qspi.h.
__IO uint32_t Qspi::QSPI_IFR |
(Qspi Offset: 0x38) Instruction Frame Register
Definition at line 59 of file component/qspi.h.
__I uint32_t Qspi::QSPI_IMR |
(Qspi Offset: 0x1C) Interrupt Mask Register
Definition at line 54 of file component/qspi.h.
__IO uint32_t Qspi::QSPI_MR |
(Qspi Offset: 0x04) Mode Register
Definition at line 48 of file component/qspi.h.
__I uint32_t Qspi::QSPI_RDR |
(Qspi Offset: 0x08) Receive Data Register
Definition at line 49 of file component/qspi.h.
__IO uint32_t Qspi::QSPI_SCR |
(Qspi Offset: 0x20) Serial Clock Register
Definition at line 55 of file component/qspi.h.
__O uint32_t Qspi::QSPI_SKR |
(Qspi Offset: 0x44) Scrambling Key Register
Definition at line 62 of file component/qspi.h.
__IO uint32_t Qspi::QSPI_SMR |
(Qspi Offset: 0x40) Scrambling Mode Register
Definition at line 61 of file component/qspi.h.
__I uint32_t Qspi::QSPI_SR |
(Qspi Offset: 0x10) Status Register
Definition at line 51 of file component/qspi.h.
__O uint32_t Qspi::QSPI_TDR |
(Qspi Offset: 0x0C) Transmit Data Register
Definition at line 50 of file component/qspi.h.
__I uint32_t Qspi::QSPI_VERSION |
(Qspi Offset: 0x00FC) Version Register
Definition at line 67 of file component/qspi.h.
__IO uint32_t Qspi::QSPI_WPMR |
(Qspi Offset: 0xE4) Write Protection Mode Register
Definition at line 64 of file component/qspi.h.
__I uint32_t Qspi::QSPI_WPSR |
(Qspi Offset: 0xE8) Write Protection Status Register
Definition at line 65 of file component/qspi.h.
__I uint32_t Qspi::Reserved1[3] |
Definition at line 56 of file component/qspi.h.
__I uint32_t Qspi::Reserved2[1] |
Definition at line 60 of file component/qspi.h.
__I uint32_t Qspi::Reserved3[39] |
Definition at line 63 of file component/qspi.h.
__I uint32_t Qspi::Reserved4[4] |
Definition at line 66 of file component/qspi.h.