component/qspi.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_QSPI_COMPONENT_
36 #define _SAME70_QSPI_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t QSPI_CR;
48  __IO uint32_t QSPI_MR;
49  __I uint32_t QSPI_RDR;
50  __O uint32_t QSPI_TDR;
51  __I uint32_t QSPI_SR;
52  __O uint32_t QSPI_IER;
53  __O uint32_t QSPI_IDR;
54  __I uint32_t QSPI_IMR;
55  __IO uint32_t QSPI_SCR;
56  __I uint32_t Reserved1[3];
57  __IO uint32_t QSPI_IAR;
58  __IO uint32_t QSPI_ICR;
59  __IO uint32_t QSPI_IFR;
60  __I uint32_t Reserved2[1];
61  __IO uint32_t QSPI_SMR;
62  __O uint32_t QSPI_SKR;
63  __I uint32_t Reserved3[39];
64  __IO uint32_t QSPI_WPMR;
65  __I uint32_t QSPI_WPSR;
66  __I uint32_t Reserved4[4];
67  __I uint32_t QSPI_VERSION;
68 } Qspi;
69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
70 /* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */
71 #define QSPI_CR_QSPIEN (0x1u << 0)
72 #define QSPI_CR_QSPIDIS (0x1u << 1)
73 #define QSPI_CR_SWRST (0x1u << 7)
74 #define QSPI_CR_LASTXFER (0x1u << 24)
75 /* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */
76 #define QSPI_MR_SMM (0x1u << 0)
77 #define QSPI_MR_SMM_SPI (0x0u << 0)
78 #define QSPI_MR_SMM_MEMORY (0x1u << 0)
79 #define QSPI_MR_LLB (0x1u << 1)
80 #define QSPI_MR_LLB_DISABLED (0x0u << 1)
81 #define QSPI_MR_LLB_ENABLED (0x1u << 1)
82 #define QSPI_MR_WDRBT (0x1u << 2)
83 #define QSPI_MR_WDRBT_DISABLED (0x0u << 2)
84 #define QSPI_MR_WDRBT_ENABLED (0x1u << 2)
85 #define QSPI_MR_CSMODE_Pos 4
86 #define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos)
87 #define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))
88 #define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4)
89 #define QSPI_MR_CSMODE_LASTXFER (0x1u << 4)
90 #define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4)
91 #define QSPI_MR_NBBITS_Pos 8
92 #define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos)
93 #define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))
94 #define QSPI_MR_NBBITS_8_BIT (0x0u << 8)
95 #define QSPI_MR_NBBITS_9_BIT (0x1u << 8)
96 #define QSPI_MR_NBBITS_10_BIT (0x2u << 8)
97 #define QSPI_MR_NBBITS_11_BIT (0x3u << 8)
98 #define QSPI_MR_NBBITS_12_BIT (0x4u << 8)
99 #define QSPI_MR_NBBITS_13_BIT (0x5u << 8)
100 #define QSPI_MR_NBBITS_14_BIT (0x6u << 8)
101 #define QSPI_MR_NBBITS_15_BIT (0x7u << 8)
102 #define QSPI_MR_NBBITS_16_BIT (0x8u << 8)
103 #define QSPI_MR_DLYBCT_Pos 16
104 #define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos)
105 #define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))
106 #define QSPI_MR_DLYCS_Pos 24
107 #define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos)
108 #define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))
109 /* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */
110 #define QSPI_RDR_RD_Pos 0
111 #define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos)
112 /* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */
113 #define QSPI_TDR_TD_Pos 0
114 #define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos)
115 #define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))
116 /* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */
117 #define QSPI_SR_RDRF (0x1u << 0)
118 #define QSPI_SR_TDRE (0x1u << 1)
119 #define QSPI_SR_TXEMPTY (0x1u << 2)
120 #define QSPI_SR_OVRES (0x1u << 3)
121 #define QSPI_SR_CSR (0x1u << 8)
122 #define QSPI_SR_CSS (0x1u << 9)
123 #define QSPI_SR_INSTRE (0x1u << 10)
124 #define QSPI_SR_QSPIENS (0x1u << 24)
125 /* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */
126 #define QSPI_IER_RDRF (0x1u << 0)
127 #define QSPI_IER_TDRE (0x1u << 1)
128 #define QSPI_IER_TXEMPTY (0x1u << 2)
129 #define QSPI_IER_OVRES (0x1u << 3)
130 #define QSPI_IER_CSR (0x1u << 8)
131 #define QSPI_IER_CSS (0x1u << 9)
132 #define QSPI_IER_INSTRE (0x1u << 10)
133 /* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */
134 #define QSPI_IDR_RDRF (0x1u << 0)
135 #define QSPI_IDR_TDRE (0x1u << 1)
136 #define QSPI_IDR_TXEMPTY (0x1u << 2)
137 #define QSPI_IDR_OVRES (0x1u << 3)
138 #define QSPI_IDR_CSR (0x1u << 8)
139 #define QSPI_IDR_CSS (0x1u << 9)
140 #define QSPI_IDR_INSTRE (0x1u << 10)
141 /* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */
142 #define QSPI_IMR_RDRF (0x1u << 0)
143 #define QSPI_IMR_TDRE (0x1u << 1)
144 #define QSPI_IMR_TXEMPTY (0x1u << 2)
145 #define QSPI_IMR_OVRES (0x1u << 3)
146 #define QSPI_IMR_CSR (0x1u << 8)
147 #define QSPI_IMR_CSS (0x1u << 9)
148 #define QSPI_IMR_INSTRE (0x1u << 10)
149 /* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */
150 #define QSPI_SCR_CPOL (0x1u << 0)
151 #define QSPI_SCR_CPHA (0x1u << 1)
152 #define QSPI_SCR_SCBR_Pos 8
153 #define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos)
154 #define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))
155 #define QSPI_SCR_DLYBS_Pos 16
156 #define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos)
157 #define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))
158 /* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */
159 #define QSPI_IAR_ADDR_Pos 0
160 #define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos)
161 #define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))
162 /* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */
163 #define QSPI_ICR_INST_Pos 0
164 #define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos)
165 #define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))
166 #define QSPI_ICR_OPT_Pos 16
167 #define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos)
168 #define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))
169 /* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */
170 #define QSPI_IFR_WIDTH_Pos 0
171 #define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos)
172 #define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))
173 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0)
174 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0)
175 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0)
176 #define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0)
177 #define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0)
178 #define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0)
179 #define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0)
180 #define QSPI_IFR_INSTEN (0x1u << 4)
181 #define QSPI_IFR_ADDREN (0x1u << 5)
182 #define QSPI_IFR_OPTEN (0x1u << 6)
183 #define QSPI_IFR_DATAEN (0x1u << 7)
184 #define QSPI_IFR_OPTL_Pos 8
185 #define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos)
186 #define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))
187 #define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8)
188 #define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8)
189 #define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8)
190 #define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8)
191 #define QSPI_IFR_ADDRL (0x1u << 10)
192 #define QSPI_IFR_ADDRL_24_BIT (0x0u << 10)
193 #define QSPI_IFR_ADDRL_32_BIT (0x1u << 10)
194 #define QSPI_IFR_TFRTYP_Pos 12
195 #define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos)
196 #define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))
197 #define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12)
198 #define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12)
199 #define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12)
200 #define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12)
201 #define QSPI_IFR_CRM (0x1u << 14)
202 #define QSPI_IFR_CRM_DISABLED (0x0u << 14)
203 #define QSPI_IFR_CRM_ENABLED (0x1u << 14)
204 #define QSPI_IFR_NBDUM_Pos 16
205 #define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos)
206 #define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))
207 /* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */
208 #define QSPI_SMR_SCREN (0x1u << 0)
209 #define QSPI_SMR_SCREN_DISABLED (0x0u << 0)
210 #define QSPI_SMR_SCREN_ENABLED (0x1u << 0)
211 #define QSPI_SMR_RVDIS (0x1u << 1)
212 /* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */
213 #define QSPI_SKR_USRK_Pos 0
214 #define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos)
215 #define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))
216 /* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */
217 #define QSPI_WPMR_WPEN (0x1u << 0)
218 #define QSPI_WPMR_WPKEY_Pos 8
219 #define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos)
220 #define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))
221 #define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8)
222 /* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */
223 #define QSPI_WPSR_WPVS (0x1u << 0)
224 #define QSPI_WPSR_WPVSRC_Pos 8
225 #define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos)
226 /* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */
227 #define QSPI_VERSION_VERSION_Pos 0
228 #define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos)
229 #define QSPI_VERSION_MFN_Pos 16
230 #define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos)
233 
234 
235 #endif /* _SAME70_QSPI_COMPONENT_ */
__IO uint32_t QSPI_SMR
(Qspi Offset: 0x40) Scrambling Mode Register
__I uint32_t QSPI_VERSION
(Qspi Offset: 0x00FC) Version Register
__O uint32_t QSPI_CR
(Qspi Offset: 0x00) Control Register
__I uint32_t QSPI_RDR
(Qspi Offset: 0x08) Receive Data Register
#define __IO
Definition: core_cm7.h:266
__IO uint32_t QSPI_WPMR
(Qspi Offset: 0xE4) Write Protection Mode Register
#define __O
Definition: core_cm7.h:265
__I uint32_t QSPI_SR
(Qspi Offset: 0x10) Status Register
__O uint32_t QSPI_IDR
(Qspi Offset: 0x18) Interrupt Disable Register
__IO uint32_t QSPI_ICR
(Qspi Offset: 0x34) Instruction Code Register
__O uint32_t QSPI_TDR
(Qspi Offset: 0x0C) Transmit Data Register
__O uint32_t QSPI_SKR
(Qspi Offset: 0x44) Scrambling Key Register
__I uint32_t QSPI_WPSR
(Qspi Offset: 0xE8) Write Protection Status Register
__IO uint32_t QSPI_IFR
(Qspi Offset: 0x38) Instruction Frame Register
__I uint32_t QSPI_IMR
(Qspi Offset: 0x1C) Interrupt Mask Register
__IO uint32_t QSPI_SCR
(Qspi Offset: 0x20) Serial Clock Register
Qspi hardware registers.
__IO uint32_t QSPI_MR
(Qspi Offset: 0x04) Mode Register
#define __I
Definition: core_cm7.h:263
__IO uint32_t QSPI_IAR
(Qspi Offset: 0x30) Instruction Address Register
__O uint32_t QSPI_IER
(Qspi Offset: 0x14) Interrupt Enable Register


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04