instance/qspi.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_QSPI_INSTANCE_
36 #define _SAME70_QSPI_INSTANCE_
37 
38 /* ========== Register definition for QSPI peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_QSPI_CR (0x4007C000U)
41  #define REG_QSPI_MR (0x4007C004U)
42  #define REG_QSPI_RDR (0x4007C008U)
43  #define REG_QSPI_TDR (0x4007C00CU)
44  #define REG_QSPI_SR (0x4007C010U)
45  #define REG_QSPI_IER (0x4007C014U)
46  #define REG_QSPI_IDR (0x4007C018U)
47  #define REG_QSPI_IMR (0x4007C01CU)
48  #define REG_QSPI_SCR (0x4007C020U)
49  #define REG_QSPI_IAR (0x4007C030U)
50  #define REG_QSPI_ICR (0x4007C034U)
51  #define REG_QSPI_IFR (0x4007C038U)
52  #define REG_QSPI_SMR (0x4007C040U)
53  #define REG_QSPI_SKR (0x4007C044U)
54  #define REG_QSPI_WPMR (0x4007C0E4U)
55  #define REG_QSPI_WPSR (0x4007C0E8U)
56  #define REG_QSPI_VERSION (0x4007C0FCU)
57 #else
58  #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U)
59  #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U)
60  #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U)
61  #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU)
62  #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U)
63  #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U)
64  #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U)
65  #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU)
66  #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U)
67  #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U)
68  #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U)
69  #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U)
70  #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U)
71  #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U)
72  #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U)
73  #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U)
74  #define REG_QSPI_VERSION (*(__I uint32_t*)0x4007C0FCU)
75 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
76 
77 #endif /* _SAME70_QSPI_INSTANCE_ */


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04