drivers/xdmac/xdmac.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef XDMAC_H_INCLUDED
#define XDMAC_H_INCLUDED

#include  <compiler.h>
#include  <status_codes.h>

#ifdef __cplusplus
extern "C" {
#endif

#include "conf_board.h"

#define XDMAC_CHANNEL_HWID_HSMCI       0
#define XDMAC_CHANNEL_HWID_SPI0_TX     1
#define XDMAC_CHANNEL_HWID_SPI0_RX     2
#define XDMAC_CHANNEL_HWID_SPI1_TX     3
#define XDMAC_CHANNEL_HWID_SPI1_RX     4
#define XDMAC_CHANNEL_HWID_QSPI_TX     5
#define XDMAC_CHANNEL_HWID_QSPI_RX     6
#define XDMAC_CHANNEL_HWID_USART0_TX   7
#define XDMAC_CHANNEL_HWID_USART0_RX   8
#define XDMAC_CHANNEL_HWID_USART1_TX   9
#define XDMAC_CHANNEL_HWID_USART1_RX   10
#define XDMAC_CHANNEL_HWID_USART2_TX   11
#define XDMAC_CHANNEL_HWID_USART2_RX   12
#define XDMAC_CHANNEL_HWID_PWM0        13
#define XDMAC_CHANNEL_HWID_TWIHS0_TX   14
#define XDMAC_CHANNEL_HWID_TWIHS0_RX   15
#define XDMAC_CHANNEL_HWID_TWIHS1_TX   16
#define XDMAC_CHANNEL_HWID_TWIHS1_RX   17
#define XDMAC_CHANNEL_HWID_TWIHS2_TX   18
#define XDMAC_CHANNEL_HWID_TWIHS2_RX   19
#define XDMAC_CHANNEL_HWID_UART0_TX    20
#define XDMAC_CHANNEL_HWID_UART0_RX    21
#define XDMAC_CHANNEL_HWID_UART1_TX    22
#define XDMAC_CHANNEL_HWID_UART1_RX    23
#define XDMAC_CHANNEL_HWID_UART2_TX    24
#define XDMAC_CHANNEL_HWID_UART2_RX    25
#define XDMAC_CHANNEL_HWID_UART3_TX    26
#define XDMAC_CHANNEL_HWID_UART3_RX    27
#define XDMAC_CHANNEL_HWID_UART4_TX    28
#define XDMAC_CHANNEL_HWID_UART4_RX    29
#define XDMAC_CHANNEL_HWID_DAC         30
#define XDMAC_CHANNEL_HWID_SSC_TX      32
#define XDMAC_CHANNEL_HWID_SSC_RX      33
#define XDMAC_CHANNEL_HWID_PIOA        34
#define XDMAC_CHANNEL_HWID_AFEC0       35
#define XDMAC_CHANNEL_HWID_AFEC1       36
#define XDMAC_CHANNEL_HWID_AES_TX      37
#define XDMAC_CHANNEL_HWID_AES_RX      38
#define XDMAC_CHANNEL_HWID_PWM1        39
#define XDMAC_CHANNEL_HWID_TC0         40
#define XDMAC_CHANNEL_HWID_TC1         41
#define XDMAC_CHANNEL_HWID_TC2         42
#define XDMAC_CHANNEL_HWID_TC3         43

/* XDMA_MBR_UBC */
#define   XDMAC_UBC_NDE            (0x1u << 24)
#define   XDMAC_UBC_NDE_FETCH_DIS  (0x0u << 24)
#define   XDMAC_UBC_NDE_FETCH_EN   (0x1u << 24)
#define   XDMAC_UBC_NSEN           (0x1u << 25)
#define   XDMAC_UBC_NSEN_UNCHANGED (0x0u << 25)
#define   XDMAC_UBC_NSEN_UPDATED   (0x1u << 25)
#define   XDMAC_UBC_NDEN           (0x1u << 26)
#define   XDMAC_UBC_NDEN_UNCHANGED (0x0u << 26)
#define   XDMAC_UBC_NDEN_UPDATED   (0x1u << 26)
#define   XDMAC_UBC_NVIEW_Pos      27
#define   XDMAC_UBC_NVIEW_Msk      (0x3u << XDMAC_UBC_NVIEW_Pos)
#define   XDMAC_UBC_NVIEW_NDV0     (0x0u << XDMAC_UBC_NVIEW_Pos)
#define   XDMAC_UBC_NVIEW_NDV1     (0x1u << XDMAC_UBC_NVIEW_Pos)
#define   XDMAC_UBC_NVIEW_NDV2     (0x2u << XDMAC_UBC_NVIEW_Pos)
#define   XDMAC_UBC_NVIEW_NDV3     (0x3u << XDMAC_UBC_NVIEW_Pos)
#define   XDMAC_UBC_UBLEN_Pos 0
#define   XDMAC_UBC_UBLEN_Msk (0xffffffu << XDMAC_UBC_UBLEN_Pos)
#define   XDMAC_UBC_UBLEN(value) ((XDMAC_UBC_UBLEN_Msk & ((value) << XDMAC_UBC_UBLEN_Pos)))

typedef struct {
        uint32_t mbr_ubc;
        uint32_t mbr_sa;
        uint32_t mbr_da;
        uint32_t mbr_cfg;
        uint32_t mbr_bc;
        uint32_t mbr_ds;
        uint32_t mbr_sus;
        uint32_t mbr_dus;
} xdmac_channel_config_t;

typedef struct {
        uint32_t mbr_nda;
        uint32_t mbr_ubc;
        uint32_t mbr_ta;
} lld_view0;

typedef struct {
        uint32_t mbr_nda;
        uint32_t mbr_ubc;
        uint32_t mbr_sa;
        uint32_t mbr_da;
} lld_view1;

typedef struct {
        uint32_t mbr_nda;
        uint32_t mbr_ubc;
        uint32_t mbr_sa;
        uint32_t mbr_da;
        uint32_t mbr_cfg;
} lld_view2;

typedef struct {
        uint32_t mbr_nda;
        uint32_t mbr_ubc;
        uint32_t mbr_sa;
        uint32_t mbr_da;
        uint32_t mbr_cfg;
        uint32_t mbr_bc;
        uint32_t mbr_ds;
        uint32_t mbr_sus;
        uint32_t mbr_dus;
} lld_view3;

static inline uint32_t xdmac_get_type( Xdmac *xdmac)
{
        Assert(xdmac);
        return xdmac->XDMAC_GTYPE;
}

static inline uint32_t xdmac_get_config(Xdmac *xdmac)
{
        Assert(xdmac);
        return xdmac->XDMAC_GCFG;
}

static inline uint32_t xdmac_get_arbiter(Xdmac *xdmac)
{
        Assert(xdmac);
        return xdmac->XDMAC_GWAC;
}

static inline void xdmac_enable_interrupt(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        xdmac->XDMAC_GIE = ( XDMAC_GIE_IE0 << channel_num) ;
}

static inline void xdmac_disable_interrupt(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        xdmac->XDMAC_GID = (XDMAC_GID_ID0 << channel_num);
}

static inline uint32_t xdmac_get_interrupt_mask(Xdmac *xdmac)
{
        Assert(xdmac);
        return (xdmac->XDMAC_GIM);
}

static inline uint32_t xdmac_get_interrupt_status(Xdmac *xdmac)
{
        Assert(xdmac);
        return (xdmac->XDMAC_GIS);
}

static inline void xdmac_channel_enable(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);

        /* Update DCache before DMA transmit */
#if CONF_BOARD_ENABLE_DCACHE == 1
        SCB_CleanInvalidateDCache();
#endif

        xdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel_num);
}

static inline void xdmac_channel_enable_no_cache(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel_num);
}

static inline void xdmac_channel_disable(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_GD =(XDMAC_GD_DI0 << channel_num);
}

static inline uint32_t xdmac_channel_get_status(Xdmac *xdmac)
{
        Assert(xdmac);
        return xdmac->XDMAC_GS;
}

static inline void xdmac_channel_read_suspend(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel_num;
}

static inline void xdmac_channel_write_suspend(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel_num;
}

static inline void xdmac_channel_readwrite_suspend(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_GRWS = (XDMAC_GRWS_RWS0 << channel_num);
}

static inline void xdmac_channel_readwrite_resume(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_GRWR = (XDMAC_GRWR_RWR0 << channel_num);
}

static inline void xdmac_channel_software_request(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_GSWR = (XDMAC_GSWR_SWREQ0 << channel_num);
}

static inline uint32_t xdmac_get_software_request_status(Xdmac *xdmac)
{
        Assert(xdmac);
        return xdmac->XDMAC_GSWS;
}

static inline void xdmac_channel_enable_interrupt(Xdmac *xdmac, uint32_t channel_num, uint32_t mask)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CIE = mask;
}

static inline void xdmac_channel_disable_interrupt(Xdmac *xdmac, uint32_t channel_num, uint32_t mask)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CID = mask;
}

static inline uint32_t xdmac_channel_get_interrupt_mask(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        return xdmac->XDMAC_CHID[channel_num].XDMAC_CIM;
}

static inline uint32_t xdmac_channel_get_interrupt_status(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        return xdmac->XDMAC_CHID[channel_num].XDMAC_CIS;
}

static inline void xdmac_channel_software_flush_request(Xdmac *xdmac, uint32_t channel_num)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_GSWF = (XDMAC_GSWF_SWF0 << channel_num);
        while( !(xdmac_channel_get_interrupt_status(xdmac, channel_num) & XDMAC_CIS_FIS) );
}

static inline void xdmac_channel_set_source_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t src_addr)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CSA = src_addr;
}

static inline void xdmac_channel_set_destination_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t dst_addr)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CDA = dst_addr;
}

static inline void xdmac_channel_set_descriptor_addr(Xdmac *xdmac, uint32_t channel_num,
                uint32_t desc_addr, uint8_t ndaif)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        Assert(ndaif<2);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CNDA = (desc_addr & 0xFFFFFFFC) | ndaif;
}

static inline void xdmac_channel_set_descriptor_control(Xdmac *xdmac, uint32_t channel_num, uint32_t config)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CNDC = config;
}

static inline void xdmac_channel_set_microblock_control(Xdmac *xdmac, uint32_t channel_num, uint32_t ublen)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CUBC = XDMAC_CUBC_UBLEN(ublen);
}

static inline void xdmac_channel_set_block_control(Xdmac *xdmac, uint32_t channel_num, uint32_t blen)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CBC = XDMAC_CBC_BLEN(blen);
}

static inline void xdmac_channel_set_config(Xdmac *xdmac, uint32_t channel_num, uint32_t config)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CC = config;
}

static inline void xdmac_channel_set_datastride_mempattern(Xdmac *xdmac, uint32_t channel_num, uint32_t dds_msp)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CDS_MSP = dds_msp;
}

static inline void xdmac_channel_set_source_microblock_stride(Xdmac *xdmac,
                uint32_t channel_num, uint32_t subs)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CSUS = XDMAC_CSUS_SUBS(subs);
}

static inline void xdmac_channel_set_destination_microblock_stride(Xdmac *xdmac,
                uint32_t channel_num, uint32_t dubs)
{
        Assert(xdmac);
        Assert(channel_num < XDMACCHID_NUMBER);
        xdmac->XDMAC_CHID[channel_num].XDMAC_CDUS = XDMAC_CDUS_DUBS(dubs);
}

void xdmac_configure_transfer(Xdmac *xdmac, uint32_t channel_num,
                xdmac_channel_config_t *p_cfg);

#ifdef __cplusplus
}
#endif

#endif /* XDMAC_H_INCLUDED */