drivers/xdmac/xdmac.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef XDMAC_H_INCLUDED
38 #define XDMAC_H_INCLUDED
39 
98 #include <compiler.h>
99 #include <status_codes.h>
100 
103 #ifdef __cplusplus
104 extern "C" {
105 #endif
106 
109 #include "conf_board.h"
110 
112 #define XDMAC_CHANNEL_HWID_HSMCI 0
113 #define XDMAC_CHANNEL_HWID_SPI0_TX 1
114 #define XDMAC_CHANNEL_HWID_SPI0_RX 2
115 #define XDMAC_CHANNEL_HWID_SPI1_TX 3
116 #define XDMAC_CHANNEL_HWID_SPI1_RX 4
117 #define XDMAC_CHANNEL_HWID_QSPI_TX 5
118 #define XDMAC_CHANNEL_HWID_QSPI_RX 6
119 #define XDMAC_CHANNEL_HWID_USART0_TX 7
120 #define XDMAC_CHANNEL_HWID_USART0_RX 8
121 #define XDMAC_CHANNEL_HWID_USART1_TX 9
122 #define XDMAC_CHANNEL_HWID_USART1_RX 10
123 #define XDMAC_CHANNEL_HWID_USART2_TX 11
124 #define XDMAC_CHANNEL_HWID_USART2_RX 12
125 #define XDMAC_CHANNEL_HWID_PWM0 13
126 #define XDMAC_CHANNEL_HWID_TWIHS0_TX 14
127 #define XDMAC_CHANNEL_HWID_TWIHS0_RX 15
128 #define XDMAC_CHANNEL_HWID_TWIHS1_TX 16
129 #define XDMAC_CHANNEL_HWID_TWIHS1_RX 17
130 #define XDMAC_CHANNEL_HWID_TWIHS2_TX 18
131 #define XDMAC_CHANNEL_HWID_TWIHS2_RX 19
132 #define XDMAC_CHANNEL_HWID_UART0_TX 20
133 #define XDMAC_CHANNEL_HWID_UART0_RX 21
134 #define XDMAC_CHANNEL_HWID_UART1_TX 22
135 #define XDMAC_CHANNEL_HWID_UART1_RX 23
136 #define XDMAC_CHANNEL_HWID_UART2_TX 24
137 #define XDMAC_CHANNEL_HWID_UART2_RX 25
138 #define XDMAC_CHANNEL_HWID_UART3_TX 26
139 #define XDMAC_CHANNEL_HWID_UART3_RX 27
140 #define XDMAC_CHANNEL_HWID_UART4_TX 28
141 #define XDMAC_CHANNEL_HWID_UART4_RX 29
142 #define XDMAC_CHANNEL_HWID_DAC 30
143 #define XDMAC_CHANNEL_HWID_SSC_TX 32
144 #define XDMAC_CHANNEL_HWID_SSC_RX 33
145 #define XDMAC_CHANNEL_HWID_PIOA 34
146 #define XDMAC_CHANNEL_HWID_AFEC0 35
147 #define XDMAC_CHANNEL_HWID_AFEC1 36
148 #define XDMAC_CHANNEL_HWID_AES_TX 37
149 #define XDMAC_CHANNEL_HWID_AES_RX 38
150 #define XDMAC_CHANNEL_HWID_PWM1 39
151 #define XDMAC_CHANNEL_HWID_TC0 40
152 #define XDMAC_CHANNEL_HWID_TC1 41
153 #define XDMAC_CHANNEL_HWID_TC2 42
154 #define XDMAC_CHANNEL_HWID_TC3 43
155 
156 /* XDMA_MBR_UBC */
157 #define XDMAC_UBC_NDE (0x1u << 24)
158 #define XDMAC_UBC_NDE_FETCH_DIS (0x0u << 24)
159 #define XDMAC_UBC_NDE_FETCH_EN (0x1u << 24)
160 #define XDMAC_UBC_NSEN (0x1u << 25)
161 #define XDMAC_UBC_NSEN_UNCHANGED (0x0u << 25)
162 #define XDMAC_UBC_NSEN_UPDATED (0x1u << 25)
163 #define XDMAC_UBC_NDEN (0x1u << 26)
164 #define XDMAC_UBC_NDEN_UNCHANGED (0x0u << 26)
165 #define XDMAC_UBC_NDEN_UPDATED (0x1u << 26)
166 #define XDMAC_UBC_NVIEW_Pos 27
167 #define XDMAC_UBC_NVIEW_Msk (0x3u << XDMAC_UBC_NVIEW_Pos)
168 #define XDMAC_UBC_NVIEW_NDV0 (0x0u << XDMAC_UBC_NVIEW_Pos)
169 #define XDMAC_UBC_NVIEW_NDV1 (0x1u << XDMAC_UBC_NVIEW_Pos)
170 #define XDMAC_UBC_NVIEW_NDV2 (0x2u << XDMAC_UBC_NVIEW_Pos)
171 #define XDMAC_UBC_NVIEW_NDV3 (0x3u << XDMAC_UBC_NVIEW_Pos)
172 #define XDMAC_UBC_UBLEN_Pos 0
173 #define XDMAC_UBC_UBLEN_Msk (0xffffffu << XDMAC_UBC_UBLEN_Pos)
174 #define XDMAC_UBC_UBLEN(value) ((XDMAC_UBC_UBLEN_Msk & ((value) << XDMAC_UBC_UBLEN_Pos)))
175 
177 typedef struct {
179  uint32_t mbr_ubc;
181  uint32_t mbr_sa;
183  uint32_t mbr_da;
185  uint32_t mbr_cfg;
187  uint32_t mbr_bc;
189  uint32_t mbr_ds;
191  uint32_t mbr_sus;
193  uint32_t mbr_dus;
195 
200 typedef struct {
202  uint32_t mbr_nda;
204  uint32_t mbr_ubc;
206  uint32_t mbr_ta;
207 } lld_view0;
208 
213 typedef struct {
215  uint32_t mbr_nda;
217  uint32_t mbr_ubc;
219  uint32_t mbr_sa;
221  uint32_t mbr_da;
222 } lld_view1;
223 
228 typedef struct {
230  uint32_t mbr_nda;
232  uint32_t mbr_ubc;
234  uint32_t mbr_sa;
236  uint32_t mbr_da;
238  uint32_t mbr_cfg;
239 } lld_view2;
240 
245 typedef struct {
247  uint32_t mbr_nda;
249  uint32_t mbr_ubc;
251  uint32_t mbr_sa;
253  uint32_t mbr_da;
255  uint32_t mbr_cfg;
257  uint32_t mbr_bc;
259  uint32_t mbr_ds;
261  uint32_t mbr_sus;
263  uint32_t mbr_dus;
264 } lld_view3;
265 
271 static inline uint32_t xdmac_get_type( Xdmac *xdmac)
272 {
273  Assert(xdmac);
274  return xdmac->XDMAC_GTYPE;
275 }
276 
282 static inline uint32_t xdmac_get_config(Xdmac *xdmac)
283 {
284  Assert(xdmac);
285  return xdmac->XDMAC_GCFG;
286 }
287 
293 static inline uint32_t xdmac_get_arbiter(Xdmac *xdmac)
294 {
295  Assert(xdmac);
296  return xdmac->XDMAC_GWAC;
297 }
298 
305 static inline void xdmac_enable_interrupt(Xdmac *xdmac, uint32_t channel_num)
306 {
307  Assert(xdmac);
308  xdmac->XDMAC_GIE = ( XDMAC_GIE_IE0 << channel_num) ;
309 }
310 
317 static inline void xdmac_disable_interrupt(Xdmac *xdmac, uint32_t channel_num)
318 {
319  Assert(xdmac);
320  xdmac->XDMAC_GID = (XDMAC_GID_ID0 << channel_num);
321 }
322 
328 static inline uint32_t xdmac_get_interrupt_mask(Xdmac *xdmac)
329 {
330  Assert(xdmac);
331  return (xdmac->XDMAC_GIM);
332 }
333 
339 static inline uint32_t xdmac_get_interrupt_status(Xdmac *xdmac)
340 {
341  Assert(xdmac);
342  return (xdmac->XDMAC_GIS);
343 }
344 
351 static inline void xdmac_channel_enable(Xdmac *xdmac, uint32_t channel_num)
352 {
353  Assert(xdmac);
354  Assert(channel_num < XDMACCHID_NUMBER);
355 
356  /* Update DCache before DMA transmit */
357 #if CONF_BOARD_ENABLE_DCACHE == 1
359 #endif
360 
361  xdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel_num);
362 }
363 
370 static inline void xdmac_channel_enable_no_cache(Xdmac *xdmac, uint32_t channel_num)
371 {
372  Assert(xdmac);
373  Assert(channel_num < XDMACCHID_NUMBER);
374  xdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel_num);
375 }
376 
383 static inline void xdmac_channel_disable(Xdmac *xdmac, uint32_t channel_num)
384 {
385  Assert(xdmac);
386  Assert(channel_num < XDMACCHID_NUMBER);
387  xdmac->XDMAC_GD =(XDMAC_GD_DI0 << channel_num);
388 }
389 
397 static inline uint32_t xdmac_channel_get_status(Xdmac *xdmac)
398 {
399  Assert(xdmac);
400  return xdmac->XDMAC_GS;
401 }
402 
409 static inline void xdmac_channel_read_suspend(Xdmac *xdmac, uint32_t channel_num)
410 {
411  Assert(xdmac);
412  Assert(channel_num < XDMACCHID_NUMBER);
413  xdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel_num;
414 }
415 
422 static inline void xdmac_channel_write_suspend(Xdmac *xdmac, uint32_t channel_num)
423 {
424  Assert(xdmac);
425  Assert(channel_num < XDMACCHID_NUMBER);
426  xdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel_num;
427 }
428 
435 static inline void xdmac_channel_readwrite_suspend(Xdmac *xdmac, uint32_t channel_num)
436 {
437  Assert(xdmac);
438  Assert(channel_num < XDMACCHID_NUMBER);
439  xdmac->XDMAC_GRWS = (XDMAC_GRWS_RWS0 << channel_num);
440 }
441 
448 static inline void xdmac_channel_readwrite_resume(Xdmac *xdmac, uint32_t channel_num)
449 {
450  Assert(xdmac);
451  Assert(channel_num < XDMACCHID_NUMBER);
452  xdmac->XDMAC_GRWR = (XDMAC_GRWR_RWR0 << channel_num);
453 }
454 
461 static inline void xdmac_channel_software_request(Xdmac *xdmac, uint32_t channel_num)
462 {
463  Assert(xdmac);
464  Assert(channel_num < XDMACCHID_NUMBER);
465  xdmac->XDMAC_GSWR = (XDMAC_GSWR_SWREQ0 << channel_num);
466 }
467 
473 static inline uint32_t xdmac_get_software_request_status(Xdmac *xdmac)
474 {
475  Assert(xdmac);
476  return xdmac->XDMAC_GSWS;
477 }
478 
486 static inline void xdmac_channel_enable_interrupt(Xdmac *xdmac, uint32_t channel_num, uint32_t mask)
487 {
488  Assert(xdmac);
489  Assert(channel_num < XDMACCHID_NUMBER);
490  xdmac->XDMAC_CHID[channel_num].XDMAC_CIE = mask;
491 }
492 
500 static inline void xdmac_channel_disable_interrupt(Xdmac *xdmac, uint32_t channel_num, uint32_t mask)
501 {
502  Assert(xdmac);
503  Assert(channel_num < XDMACCHID_NUMBER);
504  xdmac->XDMAC_CHID[channel_num].XDMAC_CID = mask;
505 }
506 
513 static inline uint32_t xdmac_channel_get_interrupt_mask(Xdmac *xdmac, uint32_t channel_num)
514 {
515  Assert(xdmac);
516  Assert(channel_num < XDMACCHID_NUMBER);
517  return xdmac->XDMAC_CHID[channel_num].XDMAC_CIM;
518 }
519 
526 static inline uint32_t xdmac_channel_get_interrupt_status(Xdmac *xdmac, uint32_t channel_num)
527 {
528  Assert(xdmac);
529  Assert(channel_num < XDMACCHID_NUMBER);
530  return xdmac->XDMAC_CHID[channel_num].XDMAC_CIS;
531 }
532 
539 static inline void xdmac_channel_software_flush_request(Xdmac *xdmac, uint32_t channel_num)
540 {
541  Assert(xdmac);
542  Assert(channel_num < XDMACCHID_NUMBER);
543  xdmac->XDMAC_GSWF = (XDMAC_GSWF_SWF0 << channel_num);
544  while( !(xdmac_channel_get_interrupt_status(xdmac, channel_num) & XDMAC_CIS_FIS) );
545 }
546 
554 static inline void xdmac_channel_set_source_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t src_addr)
555 {
556  Assert(xdmac);
557  Assert(channel_num < XDMACCHID_NUMBER);
558  xdmac->XDMAC_CHID[channel_num].XDMAC_CSA = src_addr;
559 }
560 
568 static inline void xdmac_channel_set_destination_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t dst_addr)
569 {
570  Assert(xdmac);
571  Assert(channel_num < XDMACCHID_NUMBER);
572  xdmac->XDMAC_CHID[channel_num].XDMAC_CDA = dst_addr;
573 }
574 
583 static inline void xdmac_channel_set_descriptor_addr(Xdmac *xdmac, uint32_t channel_num,
584  uint32_t desc_addr, uint8_t ndaif)
585 {
586  Assert(xdmac);
587  Assert(channel_num < XDMACCHID_NUMBER);
588  Assert(ndaif<2);
589  xdmac->XDMAC_CHID[channel_num].XDMAC_CNDA = (desc_addr & 0xFFFFFFFC) | ndaif;
590 }
591 
599 static inline void xdmac_channel_set_descriptor_control(Xdmac *xdmac, uint32_t channel_num, uint32_t config)
600 {
601  Assert(xdmac);
602  Assert(channel_num < XDMACCHID_NUMBER);
603  xdmac->XDMAC_CHID[channel_num].XDMAC_CNDC = config;
604 }
605 
613 static inline void xdmac_channel_set_microblock_control(Xdmac *xdmac, uint32_t channel_num, uint32_t ublen)
614 {
615  Assert(xdmac);
616  Assert(channel_num < XDMACCHID_NUMBER);
617  xdmac->XDMAC_CHID[channel_num].XDMAC_CUBC = XDMAC_CUBC_UBLEN(ublen);
618 }
619 
627 static inline void xdmac_channel_set_block_control(Xdmac *xdmac, uint32_t channel_num, uint32_t blen)
628 {
629  Assert(xdmac);
630  Assert(channel_num < XDMACCHID_NUMBER);
631  xdmac->XDMAC_CHID[channel_num].XDMAC_CBC = XDMAC_CBC_BLEN(blen);
632 }
633 
641 static inline void xdmac_channel_set_config(Xdmac *xdmac, uint32_t channel_num, uint32_t config)
642 {
643  Assert(xdmac);
644  Assert(channel_num < XDMACCHID_NUMBER);
645  xdmac->XDMAC_CHID[channel_num].XDMAC_CC = config;
646 }
647 
655 static inline void xdmac_channel_set_datastride_mempattern(Xdmac *xdmac, uint32_t channel_num, uint32_t dds_msp)
656 {
657  Assert(xdmac);
658  Assert(channel_num < XDMACCHID_NUMBER);
659  xdmac->XDMAC_CHID[channel_num].XDMAC_CDS_MSP = dds_msp;
660 }
661 
670  uint32_t channel_num, uint32_t subs)
671 {
672  Assert(xdmac);
673  Assert(channel_num < XDMACCHID_NUMBER);
674  xdmac->XDMAC_CHID[channel_num].XDMAC_CSUS = XDMAC_CSUS_SUBS(subs);
675 }
676 
685  uint32_t channel_num, uint32_t dubs)
686 {
687  Assert(xdmac);
688  Assert(channel_num < XDMACCHID_NUMBER);
689  xdmac->XDMAC_CHID[channel_num].XDMAC_CDUS = XDMAC_CDUS_DUBS(dubs);
690 }
691 
692 void xdmac_configure_transfer(Xdmac *xdmac, uint32_t channel_num,
693  xdmac_channel_config_t *p_cfg);
694 
697 #ifdef __cplusplus
698 }
699 #endif
700 
841 #endif /* XDMAC_H_INCLUDED */
__O uint32_t XDMAC_CIE
(XdmacChid Offset: 0x0) Channel Interrupt Enable Register
static void xdmac_channel_software_request(Xdmac *xdmac, uint32_t channel_num)
Set software transfer request on the relevant channel.
#define XDMAC_GSWR_SWREQ0
(XDMAC_GSWR) XDMAC Channel 0 Software Request Bit
static void xdmac_channel_set_block_control(Xdmac *xdmac, uint32_t channel_num, uint32_t blen)
Set block length for the relevant channel of given XDMA.
static void xdmac_channel_readwrite_suspend(Xdmac *xdmac, uint32_t channel_num)
Suspend the relevant channel&#39;s read & write.
Structure for storing parameters for DMA view3 that can be performed by the DMA Master transfer...
#define XDMAC_GWS_WS0
(XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit
static void xdmac_channel_set_descriptor_control(Xdmac *xdmac, uint32_t channel_num, uint32_t config)
Set next descriptor&#39;s configuration for the relevant channel of given XDMA.
__IO uint32_t XDMAC_CNDC
(XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register
__I uint32_t XDMAC_CIS
(XdmacChid Offset: 0xC) Channel Interrupt Status Register
#define XDMAC_CDUS_DUBS(value)
#define XDMAC_GID_ID0
(XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit
Status code definitions.
__O uint32_t XDMAC_CID
(XdmacChid Offset: 0x4) Channel Interrupt Disable Register
__IO uint32_t XDMAC_CDS_MSP
(XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern
__O uint32_t XDMAC_GSWF
(Xdmac Offset: 0x40) Global Channel Software Flush Request Register
#define XDMAC_GSWF_SWF0
(XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit
static void xdmac_disable_interrupt(Xdmac *xdmac, uint32_t channel_num)
Disables XDMAC global interrupt.
XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]
(Xdmac Offset: 0x50) chid = 0 .. 23
__IO uint32_t XDMAC_GWAC
(Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register
#define XDMAC_GRWR_RWR0
(XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit
static void xdmac_channel_software_flush_request(Xdmac *xdmac, uint32_t channel_num)
Set software flush request on the relevant channel.
__IO uint32_t XDMAC_GRS
(Xdmac Offset: 0x28) Global Channel Read Suspend Register
#define XDMAC_GRWS_RWS0
(XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit
__I uint32_t XDMAC_CIM
(XdmacChid Offset: 0x8) Channel Interrupt Mask Register
#define XDMAC_GIE_IE0
(XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit
static void xdmac_channel_set_descriptor_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t desc_addr, uint8_t ndaif)
Set next descriptor&#39;s address & interface for the relevant channel of given XDMA. ...
static void xdmac_channel_set_datastride_mempattern(Xdmac *xdmac, uint32_t channel_num, uint32_t dds_msp)
Set the relevant channel&#39;s data stride memory pattern of given XDMA.
Structure for storing parameters for DMA view2 that can be performed by the DMA Master transfer...
__O uint32_t XDMAC_GRWS
(Xdmac Offset: 0x30) Global Channel Read Write Suspend Register
static uint32_t xdmac_get_type(Xdmac *xdmac)
Get XDMAC global type.
static void xdmac_channel_set_destination_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t dst_addr)
Set destination address for the relevant channel of given XDMA.
static uint32_t xdmac_get_software_request_status(Xdmac *xdmac)
Get software transfer status of the relevant channel.
__O uint32_t XDMAC_GSWR
(Xdmac Offset: 0x38) Global Channel Software Request Register
static uint32_t xdmac_channel_get_interrupt_status(Xdmac *xdmac, uint32_t channel_num)
Get interrupt status for the relevant channel of given XDMA.
static uint32_t xdmac_channel_get_status(Xdmac *xdmac)
Get Global channel status of given XDMAC.
__I uint32_t XDMAC_GIM
(Xdmac Offset: 0x14) Global Interrupt Mask Register
static uint32_t xdmac_get_interrupt_mask(Xdmac *xdmac)
Get XDMAC global interrupt mask.
__O uint32_t XDMAC_GID
(Xdmac Offset: 0x10) Global Interrupt Disable Register
static void xdmac_channel_set_source_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t src_addr)
Set source address for the relevant channel of given XDMA.
static uint32_t xdmac_channel_get_interrupt_mask(Xdmac *xdmac, uint32_t channel_num)
Get interrupt mask for the relevant channel of given XDMA.
Commonly used includes, types and macros.
__O uint32_t XDMAC_GD
(Xdmac Offset: 0x20) Global Channel Disable Register
__IO uint32_t XDMAC_CUBC
(XdmacChid Offset: 0x20) Channel Microblock Control Register
#define XDMAC_GD_DI0
(XDMAC_GD) XDMAC Channel 0 Disable Bit
__I uint32_t XDMAC_GSWS
(Xdmac Offset: 0x3C) Global Channel Software Request Status Register
__IO uint32_t XDMAC_CDA
(XdmacChid Offset: 0x14) Channel Destination Address Register
static void xdmac_channel_set_microblock_control(Xdmac *xdmac, uint32_t channel_num, uint32_t ublen)
Set microblock length for the relevant channel of given XDMA.
static void xdmac_channel_enable(Xdmac *xdmac, uint32_t channel_num)
enables the relevant channel of given XDMAC.
__IO uint32_t XDMAC_CSA
(XdmacChid Offset: 0x10) Channel Source Address Register
static void xdmac_channel_readwrite_resume(Xdmac *xdmac, uint32_t channel_num)
Resume the relevant channel&#39;s read & write.
__IO uint32_t XDMAC_GWS
(Xdmac Offset: 0x2C) Global Channel Write Suspend Register
Structure for storing parameters for DMA view1 that can be performed by the DMA Master transfer...
static void xdmac_channel_disable_interrupt(Xdmac *xdmac, uint32_t channel_num, uint32_t mask)
Disable interrupt with mask on the relevant channel of given XDMA.
static void xdmac_enable_interrupt(Xdmac *xdmac, uint32_t channel_num)
Enables XDMAC global interrupt.
__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: core_cm7.h:2069
static uint32_t xdmac_get_config(Xdmac *xdmac)
Get XDMAC global configuration.
static void xdmac_channel_disable(Xdmac *xdmac, uint32_t channel_num)
Disables the relevant channel of given XDMAC.
#define XDMAC_GRS_RS0
(XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit
__I uint32_t XDMAC_GS
(Xdmac Offset: 0x24) Global Channel Status Register
static void xdmac_channel_enable_interrupt(Xdmac *xdmac, uint32_t channel_num, uint32_t mask)
Enable interrupt with mask on the relevant channel of given XDMA.
Board configuration.
static void xdmac_channel_set_destination_microblock_stride(Xdmac *xdmac, uint32_t channel_num, uint32_t dubs)
Set the relevant channel&#39;s destination microblock stride of given XDMA.
static void xdmac_channel_read_suspend(Xdmac *xdmac, uint32_t channel_num)
Suspend the relevant channel&#39;s read.
__O uint32_t XDMAC_GE
(Xdmac Offset: 0x1C) Global Channel Enable Register
void xdmac_configure_transfer(Xdmac *xdmac, uint32_t channel_num, xdmac_channel_config_t *p_cfg)
Configure DMA for a transfer.
Definition: xdmac.c:46
__IO uint32_t XDMAC_CSUS
(XdmacChid Offset: 0x30) Channel Source Microblock Stride
static uint32_t xdmac_get_interrupt_status(Xdmac *xdmac)
Get XDMAC global interrupt status.
#define XDMAC_CUBC_UBLEN(value)
__O uint32_t XDMAC_GIE
(Xdmac Offset: 0x0C) Global Interrupt Enable Register
static void xdmac_channel_enable_no_cache(Xdmac *xdmac, uint32_t channel_num)
enables the relevant channel of given XDMAC without invalidating data cache.
static void xdmac_channel_set_config(Xdmac *xdmac, uint32_t channel_num, uint32_t config)
Set configuration for the relevant channel of given XDMA.
Structure for storing parameters for DMA view0 that can be performed by the DMA Master transfer...
static void xdmac_channel_write_suspend(Xdmac *xdmac, uint32_t channel_num)
Suspend the relevant channel&#39;s write.
__IO uint32_t XDMAC_CC
(XdmacChid Offset: 0x28) Channel Configuration Register
__IO uint32_t XDMAC_GCFG
(Xdmac Offset: 0x04) Global Configuration Register
static uint32_t xdmac_get_arbiter(Xdmac *xdmac)
Get XDMAC global weighted arbiter configuration.
#define XDMACCHID_NUMBER
Xdmac hardware registers.
__IO uint32_t XDMAC_CBC
(XdmacChid Offset: 0x24) Channel Block Control Register
#define XDMAC_CSUS_SUBS(value)
__I uint32_t XDMAC_GIS
(Xdmac Offset: 0x18) Global Interrupt Status Register
__IO uint32_t XDMAC_CDUS
(XdmacChid Offset: 0x34) Channel Destination Microblock Stride
#define XDMAC_CIS_FIS
(XDMAC_CIS) End of Flush Interrupt Status Bit
#define XDMAC_GE_EN0
(XDMAC_GE) XDMAC Channel 0 Enable Bit
__O uint32_t XDMAC_GRWR
(Xdmac Offset: 0x34) Global Channel Read Write Resume Register
__I uint32_t XDMAC_GTYPE
(Xdmac Offset: 0x00) Global Type Register
#define Assert(expr)
This macro is used to test fatal errors.
Definition: compiler.h:196
__IO uint32_t XDMAC_CNDA
(XdmacChid Offset: 0x18) Channel Next Descriptor Address Register
static void xdmac_channel_set_source_microblock_stride(Xdmac *xdmac, uint32_t channel_num, uint32_t subs)
Set the relevant channel&#39;s source microblock stride of given XDMA.


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:05