utils/cmsis/same70/include/component/xdmac.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_XDMAC_COMPONENT_
36 #define _SAME70_XDMAC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t XDMAC_CIE;
48  __O uint32_t XDMAC_CID;
49  __I uint32_t XDMAC_CIM;
50  __I uint32_t XDMAC_CIS;
51  __IO uint32_t XDMAC_CSA;
52  __IO uint32_t XDMAC_CDA;
53  __IO uint32_t XDMAC_CNDA;
54  __IO uint32_t XDMAC_CNDC;
55  __IO uint32_t XDMAC_CUBC;
56  __IO uint32_t XDMAC_CBC;
57  __IO uint32_t XDMAC_CC;
58  __IO uint32_t XDMAC_CDS_MSP;
59  __IO uint32_t XDMAC_CSUS;
60  __IO uint32_t XDMAC_CDUS;
61  __I uint32_t Reserved1[2];
62 } XdmacChid;
64 #define XDMACCHID_NUMBER 24
65 typedef struct {
66  __I uint32_t XDMAC_GTYPE;
67  __IO uint32_t XDMAC_GCFG;
68  __IO uint32_t XDMAC_GWAC;
69  __O uint32_t XDMAC_GIE;
70  __O uint32_t XDMAC_GID;
71  __I uint32_t XDMAC_GIM;
72  __I uint32_t XDMAC_GIS;
73  __O uint32_t XDMAC_GE;
74  __O uint32_t XDMAC_GD;
75  __I uint32_t XDMAC_GS;
76  __IO uint32_t XDMAC_GRS;
77  __IO uint32_t XDMAC_GWS;
78  __O uint32_t XDMAC_GRWS;
79  __O uint32_t XDMAC_GRWR;
80  __O uint32_t XDMAC_GSWR;
81  __I uint32_t XDMAC_GSWS;
82  __O uint32_t XDMAC_GSWF;
83  __I uint32_t Reserved1[3];
85  __I uint32_t Reserved2[619];
86  __IO uint32_t XDMAC_VERSION;
87 } Xdmac;
88 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
89 /* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */
90 #define XDMAC_GTYPE_NB_CH_Pos 0
91 #define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos)
92 #define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)))
93 #define XDMAC_GTYPE_FIFO_SZ_Pos 5
94 #define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos)
95 #define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)))
96 #define XDMAC_GTYPE_NB_REQ_Pos 16
97 #define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos)
98 #define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)))
99 /* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */
100 #define XDMAC_GCFG_CGDISREG (0x1u << 0)
101 #define XDMAC_GCFG_CGDISPIPE (0x1u << 1)
102 #define XDMAC_GCFG_CGDISFIFO (0x1u << 2)
103 #define XDMAC_GCFG_CGDISIF (0x1u << 3)
104 #define XDMAC_GCFG_BXKBEN (0x1u << 8)
105 /* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */
106 #define XDMAC_GWAC_PW0_Pos 0
107 #define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos)
108 #define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)))
109 #define XDMAC_GWAC_PW1_Pos 4
110 #define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos)
111 #define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)))
112 #define XDMAC_GWAC_PW2_Pos 8
113 #define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos)
114 #define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)))
115 #define XDMAC_GWAC_PW3_Pos 12
116 #define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos)
117 #define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)))
118 /* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */
119 #define XDMAC_GIE_IE0 (0x1u << 0)
120 #define XDMAC_GIE_IE1 (0x1u << 1)
121 #define XDMAC_GIE_IE2 (0x1u << 2)
122 #define XDMAC_GIE_IE3 (0x1u << 3)
123 #define XDMAC_GIE_IE4 (0x1u << 4)
124 #define XDMAC_GIE_IE5 (0x1u << 5)
125 #define XDMAC_GIE_IE6 (0x1u << 6)
126 #define XDMAC_GIE_IE7 (0x1u << 7)
127 #define XDMAC_GIE_IE8 (0x1u << 8)
128 #define XDMAC_GIE_IE9 (0x1u << 9)
129 #define XDMAC_GIE_IE10 (0x1u << 10)
130 #define XDMAC_GIE_IE11 (0x1u << 11)
131 #define XDMAC_GIE_IE12 (0x1u << 12)
132 #define XDMAC_GIE_IE13 (0x1u << 13)
133 #define XDMAC_GIE_IE14 (0x1u << 14)
134 #define XDMAC_GIE_IE15 (0x1u << 15)
135 #define XDMAC_GIE_IE16 (0x1u << 16)
136 #define XDMAC_GIE_IE17 (0x1u << 17)
137 #define XDMAC_GIE_IE18 (0x1u << 18)
138 #define XDMAC_GIE_IE19 (0x1u << 19)
139 #define XDMAC_GIE_IE20 (0x1u << 20)
140 #define XDMAC_GIE_IE21 (0x1u << 21)
141 #define XDMAC_GIE_IE22 (0x1u << 22)
142 #define XDMAC_GIE_IE23 (0x1u << 23)
143 /* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */
144 #define XDMAC_GID_ID0 (0x1u << 0)
145 #define XDMAC_GID_ID1 (0x1u << 1)
146 #define XDMAC_GID_ID2 (0x1u << 2)
147 #define XDMAC_GID_ID3 (0x1u << 3)
148 #define XDMAC_GID_ID4 (0x1u << 4)
149 #define XDMAC_GID_ID5 (0x1u << 5)
150 #define XDMAC_GID_ID6 (0x1u << 6)
151 #define XDMAC_GID_ID7 (0x1u << 7)
152 #define XDMAC_GID_ID8 (0x1u << 8)
153 #define XDMAC_GID_ID9 (0x1u << 9)
154 #define XDMAC_GID_ID10 (0x1u << 10)
155 #define XDMAC_GID_ID11 (0x1u << 11)
156 #define XDMAC_GID_ID12 (0x1u << 12)
157 #define XDMAC_GID_ID13 (0x1u << 13)
158 #define XDMAC_GID_ID14 (0x1u << 14)
159 #define XDMAC_GID_ID15 (0x1u << 15)
160 #define XDMAC_GID_ID16 (0x1u << 16)
161 #define XDMAC_GID_ID17 (0x1u << 17)
162 #define XDMAC_GID_ID18 (0x1u << 18)
163 #define XDMAC_GID_ID19 (0x1u << 19)
164 #define XDMAC_GID_ID20 (0x1u << 20)
165 #define XDMAC_GID_ID21 (0x1u << 21)
166 #define XDMAC_GID_ID22 (0x1u << 22)
167 #define XDMAC_GID_ID23 (0x1u << 23)
168 /* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */
169 #define XDMAC_GIM_IM0 (0x1u << 0)
170 #define XDMAC_GIM_IM1 (0x1u << 1)
171 #define XDMAC_GIM_IM2 (0x1u << 2)
172 #define XDMAC_GIM_IM3 (0x1u << 3)
173 #define XDMAC_GIM_IM4 (0x1u << 4)
174 #define XDMAC_GIM_IM5 (0x1u << 5)
175 #define XDMAC_GIM_IM6 (0x1u << 6)
176 #define XDMAC_GIM_IM7 (0x1u << 7)
177 #define XDMAC_GIM_IM8 (0x1u << 8)
178 #define XDMAC_GIM_IM9 (0x1u << 9)
179 #define XDMAC_GIM_IM10 (0x1u << 10)
180 #define XDMAC_GIM_IM11 (0x1u << 11)
181 #define XDMAC_GIM_IM12 (0x1u << 12)
182 #define XDMAC_GIM_IM13 (0x1u << 13)
183 #define XDMAC_GIM_IM14 (0x1u << 14)
184 #define XDMAC_GIM_IM15 (0x1u << 15)
185 #define XDMAC_GIM_IM16 (0x1u << 16)
186 #define XDMAC_GIM_IM17 (0x1u << 17)
187 #define XDMAC_GIM_IM18 (0x1u << 18)
188 #define XDMAC_GIM_IM19 (0x1u << 19)
189 #define XDMAC_GIM_IM20 (0x1u << 20)
190 #define XDMAC_GIM_IM21 (0x1u << 21)
191 #define XDMAC_GIM_IM22 (0x1u << 22)
192 #define XDMAC_GIM_IM23 (0x1u << 23)
193 /* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */
194 #define XDMAC_GIS_IS0 (0x1u << 0)
195 #define XDMAC_GIS_IS1 (0x1u << 1)
196 #define XDMAC_GIS_IS2 (0x1u << 2)
197 #define XDMAC_GIS_IS3 (0x1u << 3)
198 #define XDMAC_GIS_IS4 (0x1u << 4)
199 #define XDMAC_GIS_IS5 (0x1u << 5)
200 #define XDMAC_GIS_IS6 (0x1u << 6)
201 #define XDMAC_GIS_IS7 (0x1u << 7)
202 #define XDMAC_GIS_IS8 (0x1u << 8)
203 #define XDMAC_GIS_IS9 (0x1u << 9)
204 #define XDMAC_GIS_IS10 (0x1u << 10)
205 #define XDMAC_GIS_IS11 (0x1u << 11)
206 #define XDMAC_GIS_IS12 (0x1u << 12)
207 #define XDMAC_GIS_IS13 (0x1u << 13)
208 #define XDMAC_GIS_IS14 (0x1u << 14)
209 #define XDMAC_GIS_IS15 (0x1u << 15)
210 #define XDMAC_GIS_IS16 (0x1u << 16)
211 #define XDMAC_GIS_IS17 (0x1u << 17)
212 #define XDMAC_GIS_IS18 (0x1u << 18)
213 #define XDMAC_GIS_IS19 (0x1u << 19)
214 #define XDMAC_GIS_IS20 (0x1u << 20)
215 #define XDMAC_GIS_IS21 (0x1u << 21)
216 #define XDMAC_GIS_IS22 (0x1u << 22)
217 #define XDMAC_GIS_IS23 (0x1u << 23)
218 /* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */
219 #define XDMAC_GE_EN0 (0x1u << 0)
220 #define XDMAC_GE_EN1 (0x1u << 1)
221 #define XDMAC_GE_EN2 (0x1u << 2)
222 #define XDMAC_GE_EN3 (0x1u << 3)
223 #define XDMAC_GE_EN4 (0x1u << 4)
224 #define XDMAC_GE_EN5 (0x1u << 5)
225 #define XDMAC_GE_EN6 (0x1u << 6)
226 #define XDMAC_GE_EN7 (0x1u << 7)
227 #define XDMAC_GE_EN8 (0x1u << 8)
228 #define XDMAC_GE_EN9 (0x1u << 9)
229 #define XDMAC_GE_EN10 (0x1u << 10)
230 #define XDMAC_GE_EN11 (0x1u << 11)
231 #define XDMAC_GE_EN12 (0x1u << 12)
232 #define XDMAC_GE_EN13 (0x1u << 13)
233 #define XDMAC_GE_EN14 (0x1u << 14)
234 #define XDMAC_GE_EN15 (0x1u << 15)
235 #define XDMAC_GE_EN16 (0x1u << 16)
236 #define XDMAC_GE_EN17 (0x1u << 17)
237 #define XDMAC_GE_EN18 (0x1u << 18)
238 #define XDMAC_GE_EN19 (0x1u << 19)
239 #define XDMAC_GE_EN20 (0x1u << 20)
240 #define XDMAC_GE_EN21 (0x1u << 21)
241 #define XDMAC_GE_EN22 (0x1u << 22)
242 #define XDMAC_GE_EN23 (0x1u << 23)
243 /* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */
244 #define XDMAC_GD_DI0 (0x1u << 0)
245 #define XDMAC_GD_DI1 (0x1u << 1)
246 #define XDMAC_GD_DI2 (0x1u << 2)
247 #define XDMAC_GD_DI3 (0x1u << 3)
248 #define XDMAC_GD_DI4 (0x1u << 4)
249 #define XDMAC_GD_DI5 (0x1u << 5)
250 #define XDMAC_GD_DI6 (0x1u << 6)
251 #define XDMAC_GD_DI7 (0x1u << 7)
252 #define XDMAC_GD_DI8 (0x1u << 8)
253 #define XDMAC_GD_DI9 (0x1u << 9)
254 #define XDMAC_GD_DI10 (0x1u << 10)
255 #define XDMAC_GD_DI11 (0x1u << 11)
256 #define XDMAC_GD_DI12 (0x1u << 12)
257 #define XDMAC_GD_DI13 (0x1u << 13)
258 #define XDMAC_GD_DI14 (0x1u << 14)
259 #define XDMAC_GD_DI15 (0x1u << 15)
260 #define XDMAC_GD_DI16 (0x1u << 16)
261 #define XDMAC_GD_DI17 (0x1u << 17)
262 #define XDMAC_GD_DI18 (0x1u << 18)
263 #define XDMAC_GD_DI19 (0x1u << 19)
264 #define XDMAC_GD_DI20 (0x1u << 20)
265 #define XDMAC_GD_DI21 (0x1u << 21)
266 #define XDMAC_GD_DI22 (0x1u << 22)
267 #define XDMAC_GD_DI23 (0x1u << 23)
268 /* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */
269 #define XDMAC_GS_ST0 (0x1u << 0)
270 #define XDMAC_GS_ST1 (0x1u << 1)
271 #define XDMAC_GS_ST2 (0x1u << 2)
272 #define XDMAC_GS_ST3 (0x1u << 3)
273 #define XDMAC_GS_ST4 (0x1u << 4)
274 #define XDMAC_GS_ST5 (0x1u << 5)
275 #define XDMAC_GS_ST6 (0x1u << 6)
276 #define XDMAC_GS_ST7 (0x1u << 7)
277 #define XDMAC_GS_ST8 (0x1u << 8)
278 #define XDMAC_GS_ST9 (0x1u << 9)
279 #define XDMAC_GS_ST10 (0x1u << 10)
280 #define XDMAC_GS_ST11 (0x1u << 11)
281 #define XDMAC_GS_ST12 (0x1u << 12)
282 #define XDMAC_GS_ST13 (0x1u << 13)
283 #define XDMAC_GS_ST14 (0x1u << 14)
284 #define XDMAC_GS_ST15 (0x1u << 15)
285 #define XDMAC_GS_ST16 (0x1u << 16)
286 #define XDMAC_GS_ST17 (0x1u << 17)
287 #define XDMAC_GS_ST18 (0x1u << 18)
288 #define XDMAC_GS_ST19 (0x1u << 19)
289 #define XDMAC_GS_ST20 (0x1u << 20)
290 #define XDMAC_GS_ST21 (0x1u << 21)
291 #define XDMAC_GS_ST22 (0x1u << 22)
292 #define XDMAC_GS_ST23 (0x1u << 23)
293 /* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */
294 #define XDMAC_GRS_RS0 (0x1u << 0)
295 #define XDMAC_GRS_RS1 (0x1u << 1)
296 #define XDMAC_GRS_RS2 (0x1u << 2)
297 #define XDMAC_GRS_RS3 (0x1u << 3)
298 #define XDMAC_GRS_RS4 (0x1u << 4)
299 #define XDMAC_GRS_RS5 (0x1u << 5)
300 #define XDMAC_GRS_RS6 (0x1u << 6)
301 #define XDMAC_GRS_RS7 (0x1u << 7)
302 #define XDMAC_GRS_RS8 (0x1u << 8)
303 #define XDMAC_GRS_RS9 (0x1u << 9)
304 #define XDMAC_GRS_RS10 (0x1u << 10)
305 #define XDMAC_GRS_RS11 (0x1u << 11)
306 #define XDMAC_GRS_RS12 (0x1u << 12)
307 #define XDMAC_GRS_RS13 (0x1u << 13)
308 #define XDMAC_GRS_RS14 (0x1u << 14)
309 #define XDMAC_GRS_RS15 (0x1u << 15)
310 #define XDMAC_GRS_RS16 (0x1u << 16)
311 #define XDMAC_GRS_RS17 (0x1u << 17)
312 #define XDMAC_GRS_RS18 (0x1u << 18)
313 #define XDMAC_GRS_RS19 (0x1u << 19)
314 #define XDMAC_GRS_RS20 (0x1u << 20)
315 #define XDMAC_GRS_RS21 (0x1u << 21)
316 #define XDMAC_GRS_RS22 (0x1u << 22)
317 #define XDMAC_GRS_RS23 (0x1u << 23)
318 /* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */
319 #define XDMAC_GWS_WS0 (0x1u << 0)
320 #define XDMAC_GWS_WS1 (0x1u << 1)
321 #define XDMAC_GWS_WS2 (0x1u << 2)
322 #define XDMAC_GWS_WS3 (0x1u << 3)
323 #define XDMAC_GWS_WS4 (0x1u << 4)
324 #define XDMAC_GWS_WS5 (0x1u << 5)
325 #define XDMAC_GWS_WS6 (0x1u << 6)
326 #define XDMAC_GWS_WS7 (0x1u << 7)
327 #define XDMAC_GWS_WS8 (0x1u << 8)
328 #define XDMAC_GWS_WS9 (0x1u << 9)
329 #define XDMAC_GWS_WS10 (0x1u << 10)
330 #define XDMAC_GWS_WS11 (0x1u << 11)
331 #define XDMAC_GWS_WS12 (0x1u << 12)
332 #define XDMAC_GWS_WS13 (0x1u << 13)
333 #define XDMAC_GWS_WS14 (0x1u << 14)
334 #define XDMAC_GWS_WS15 (0x1u << 15)
335 #define XDMAC_GWS_WS16 (0x1u << 16)
336 #define XDMAC_GWS_WS17 (0x1u << 17)
337 #define XDMAC_GWS_WS18 (0x1u << 18)
338 #define XDMAC_GWS_WS19 (0x1u << 19)
339 #define XDMAC_GWS_WS20 (0x1u << 20)
340 #define XDMAC_GWS_WS21 (0x1u << 21)
341 #define XDMAC_GWS_WS22 (0x1u << 22)
342 #define XDMAC_GWS_WS23 (0x1u << 23)
343 /* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */
344 #define XDMAC_GRWS_RWS0 (0x1u << 0)
345 #define XDMAC_GRWS_RWS1 (0x1u << 1)
346 #define XDMAC_GRWS_RWS2 (0x1u << 2)
347 #define XDMAC_GRWS_RWS3 (0x1u << 3)
348 #define XDMAC_GRWS_RWS4 (0x1u << 4)
349 #define XDMAC_GRWS_RWS5 (0x1u << 5)
350 #define XDMAC_GRWS_RWS6 (0x1u << 6)
351 #define XDMAC_GRWS_RWS7 (0x1u << 7)
352 #define XDMAC_GRWS_RWS8 (0x1u << 8)
353 #define XDMAC_GRWS_RWS9 (0x1u << 9)
354 #define XDMAC_GRWS_RWS10 (0x1u << 10)
355 #define XDMAC_GRWS_RWS11 (0x1u << 11)
356 #define XDMAC_GRWS_RWS12 (0x1u << 12)
357 #define XDMAC_GRWS_RWS13 (0x1u << 13)
358 #define XDMAC_GRWS_RWS14 (0x1u << 14)
359 #define XDMAC_GRWS_RWS15 (0x1u << 15)
360 #define XDMAC_GRWS_RWS16 (0x1u << 16)
361 #define XDMAC_GRWS_RWS17 (0x1u << 17)
362 #define XDMAC_GRWS_RWS18 (0x1u << 18)
363 #define XDMAC_GRWS_RWS19 (0x1u << 19)
364 #define XDMAC_GRWS_RWS20 (0x1u << 20)
365 #define XDMAC_GRWS_RWS21 (0x1u << 21)
366 #define XDMAC_GRWS_RWS22 (0x1u << 22)
367 #define XDMAC_GRWS_RWS23 (0x1u << 23)
368 /* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */
369 #define XDMAC_GRWR_RWR0 (0x1u << 0)
370 #define XDMAC_GRWR_RWR1 (0x1u << 1)
371 #define XDMAC_GRWR_RWR2 (0x1u << 2)
372 #define XDMAC_GRWR_RWR3 (0x1u << 3)
373 #define XDMAC_GRWR_RWR4 (0x1u << 4)
374 #define XDMAC_GRWR_RWR5 (0x1u << 5)
375 #define XDMAC_GRWR_RWR6 (0x1u << 6)
376 #define XDMAC_GRWR_RWR7 (0x1u << 7)
377 #define XDMAC_GRWR_RWR8 (0x1u << 8)
378 #define XDMAC_GRWR_RWR9 (0x1u << 9)
379 #define XDMAC_GRWR_RWR10 (0x1u << 10)
380 #define XDMAC_GRWR_RWR11 (0x1u << 11)
381 #define XDMAC_GRWR_RWR12 (0x1u << 12)
382 #define XDMAC_GRWR_RWR13 (0x1u << 13)
383 #define XDMAC_GRWR_RWR14 (0x1u << 14)
384 #define XDMAC_GRWR_RWR15 (0x1u << 15)
385 #define XDMAC_GRWR_RWR16 (0x1u << 16)
386 #define XDMAC_GRWR_RWR17 (0x1u << 17)
387 #define XDMAC_GRWR_RWR18 (0x1u << 18)
388 #define XDMAC_GRWR_RWR19 (0x1u << 19)
389 #define XDMAC_GRWR_RWR20 (0x1u << 20)
390 #define XDMAC_GRWR_RWR21 (0x1u << 21)
391 #define XDMAC_GRWR_RWR22 (0x1u << 22)
392 #define XDMAC_GRWR_RWR23 (0x1u << 23)
393 /* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */
394 #define XDMAC_GSWR_SWREQ0 (0x1u << 0)
395 #define XDMAC_GSWR_SWREQ1 (0x1u << 1)
396 #define XDMAC_GSWR_SWREQ2 (0x1u << 2)
397 #define XDMAC_GSWR_SWREQ3 (0x1u << 3)
398 #define XDMAC_GSWR_SWREQ4 (0x1u << 4)
399 #define XDMAC_GSWR_SWREQ5 (0x1u << 5)
400 #define XDMAC_GSWR_SWREQ6 (0x1u << 6)
401 #define XDMAC_GSWR_SWREQ7 (0x1u << 7)
402 #define XDMAC_GSWR_SWREQ8 (0x1u << 8)
403 #define XDMAC_GSWR_SWREQ9 (0x1u << 9)
404 #define XDMAC_GSWR_SWREQ10 (0x1u << 10)
405 #define XDMAC_GSWR_SWREQ11 (0x1u << 11)
406 #define XDMAC_GSWR_SWREQ12 (0x1u << 12)
407 #define XDMAC_GSWR_SWREQ13 (0x1u << 13)
408 #define XDMAC_GSWR_SWREQ14 (0x1u << 14)
409 #define XDMAC_GSWR_SWREQ15 (0x1u << 15)
410 #define XDMAC_GSWR_SWREQ16 (0x1u << 16)
411 #define XDMAC_GSWR_SWREQ17 (0x1u << 17)
412 #define XDMAC_GSWR_SWREQ18 (0x1u << 18)
413 #define XDMAC_GSWR_SWREQ19 (0x1u << 19)
414 #define XDMAC_GSWR_SWREQ20 (0x1u << 20)
415 #define XDMAC_GSWR_SWREQ21 (0x1u << 21)
416 #define XDMAC_GSWR_SWREQ22 (0x1u << 22)
417 #define XDMAC_GSWR_SWREQ23 (0x1u << 23)
418 /* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */
419 #define XDMAC_GSWS_SWRS0 (0x1u << 0)
420 #define XDMAC_GSWS_SWRS1 (0x1u << 1)
421 #define XDMAC_GSWS_SWRS2 (0x1u << 2)
422 #define XDMAC_GSWS_SWRS3 (0x1u << 3)
423 #define XDMAC_GSWS_SWRS4 (0x1u << 4)
424 #define XDMAC_GSWS_SWRS5 (0x1u << 5)
425 #define XDMAC_GSWS_SWRS6 (0x1u << 6)
426 #define XDMAC_GSWS_SWRS7 (0x1u << 7)
427 #define XDMAC_GSWS_SWRS8 (0x1u << 8)
428 #define XDMAC_GSWS_SWRS9 (0x1u << 9)
429 #define XDMAC_GSWS_SWRS10 (0x1u << 10)
430 #define XDMAC_GSWS_SWRS11 (0x1u << 11)
431 #define XDMAC_GSWS_SWRS12 (0x1u << 12)
432 #define XDMAC_GSWS_SWRS13 (0x1u << 13)
433 #define XDMAC_GSWS_SWRS14 (0x1u << 14)
434 #define XDMAC_GSWS_SWRS15 (0x1u << 15)
435 #define XDMAC_GSWS_SWRS16 (0x1u << 16)
436 #define XDMAC_GSWS_SWRS17 (0x1u << 17)
437 #define XDMAC_GSWS_SWRS18 (0x1u << 18)
438 #define XDMAC_GSWS_SWRS19 (0x1u << 19)
439 #define XDMAC_GSWS_SWRS20 (0x1u << 20)
440 #define XDMAC_GSWS_SWRS21 (0x1u << 21)
441 #define XDMAC_GSWS_SWRS22 (0x1u << 22)
442 #define XDMAC_GSWS_SWRS23 (0x1u << 23)
443 /* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */
444 #define XDMAC_GSWF_SWF0 (0x1u << 0)
445 #define XDMAC_GSWF_SWF1 (0x1u << 1)
446 #define XDMAC_GSWF_SWF2 (0x1u << 2)
447 #define XDMAC_GSWF_SWF3 (0x1u << 3)
448 #define XDMAC_GSWF_SWF4 (0x1u << 4)
449 #define XDMAC_GSWF_SWF5 (0x1u << 5)
450 #define XDMAC_GSWF_SWF6 (0x1u << 6)
451 #define XDMAC_GSWF_SWF7 (0x1u << 7)
452 #define XDMAC_GSWF_SWF8 (0x1u << 8)
453 #define XDMAC_GSWF_SWF9 (0x1u << 9)
454 #define XDMAC_GSWF_SWF10 (0x1u << 10)
455 #define XDMAC_GSWF_SWF11 (0x1u << 11)
456 #define XDMAC_GSWF_SWF12 (0x1u << 12)
457 #define XDMAC_GSWF_SWF13 (0x1u << 13)
458 #define XDMAC_GSWF_SWF14 (0x1u << 14)
459 #define XDMAC_GSWF_SWF15 (0x1u << 15)
460 #define XDMAC_GSWF_SWF16 (0x1u << 16)
461 #define XDMAC_GSWF_SWF17 (0x1u << 17)
462 #define XDMAC_GSWF_SWF18 (0x1u << 18)
463 #define XDMAC_GSWF_SWF19 (0x1u << 19)
464 #define XDMAC_GSWF_SWF20 (0x1u << 20)
465 #define XDMAC_GSWF_SWF21 (0x1u << 21)
466 #define XDMAC_GSWF_SWF22 (0x1u << 22)
467 #define XDMAC_GSWF_SWF23 (0x1u << 23)
468 /* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */
469 #define XDMAC_CIE_BIE (0x1u << 0)
470 #define XDMAC_CIE_LIE (0x1u << 1)
471 #define XDMAC_CIE_DIE (0x1u << 2)
472 #define XDMAC_CIE_FIE (0x1u << 3)
473 #define XDMAC_CIE_RBIE (0x1u << 4)
474 #define XDMAC_CIE_WBIE (0x1u << 5)
475 #define XDMAC_CIE_ROIE (0x1u << 6)
476 /* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */
477 #define XDMAC_CID_BID (0x1u << 0)
478 #define XDMAC_CID_LID (0x1u << 1)
479 #define XDMAC_CID_DID (0x1u << 2)
480 #define XDMAC_CID_FID (0x1u << 3)
481 #define XDMAC_CID_RBEID (0x1u << 4)
482 #define XDMAC_CID_WBEID (0x1u << 5)
483 #define XDMAC_CID_ROID (0x1u << 6)
484 /* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */
485 #define XDMAC_CIM_BIM (0x1u << 0)
486 #define XDMAC_CIM_LIM (0x1u << 1)
487 #define XDMAC_CIM_DIM (0x1u << 2)
488 #define XDMAC_CIM_FIM (0x1u << 3)
489 #define XDMAC_CIM_RBEIM (0x1u << 4)
490 #define XDMAC_CIM_WBEIM (0x1u << 5)
491 #define XDMAC_CIM_ROIM (0x1u << 6)
492 /* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */
493 #define XDMAC_CIS_BIS (0x1u << 0)
494 #define XDMAC_CIS_LIS (0x1u << 1)
495 #define XDMAC_CIS_DIS (0x1u << 2)
496 #define XDMAC_CIS_FIS (0x1u << 3)
497 #define XDMAC_CIS_RBEIS (0x1u << 4)
498 #define XDMAC_CIS_WBEIS (0x1u << 5)
499 #define XDMAC_CIS_ROIS (0x1u << 6)
500 /* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */
501 #define XDMAC_CSA_SA_Pos 0
502 #define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos)
503 #define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)))
504 /* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */
505 #define XDMAC_CDA_DA_Pos 0
506 #define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos)
507 #define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)))
508 /* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */
509 #define XDMAC_CNDA_NDAIF (0x1u << 0)
510 #define XDMAC_CNDA_NDA_Pos 2
511 #define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos)
512 #define XDMAC_CNDA_NDA(value) (XDMAC_CNDA_NDA_Msk & (value))
513 /* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */
514 #define XDMAC_CNDC_NDE (0x1u << 0)
515 #define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0)
516 #define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0)
517 #define XDMAC_CNDC_NDSUP (0x1u << 1)
518 #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1)
519 #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1)
520 #define XDMAC_CNDC_NDDUP (0x1u << 2)
521 #define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2)
522 #define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2)
523 #define XDMAC_CNDC_NDVIEW_Pos 3
524 #define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos)
525 #define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)))
526 #define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3)
527 #define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3)
528 #define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3)
529 #define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3)
530 /* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */
531 #define XDMAC_CUBC_UBLEN_Pos 0
532 #define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos)
533 #define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)))
534 /* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */
535 #define XDMAC_CBC_BLEN_Pos 0
536 #define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos)
537 #define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)))
538 /* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */
539 #define XDMAC_CC_TYPE (0x1u << 0)
540 #define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0)
541 #define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0)
542 #define XDMAC_CC_MBSIZE_Pos 1
543 #define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos)
544 #define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)))
545 #define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1)
546 #define XDMAC_CC_MBSIZE_FOUR (0x1u << 1)
547 #define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1)
548 #define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1)
549 #define XDMAC_CC_DSYNC (0x1u << 4)
550 #define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4)
551 #define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4)
552 #define XDMAC_CC_PROT (0x1u << 5)
553 #define XDMAC_CC_PROT_SEC (0x0u << 5)
554 #define XDMAC_CC_PROT_UNSEC (0x1u << 5)
555 #define XDMAC_CC_SWREQ (0x1u << 6)
556 #define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6)
557 #define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6)
558 #define XDMAC_CC_MEMSET (0x1u << 7)
559 #define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7)
560 #define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7)
561 #define XDMAC_CC_CSIZE_Pos 8
562 #define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos)
563 #define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)))
564 #define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8)
565 #define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8)
566 #define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8)
567 #define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8)
568 #define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8)
569 #define XDMAC_CC_DWIDTH_Pos 11
570 #define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos)
571 #define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)))
572 #define XDMAC_CC_DWIDTH_BYTE (0x0u << 11)
573 #define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11)
574 #define XDMAC_CC_DWIDTH_WORD (0x2u << 11)
575 #define XDMAC_CC_SIF (0x1u << 13)
576 #define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13)
577 #define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13)
578 #define XDMAC_CC_DIF (0x1u << 14)
579 #define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14)
580 #define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14)
581 #define XDMAC_CC_SAM_Pos 16
582 #define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos)
583 #define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)))
584 #define XDMAC_CC_SAM_FIXED_AM (0x0u << 16)
585 #define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16)
586 #define XDMAC_CC_SAM_UBS_AM (0x2u << 16)
587 #define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16)
588 #define XDMAC_CC_DAM_Pos 18
589 #define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos)
590 #define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)))
591 #define XDMAC_CC_DAM_FIXED_AM (0x0u << 18)
592 #define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18)
593 #define XDMAC_CC_DAM_UBS_AM (0x2u << 18)
594 #define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18)
595 #define XDMAC_CC_INITD (0x1u << 21)
596 #define XDMAC_CC_INITD_IN_PROGRESS (0x0u << 21)
597 #define XDMAC_CC_INITD_TERMINATED (0x1u << 21)
598 #define XDMAC_CC_RDIP (0x1u << 22)
599 #define XDMAC_CC_RDIP_DONE (0x0u << 22)
600 #define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22)
601 #define XDMAC_CC_WRIP (0x1u << 23)
602 #define XDMAC_CC_WRIP_DONE (0x0u << 23)
603 #define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23)
604 #define XDMAC_CC_PERID_Pos 24
605 #define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos)
606 #define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)))
607 /* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */
608 #define XDMAC_CDS_MSP_SDS_MSP_Pos 0
609 #define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos)
610 #define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)))
611 #define XDMAC_CDS_MSP_DDS_MSP_Pos 16
612 #define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos)
613 #define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)))
614 /* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */
615 #define XDMAC_CSUS_SUBS_Pos 0
616 #define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos)
617 #define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)))
618 /* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */
619 #define XDMAC_CDUS_DUBS_Pos 0
620 #define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos)
621 #define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)))
622 /* -------- XDMAC_VERSION : (XDMAC Offset: 0xFFC) XDMAC Version Register -------- */
623 #define XDMAC_VERSION_VERSION_Pos 0
624 #define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos)
625 #define XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos)))
626 #define XDMAC_VERSION_MFN_Pos 16
627 #define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos)
628 #define XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos)))
629 
633 #endif /* _SAME70_XDMAC_COMPONENT_ */
__O uint32_t XDMAC_CIE
(XdmacChid Offset: 0x0) Channel Interrupt Enable Register
__IO uint32_t XDMAC_CNDC
(XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register
__I uint32_t XDMAC_CIS
(XdmacChid Offset: 0xC) Channel Interrupt Status Register
__O uint32_t XDMAC_CID
(XdmacChid Offset: 0x4) Channel Interrupt Disable Register
__IO uint32_t XDMAC_CDS_MSP
(XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern
__O uint32_t XDMAC_GSWF
(Xdmac Offset: 0x40) Global Channel Software Flush Request Register
__IO uint32_t XDMAC_GWAC
(Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__IO uint32_t XDMAC_GRS
(Xdmac Offset: 0x28) Global Channel Read Suspend Register
__I uint32_t XDMAC_CIM
(XdmacChid Offset: 0x8) Channel Interrupt Mask Register
__O uint32_t XDMAC_GRWS
(Xdmac Offset: 0x30) Global Channel Read Write Suspend Register
__O uint32_t XDMAC_GSWR
(Xdmac Offset: 0x38) Global Channel Software Request Register
__I uint32_t XDMAC_GIM
(Xdmac Offset: 0x14) Global Interrupt Mask Register
__O uint32_t XDMAC_GID
(Xdmac Offset: 0x10) Global Interrupt Disable Register
XdmacChid hardware registers.
__O uint32_t XDMAC_GD
(Xdmac Offset: 0x20) Global Channel Disable Register
__IO uint32_t XDMAC_CUBC
(XdmacChid Offset: 0x20) Channel Microblock Control Register
__I uint32_t XDMAC_GSWS
(Xdmac Offset: 0x3C) Global Channel Software Request Status Register
__IO uint32_t XDMAC_CDA
(XdmacChid Offset: 0x14) Channel Destination Address Register
__IO uint32_t XDMAC_CSA
(XdmacChid Offset: 0x10) Channel Source Address Register
__IO uint32_t XDMAC_GWS
(Xdmac Offset: 0x2C) Global Channel Write Suspend Register
__I uint32_t XDMAC_GS
(Xdmac Offset: 0x24) Global Channel Status Register
__O uint32_t XDMAC_GE
(Xdmac Offset: 0x1C) Global Channel Enable Register
__IO uint32_t XDMAC_CSUS
(XdmacChid Offset: 0x30) Channel Source Microblock Stride
__O uint32_t XDMAC_GIE
(Xdmac Offset: 0x0C) Global Interrupt Enable Register
__IO uint32_t XDMAC_CC
(XdmacChid Offset: 0x28) Channel Configuration Register
__IO uint32_t XDMAC_VERSION
(Xdmac Offset: 0xFFC) XDMAC Version Register
__IO uint32_t XDMAC_GCFG
(Xdmac Offset: 0x04) Global Configuration Register
#define XDMACCHID_NUMBER
Xdmac hardware registers.
__IO uint32_t XDMAC_CBC
(XdmacChid Offset: 0x24) Channel Block Control Register
__I uint32_t XDMAC_GIS
(Xdmac Offset: 0x18) Global Interrupt Status Register
__IO uint32_t XDMAC_CDUS
(XdmacChid Offset: 0x34) Channel Destination Microblock Stride
__O uint32_t XDMAC_GRWR
(Xdmac Offset: 0x34) Global Channel Read Write Resume Register
__I uint32_t XDMAC_GTYPE
(Xdmac Offset: 0x00) Global Type Register
__IO uint32_t XDMAC_CNDA
(XdmacChid Offset: 0x18) Channel Next Descriptor Address Register
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:05