drivers/spi/spi.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef SPI_H_INCLUDED
38 #define SPI_H_INCLUDED
39 
40 #include "compiler.h"
41 
43 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47 
48 
51 #define SPI_TIMEOUT 15000
52 
54 typedef enum
55 {
56  SPI_ERROR = -1,
57  SPI_OK = 0,
63 } spi_status_t;
64 
66 typedef enum spi_cs_behavior {
74 
81 #define spi_get_pcs(chip_sel_id) ((~(1u<<(chip_sel_id)))&0xF)
82 
88 static inline void spi_reset(Spi *p_spi)
89 {
90  p_spi->SPI_CR = SPI_CR_SWRST;
91 }
92 
98 static inline void spi_enable(Spi *p_spi)
99 {
100  p_spi->SPI_CR = SPI_CR_SPIEN;
101 }
102 
111 static inline void spi_disable(Spi *p_spi)
112 {
113  p_spi->SPI_CR = SPI_CR_SPIDIS;
114 }
115 
122 static inline void spi_set_lastxfer(Spi *p_spi)
123 {
124  p_spi->SPI_CR = SPI_CR_LASTXFER;
125 }
126 
132 static inline void spi_set_master_mode(Spi *p_spi)
133 {
134  p_spi->SPI_MR |= SPI_MR_MSTR;
135 }
136 
142 static inline void spi_set_slave_mode(Spi *p_spi)
143 {
144  p_spi->SPI_MR &= (~SPI_MR_MSTR);
145 }
146 
154 static inline uint32_t spi_get_mode(Spi *p_spi)
155 {
156  if (p_spi->SPI_MR & SPI_MR_MSTR) {
157  return 1;
158  } else {
159  return 0;
160  }
161 }
162 
169 static inline void spi_set_variable_peripheral_select(Spi *p_spi)
170 {
171  p_spi->SPI_MR |= SPI_MR_PS;
172 }
173 
180 static inline void spi_set_fixed_peripheral_select(Spi *p_spi)
181 {
182  p_spi->SPI_MR &= (~SPI_MR_PS);
183 }
184 
192 static inline uint32_t spi_get_peripheral_select_mode(Spi *p_spi)
193 {
194  if (p_spi->SPI_MR & SPI_MR_PS) {
195  return 1;
196  } else {
197  return 0;
198  }
199 }
200 
206 static inline void spi_enable_peripheral_select_decode(Spi *p_spi)
207 {
208  p_spi->SPI_MR |= SPI_MR_PCSDEC;
209 }
210 
216 static inline void spi_disable_peripheral_select_decode(Spi *p_spi)
217 {
218  p_spi->SPI_MR &= (~SPI_MR_PCSDEC);
219 }
220 
228 static inline uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi)
229 {
230  if (p_spi->SPI_MR & SPI_MR_PCSDEC) {
231  return 1;
232  } else {
233  return 0;
234  }
235 }
236 
242 static inline void spi_enable_mode_fault_detect(Spi *p_spi)
243 {
244  p_spi->SPI_MR &= (~SPI_MR_MODFDIS);
245 }
246 
252 static inline void spi_disable_mode_fault_detect(Spi *p_spi)
253 {
254  p_spi->SPI_MR |= SPI_MR_MODFDIS;
255 }
256 
264 static inline uint32_t spi_get_mode_fault_detect_setting(Spi *p_spi)
265 {
266  if (p_spi->SPI_MR & SPI_MR_MODFDIS) {
267  return 1;
268  } else {
269  return 0;
270  }
271 }
272 
278 static inline void spi_enable_tx_on_rx_empty(Spi *p_spi)
279 {
280  p_spi->SPI_MR |= SPI_MR_WDRBT;
281 }
282 
288 static inline void spi_disable_tx_on_rx_empty(Spi *p_spi)
289 {
290  p_spi->SPI_MR &= (~SPI_MR_WDRBT);
291 }
292 
300 static inline uint32_t spi_get_tx_on_rx_empty_setting(Spi *p_spi)
301 {
302  if (p_spi->SPI_MR & SPI_MR_WDRBT) {
303  return 1;
304  } else {
305  return 0;
306  }
307 }
308 
314 static inline void spi_enable_loopback(Spi *p_spi)
315 {
316  p_spi->SPI_MR |= SPI_MR_LLB;
317 }
318 
324 static inline void spi_disable_loopback(Spi *p_spi)
325 {
326  p_spi->SPI_MR &= (~SPI_MR_LLB);
327 }
328 
329 void spi_enable_clock(Spi *p_spi);
330 void spi_disable_clock(Spi *p_spi);
331 void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value);
332 void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay);
333 spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs);
334 spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs,
335  uint8_t uc_last);
336 
344 static inline uint32_t spi_read_status(Spi *p_spi)
345 {
346  return p_spi->SPI_SR;
347 }
348 
356 static inline uint32_t spi_is_enabled(Spi *p_spi)
357 {
358  if (p_spi->SPI_SR & SPI_SR_SPIENS) {
359  return 1;
360  } else {
361  return 0;
362  }
363 }
364 
372 static inline void spi_put(Spi *p_spi, uint16_t data)
373 {
374  p_spi->SPI_TDR = SPI_TDR_TD(data);
375 }
376 
383 static inline uint16_t spi_get(Spi *p_spi)
384 {
385  return (p_spi->SPI_RDR & SPI_RDR_RD_Msk);
386 }
387 
396 static inline uint32_t spi_is_tx_empty(Spi *p_spi)
397 {
398  if (p_spi->SPI_SR & SPI_SR_TXEMPTY) {
399  return 1;
400  } else {
401  return 0;
402  }
403 }
404 
413 static inline uint32_t spi_is_tx_ready(Spi *p_spi)
414 {
415  if (p_spi->SPI_SR & SPI_SR_TDRE) {
416  return 1;
417  } else {
418  return 0;
419  }
420 }
421 
429 static inline uint32_t spi_is_rx_full(Spi *p_spi)
430 {
431  if (p_spi->SPI_SR & SPI_SR_RDRF) {
432  return 1;
433  } else {
434  return 0;
435  }
436 }
437 
445 static inline uint32_t spi_is_rx_ready(Spi *p_spi)
446 {
447  if ((p_spi->SPI_SR & (SPI_SR_RDRF | SPI_SR_TXEMPTY))
448  == (SPI_SR_RDRF | SPI_SR_TXEMPTY)) {
449  return 1;
450  } else {
451  return 0;
452  }
453 }
454 
461 static inline void spi_enable_interrupt(Spi *p_spi, uint32_t ul_sources)
462 {
463  p_spi->SPI_IER = ul_sources;
464 }
465 
472 static inline void spi_disable_interrupt(Spi *p_spi, uint32_t ul_sources)
473 {
474  p_spi->SPI_IDR = ul_sources;
475 }
476 
484 static inline uint32_t spi_read_interrupt_mask(Spi *p_spi)
485 {
486  return p_spi->SPI_IMR;
487 }
488 
489 void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch,
490  uint32_t ul_polarity);
491 void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase);
492 void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch,
493  uint32_t ul_cs_behavior);
494 void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits);
495 int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck);
496 int16_t spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch,
497  uint8_t uc_baudrate_divider);
498 void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs,
499  uint8_t uc_dlybct);
500 
501 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)
502 
509 static inline Pdc *spi_get_pdc_base(Spi *p_spi)
510 {
511  return (Pdc *)&(p_spi->SPI_RPR);
512 }
513 #endif
514 
515 #if (SAM3U || SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
516 
523 static inline void *spi_get_tx_access(Spi *p_spi)
524 {
525  return (void *)&(p_spi->SPI_TDR);
526 }
527 
535 static inline void *spi_get_rx_access(Spi *p_spi)
536 {
537  return (void *)&(p_spi->SPI_RDR);
538 }
539 #endif
540 
541 void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable);
542 uint32_t spi_get_writeprotect_status(Spi *p_spi);
543 
545 
546 #ifdef __cplusplus
547 }
548 #endif
549 
550 
618 #endif /* SPI_H_INCLUDED */
__I uint32_t SPI_SR
(Spi Offset: 0x10) Status Register
static void spi_set_master_mode(Spi *p_spi)
Set SPI to Master mode.
#define SPI_MR_WDRBT
(SPI_MR) Wait Data Read Before Transfer
void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase)
Set Data Capture Phase.
Definition: spi.c:307
static uint32_t spi_is_enabled(Spi *p_spi)
Test if the SPI is enabled.
void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_cs_behavior)
Configure CS behavior for SPI transfer (spi_cs_behavior_t).
Definition: spi.c:323
#define SPI_MR_MODFDIS
(SPI_MR) Mode Fault Detection
static void spi_enable(Spi *p_spi)
Enable SPI.
static uint32_t spi_get_mode_fault_detect_setting(Spi *p_spi)
Check if mode fault detection is enabled.
#define SPI_CR_SPIEN
(SPI_CR) SPI Enable
__I uint32_t SPI_IMR
(Spi Offset: 0x1C) Interrupt Mask Register
__I uint32_t SPI_RDR
(Spi Offset: 0x08) Receive Data Register
#define SPI_CR_SPIDIS
(SPI_CR) SPI Disable
#define SPI_MR_MSTR
(SPI_MR) Master/Slave Mode
static void spi_enable_loopback(Spi *p_spi)
Enable loopback mode.
spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs)
Read the received data and it&#39;s peripheral chip select value. While SPI works in fixed peripheral sel...
Definition: spi.c:224
int16_t spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_baudrate_divider)
Set Serial Clock Baud Rate divider value (SCBR).
Definition: spi.c:385
#define SPI_MR_PCSDEC
(SPI_MR) Chip Select Decode
static uint32_t spi_get_tx_on_rx_empty_setting(Spi *p_spi)
Check if SPI waits RX_EMPTY before transfer starts.
static void spi_enable_interrupt(Spi *p_spi, uint32_t ul_sources)
Enable SPI interrupts.
enum spi_cs_behavior spi_cs_behavior_t
static uint32_t spi_is_rx_full(Spi *p_spi)
Check if the SPI contains a received character.
static uint32_t spi_get_mode(Spi *p_spi)
Get SPI work mode.
Spi hardware registers.
void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits)
Set number of bits per transfer.
Definition: spi.c:345
#define SPI_CSR_CSNAAT
(SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
static uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi)
Get Peripheral Select Decode mode.
void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_polarity)
Set clock default state.
Definition: spi.c:290
static void spi_disable_interrupt(Spi *p_spi, uint32_t ul_sources)
Disable SPI interrupts.
#define SPI_CR_SWRST
(SPI_CR) SPI Software Reset
#define SPI_TDR_TD(value)
__O uint32_t SPI_IER
(Spi Offset: 0x14) Interrupt Enable Register
static uint32_t spi_read_status(Spi *p_spi)
Read status register.
#define SPI_MR_LLB
(SPI_MR) Local Loopback Enable
Commonly used includes, types and macros.
#define SPI_MR_PS
(SPI_MR) Peripheral Select
static void spi_reset(Spi *p_spi)
Reset SPI and set it to Slave mode.
static uint32_t spi_is_tx_ready(Spi *p_spi)
Check if all transmissions are ready.
static void spi_disable_loopback(Spi *p_spi)
Disable loopback mode.
#define SPI_SR_SPIENS
(SPI_SR) SPI Enable Status
void spi_enable_clock(Spi *p_spi)
Enable SPI clock.
Definition: spi.c:60
static void spi_disable_tx_on_rx_empty(Spi *p_spi)
Disable waiting RX_EMPTY before transfer starts.
__O uint32_t SPI_TDR
(Spi Offset: 0x0C) Transmit Data Register
spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs, uint8_t uc_last)
Write the transmitted data with specified peripheral chip select value.
Definition: spi.c:257
#define SPI_SR_TDRE
(SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR)
spi_cs_behavior
spi_status_t
void spi_disable_clock(Spi *p_spi)
Disable SPI clock.
Definition: spi.c:123
static void spi_disable_peripheral_select_decode(Spi *p_spi)
Disable Peripheral Select Decode.
static void spi_disable_mode_fault_detect(Spi *p_spi)
Disable Mode Fault Detection.
void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value)
Set Peripheral Chip Select (PCS) value.
Definition: spi.c:193
USBInterfaceDescriptor data
__O uint32_t SPI_IDR
(Spi Offset: 0x18) Interrupt Disable Register
static uint32_t spi_read_interrupt_mask(Spi *p_spi)
Read SPI interrupt mask.
static void spi_put(Spi *p_spi, uint16_t data)
Put one data to a SPI peripheral.
int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck)
Calculate the baudrate divider.
Definition: spi.c:362
static uint32_t spi_is_rx_ready(Spi *p_spi)
Check if all receptions are ready.
static uint32_t spi_is_tx_empty(Spi *p_spi)
Check if all transmissions are complete.
static void spi_set_fixed_peripheral_select(Spi *p_spi)
Set Fixed Peripheral Select. Peripheral Chip Select is controlled by SPI_MR.
void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs, uint8_t uc_dlybct)
Configure timing for SPI transfer.
Definition: spi.c:405
static void spi_enable_mode_fault_detect(Spi *p_spi)
Enable Mode Fault Detection.
static void spi_enable_peripheral_select_decode(Spi *p_spi)
Enable Peripheral Select Decode.
void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay)
Set delay between chip selects (in number of MCK clocks). If DLYBCS <= 6, 6 MCK clocks will be insert...
Definition: spi.c:206
#define SPI_CR_LASTXFER
(SPI_CR) Last Transfer
void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable)
Enable or disable write protection of SPI registers.
Definition: spi.c:420
#define SPI_SR_RDRF
(SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR)
static uint16_t spi_get(Spi *p_spi)
Get one data to a SPI peripheral.
static void spi_set_variable_peripheral_select(Spi *p_spi)
Set Variable Peripheral Select. Peripheral Chip Select can be controlled by SPI_TDR.
static void spi_disable(Spi *p_spi)
Disable SPI.
static uint32_t spi_get_peripheral_select_mode(Spi *p_spi)
Get Peripheral Select mode.
#define SPI_RDR_RD_Msk
(SPI_RDR) Receive Data
static void spi_enable_tx_on_rx_empty(Spi *p_spi)
Enable waiting RX_EMPTY before transfer starts.
__O uint32_t SPI_CR
(Spi Offset: 0x00) Control Register
#define SPI_SR_TXEMPTY
(SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR)
__IO uint32_t SPI_MR
(Spi Offset: 0x04) Mode Register
static void spi_set_slave_mode(Spi *p_spi)
Set SPI to Slave mode.
uint32_t spi_get_writeprotect_status(Spi *p_spi)
Indicate write protect status.
Definition: spi.c:444
#define SPI_CSR_CSAAT
(SPI_CSR[4]) Chip Select Active After Transfer
static void spi_set_lastxfer(Spi *p_spi)
Issue a LASTXFER command. The next transfer is the last transfer and after that CS is de-asserted...


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:05